Low-power input reverse connection prevention function control circuit

Abstract

The application discloses a low-power-consumption input anti-reverse-connection function control circuit, which comprises a surge suppression circuit, a MOS tube driving circuit, an input anti-reverse-connection circuit and an isolation auxiliary power supply; the input end of the surge suppression circuit is connected with an input power supply, and the output end is connected with the input end of the MOS tube driving circuit; the output end of the MOS tube driving circuit is connected with the input end of a power module; the input end of the input anti-reverse-connection circuit is connected with the input power supply, and the output end is connected with the input positive end of the isolation auxiliary power supply; the input negative end of the isolation auxiliary power supply is connected with the input power supply, and the output end is connected with the control end of the MOS tube driving circuit; the anti-reverse-connection function control circuit improves the overall efficiency of the combined power supply, reduces power consumption, and protects the power module of the power load in the later stage.

Description

Technical Field

[0001] This invention relates to the field of power protection technology, and in particular to a low-power input reverse connection protection control circuit. Background Technology

[0002] Currently, in the development of power supply and distribution technology in missile-borne and airborne applications both domestically and internationally, due to the diverse power supply requirements of loads, modular combined power supply solutions are generally adopted for various electronic systems. Due to the complexity of the internal working principles of electronic systems, the entire system requires monitoring the polarity of the power module input terminals to prevent irreversible damage to the system caused by reverse connection. In missile-borne and airborne applications, DC / DC converters connected in parallel to the primary bus do not inherently possess reverse connection protection. To improve the reliability of the combined power supply and the safety of the electrical equipment, it is necessary to monitor and protect the polarity of the combined power supply input terminals.

[0003] The current conventional approach is to connect a diode in series on the power bus and use the unidirectional conductivity of the diode to achieve reverse connection protection. However, when multiple power modules are used and the power bus current is large, the existing reverse connection protection circuit consumes too much power, resulting in low overall efficiency of the combined power supply and failing to meet the efficiency requirements of the whole machine. Summary of the Invention

[0004] Based on the technical problems existing in the background technology, the present invention proposes a low-power input reverse connection protection control circuit, which improves the overall efficiency of the combined power supply, reduces power consumption, and protects the power supply module of the downstream load.

[0005] This invention proposes a low-power input reverse connection protection control circuit, comprising a surge suppression circuit, a MOSFET driving circuit, an input reverse connection protection circuit, and an isolation auxiliary power supply. The input terminal of the surge suppression circuit is connected to the input power supply, and the output terminal is connected to the input terminal of the MOSFET driving circuit. The output terminal of the MOSFET driving circuit is connected to the input terminal of the power module. The input terminal of the input reverse connection protection circuit is connected to the input power supply, and the output terminal is connected to the positive input terminal of the isolation auxiliary power supply. The negative input terminal of the isolation auxiliary power supply is connected to the input power supply, and the output terminal is connected to the control terminal of the MOSFET driving circuit.

[0006] Furthermore, the surge suppression circuit includes a capacitor C1, a diode D2, and a PMOS transistor VM1. One end of the capacitor C1 is connected to the positive terminal of the input power supply, and the other end of the capacitor C1 is connected to the positive terminal of the diode D2 and the gate of the PMOS transistor VM1. The negative terminal of the diode D2 is connected to the negative terminal of the input power supply and the negative input terminal of the power module. The source of the PMOS transistor VM1 is connected to the positive terminal of the input power supply, and the drain is connected to the input terminal of the MOS transistor drive circuit.

[0007] Furthermore, the surge suppression circuit also includes a Zener diode V1, resistors R1, R2, and R3. One end of the Zener diode V1, resistor R1, and capacitor C connected in parallel is connected to the source of the PMOS transistor VM1. The other end of the parallel connection is connected to one end of resistor R3 and the other end of resistor R2. The other end of resistor R3 is connected to the gate of the PMOS transistor VM1, and the other end of resistor R2 is connected to the positive terminal of diode D2.

[0008] Furthermore, the MOS transistor driving circuit includes an NMOS transistor VM2 and a Schottky diode D3. The source of the NMOS transistor VM2 is connected to the drain of the PMOS transistor VM1, and the drain is connected to the positive input terminal of the power supply module. The positive terminal of the Schottky diode D3 is connected to the source of the NMOS transistor VM2, and the negative terminal is connected to the negative output terminal of the isolation auxiliary power supply. The positive output terminal of the isolation auxiliary power supply is connected to the gate of the NMOS transistor VM2.

[0009] Furthermore, the MOS transistor driving circuit includes a resistor R4 and a Zener diode V2. The two ends of the resistor R4 are connected to the positive output terminal of the isolation auxiliary power supply and the gate of the NMOS transistor VM2, respectively. The positive terminal of the Zener diode V2 is connected to the source terminal of the NMOS transistor VM2, and the negative terminal is connected to the connection node between the NMOS transistor VM2 and the resistor R4.

[0010] Furthermore, the body diode in PMOS transistor VM1 is oriented with the drain pointing towards the source, and the body diode in NMOS transistor VM2 is oriented with the source pointing towards the drain. MOS transistor VM1 and NMOS transistor VM2 are connected in series on the power bus.

[0011] Furthermore, the isolated auxiliary power supply includes an auxiliary power module M1, which can be a micro-power module from Shanghai Nautical Technology Co., Ltd., model ZA18C120P005.

[0012] Furthermore, the input reverse connection protection circuit includes a diode D1, with the positive terminal of diode D1 connected to the positive terminal of the input voltage and the negative terminal connected to the positive input terminal of the isolation auxiliary power supply.

[0013] The advantages of the low-power input reverse connection protection control circuit provided by this invention are as follows: When the input power supply polarity is correctly applied, as the voltage continues to increase, the on-resistance of PMOS transistor VM1 gradually decreases, suppressing the surge current at the moment of power-on and preventing the surge current from damaging NMOS transistor VM2 through the body diode. When the input power supply polarity is reversed, the channel between PMOS transistor VM1 and NMOS transistor VM2 is not established, and the body diode of PMOS transistor VM1 is turned on while the body diode of NMOS transistor VM2 is not turned on. Since they are in series, the positive terminal of the input power supply is not conducting, and the downstream electrical equipment cannot be powered normally, thus achieving the reverse connection protection effect. By replacing the input reverse connection protection circuit with the input power bus of the isolation auxiliary power supply, the output voltage of the isolation auxiliary power supply 4 drives the MOS transistor drive circuit, thereby achieving the purpose of low power consumption. By improving the overall efficiency of the combined power supply and reducing power consumption, it can protect the power supply modules of the downstream loads. The circuit design is simple, the structure is flexible and simple, the cost is low, the operation is reliable, and it has significant economic benefits. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of the present invention;

[0015] Figure 2 for Figure 1 Detailed circuit diagram;

[0016] Figure 3 A comparison chart of power consumption between this reverse connection protection control circuit and a traditional reverse connection protection circuit;

[0017] Among them, 1-surge suppression circuit, 2-MOS transistor drive circuit, 3-input reverse connection protection circuit, 4-isolation auxiliary power supply, and 5-power module. Detailed Implementation

[0018] The technical solution of the present invention will now be described in detail through specific embodiments. Many specific details are set forth in the following description to provide a thorough understanding of the invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0019] like Figures 1 to 3As shown, this invention proposes a low-power input reverse connection protection control circuit for protecting a power module 5 from reverse connection. The circuit is characterized by comprising a surge suppression circuit 1, a MOSFET driver circuit 2, an input reverse connection protection circuit 3, and an isolation auxiliary power supply 4. The input terminal of the surge suppression circuit 1 is connected to the input power supply, and its output terminal is connected to the input terminal of the MOSFET driver circuit 2. The output terminal of the MOSFET driver circuit 2 is connected to the input terminal of the power module 5. The input terminal of the input reverse connection protection circuit 3 is connected to the input power supply, and its output terminal is connected to the positive input terminal of the isolation auxiliary power supply 4. The negative input terminal of the isolation auxiliary power supply 4 is connected to the input power supply, and its output terminal is connected to the control terminal of the MOSFET driver circuit 2.

[0020] In surge suppression circuit 1, the body diodes inside PMOS transistor VM1 and NMOS transistor VM2 in MOS transistor drive circuit 2 have opposite current directions. Therefore, surge suppression circuit 1 and MOS transistor drive circuit 2 are inactive at the moment of forward power-on, while the isolation auxiliary power supply 4 operates normally, supplying power to MOS transistor drive circuit 2 and turning it on. As time progresses, when the voltage reaches the turn-on threshold of surge suppression circuit 1, surge suppression circuit 1 turns on, forming a circuit between the input power supply, surge suppression circuit 1, MOS transistor drive circuit 2, and power module 5 to supply power to power module 5. When the polarity of the input power supply is abnormal, the auxiliary isolation power supply module 4 cannot operate normally, thus preventing MOS transistor drive circuit 2 from being driven. Consequently, the input power supply, surge suppression circuit 1, MOS transistor drive circuit 2, and power module 5 do not conduct, achieving the purpose of reverse connection protection.

[0021] Furthermore, compared to the traditional input reverse connection protection circuit that uses a diode connected in series at the input power bus, this circuit achieves low power consumption by replacing the input reverse connection protection circuit 3 at the input power bus of the isolation auxiliary power supply 4 and using the output voltage of the isolation auxiliary power supply 4 to drive the MOSFET driver circuit 2. This improves the overall efficiency of the combined power supply, reduces power consumption, and protects the downstream power load modules. The circuit design is simple, flexible, inexpensive, and reliable, offering significant economic benefits.

[0022] In this embodiment, the surge suppression circuit 1 includes a capacitor C1, a diode D2, and a PMOS transistor VM1. One end of the capacitor C1 is connected to the positive terminal of the input power supply, and the other end of the capacitor C1 is connected to both the positive terminal of the diode D2 and the gate of the PMOS transistor VM1. The negative terminal of the diode D2 is connected to both the negative terminal of the input power supply and the negative input terminal of the power module 5. The source of the PMOS transistor VM1 is connected to the positive terminal of the input power supply, and the drain is connected to the input terminal of the MOS transistor drive circuit 2. The surge suppression circuit 1 also includes a Zener diode V1, resistors R1, R2, and R3. One end of the parallel connection of the Zener diode V1, resistor R1, and capacitor C is connected to the source of the PMOS transistor VM1. The other end of the parallel connection is connected to both one end of resistor R3 and one end of resistor R2. The other end of resistor R3 is connected to the gate of the PMOS transistor VM1, and the other end of resistor R2 is connected to the positive terminal of the diode D2.

[0023] The MOS transistor driving circuit 2 includes an NMOS transistor VM2 and a Schottky diode D3. The source of the NMOS transistor VM2 is connected to the drain of the PMOS transistor VM1, and the drain is connected to the positive input terminal of the power supply module 5. The positive terminal of the Schottky diode D3 is connected to the source of the NMOS transistor VM2, and the negative terminal is connected to the negative output terminal of the isolation auxiliary power supply 4. The positive output terminal of the isolation auxiliary power supply 4 is connected to the gate of the NMOS transistor VM2. The MOS transistor driving circuit 2 includes a resistor R4 and a Zener diode V2. The two ends of the resistor R4 are connected to the positive output terminal of the isolation auxiliary power supply 4 and the gate of the NMOS transistor VM2, respectively. The positive terminal of the Zener diode V2 is connected to the source terminal of the NMOS transistor VM2, and the negative terminal is connected to the connection node between the NMOS transistor VM2 and the resistor R4.

[0024] Among them, resistors R1 and R2 are used to divide the voltage and provide the driving voltage for PMOS transistor VM1. Resistor R3 is used to limit the current. Zener diode V1 is used to prevent the voltage across resistor R1 from being too high and breaking down PMOS transistor VM1. Resistor R4 has the same function as resistor R3, which is to limit the current. Zener diode V2 has the same function as Zener diode V1, which is to prevent the voltage at the gate-gate terminals of NMOS transistor VM2 from being too high and breaking down NMOS transistor VM2.

[0025] The working principle of the low-power input reverse connection protection control circuit of the present invention is as follows:

[0026] First, the field-effect transistors have a body diode. In the PMOS transistor VM1, the body diode is oriented from the drain (D) to the source (S), and in the NMOS transistor VM2, the body diode is oriented from the source (S) to the drain (D). Since the PMOS transistor VM1 and the NMOS transistor VM2 are connected in series on the power bus, the circuit cannot be turned on.

[0027] When the input power supply polarity is correctly applied, the current should flow from Vin+ to Vin-. At the moment the circuit starts working, since the voltage across capacitor C1 cannot change abruptly, the voltage value increases slowly from zero, and the source and gate voltages of PMOS transistor VM1 gradually rise. Before the voltage across capacitor C1 reaches the threshold voltage of the source and gate of PMOS transistor VM1, the channel between the source and drain of PMOS transistor VM1 is not established, and the circuit cannot conduct. When the input polarity of the isolation auxiliary power supply 4 is correct, it outputs normally. Since the negative output terminal of the isolation auxiliary power supply 4 is connected to the source S terminal of NMOS transistor VM2, and the positive output terminal is connected to the gate G terminal of NMOS transistor VM2 through resistor R4, NMOS transistor VM2 is turned on, which in turn drives the formation of a channel between the source S and drain D of NMOS transistor VM2 for current to flow. As time goes on, the voltage across capacitor C1 gradually increases. When the voltage across capacitor C1 reaches the threshold voltage between the source (S) and drain (G) of PMOS transistor VM1, PMOS transistor VM1 turns on and supplies power to the subsequent load power module. As the voltage continues to increase, the on-resistance of PMOS transistor VM1 gradually decreases, suppressing the surge current at the moment of power-on and preventing the surge current from passing through the body diode of NMOS transistor VM2 and damaging NMOS transistor VM2. Specific understanding of surge suppression: Both PMOS transistors VM1 and NMOS transistors VM2 have internal body diodes. Under normal conditions, if there is no driving voltage between the source and gate, for PMOS transistor VM1, current can flow from the drain (D) to the source (S) through its body diode; for NMOS transistor VM2, current can flow from the source (S) to the drain (D) through its body diode. Therefore, without a surge suppression circuit, there will be a large surge current at the moment of power-on. Before the N-channel of NMOS transistor VM2 is established, all the surge current will pass through the body diode of NMOS transistor VM2. A large current passing through the body diode may burn out NMOS transistor VM2.

[0028] When the input power polarity is reversed, the current should flow from Vin- to Vin+. At the instant the circuit starts working, due to the unidirectional conductivity of diode D2, capacitor C1 cannot be charged through diode D2. The P-channel of PMOS transistor VM1 is not established, and VM1 is not conducting. At this time, because diode D1 is connected in series with the positive input terminal of the isolation auxiliary power supply 4, the input power supply of the isolation auxiliary power supply 4 is abnormal and cannot output voltage normally. Consequently, it cannot drive NMOS transistor VM2 to conduct. The N-channel of NMOS transistor VM2 is not established, and PMOS transistor VM1 cannot be driven either, nor is its P-channel established. Therefore, current cannot flow through the channels of PMOS transistor VM1 and NMOS transistor VM2, and can only flow through the body diodes of the transistors. At this time, the body diode of PMOS transistor VM1 is conducting, while the body diode of NMOS transistor VM2 is not conducting. Since they are in series, the positive terminal of the input power supply is not conducting, and the downstream equipment cannot be powered normally, thus achieving the effect of reverse connection protection.

[0029] Since the MOSFET is a voltage-driven device, the output voltage of the isolation auxiliary power supply 4 drives the NMOS transistor VM2, and the current is negligible. Therefore, the power consumption of this part of the isolation auxiliary power supply 4 driving the NMOS transistor VM2 is negligible. The power consumption of this reverse connection protection control circuit is mainly concentrated in the on-resistance R of the NMOS transistor VM2. ds Above, the on-resistance of NMOS transistor VM2 is typically R ds ≤20mΩ, input power bus current I, therefore, as Figure 3 As shown, the power consumption P1 is:

[0030] P1=(I×I)×R ds

[0031] Traditional reverse connection protection circuits use a diode connected in series with the positive terminal of the input power supply, resulting in a forward voltage drop of U. FM Therefore, as Figure 3 As shown, the power consumption P2 is:

[0032] P2 = U FM ×I

[0033] Among them, the forward voltage drop U of the diode FM The minimum voltage is 0.2V. As the forward current gradually increases, the forward voltage drop U of the Schrödinger diode increases. FM It also gradually increases. Therefore, through methods such as Figure 3 As shown, it can be intuitively seen that the low-power input reverse connection protection control circuit of this embodiment has the effect of reducing power consumption.

[0034] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A low-power input reverse connection protection control circuit for providing reverse connection protection for a power supply module (5), characterized in that, It includes a surge suppression circuit (1), a MOSFET driving circuit (2), an input reverse connection protection circuit (3), and an isolation auxiliary power supply (4). The input terminal of the surge suppression circuit (1) is connected to the input power supply, and the output terminal is connected to the input terminal of the MOS transistor drive circuit (2). The output terminal of the MOS transistor drive circuit (2) is connected to the input terminal of the power module (5). The input terminal of the input reverse connection protection circuit (3) is connected to the input power supply, and the output terminal is connected to the positive input terminal of the isolation auxiliary power supply (4). The negative input terminal of the isolation auxiliary power supply (4) is connected to the input power supply, and the output terminal is connected to the control terminal of the MOS transistor drive circuit (2). The MOS transistor driving circuit (2) includes an NMOS transistor VM2 and a Schottky diode D3. The source of the NMOS transistor VM2 is connected to the drain of the PMOS transistor VM1, and the drain is connected to the positive input of the power supply module (5). The positive terminal of the Schottky diode D3 is connected to the source of the NMOS transistor VM2, and the negative terminal is connected to the negative output of the isolation auxiliary power supply (4). The positive output of the isolation auxiliary power supply (4) is connected to the gate of the NMOS transistor VM2.

2. The low-power input reverse connection protection control circuit according to claim 1, characterized in that, The surge suppression circuit (1) includes a capacitor C1, a diode D2 and a PMOS transistor VM1. One end of the capacitor C1 is connected to the positive terminal of the input power supply, and the other end of the capacitor C1 is connected to the positive terminal of the diode D2 and the gate of the PMOS transistor VM1. The negative terminal of the diode D2 is connected to the negative terminal of the input power supply and the negative terminal of the power supply module (5). The source of the PMOS transistor VM1 is connected to the positive terminal of the input power supply and the drain is connected to the input terminal of the MOS transistor driving circuit (2).

3. The low-power input reverse connection protection control circuit according to claim 2, characterized in that, The surge suppression circuit (1) also includes a Zener diode V1, resistors R1, R2 and R3. One end of the Zener diode V1, resistor R1 and capacitor C connected in parallel is connected to the source of PMOS transistor VM1. The other end of the parallel connection is connected to one end of resistor R3 and one end of resistor R2. The other end of resistor R3 is connected to the gate of PMOS transistor VM1 and the other end of resistor R2 is connected to the positive terminal of diode D2.

4. The low-power input reverse connection protection control circuit according to claim 1, characterized in that, The MOS transistor driving circuit (2) includes a resistor R4 and a Zener diode V2. The two ends of the resistor R4 are connected to the positive output terminal of the isolation auxiliary power supply (4) and the gate of the NMOS transistor VM2, respectively. The positive terminal of the Zener diode V2 is connected to the source terminal of the NMOS transistor VM2, and the negative terminal is connected to the connection node between the NMOS transistor VM2 and the resistor R4.

5. The low-power input reverse connection protection control circuit according to claim 1, characterized in that, In PMOS transistor VM1, the body diode is oriented with the drain pointing towards the source, and in NMOS transistor VM2, the body diode is oriented with the source pointing towards the drain. PMOS transistor VM1 and NMOS transistor VM2 are connected in series on the power bus.

6. A low-power input reverse connection protection control circuit according to any one of claims 1-5, characterized in that, The isolated auxiliary power supply (4) includes an auxiliary power supply module M1.

7. A low-power input reverse connection protection control circuit according to any one of claims 1-5, characterized in that, The input reverse connection protection circuit (3) includes a diode D1, with the positive terminal of the diode D1 connected to the positive terminal of the input voltage and the negative terminal connected to the positive input terminal of the isolation auxiliary power supply (4).

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