Method of manufacturing three-dimensional memory
By implanting ions into the substrate to form a release layer and disconnecting the second substrate portion after forming the array device, the problems of high cost and process inhomogeneity in the fabrication of three-dimensional memory are solved, and the reuse of materials and the stability of the fabrication process are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2021-09-06
- Publication Date
- 2026-06-09
AI Technical Summary
In current 3D memory fabrication, the waste of substrate material leads to excessively high production costs, and the uniformity and consistency of the process are insufficient.
Ions are implanted into the substrate to form a release layer, dividing the substrate into first and second parts. After forming the array device, the second substrate part is disconnected at the release layer and peeled off by heat or mechanical force, and the peeled substrate material is reused.
This achieved cost savings, improved process uniformity and consistency, reduced substrate material waste, and enhanced the stability and reliability of the fabrication process.
Smart Images
Figure CN115776821B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a method for fabricating a three-dimensional memory. Background Technology
[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.
[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate.
[0004] In related technologies, when fabricating 3D memory, processes such as grinding and etching are typically used to remove the substrate to expose the ends of the channel structure. However, this leads to waste of substrate material and excessively high production costs. Summary of the Invention
[0005] The embodiments of this disclosure provide a method for fabricating a three-dimensional memory, which aims to achieve cost savings and improve process uniformity and consistency.
[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:
[0007] A method for fabricating a three-dimensional memory is provided. The method includes: implanting ions into a substrate to form a release layer; the release layer dividing the substrate into a first substrate portion and a second substrate portion stacked along its thickness direction; forming an array device on the first substrate portion, the array device including a channel structure extending into the first substrate portion, the channel structure including a channel aperture and a storage functional layer and a channel layer sequentially formed within the channel aperture; disconnecting the substrate at the release layer to peel off the second substrate portion; etching the first substrate portion and portions of the storage functional layer extending into the first substrate portion to expose portions of the channel layer; and forming a source layer, the source layer being in electrical contact with the exposed portion of the channel layer.
[0008] In some embodiments, the step of breaking the substrate at the release layer includes: breaking the substrate at the release layer by a heat treatment process.
[0009] In some embodiments, the step of breaking the substrate at the release layer includes: breaking the substrate at the release layer by mechanical force.
[0010] In some embodiments, prior to the step of disconnecting the substrate at the release layer, the fabrication method further includes: forming a semiconductor structure, the semiconductor structure including a substrate and peripheral devices located on the substrate; and bonding the peripheral devices to the array devices.
[0011] In some embodiments, prior to the step of forming the source layer, the fabrication method further includes: ion doping at least a portion of the exposed channel layer, wherein the type of ion doping is the same as the type of doping of the source layer.
[0012] In some embodiments, prior to the step of forming the array device, the fabrication method further includes: sequentially forming a first etch stop layer and a second etch stop layer on the first substrate portion, wherein the first etch stop layer and the second etch stop layer have different etch selectivity ratios. The step of etching the first substrate portion and the portion of the storage functional layer extending into the first substrate portion to expose a portion of the channel layer includes: etching the first substrate portion to the first etch stop layer to expose the portion of the storage functional layer extending into the first substrate portion; and etching the first etch stop layer and the exposed portion of the storage functional layer to the second etch stop layer to expose a portion of the channel layer.
[0013] In some embodiments, the array device includes a storage region; the step of forming the array device includes: forming a stacked structure on a first substrate portion; forming a channel via through the stacked structure and extending into the first substrate portion in the storage region, and sequentially forming the storage functional layer and the channel layer within the channel via to form the channel structure.
[0014] In some embodiments, the array device further includes a step region; the step of forming the array device further includes: forming a virtual channel structure in the step region that penetrates the stacked structure and extends into the first substrate portion; wherein, after etching the first substrate portion, a portion of the virtual channel structure extending into the first substrate portion is exposed; during the etching of the first etch stop layer and the exposed portion of the memory function layer, at least a portion of the exposed virtual channel structure is removed; the source layer further covers the exposed portion of the virtual channel structure.
[0015] In some embodiments, the fabrication method further includes: forming an interlayer dielectric layer on the side of the source layer away from the stacked structure; forming a first source contact in the interlayer dielectric layer, the first source contact being electrically connected to the source layer; and forming a metal interconnect layer on the side of the interlayer dielectric layer away from the stacked structure, the metal interconnect layer being electrically connected to the first source contact.
[0016] In some embodiments, the array device further includes a peripheral region; the step of forming the array device further includes: forming an insulating capping layer on the side of the stacked structure away from the first substrate portion; forming a source conductive structure and a peripheral conductive structure in the peripheral region that penetrate the insulating capping layer and extend into the first substrate portion. Wherein, after etching the first substrate portion and the first etch barrier layer, portions of the source conductive structure extending into both the first substrate portion and the first etch barrier layer and portions of the peripheral conductive structure extending into both the first substrate portion and the first etch barrier layer are exposed; the interlayer dielectric layer separates the source layer from the source conductive structure and the peripheral conductive structure.
[0017] In some embodiments, during the formation of the first source contact, a second source contact and a peripheral contact are also formed in the interlayer dielectric layer. The second source contact is electrically connected to the source conductive structure, and the peripheral contact is electrically connected to the peripheral conductive structure. The metal interconnect layer is also electrically connected to the second source contact.
[0018] In some embodiments, during the formation of the metal interconnect layer, a connection pad is also formed on the side of the interlayer dielectric layer away from the stacked structure, and the connection pad is electrically connected to the peripheral contacts.
[0019] The method for fabricating a three-dimensional memory provided in the above embodiments of this disclosure achieves substrate thinning by first implanting ions into the substrate to form a release layer before forming the array device, and then breaking the substrate at the release layer to peel off the second substrate portion after forming the array device. This allows the peeled-off second substrate portion to be reused, saving process costs. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.
[0021] Figures 1A to 1E This is a flowchart of a method for fabricating a three-dimensional memory according to some embodiments;
[0022] Figures 2A to 2L This is a cross-sectional structural diagram corresponding to each step in the fabrication method of a three-dimensional memory according to some embodiments. Detailed Implementation
[0023] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0024] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.
[0025] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.
[0026] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0027] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.
[0028] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.
[0029] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0030] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.
[0031] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.
[0032] As used herein, “approximation” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).
[0033] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).
[0034] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
[0035] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.
[0036] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).
[0037] Figures 1A to 1E A flowchart illustrating a method for fabricating a three-dimensional memory according to some embodiments of this disclosure; Figures 2A to 2L The images show cross-sectional structural diagrams corresponding to each step in the fabrication method of a three-dimensional memory according to some embodiments. It should be understood that... Figures 1A to 1E The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps may be performed simultaneously, or they may be performed in a sequence different from the steps described. Figures 1A to 1E The execution order is shown below. (Followed by...) Figures 1A to 1E ,as well as Figures 2A to 2L The fabrication methods of the three-dimensional memory in some embodiments are described.
[0038] Please see Figure 1A This disclosure provides a method for fabricating a three-dimensional memory, which includes steps S1 to S5.
[0039] S1. Ions are implanted into the substrate to form a release layer; the release layer divides the substrate into a first substrate portion and a second substrate portion that are stacked along the thickness direction.
[0040] In step S1, refer to Figure 2A and Figure 2B By implanting ions into the substrate 1, a release layer 2 can be formed. The release layer 2 can divide the substrate 1 into a first substrate portion 11 and a second substrate portion 12 that are stacked along the thickness direction X.
[0041] In some examples, substrate 1 is a silicon substrate. For instance, substrate 1 can be made of monocrystalline silicon, so that after the second substrate portion 12 is removed in a subsequent step, the exposed surface of the first substrate portion 11 is a monocrystalline silicon surface. Compared to other materials (such as polycrystalline silicon), monocrystalline silicon helps to produce films with better uniformity and consistency in subsequent thin film fabrication processes.
[0042] In some examples, the step of implanting ions into the substrate 1 includes implanting hydrogen ions and / or oxygen ions into the substrate 1. This allows the aforementioned release layer 2 to be formed.
[0043] S2. An array device is formed on the first substrate portion.
[0044] In step S2, refer to Figure 2C The formed array device 100 includes a stacked structure 3. The stacked structure 3 includes a gate dielectric layer 31 and a gate sacrificial layer 32 formed on a first substrate portion 11 and alternately stacked. Exemplarily, the stacked structure 3 is formed by methods such as thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0045] In the stacked structure 3, the thicknesses of the multiple gate dielectric layers 31 can be the same or different; the thicknesses of the multiple gate sacrificial layers 32 can also be the same or different; the specific settings can be made according to process requirements. Furthermore, in the fabrication process of the stacked structure 3, different numbers of stacked layers correspond to different stacking heights. For example, the stacked structure 3 can have 8, 32, 64, or 128 layers, etc. The more layers in the stacked structure 3, the higher the integration density, meaning the more memory cells are formed subsequently. The specific number of stacked layers and stacking height of the stacked structure 3 can be designed according to actual memory requirements; this disclosure does not impose specific limitations in this regard.
[0046] In some embodiments, the gate dielectric layer 31 and the gate sacrificial layer 32 have different etch selectivity ratios. The gate sacrificial layer 122 can be removed in a subsequent process to form a sacrificial gap, and the sacrificial gap (i.e., the space where the gate sacrificial layer 31 is located) can be filled with conductive material to form a gate layer, i.e., a word line. Exemplarily, the material of the gate dielectric layer 31 includes silicon oxide, and the material of the gate sacrificial layer includes silicon nitride. The steps for forming the gate layer will be described in detail in some later embodiments.
[0047] It is understood that although some embodiments of this disclosure employ a gate sacrificial layer 31 that is subsequently filled with conductive material to form a gate layer, the embodiments for forming the gate layer in this disclosure are not limited to this. For example, it may also be achieved by directly forming overlapping gate dielectric layers and gate layers.
[0048] In step S2, refer to Figure 2D The formed array device 100 also includes a channel structure 4. The formed channel structure 4 penetrates the stacked structure 3 and extends into the first substrate portion 11.
[0049] In some examples, the channel structure 4 includes a channel aperture 40 and a storage function layer 41 and a channel layer 42 sequentially formed within the channel aperture 40.
[0050] The channel hole 40 can be formed in the stacked structure 3 using, for example, a dry / wet etching process. The channel hole 40 can be perpendicular to the first substrate portion 11 and extend in a direction close to the first substrate portion 11 to extend into the first substrate portion 11.
[0051] Continue reading Figure 2D Thin-film deposition processes such as CVD, PVD, or ALD can be used to sequentially deposit a charge barrier layer 411, a charge trapping layer 412, a tunneling layer 413, and a channel layer 42 on the inner wall (including the bottom and sidewalls) of the channel hole 40. The charge barrier layer 411, charge trapping layer 412, and tunneling layer 413 constitute the storage functional layer 41. For example, the material of the charge barrier layer 411 is silicon oxide, the material of the charge trapping layer 412 is silicon nitride, and the material of the tunneling layer 413 is silicon oxide, to form an "ONO" structure.
[0052] In some examples, the material of the channel layer 42 is polycrystalline silicon.
[0053] In the above steps, thin film deposition processes such as CVD, PVD, or ALD can also be used to fill the channel holes where the storage functional layer 41 and the channel layer 42 are formed with a dielectric material, such as silicon oxide, to form a channel structure 4 having the channel layer 42, the storage functional layer 41, and the filled dielectric material. Exemplarily, one or more air gaps can be formed during the channel filling process by controlling the channel filling process to reduce structural stress.
[0054] When the materials of the charge blocking layer 411, charge trapping layer 412, tunneling layer 413 and channel layer 42 are silicon oxide, silicon nitride, silicon oxide and polysilicon respectively, and the dielectric material filled is silicon oxide, the formed channel structure 4 can be called an "ONOPO" structure.
[0055] It should be noted that, in this example, Figure 2D The illustration uses only two channel structures as an example. In actual fabrication, multiple channel structures 4 can be formed that penetrate the stacked structure 3 and extend into the first substrate portion 11. The number and arrangement of the channel structures 4 can be fabricated according to actual storage requirements. After the above-described process, the region corresponding to the channel structures 4 formed on the first substrate portion 11 through the stacked structure 3 can be referred to as the storage region A of the array device 100 (e.g., Figure 2E The storage area A shown can be used to implement the storage function of a three-dimensional memory.
[0056] Please see Figure 2E In some embodiments, a stepped structure is formed at the edge of the stacked structure 3, which can be formed by performing multiple trim-etch cycles on the multiple gate dielectric layers 31 and multiple gate sacrificial layers 32 of the stacked structure 3.
[0057] Based on this, a barrier layer and an insulating cover layer 5 can be sequentially formed on the stepped structure. The insulating cover layer 5 can be formed by filling the stepped structure with a dielectric material and covering the stepped structure. For example, the insulating cover layer 5 can extend towards the edge of the stacked structure 3 (e.g., towards the peripheral region C).
[0058] The insulating capping layer 5 can be formed using a thin film deposition process such as CVD, PVD, or ALD. The material of the insulating capping layer 5 can be the same as that used in the gate dielectric layer, such as silicon oxide. For example, a chemical mechanical polishing (CMP) process can be used to planarize the surface of the insulating capping layer 5 away from the first substrate portion 11.
[0059] After the above-described processing, the region corresponding to the stepped structure formed by the stacked structure 3 on the first substrate portion 11 can be referred to as the stepped region B of the array device 100. The stepped region B can be the electrical connection region of the word line (gate layer). The region on the first substrate portion 11 entirely covered by the insulating cover layer 5 can be referred to as the peripheral region C. The peripheral region C can be used to form peripheral contact structures and source contact structures that are electrically connected to the peripheral circuit layers in subsequent processes. The steps for forming the peripheral contact structures and source contact structures will be described in detail in some later embodiments.
[0060] Please see Figure 2FIn some embodiments, the array device 100 formed in step S2 further includes a virtual channel structure 4'. For example, a virtual channel structure 4' is formed in the step region B, penetrating the stacked structure 3 and extending into the first substrate portion 11. It should be noted that the depth to which the virtual channel structure 4' extends into the first substrate portion 11 can be the same as or different from the depth to which the channel structure 4 extends into the first substrate portion 11. Furthermore, there can be multiple virtual channel structures 4', and the depths to which multiple virtual channel structures 4' extend into the first substrate portion 11 can also be the same or different. Figure 2F In the example shown, the depth to which multiple virtual channel structures 4′ extend into the first substrate portion 11 is the same as the depth to which multiple channel structures 4 extend into the first substrate portion 11.
[0061] In the step of forming the virtual channel structure 4′, thin film deposition processes such as CVD, PVD, or ALD can be employed. A dielectric material, such as silicon oxide, is filled into the pores where the virtual channel structure 4′ is to be formed to create the virtual channel structure 4′. Exemplarily, by controlling the filling process, one or more air gaps can be formed during the filling process to alleviate structural stress. In embodiments of this disclosure, the virtual channel structure 4′ can be used to provide mechanical support without forming a storage functional layer and a channel layer with storage capabilities.
[0062] It should be noted that this article only uses the example of virtual channel structure 4′ and channel structure 4 being formed separately (channel structure 4 is formed before the step of forming a stepped structure at the edge of stacked structure 3, while virtual channel structure 4′ is formed after the step of forming a stepped structure at the edge of stacked structure 3) for illustration. In some other embodiments, virtual channel structure 4′ and channel structure 4 may also be formed under the same process.
[0063] In some examples, such as Figure 2F As shown, a first capping layer 61 is formed on the side of the stacked structure 33 away from the first substrate portion 11 using a thin-film deposition process. The first capping layer 61 can cover the end face of the channel structure 4 away from the first substrate portion 11 and the end face of the virtual channel structure 4' away from the first substrate portion 11. Exemplarily, the first capping layer 61 can be made of the same material (e.g., silicon oxide) as the insulating capping layer 5 and the gate dielectric layer 31.
[0064] In some embodiments, the step of forming the array device 100 includes replacing the gate sacrificial layer to form a gate layer. In this step, such as Figure 2F and Figure 2G As shown, firstly, a slot U is formed that penetrates the stacked structure 3 and extends into the first substrate portion 11 (it can be understood that, in the case where the aforementioned first capping layer 61 is provided, as...). Figure 2FAs shown, the slot U can also penetrate the first capping layer 61), and there is a gap between the slot U and the channel structure 4; then, the gate sacrificial layer 32 is removed through the slot U to form a sacrificial gap; finally, the gate layer 33 is formed in the sacrificial gap.
[0065] For example, the slot U is filled with dielectric material to form a slot structure Ux comprising the slot U and the dielectric material.
[0066] For example, the aforementioned slot U can be formed using, for example, a dry / wet etching process. Furthermore, the depth of the slot U extending into the first substrate portion 11 can be the same as or different from the depth of the channel structure 4 extending into the first substrate portion 11.
[0067] In the step of removing the gate sacrificial layer via the slot U to form a sacrificial gap, the slot U formed after the above process can be used as a channel for the etchant, and a wet etching process can be used to remove all the gate sacrificial layers 32 in the stacked structure 3 to form multiple sacrificial gaps.
[0068] In the step of forming the gate layer within the sacrificial gap, a thin film deposition process such as CVD, PVD, or ALD can be used to form the gate layer 33 within the sacrificial gap. The material of the gate layer 33 can be any one or a combination of conductive materials selected from tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicides.
[0069] In some examples, prior to the step of forming the gate layer within the sacrificial gap, a gate barrier layer is formed on the inner walls of the gate gap and the plurality of sacrificial gaps using a thin-film deposition process. Based on this, exemplaryly, an adhesive layer is formed on the surface of the gate barrier layer located within the sacrificial gap using a thin-film deposition process.
[0070] The gate barrier layer can be made of a high dielectric constant material, such as aluminum oxide. The adhesive layer can be made of materials such as tantalum nitride or titanium nitride. The adhesive layer helps to increase the adhesion between the gate Zehnder layer and the gate layer 33 formed in subsequent processes.
[0071] For example, after forming the gate barrier layer and the adhesive layer, a wet etching process can be used to remove portions of the adhesive layer and the gate barrier layer near the slot U to form a groove in the slot, but the disclosed implementation is not limited to this. In other embodiments, the filled gate layer can be aligned with the inner wall of the slot U without forming a groove. Thus, the gate barrier layer, the adhesive layer, and the gate layer 33 are sequentially deposited on the inner wall of the sacrificial gap.
[0072] In the step of filling the trench U with a dielectric material to form the trench structure Ux, one or more dielectric materials can be selected, such as silicon oxide, to fill the trench U. Exemplarily, by controlling the channel filling process, one or more air gaps are formed during the filling process to alleviate structural stress. The formed trench structure Ux can effectively reduce the deformation of the storage region A and provide good support for the storage region A.
[0073] In some examples, such as Figure 2H As shown, a second capping layer 62 is formed on the side of the first capping layer 61 away from the first substrate portion 11 using a thin-film deposition process. The second capping layer 62 can cover the end face of the slot structure Ux away from the first substrate portion 11. Exemplarily, the second capping layer 62 can be made of the same material as the first capping layer 61 (e.g., silicon oxide).
[0074] In some embodiments, the step of forming the array device 100 further includes the step of forming a source conductive structure 71 and a peripheral conductive structure 72 that penetrate the insulating cover layer 5 and extend to the first substrate portion 11 in the peripheral region C.
[0075] In this step, such as Figure 2H As shown, the source conductive structure 71 and the peripheral conductive structure 72 can vertically penetrate the insulating cover layer 5 and extend into the first substrate portion 11 in the peripheral region C. The depth to which the source conductive structure 71 extends into the first substrate portion 11 can be the same as or different from the depth to which the channel structure 4 extends into the first substrate portion 11. Similarly, the depth to which the peripheral conductive structure 72 extends into the first substrate portion 11 can be the same as or different from the depth to which the channel structure 4 extends into the first substrate portion 11. The number and arrangement of the source conductive structure 71 and the peripheral conductive structure 72 can be fabricated according to actual needs, for example, designed according to the signal transmission requirements of the three-dimensional memory. The embodiments of this disclosure do not limit this.
[0076] While fabricating the aforementioned source conductive structure 71 and peripheral conductive structure 72, for example, such as Figure 2H As shown, word line conductive structure 73 and channel conductive structure 74 can also be fabricated simultaneously. The word line conductive structure 73 is electrically connected to the gate layer 33, and the channel conductive structure 74 is electrically connected to the channel structure 4.
[0077] It is understandable that, with the aforementioned first sealing layer 61 and second sealing layer 62 provided, such as Figure 2H As shown, the aforementioned source conductive structure 71, peripheral conductive structure 72, word line conductive structure 73, and channel conductive structure 74 can all penetrate the first capping layer 61 and the second capping layer 62.
[0078] In some embodiments, please refer to Figure 1BThe above-mentioned method for fabricating three-dimensional memory also includes:
[0079] S01. Forming a semiconductor structure, which includes a substrate and peripheral devices located on the substrate.
[0080] S02, Bond the peripheral devices to the array devices.
[0081] In steps S01 and S02, as follows Figure 2I As shown, the semiconductor structure 8 includes a substrate 81 and peripheral devices 82 located on the substrate 81. The array device 100 can be inverted and then bonded to the peripheral devices 8. In this embodiment, the bonding method between the array device 100 and the peripheral devices 8 can be hybrid bonding.
[0082] The peripheral device 82 can be electrically connected to the aforementioned polar conductive structure 71, peripheral conductive structure 72, word line conductive structure 73, and channel conductive structure 74.
[0083] The peripheral device 82 is configured to control and sense the array device 100. The peripheral device 82 may include any active (or passive) components of the circuit, such as page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), or transistors, diodes, resistors, capacitors, etc.
[0084] Peripheral device 82 may include multiple transistors, all or some of which are formed in substrate 81 (e.g., below the top surface of substrate 81) and / or directly on substrate 81. Similarly, shallow trench isolation and doped regions (e.g., source and drain regions of transistors) may also be formed in substrate 81.
[0085] It should be noted that peripheral device 82 may also include any other circuitry compatible with advanced logic processes. For example, peripheral device 82 may include logic circuitry (e.g., processors and programmable logic devices (PLDs)) and / or memory circuitry (e.g., static random access memory (SRAM)).
[0086] S3. The substrate is broken at the release layer to peel off the second substrate portion. This design achieves substrate thinning, allowing the peeled-off second substrate portion to be reused, thus saving process costs.
[0087] In step S3, as Figure 2I and Figure 2J As shown, the substrate 1 is broken at the release layer 2, thereby peeling off the second substrate portion 12.
[0088] In some examples, the substrate 1 is broken at the release layer 2 by a heat treatment process. Here, the release layer 2 is formed by gas ion implantation, and therefore includes many bubbles. By heating, the bubbles in the release layer 2 can be expanded. The expansion of the bubbles can break the substrate 1 at the release layer 2, that is, a peel occurs, thereby dividing the substrate 1 into a first substrate portion 11 and a second substrate portion 12.
[0089] In other examples, the substrate 1 is separated at the release layer 2 by mechanical force. Here, the substrate 1 is divided into a first substrate portion 11 and a second substrate portion 12 by mechanical force, which does not require heating. This reduces the risk of the bonding effect of the aforementioned bonded peripheral devices 8 being affected by excessive temperature, thereby helping to improve the device stability of the fabricated three-dimensional memory.
[0090] S4. Etch the first substrate portion and the portion of the storage functional layer extending into the first substrate portion to expose the portion of the trench layer.
[0091] In this step, refer to Figure 2J and Figure 2K After etching the portion of the first substrate portion 11 and the portion of the storage function layer 41 extending into the first substrate portion 11, a portion Q1 in the channel layer 42 can be exposed, that is, the end of the channel layer 42 is exposed.
[0092] S5. A source layer is formed, and the source layer makes electrical contact with the exposed portion of the channel layer.
[0093] In this step, refer to Figure 2L The source layer 101 formed covers the exposed portion Q1 of the channel layer 42, thereby enabling electrical contact between the source layer 101 and the end of the channel layer 42.
[0094] The method for fabricating a three-dimensional memory provided in some embodiments of this disclosure includes the steps S1 to S5 described above, namely, before forming the array device 100, ions are implanted into the substrate 1 to form a release layer 2, and after forming the array device 100, the substrate 1 is broken at the release layer 2 to peel off the second substrate portion 12. This allows the peeled-off second substrate portion 12 to be reused. For example, in the fabrication of a new three-dimensional memory, the peeled-off second substrate portion 12 can be used as a new substrate. Ions are implanted into the new substrate again to form a release layer inside the new substrate, and after forming the new array device, the new substrate is broken at the release layer. This process is repeated, so a single substrate can be used for the fabrication of multiple three-dimensional memories, thus achieving substrate reuse and saving process costs.
[0095] Furthermore, it is worth noting that in some embodiments of this disclosure, the array device 100 and the peripheral device 8 are bonded first, and then the substrate 1 is thinned. Since the second substrate portion 12 in the substrate 1 has not been peeled off during the bonding process of the array device 100 and the peripheral device 8, that is, the substrate 1 is relatively thick and has a strong load-bearing capacity, it helps to improve the bonding effect, and the stability and reliability after bonding are high.
[0096] In some examples, the ion implantation depth is the same at all locations on substrate 1, which facilitates making the release layer 2 parallel to the surface of the first substrate portion 11 away from the second substrate portion 12. Here, "parallel" includes the case of absolute parallelism, while "parallelism" also includes the case of approximate parallelism due to some uncontrollable errors (such as measurement errors, equipment errors, etc.). "Approximate parallelism" can be, for example, the existence of a small angle between the two (such as within 10°), or the presence of small protrusions or depressions on the surface of the release layer.
[0097] This design allows for a relatively smooth peeled surface on the second substrate portion after peeling, making it easier to use in the next fabrication process.
[0098] Please see Figure 1C In some embodiments of this disclosure, prior to the step of forming the array device described above, the method for fabricating the three-dimensional memory further includes:
[0099] S001, A first etch stop layer and a second etch stop layer are sequentially formed on the first substrate portion.
[0100] In this step, such as Figure 2C As shown, a first etch stop layer 91 is formed on the surface of the first substrate portion 11, and a second etch stop layer 92 is formed on the surface of the first etch stop layer 91 away from the first substrate portion 11. The first etch stop layer 91 is used to stop the subsequent step S4 at this layer, and the second etch stop layer 92 is used to stop the subsequent step 5 at this layer.
[0101] For example, the first etch stop layer 91 and the second etch stop layer 92 can be formed using at least one thin film deposition process such as CVD, PVD, or ALD. The first etch stop layer 91 can be made of silicon oxide. The second etch stop layer 92 can be made of polycrystalline silicon. It should be noted that the first etch stop layer 91 and the second etch stop layer 92 should be made of materials that achieve a predetermined etch selectivity ratio with the subsequent etchable material, and the first etch stop layer 91 and the second etch stop layer 92 should have different etch selectivity ratios.
[0102] Based on this, see some implementation methods. Figure 1DThe steps S4 above, including etching the first substrate portion and the portion of the storage functional layer extending into the first substrate portion to expose the portion of the trench layer, include steps S41 to S42.
[0103] S41. Etch the first substrate portion to the first etch stop layer to expose the portion of the storage functional layer extending into the first substrate portion.
[0104] See Figure 2J and Figure 2K In this step, for example, a wet etching process can be used to remove the first substrate portion, and the etching can be stopped at the first etch stop layer 91 by selecting a predetermined etchant.
[0105] The etching selectivity of the first etch stop layer 91 is the same as or similar to that of the storage function layer 41. For example, the material of the first etch stop layer 91 is the same as the material of the charge blocking layer 411 of the storage function layer 41, that is, the etching selectivity of the first etch stop layer 91 is the same as that of the storage function layer 41.
[0106] When the material of the first etch stop layer 91 is the same as the material of the charge barrier layer 411 of the storage functional layer 41, for example, both are made of silicon oxide, the etching can be stopped at the charge barrier layer 411 when the first substrate portion is removed using, for example, a wet etching process, thereby exposing the portion of the storage functional layer 41 of the channel structure 4 that extends into the first substrate portion 11. By adding the first etch stop layer 91, it is helpful to control the process uniformity during the removal of the first substrate portion 11.
[0107] S42. Etch the portion of the first etch stop layer and the exposed portion of the storage function layer to the second stop layer to expose a portion of the channel layer.
[0108] See Figure 2J and Figure 2K In this step, for example, a wet etching process can be used to remove the first etch stop layer 91, and the etching can be stopped at the second etch stop layer 92 by selecting a predetermined etchant.
[0109] The etching selectivity of the second etch stop layer 92 is the same as or similar to that of the channel layer 42. For example, the material of the second etch stop layer 92 is the same as that of the channel layer 42, that is, the etching selectivity of the second etch stop layer 92 and the channel layer 42 is the same.
[0110] When the material of the second etch stop layer 92 is the same as the material of the channel layer 42 of the channel structure 4, for example, both are made of polysilicon, when removing the first etch stop layer 91 and the memory functional layer 41 using, for example, a wet etching process, the etching can be stopped at the channel layer 132, thereby exposing the portion Q1 of the channel layer 42 of the channel structure 4 extending into the first substrate portion 11. By adding the second etch stop layer 92, it is helpful to control the process uniformity during the removal of the first etch stop layer 91 and the memory functional layer 41. The semiconductor structure after the process in step S42 is as follows: Figure 2K As shown.
[0111] Based on this, by way of example, the portion of the storage function layer 41 of the channel structure 4 extending into the second etch stop layer 92 can be further removed by controlling the etching time, so that the channel layer 42 of the channel structure 4 has a larger exposed area.
[0112] In some implementations, see Figure 2K After etching the first substrate portion 11, a portion of the virtual channel structure 4' extending into the first substrate portion 11 is also exposed; during the etching of the exposed portions of the first etch stop layer 91 and the storage function layer 41, at least a portion of the exposed virtual channel structure 4' is removed. For example Figure 2K The example shown is that the exposed portion of the virtual channel structure 4′ is partially removed. It can be understood that in other examples, the exposed portion of the virtual channel structure 4′ can also be completely removed.
[0113] In some implementations, see Figure 2K After etching the first substrate portion 11 and the first etch stop layer 91, portions of the source conductive structure 71 extending into both the first substrate portion 11 and the first etch stop layer 91 and portions of the peripheral conductive structure 72 extending into both the first substrate portion 11 and the first etch stop layer 91 are also exposed.
[0114] In some implementations, see Figure 2K After etching the first substrate portion 11 and the first etch stop layer 91, portions of the slot structure Ux extending into both the first substrate portion 11 and the first etch stop layer 91 are also exposed.
[0115] For example, a wet etching process can be used to remove the first substrate portion 11 and the first etch stop layer 91. By selecting a predetermined etchant or controlling the etching time, the etching can be stopped at the outer surfaces of the virtual channel structure 4′ extending to both the first substrate portion 11 and the first etch stop layer 91, the source conductive structure 71 extending to both the first substrate portion 11 and the first etch stop layer 91, the peripheral conductive structure 72 extending to both the first substrate portion 11 and the first etch stop layer 91, and the slot structure Ux. The virtual channel structure 4′ extends to the outer surface of both the first substrate portion 11 and the first etch barrier layer 91 to expose the ends of the virtual channel structure 4′ extending to both the first substrate portion 11 and the first etch barrier layer 91, the source conductive structure 71 extending to the ends of both the first substrate portion 11 and the first etch barrier layer 91, the peripheral conductive structure 72 extending to the ends of both the first substrate portion 11 and the first etch barrier layer 91, and the slot structure Ux extending to the ends of both the first substrate portion 11 and the first etch barrier layer 91.
[0116] The three-dimensional memory processed by step S42 is as follows Figure 2K As shown. Figure 2K The three-dimensional memory formed in this process does not have the first substrate portion 11 and the first etch stop layer 91 described above, but still retains the second etch stop layer 92. The second etch stop layer 92 can also serve as a spacer layer between the stacked structure 3 and the source layer formed in subsequent processes. Furthermore, by controlling the thickness of the second etch stop layer 92, the distance between the gate layer 33 (word line) and the source layer in the stacked structure 3 can be effectively controlled.
[0117] According to the method for fabricating a three-dimensional memory provided in some embodiments of this disclosure, by adding a first etch stop layer 91 and a second etch stop layer 92, and by removing part of the storage functional layer 41 of the channel structure through an etching process to expose part of the channel layer 42 of the channel structure 4, the etching can be stopped at the second etch stop layer 92. This helps to control the process uniformity during the removal of the first substrate portion 11 and the first etch stop layer 91, thereby ensuring the uniformity of the channel layer 42 after removing part of the storage functional layer 41 of the channel structure 4.
[0118] Based on the above embodiments, please continue to refer to Figure 1D The step S5, forming a source layer and making electrical contact between the exposed portion of the source layer and the channel layer, includes step S51.
[0119] S51. A source layer is formed on the side of the second etch stop layer away from the stacked structure, and the source layer covers the exposed portion of the channel layer.
[0120] In this step, refer to Figure 2LA polysilicon layer can be deposited on the side of the second etch stop layer 92 away from the stacked structure 3 using a thin film deposition process to form the source layer 101.
[0121] After processing in step S51, as follows Figure 2L As shown, the source layer 101 can make electrical contact with the exposed portion of the channel layer 42 after the processing in step S5, thereby achieving electrical connection between the channel structure 4 and the source layer 101. For example, as... Figure 2L As shown, the source layer 101 surrounds the channel layer 42 at the end of the channel structure 4, which enables the source layer 101 and the channel layer 42 at the end of the channel structure 4 to have a large contact area, which is beneficial to increase the reliability of the contact connection and improve the performance of the three-dimensional memory after the fabrication is completed.
[0122] It's worth noting that in related technologies, achieving electrical connection between the channel layer and the source can be accomplished by drilling holes at the bottom of the channel structure to form an epitaxial structure (i.e., bottom SEG (Selective Epitaxy Growth)). However, this method suffers from difficulty in controlling the drilling precision, easily leading to over-etching or under-etching, which in turn causes difficulties in bottom epitaxial growth and poor connection. Alternatively, the channel layer can be exposed by opening the storage functional layer (e.g., the "ONO" film layer) on the sidewalls of the channel structure, thereby achieving electrical connection between the channel and the source (i.e., sidewall SEG). However, this method requires multiple etching processes and the fabrication of various protective films before opening the storage functional layer on the sidewalls of the channel structure, resulting in a complex process, high cost, and poor scalability.
[0123] Compared to the two methods described above, this embodiment exposes the bottom of the channel structure 4 by directly removing the substrate material (i.e., the first substrate portion 11) at the bottom of the channel. This allows for convenient etching from the bottom of the channel structure to expose the channel layer, and then the electrical connection between the channel layer and the source is achieved by forming the source layer 101. This avoids drilling holes at the bottom of the channel and eliminates the need for multiple etching operations through slits to open the storage functional layer on the sidewalls of the channel structure, significantly reducing the complexity of the manufacturing process.
[0124] In some embodiments, the source layer 101 also covers the ends of the exposed virtual channel structure 4′, the ends of the source conductive structure 71, the ends of the peripheral conductive structure 72, and the ends of the slot structure Ux.
[0125] In some embodiments, prior to step S5 (or step S51) above, the preparation method further includes: ion doping at least the exposed portion of the channel layer, wherein the type of ion doping is the same as the doping type of the source layer.
[0126] In this step, refer to Figure 2K and Figure 2LWhen the source layer 101 is doped with an N-type ion dopant, at least the portion of Q1 exposed to the channel layer 42 will also be doped with an N-type ion dopant; when the source layer 101 is doped with a P-type ion dopant, at least the portion of Q1 exposed to the channel layer 42 will also be doped with a P-type ion dopant. Since the ion doping types are the same, this helps to improve the conductivity between the source layer 101 and the channel layer 42.
[0127] In some embodiments, the same type of ion doping can also be applied to the portion Q2 of the channel layer 42 near the exposed portion Q1 to improve conductivity stability.
[0128] Please see Figure 1E In some embodiments, the method for fabricating a three-dimensional memory further includes steps S6 to S8.
[0129] S6. An interlayer dielectric layer is formed on the side of the source layer away from the stacked structure.
[0130] In this step, refer to Figure 2L A dielectric material, such as silicon oxide, can be filled into the side of the source layer 101 away from the stacked structure 3 using, for example, high-density plasma chemical vapor deposition (HDPD) to form an interlayer dielectric layer 102. Based on this, for example, a CMP process can be used to planarize the surface of the interlayer dielectric layer 102 away from the stacked structure 3.
[0131] In some implementations, see Figure 2L Before fabricating the interlayer dielectric layer 102, a dry or wet etching process can be used to remove the portion of the source layer 101 corresponding to the source conductive structure 71, and also to remove the portion of the source layer 101 corresponding to the peripheral conductive structure 72. Based on this, for example, by controlling the etching time, the portion of the second etch stop layer 92 corresponding to the source conductive structure 71 can be removed, and the portion of the second etch stop layer 92 corresponding to the peripheral conductive structure 72 can also be removed.
[0132] S7. A first source contact is formed in the interlayer dielectric layer, and the first source contact is electrically connected to the source layer.
[0133] In this step, refer to Figure 2L Dry or wet etching processes can be used to remove the portion of the interlayer dielectric layer 102 corresponding to the source layer 101 (e.g., ...). Figure 2L The portion of the interlayer dielectric layer 102 corresponding to the channel structure 4 forms an opening region, and then a conductive material is deposited in the opening region to form a first source contact A1 electrically connected to the source layer 101.
[0134] Based on this, for example, a dry or wet etching process can be used to remove the portion of the interlayer dielectric layer 102 corresponding to the source conductive structure 71, and also to remove the portion of the interlayer dielectric layer 102 corresponding to the peripheral conductive structure 72. This exposes the ends of the source conductive structure 71 and the peripheral conductive structure 72, and then forms a second source contact A2 electrically connected to the end of the source conductive structure 71, and a peripheral contact A3 electrically connected to the end of the peripheral conductive structure 72, in the interlayer dielectric layer 102.
[0135] The methods for forming the first source contact A1, the second source contact A2, and the peripheral contact A3 include, but are not limited to, thin film deposition processes such as CVD, PVD, and ALD.
[0136] In some implementations, such as Figure 2L As shown, the interlayer dielectric layer 102 separates the source layer 101 from the source conductive structure 71 and the peripheral conductive structure 72, preventing direct electrical contact between the source layer 101 and any two of the source conductive structure 71 and the peripheral conductive structure 72. This prevents crosstalk between the source layer 101, the source conductive structure 71, and the peripheral conductive structure 72 during signal reception and transmission.
[0137] S8. A metal interconnect layer is formed on the side of the interlayer dielectric layer away from the stacked structure, and the metal interconnect layer is electrically connected to the first source contact.
[0138] In this step, thin film deposition processes such as CVD, PVD, and ALD can be used to form a metal thin film. Then, the metal thin film is patterned (e.g., exposed, developed) to form the metal interconnect layer 103. See also... Figure 2L The metal interconnect layer 103 can be electrically connected to both the first source contact A1 and the second source contact A2 simultaneously, thereby enabling the transmission of source signals.
[0139] In some implementations, see Figure 2L During the formation of the metal interconnect layer 103, a connection pad 103' is also formed on the side of the interlayer dielectric layer 102 away from the stacked structure 3. The connection pad 103' is electrically connected to the peripheral contact A3. This connection substrate connection pad 103' is used for connection with external circuitry.
[0140] In some embodiments, the method for fabricating a three-dimensional memory further includes the step of forming a barrier layer 104, see [reference]. Figure 2L The barrier layer 104 blocks the connection pad 103′ from the metal interconnect layer 103, making it less likely for signal interference to occur between the connection pad 103′ and the metal interconnect layer 103.
[0141] See Figure 2LSome embodiments of this disclosure provide a three-dimensional memory 1000, which includes: a source layer 101, a stacked structure 3 located on one side of the source layer 101, and a channel structure 4 that penetrates the stacked structure 3 and extends into the source layer 101.
[0142] The channel structure 4 includes a channel hole and a storage function layer 41 and a channel layer 42 sequentially disposed within the channel hole. The specific arrangement of the storage function layer 41 can be found in the foregoing content and will not be repeated here.
[0143] The storage layer 41 has an opening near the source layer 101, and the channel layer 42 extends into the source layer 101 through the opening and is in electrical contact with the source layer 101. That is, in Figure 2L In the example, the exposed portion Q1 of the channel layer 42 extends into the source layer 101, and the exposed portion Q1 of the channel layer 42 is in electrical contact with the source layer 101.
[0144] In some embodiments of the present disclosure, the three-dimensional memory 1000 extends the exposed portion Q1 of the channel layer 42 directly into the source layer 101 to achieve electrical contact. Compared with the scheme of achieving electrical connection between the channel layer and the source using a bottom SEG or a sidewall SEG, the three-dimensional memory 1000 in some embodiments of the present disclosure has a simpler structure, is easier to manufacture, and has higher stability and reliability of electrical connection.
[0145] In some embodiments, continue reading Figure 2L At least the portion of the channel layer 42 extending into the source layer 101 is doped with ions of the same type as those in the source layer 101. For example, when the source layer 101 is doped with an N-type ion dopant, at least the portion Q1 exposed to the channel layer 42 will be doped with an N-type ion dopant; when the source layer 101 is doped with a P-type ion dopant, at least the portion Q1 exposed to the channel layer 42 will be doped with a P-type ion dopant. Since both have the same ion doping type, this helps to improve the conductivity between the source layer 101 and the channel layer 42.
[0146] In some embodiments, the same type of ion doping is also performed on the portion Q2 of the channel layer 42 near the exposed portion Q1, thereby further improving conductivity stability.
[0147] In some embodiments, the three-dimensional memory 1000 further includes a second etch barrier layer 92 located between the source layer 101 and the stacked structure 3. By providing the second etch barrier layer 92, it is helpful to control the process uniformity during the removal of the memory functional layer 41, thereby making it easier to extend the exposed portion Q1 of the channel layer 42 into the source layer 101, and improving the contact effect between the source layer 101 and the channel layer 42.
[0148] Furthermore, the three-dimensional memory 1000 provided in some embodiments of this disclosure is fabricated using the fabrication method of any of the embodiments described above. The beneficial effects of fabrication using the fabrication method of any of the above embodiments can be found in the foregoing description, and will not be repeated here.
[0149] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for fabricating a three-dimensional memory, characterized in that, include: Ions are implanted into the substrate to form a release layer; The release layer divides the substrate into a first substrate portion and a second substrate portion that are stacked along the thickness direction. An array device is formed on the first substrate portion, the array device including a channel structure extending into the first substrate portion, the end of the channel structure near the second substrate portion being spaced from the second substrate portion, the channel structure including a channel hole and a storage functional layer and a channel layer sequentially formed in the channel hole; A semiconductor structure is formed, the semiconductor structure including a substrate and peripheral devices located on the substrate; Bond the peripheral devices to the array devices; The substrate is broken at the release layer to peel off a portion of the second substrate; Etch the first substrate portion and the portion of the storage functional layer extending into the first substrate portion to expose a portion of the channel layer; as well as, A source layer is formed, which is in electrical contact with the exposed portion of the channel layer.
2. The preparation method according to claim 1, characterized in that, The step of breaking the substrate at the release layer includes: The substrate is broken at the release layer by a heat treatment process.
3. The preparation method according to claim 1, characterized in that, The step of breaking the substrate at the release layer includes: The substrate is broken at the release layer by mechanical force.
4. The preparation method according to claim 1, characterized in that, Prior to the step of forming the source layer, the method further includes: At least the exposed portion of the channel layer is ion-doped, and the type of ion doping is the same as the type of doping of the source layer.
5. The preparation method according to any one of claims 1 to 4, characterized in that, Prior to the step of forming the array device, the method further includes: A first etch stop layer and a second etch stop layer are sequentially formed on the first substrate portion, wherein the first etch stop layer and the second etch stop layer have different etch selectivity ratios; The step of etching the first substrate portion and the portion of the storage functional layer extending into the first substrate portion to expose a portion of the channel layer includes: The first substrate portion is etched down to the first etch stop layer to expose the portion of the storage function layer that extends into the first substrate portion; The first etch stop layer and the exposed portion of the storage function layer are etched to the second etch stop layer to expose a portion of the channel layer.
6. The preparation method according to claim 5, characterized in that, The array device includes a storage area; the steps of forming the array device include: A multilayer structure is formed on the first substrate portion; A channel hole is formed in the storage area, penetrating the stacked structure and extending into the first substrate portion, and the storage functional layer and the channel layer are sequentially formed in the channel hole to form the channel structure.
7. The preparation method according to claim 6, characterized in that, The array device further includes a stepped region; the step of forming the array device further includes: forming a virtual channel structure in the stepped region that penetrates the stacked structure and extends into the first substrate portion; Specifically, after etching the first substrate portion, a portion of the virtual channel structure extending into the first substrate portion is exposed; during the etching of the first etch stop layer and the exposed portions of the memory function layer, at least a portion of the exposed virtual channel structure is removed; The source layer also covers the exposed portion of the virtual channel structure.
8. The preparation method according to claim 6, characterized in that, Also includes: An interlayer dielectric layer is formed on the side of the source layer away from the stacked structure; A first source contact is formed in the interlayer dielectric layer, and the first source contact is electrically connected to the source layer; A metal interconnect layer is formed on the side of the interlayer dielectric layer away from the stacked structure, and the metal interconnect layer is electrically connected to the first source contact.
9. The preparation method according to claim 8, characterized in that, The array device further includes a peripheral region; the step of forming the array device further includes: An insulating cover layer is formed on the side of the stacked structure away from the first substrate portion; A source conductive structure and a peripheral conductive structure are formed in the peripheral region, penetrating the insulating cover layer and extending into the first substrate portion; In this process, after etching the first substrate portion and the first etch stop layer, portions of the source conductive structure extending into both the first substrate portion and the first etch stop layer, and portions of the peripheral conductive structure extending into both the first substrate portion and the first etch stop layer are also exposed. The interlayer dielectric layer separates the source layer from the source conductive structure and the peripheral conductive structure.
10. The preparation method according to claim 9, characterized in that, During the formation of the first source contact, a second source contact and a peripheral contact are also formed in the interlayer dielectric layer. The second source contact is electrically connected to the source conductive structure, and the peripheral contact is electrically connected to the peripheral conductive structure. The metal interconnect layer is also electrically connected to the second source contact.
11. The preparation method according to claim 10, characterized in that, During the formation of the metal interconnect layer, a connection pad is also formed on the side of the interlayer dielectric layer away from the stacked structure, and the connection pad is electrically connected to the peripheral contacts.