Power-on detection circuit and electronic device

Abstract

The application discloses a power-on detection circuit and an electronic device. The power-on detection circuit is used in a processor and comprises a first logic unit, which receives multiple power supply voltages, generates one first intermediate detection signal according to each two power supply voltages, and generates at least two first intermediate detection signals. A second logic unit performs logic operation on the at least two first intermediate detection signals to generate a power-on detection signal. The power-on detection signal is provided to a reset end of the processor, and the reset end is set or reset according to the power-on detection signal. The application performs power-on detection on the processor through a simple logic circuit, and reduces circuit complexity and debugging complexity.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a power-on detection circuit and electronic device. Background Technology

[0002] With the advancement of technology and the improvement of living standards, electronic devices are becoming increasingly integrated. The processors in these devices require multiple different power supply voltages to operate normally. To ensure proper functioning, the processor typically enters its working state after all power supply voltages have been applied, thereby controlling the operation of other modules within the electronic device.

[0003] Currently, the above functions are often achieved by connecting a detection chip and a delay circuit to the processor's reset terminal. However, adding a detection chip and a delay circuit increases material costs and debugging costs. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a power-on detection circuit and electronic device for a processor, which implements power-on detection of the processor through a simple logic circuit.

[0005] According to a first aspect of the present invention, a power-on detection circuit is provided for use in a processor, comprising:

[0006] The first logic unit receives multiple power supply voltages and generates a first intermediate detection signal based on every two power supply voltages, and the first logic unit generates at least two first intermediate detection signals.

[0007] The second logic unit performs logical operations on the at least two first intermediate detection signals to generate a power-on detection signal.

[0008] The power-on detection signal is provided to the processor's reset terminal, which is set or reset according to the power-on detection signal.

[0009] Optionally, when all the power supply voltages are fully powered on, the processor's reset terminal is set according to the power-on detection signal; when at least one power supply voltage is not fully powered on, the processor's reset terminal is reset according to the power-on detection signal.

[0010] Optionally, it also includes:

[0011] An indicator unit, connected to the second logic unit, characterizes the detection result based on the power-on detection signal, wherein the indicator unit indicates whether the power-on was successful or failed based on the power-on detection signal.

[0012] Optionally, the indicating unit may include an LED or a buzzer.

[0013] Optionally, the first logic unit includes:

[0014] Multiple first-stage AND gates are provided. The first input terminal of each first-stage AND gate receives one of the multiple power supply voltages, the second input terminal of each first-stage AND gate receives another of the multiple power supply voltages, and the output terminal of each first-stage AND gate outputs a first intermediate detection signal.

[0015] Optionally, the second logic unit includes:

[0016] A first multi-input AND gate, each input terminal receiving one of the first intermediate detection signals, and an output terminal outputting the power-on detection signal, wherein the number of input terminals of the first multi-input AND gate is greater than or equal to the number of the first intermediate detection signals.

[0017] Optionally,

[0018] When the number of first intermediate detection signals generated by the first logic unit is less than three, the second logic unit includes:

[0019] A second-stage AND gate is used, with its first input receiving a first intermediate detection signal and its second input receiving another first intermediate detection signal. The output of the second-stage AND gate outputs the power-on detection signal.

[0020] When the first logic unit generates at least three first intermediate detection signals, the second logic unit includes:

[0021] At least two second-stage AND gates, each second-stage AND gate's first input receives one of the first intermediate detection signals, each second-stage AND gate's second input receives the other of the first intermediate detection signals, and each second-stage AND gate's output outputs a second intermediate detection signal;

[0022] And a second multiple-input AND gate, each input of the second multiple-input AND gate receiving a second intermediate detection signal, and the output outputting the power-on detection signal, wherein the number of inputs of the second multiple-input AND gate is greater than or equal to the number of the second intermediate detection signals.

[0023] Optionally, the second logic unit includes:

[0024] Multiple two-input AND gates are configured hierarchically according to the number of first intermediate detection signals. Each two-input AND gate in the first layer receives two of the first intermediate detection signals and generates a second intermediate detection signal. The number of two-input AND gates in each subsequent layer is determined according to the number of intermediate detection signals generated in the previous layer. The intermediate detection signal output by the layer including one of the two-input AND gates is used as the power-on detection signal.

[0025] Optionally, the input of the AND gate that does not receive the power supply voltage or the intermediate detection signal receives a high-level signal.

[0026] According to a second aspect of the present invention, an electronic device is provided, comprising:

[0027] Power-on detection circuit, including:

[0028] A first logic unit receives multiple power supply voltages and generates a first intermediate detection signal based on every two power supply voltages, and the first logic unit generates at least two first intermediate detection signals; a second logic unit performs logical operations on the at least two first intermediate detection signals to generate a power-on detection signal; and

[0029] The processor includes a reset terminal and receives the power-on detection signal. When the multiple power supply voltages are fully powered on, the reset terminal of the processor is set according to the power-on detection signal; when at least one power supply voltage is not fully powered on, the reset terminal of the processor is reset according to the power-on detection signal.

[0030] The power-on detection circuit provided in this application performs at least two levels of logic operations on the power supply voltage required by the processor and outputs a power-on detection signal. Based on the power-on detection signal, it sets or resets the processor's reset terminal to determine the processor's working state, thereby reducing circuit complexity and debugging complexity.

[0031] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application. Attached Figure Description

[0032] Figure 1 This diagram illustrates the structure of an electronic device provided according to an embodiment of this application.

[0033] Figure 2 A flowchart illustrating a power-on detection method for a processor in an electronic device according to an embodiment of this application is shown.

[0034] Figure 3 A schematic diagram of a power-on detection circuit for a processor according to an embodiment of this application is shown;

[0035] Figure 4 A schematic diagram of a power-on detection circuit for another processor according to an embodiment of this application is shown;

[0036] Figure 5 A schematic diagram of a power-on detection circuit for another processor according to an embodiment of this application is shown. Detailed Implementation

[0037] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0038] Figure 1 A schematic diagram of the structure of an electronic device provided according to an embodiment of this application is shown.

[0039] See Figure 1 The electronic device includes a power-on detection circuit 100 and a processor 200.

[0040] Processor 200 includes a reset pin. After normal power-on, the reset pin of processor 200 is set. When the reset pin is set, processor 200 is in normal working state. When the reset pin is reset, processor 200 is in abnormal working state (stops working or does not work normally). That is, the potential of the reset pin can characterize whether processor 200 has entered normal working state.

[0041] The power-on detection circuit 100 includes a first logic unit 110 and a second logic unit 120. The first logic unit 110 receives multiple power supply voltages (power supply voltage VCC1, power supply voltage VCC2, ..., power supply voltage VCCn) required for the processor 200 to operate, and generates a first intermediate detection signal (first intermediate detection signal OUT1, ..., first intermediate detection signal OUTi) for every two power supply voltages. The first logic unit 110 generates at least two first intermediate detection signals based on the number of power supply voltages. The second logic unit 120 is connected to the first logic unit 110, performs logical operations on the at least two first intermediate detection signals generated by the first logic unit 110 to generate a power-on detection signal Vout, and provides the power-on detection signal Vout to the reset pin of the processor 200. The reset pin of the processor 200 is set or reset according to the power-on detection signal Vout.

[0042] Furthermore, when all power supply voltages are fully powered on, the reset terminal of the processor 200 is set according to the power-on detection signal Vout, indicating that the processor 200 has entered a normal working state; when at least one power supply voltage is not fully powered on, the reset terminal of the processor 200 is reset according to the power-on detection signal Vout, indicating that the processor 200 has entered an abnormal working state.

[0043] In some embodiments, the power-on detection circuit 100 further includes an indication unit 130. The indication unit 130 is connected to the second logic unit 120 and represents the power-on detection result based on the received power-on detection signal Vout. Further, the indication unit indicates whether the processor 200 has successfully powered on or failed to power on based on the power-on detection signal Vout, thereby indicating the operating state of the processor 200.

[0044] Figure 2 This is a schematic flowchart illustrating a power-on detection method for a processor in an electronic device according to an embodiment of this application.

[0045] See Figure 2 The power-on detection method for processor 200 includes:

[0046] Step S100: Provide the power supply voltages required by the processor to the power-on detection circuit. Further, the power-on detection circuit 100 performs logical operations on the power supply voltages required by the processor 200 to obtain multiple first intermediate detection signals, performs logical operations on the multiple first intermediate detection signals to generate a power-on detection signal Vout, provides the power-on detection signal Vout to the reset terminal of the processor 200 to set or reset it, and provides the power-on detection signal Vout to the indicator unit 130.

[0047] Step S200: Determine whether power-on was successful based on the indicator unit of the power-on detection circuit. Further, the indicator unit 130 includes, for example, an LED. When the power-on detection signal Vout is set at the reset terminal of the processor 200, the power-on detection signal Vout illuminates the LED in the indicator unit 130 to indicate successful power-on. When the power-on detection signal Vout is reset at the reset terminal of the processor 200, the power-on detection signal Vout extinguishes the LED in the indicator unit 130 to indicate power-on failure.

[0048] In other alternative embodiments, the indicator unit 130 may include, for example, a buzzer. When the power-on detection signal Vout sets the reset terminal of the processor 200, the power-on detection signal Vout turns on the buzzer in the indicator unit 130 to indicate successful power-on. When the power-on detection signal Vout resets the reset terminal of the processor 200, the power-on detection signal Vout turns off the buzzer in the indicator unit 130 to indicate power-on failure.

[0049] If power-on is successful, step S300 is executed: the processor is in normal operating state. Further, when the power-on detection signal Vout is set to the reset pin of processor 200, processor 200 enters normal operating state.

[0050] If power-on fails, step S400 is executed: the processor is in an abnormal operating state. Further, when the power-on detection signal Vout resets the reset pin of the processor 200, the processor 200 enters an abnormal operating state.

[0051] Figure 3 This diagram illustrates a power-on detection circuit for a processor according to an embodiment of this application.

[0052] See Figure 3 The first logic unit 110 includes multiple first-level AND gates U1. The first input of each first-level AND gate U1 receives one of the multiple supply voltages, the second input of each first-level AND gate receives the other of the multiple supply voltages, and the output of each first-level AND gate outputs a first intermediate detection signal. Specifically, the two supply voltages received by each first-level AND gate U1 are different. Each supply voltage is provided, for example, to one input of one of the first-level AND gates U1, and the input of the first-level AND gate U1 that does not receive a supply voltage receives a high-level signal (not shown in the figure). Here, n refers to the number of supply voltages VCC required by the processor 200, and i is a positive integer greater than half of n.

[0053] The second logic unit 120 includes a first multiple-input AND gate U2. Each input of the first multiple-input AND gate U2 receives a first intermediate detection signal, and the output of the first multiple-input AND gate U2 outputs a power-on detection signal Vout. The number of inputs of the first multiple-input AND gate U2 is greater than or equal to the number of first intermediate detection signals generated by the first logic unit 110.

[0054] The anode of the LED in the indicator unit 130 receives the power-on detection signal Vout, and the cathode of the LED is grounded.

[0055] Figure 4 A schematic diagram of a power-on detection circuit for another processor provided according to an embodiment of this application is shown.

[0056] See Figure 4 The power-on detection circuit 300 includes a first logic unit 110, a second logic unit 320, and an indicator unit 130. The circuit structures of the first logic unit 110 and the indicator unit 130 are the same as those in the power-on detection circuit 100, and will not be described again here.

[0057] When the first logic unit 110 generates at least three first intermediate detection signals, the second logic unit 320 includes at least two second-stage AND gates U3 and a second multi-input AND gate U4. The first input of each second-stage AND gate U3 receives one of the first intermediate detection signals, the second input of each second-stage AND gate U3 receives another first intermediate detection signal, and the output of each second-stage AND gate U3 outputs a second intermediate detection signal. Each input of the second multi-input AND gate U4 receives one second intermediate detection signal, and the output of the second multi-input AND gate U4 outputs a power-on detection signal Vout. The number of inputs of the second multi-input AND gate U4 is greater than or equal to the number of second intermediate detection signals generated by all the second-stage AND gates U3 in the second logic unit 320. Specifically, the two first intermediate detection signals received by each second-stage AND gate U3 are different. Each first intermediate detection signal is provided, for example, to one input of one of the second-stage AND gates U3, and the input of the second-stage AND gate U3 that does not receive a first intermediate detection signal receives, for example, a high-level signal (not shown in the figure).

[0058] When the first logic unit 110 generates fewer than three first intermediate detection signals, the second logic unit 320 includes a second-stage AND gate U3. The first input of the second-stage AND gate U3 receives one first intermediate detection signal, the second input of the second-stage AND gate receives another first intermediate detection signal or a high-level signal, and the output of the second-stage AND gate outputs a power-on detection signal Vout.

[0059] Figure 5 A schematic diagram of a power-on detection circuit for another processor according to an embodiment of this application is shown.

[0060] See Figure 5 The power-on detection circuit 400 includes a first logic unit 110, a second logic unit 420, and an indicator unit 130. The circuit structures of the first logic unit 110 and the indicator unit 130 are the same as those in the power-on detection circuit 100, and will not be described again here.

[0061] The second logic unit 420 includes multiple two-input AND gates U5. The multiple two-input AND gates U5 are arranged hierarchically according to the number of first intermediate detection signals. Each two-input AND gate U5 in the first layer receives two of the first intermediate detection signals and generates one second intermediate detection signal. The number of two-input AND gates U5 in each subsequent layer is determined by the number of intermediate detection signals generated in the previous layer. The last layer includes only one two-input AND gate U5, whose output intermediate detection signal serves as the power-on detection signal Vout. Further, the number of two-input AND gates U5 in each layer is a positive integer greater than half the number of intermediate detection signals generated in the previous layer. Further, the two intermediate detection signals received by each two-input AND gate U5 are different; each intermediate detection signal is, for example, provided to one input of one of the two-input AND gates U5, and the input of the two-input AND gate U5 that does not receive an intermediate detection signal receives, for example, a high-level signal (not shown in the figure).

[0062] It should be noted that the power-on detection circuit provided in this application performs at least two levels of logic operations on the power supply voltage required by the processor before outputting a power-on detection signal. Based on the power-on detection signal, it sets or resets the processor's reset pin and indicates the processor's power-on status. By using a simple logic circuit to detect the processor's power-on, the circuit complexity and debugging complexity are reduced. Furthermore, the processor's operating state can be determined by judging the state of the indicator unit in the power-on detection circuit, saving the tedious steps of testing and timing verification of the processor's required power supply voltage.

[0063] It should be noted that the numerical values ​​in this article are for illustrative purposes only. In other embodiments of this application, other numerical values ​​may be sampled to implement this solution. The specific values ​​should be reasonably set according to the actual situation, and this application does not limit them.

[0064] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this application and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

[0065] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A power-on detection circuit for use in a processor, wherein, include: The first logic unit receives multiple power supply voltages and generates a first intermediate detection signal based on every two power supply voltages, and the first logic unit generates at least two first intermediate detection signals. The second logic unit performs logical operations on the at least two first intermediate detection signals to generate a power-on detection signal. The power-on detection signal is provided to the processor's reset terminal, which is then set or reset according to the power-on detection signal. The power-on detection circuit performs at least two levels of logic operations on the multiple power supply voltages and then outputs the power-on detection signal. The first logic unit includes: a plurality of first-stage AND gates, wherein the first input terminal of each first-stage AND gate directly receives one of the multiple power supply voltages, the second input terminal of each first-stage AND gate directly receives another of the multiple power supply voltages, and the output terminal of each first-stage AND gate outputs a first intermediate detection signal. The second logic unit includes multiple two-input AND gates, configured hierarchically according to the number of first intermediate detection signals. Each two-input AND gate in the first layer receives two of the first intermediate detection signals and generates a second intermediate detection signal. The number of two-input AND gates in each subsequent layer is determined according to the number of intermediate detection signals generated in the previous layer. The intermediate detection signal output by the layer including one of the two-input AND gates is used as the power-on detection signal.

2. The circuit according to claim 1, wherein, When all the power supply voltages are fully powered on, the processor's reset terminal is set according to the power-on detection signal; when at least one power supply voltage is not fully powered on, the processor's reset terminal is reset according to the power-on detection signal.

3. The circuit according to claim 1, wherein, Also includes: An indicator unit, connected to the second logic unit, characterizes the detection result based on the power-on detection signal, wherein the indicator unit indicates whether the power-on was successful or failed based on the power-on detection signal.

4. The circuit according to claim 3, wherein, The indicator unit includes an LED or a buzzer.

5. The circuit according to claim 1, wherein, The second logic unit is replaced with: A first multi-input AND gate, each input terminal receiving one of the first intermediate detection signals, and an output terminal outputting the power-on detection signal, wherein the number of input terminals of the first multi-input AND gate is greater than or equal to the number of the first intermediate detection signals.

6. The circuit according to claim 1, wherein, When the number of first intermediate detection signals generated by the first logic unit is less than three, the second logic unit is replaced with one including: A second-stage AND gate is used, with its first input receiving a first intermediate detection signal and its second input receiving another first intermediate detection signal. The output of the second-stage AND gate outputs the power-on detection signal. When the first logic unit generates at least three first intermediate detection signals, the second logic unit is replaced with: At least two second-stage AND gates, each second-stage AND gate's first input receives one of the first intermediate detection signals, each second-stage AND gate's second input receives the other of the first intermediate detection signals, and each second-stage AND gate's output outputs a second intermediate detection signal; And a second multiple-input AND gate, each input of the second multiple-input AND gate receiving a second intermediate detection signal, and the output outputting the power-on detection signal, wherein the number of inputs of the second multiple-input AND gate is greater than or equal to the number of the second intermediate detection signals.

7. The circuit according to any one of claims 1-6, wherein, The input of the AND gate that has not received the power supply voltage or the intermediate detection signal receives a high-level signal.

8. An electronic device, wherein, include: Power-on detection circuit, including: A first logic unit receives multiple power supply voltages and generates a first intermediate detection signal based on every two power supply voltages, and the first logic unit generates at least two first intermediate detection signals; a second logic unit performs logical operations on the at least two first intermediate detection signals to generate a power-on detection signal; and The processor includes a reset terminal, which receives the power-on detection signal. When all the multiple power supply voltages are fully powered on, the processor's reset terminal is set according to the power-on detection signal; when at least one power supply voltage is not fully powered on, the processor's reset terminal is reset according to the power-on detection signal. The power-on detection circuit performs at least two levels of logic operations on the multiple power supply voltages and then outputs the power-on detection signal. The first logic unit includes: a plurality of first-stage AND gates, wherein the first input terminal of each first-stage AND gate directly receives one of the multiple power supply voltages, the second input terminal of each first-stage AND gate directly receives another of the multiple power supply voltages, and the output terminal of each first-stage AND gate outputs a first intermediate detection signal. The second logic unit includes multiple two-input AND gates, configured hierarchically according to the number of first intermediate detection signals. Each two-input AND gate in the first layer receives two of the first intermediate detection signals and generates a second intermediate detection signal. The number of two-input AND gates in each subsequent layer is determined according to the number of intermediate detection signals generated in the previous layer. The intermediate detection signal output by the layer including one of the two-input AND gates is used as the power-on detection signal.

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