Storage device and method of operating the same

Abstract

A storage device and an operating method thereof are disclosed. The storage device can reduce a leakage current. The storage device includes a plurality of power switching units for controlling supply of power to a memory device and a memory controller that controls the memory device, a power management circuit for providing a power voltage corresponding to the power to the plurality of power switching units, and a power management circuit controller for controlling the power management circuit to determine a size of the power voltage according to whether the plurality of power switching units supply the power to the memory device and the memory controller.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0121731, filed on September 13, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to an electronic device, and more specifically, to a storage device and a method of operating the same. Background Technology

[0004] A storage device is a means of storing data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are memory devices that store data only when power is supplied and lose the stored data when the power supply is interrupted. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices are memory devices whose data is not lost even when the power supply is interrupted. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the Invention

[0007] Embodiments of this disclosure provide a storage device capable of reducing leakage current and a method of operating the storage device.

[0008] According to one aspect of this disclosure, a storage device is provided, comprising: a plurality of power switch cells configured to control the supply of power to a memory device and a memory controller for controlling the memory device; a power management circuit configured to provide a power voltage corresponding to the power to the plurality of power switch cells; and a power management circuit controller configured to control the power management circuit to determine the magnitude of the power voltage based on whether the plurality of power switch cells supply power to the memory device and the memory controller.

[0009] According to another aspect of this disclosure, a method for operating a storage device is provided, the method comprising: determining whether to supply power to the storage device and a storage controller via a plurality of power switching units; changing the magnitude of a power voltage corresponding to the power supply based on the determination result; and supplying a power voltage having the changed magnitude to the plurality of power switching units.

[0010] According to one aspect of this disclosure, a power supply circuit is provided, comprising: a power circuit configured to supply power to components in a first mode and to cut off power in a second mode; and a charging circuit configured to supply a first charging voltage to the power circuit in the first mode and to supply a second charging voltage to the power circuit in the second mode, wherein the second charging voltage is lower than the first charging voltage and has a minimum size required for normal operation of a power switching unit in the power circuit. Attached Figure Description

[0011] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings; however, embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the embodiments to those skilled in the art.

[0012] In the accompanying drawings, dimensions may be enlarged for clarity. It will be understood that when an element is referred to as being "between" two elements, that element can be the only element between the two elements, or there may be one or more intermediate elements. Furthermore, throughout the specification, the same reference numerals refer to the same elements.

[0013] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0014] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of the memory device shown.

[0015] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram showing the structure of one of the storage blocks shown.

[0016] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 1 The diagram shows a memory controller.

[0017] Figure 5 This illustrates an embodiment according to the present disclosure. Figure 1The diagram shows a power management circuit.

[0018] Figure 6A This is a diagram illustrating an example of a power controller according to an embodiment of the present disclosure.

[0019] Figure 6B This is a diagram illustrating another example of a power controller according to an embodiment of the present disclosure.

[0020] Figure 7 This is a diagram illustrating a first operating area and a second operating area according to an embodiment of the present disclosure.

[0021] Figure 8 This is a diagram illustrating an example of the operation of determining the magnitude of the electrical voltage according to an embodiment of the present disclosure.

[0022] Figure 9 This is a diagram illustrating another example of the operation of determining the magnitude of the electrical voltage according to an embodiment of the present disclosure.

[0023] Figure 10 This is a diagram illustrating a method of operating a storage device according to an embodiment of the present disclosure.

[0024] Figure 11 This is a block diagram illustrating a memory card system for an application storage device according to an embodiment of the present disclosure.

[0025] Figure 12 This is a block diagram illustrating a solid-state drive (SSD) system for an application storage device according to an embodiment of the present disclosure.

[0026] Figure 13 This is a block diagram illustrating a user system of an application storage device according to an embodiment of the present disclosure. Detailed Implementation

[0027] The specific structural or functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0028] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0029] Reference Figure 1The storage device 50 may include a memory device 100 and a memory controller 200 for controlling the operation of the memory device 100. The storage device 50 may be a device for storing data under the control of a host 400 such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television, tablet PC, or in-vehicle infotainment system.

[0030] Depending on the host interface, which serves as the communication scheme with host 400, storage device 50 can be manufactured as any of various types of storage devices. For example, storage device 50 can be implemented using any of the following types of storage devices: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), size-reduced MMC (RS-MMC), micro MMC (micro-MMC), secure digital card (SD), mini SD card, micro SD card, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash memory (CF) card, smart media card (SMC), memory stick, etc.

[0031] The storage device 50 can be manufactured in any of a variety of package types. For example, the storage device 50 can be manufactured in any of the following package types: POP (Package-on-Package), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP).

[0032] The memory device 100 can store data. The memory device 100 can operate under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown), which includes a plurality of memory cells for storing data.

[0033] Each memory cell can be configured as any of the following: a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, and a four-level cell (QLC) storing four data bits.

[0034] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0035] In embodiments, the memory device 100 may be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), a fourth-generation low-power Double Data Rate (LPDDR4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, low-power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. In this specification, for ease of description, the case where the memory device 100 is a NAND flash memory is described.

[0036] Memory device 100 can receive a command CMD and an address ADDR from memory controller 200, and access the region in the memory cell array selected by the address ADDR. Memory device 100 can perform the operation indicated by command CMD on the region selected by address ADDR. For example, memory device 100 can perform a write operation (programming operation), a read operation, and an erase operation. In a programming operation, memory device 100 can program data into the region selected by address ADDR. In a read operation, memory device 100 can read data from the region selected by address ADDR. In an erase operation, memory device 100 can erase the data stored in the region selected by address ADDR.

[0037] exist Figure 1 The image shows a configuration with a single memory device 100. However, in some embodiments, the memory device 50 may include multiple memory devices. (Refer to...) Figure 2 Describe the connection relationships between multiple memory devices and memory controller 200.

[0038] The memory controller 200 can control all operations of the storage device 50.

[0039] When power is applied to storage device 50, memory controller 200 can run firmware (FW). When storage device 100 is a flash memory device, FW may include a host interface layer (HIL) for controlling communication with host 400, a flash translation layer (FTL) for controlling communication between host and storage device 100, and a flash interface layer (FIL) for controlling communication with storage device 100.

[0040] In this embodiment, the memory controller 200 can receive data and logical block addresses (LBAs) from the host 400 and convert the LBAs into physical block addresses (PBAs), where the PBA represents the address of a memory cell in the memory device 100 containing data to be stored. In this specification, LBA and "logic address" or "logical address" can be used with the same meaning. Similarly, PBA and "physical address" can be used with the same meaning.

[0041] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, erase operations, etc., in response to requests from the host 400. During a programming operation, the memory controller 200 can provide programming commands, PBAs, and data to the memory device 100. During a read operation, the memory controller 200 can provide read commands and PBAs to the memory device 100. During an erase operation, the memory controller 200 can provide erase commands and PBAs to the memory device 100.

[0042] In this embodiment, the memory controller 200 can be connected to the memory device 100 via a channel. For example, the memory controller 200 can provide commands and addresses to the memory device 100 via the channel to control the memory device 100 to perform programming operations, read operations, erase operations, etc.

[0043] In this embodiment, the memory controller 200 can autonomously generate commands, addresses, and data regardless of any requests from the host 400, and transmit these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 for performing read operations and programming operations involved in performing operations such as wear leveling, read recycling, and garbage collection.

[0044] In this embodiment, the memory controller 200 can control at least two memory devices 100. The memory controller 200 can control the memory devices according to an interleaving scheme, thereby improving operational performance. The interleaving scheme can be a scheme for controlling the overlapping of operations on at least two memory devices 100.

[0045] In one embodiment, the memory controller 200 may include a power management circuit controller 210.

[0046] The power management circuit controller 210 can control the operation of the power management circuit 300.

[0047] The power management circuit 300 can provide voltage to the memory device 100 and the memory controller 200. In embodiments, the power management circuit 300 can provide voltages with various levels required depending on the type of memory device 50. The voltage provided by the power management circuit 300 to the memory device 100 and the memory controller 200 can be the power voltage of the memory device 100 and the memory controller 200. The power management circuit 300 can be supplied with external power.

[0048] In this embodiment, the power management circuit 300 may include an auxiliary power device. The power management circuit 300 can charge the auxiliary power device using supplied external power. The power management circuit 300 can provide either external power or auxiliary power included in the auxiliary power device to the memory device 100 and the memory controller 200.

[0049] There may be situations where the voltage level of the external power supplied to the storage device falls below a certain voltage level. For example, a sudden power outage (SPO) may occur, causing a sudden interruption of external power. Even during a power outage, the memory device 100 and memory controller 200 included in storage device 50 can still perform various operations that should be performed. For example, even during a power outage, memory controller 200 should move data from the write cache buffer included in storage device 50 to memory device 100. In another example, even during a power outage, a mapping update operation that stores mapped data indicating the relationship between logical addresses and physical addresses in the memory device should be completed. When a power outage occurs, storage device 50 can provide auxiliary power to memory device 100 and memory controller 200 for a period of time to complete operations that should be performed even during a power outage.

[0050] The host 400 can communicate with the storage device 50 using at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduction DIMM (LRDIMM).

[0051] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of the memory device shown.

[0052] Reference Figure 2 The memory device 100 may include a memory cell array 110, a voltage generator 120, an address decoder 130, an input / output circuit 140, and control logic 150.

[0053] The memory cell array 110 may include multiple memory blocks BLK1 to BLKi. The multiple memory blocks BLK1 to BLKi can be connected to the address decoder 130 via row lines RL. The multiple memory blocks BLK1 to BLKi can be connected to the input / output circuitry 140 via column lines CL. In an embodiment, the row lines RL may include word lines, source select lines, and drain select lines. In an embodiment, the column lines CL may include bit lines.

[0054] Each of the plurality of memory blocks BLK1 to BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the plurality of memory cells may be defined as a physical page. That is, the memory cell array 110 may include a plurality of physical pages. Each of the memory cells in the memory device 100 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0055] In this embodiment, the voltage generator 120, address decoder 130, and input / output circuitry 140 can be collectively referred to as peripheral circuitry. The peripheral circuitry can drive the memory cell array 110 under the control of control logic 150. The peripheral circuitry can drive the memory cell array 110 to perform programming, reading, and erasing operations.

[0056] Voltage generator 120 can generate multiple operating voltages using external power voltage supplied to memory device 100. Voltage generator 120 can operate under the control of control logic 150.

[0057] In this embodiment, the voltage generator 120 can generate an internal power voltage by adjusting an external power voltage. The internal power voltage generated by the voltage generator 120 can be used as the operating voltage of the memory device 100.

[0058] In this embodiment, voltage generator 120 can generate multiple operating voltages using either external or internal power voltages. Voltage generator 120 can generate various voltages required in the memory device 100. For example, voltage generator 120 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0059] To generate multiple operating voltages with various voltage levels, voltage generator 120 may include multiple pump capacitors that receive internal power voltages. Voltage generator 120 can generate multiple operating voltages by selectively activating the multiple pump capacitors under the control of control logic 150.

[0060] Multiple operating voltages generated by voltage generator 120 can be supplied to memory cell array 110 via address decoder 130.

[0061] Address decoder 130 can be connected to memory cell array 110 via row line RL. Address decoder 130 operates under the control of control logic 150. Address decoder 130 can receive address ADDR from control logic 150. Address decoder 130 can decode the block address in the received address ADDR. Address decoder 130 can select at least one memory block from BLK1 to BLKi based on the decoded block address. Address decoder 130 can decode the row address in the received address ADDR. Address decoder 130 can select at least one word line from the word lines of the selected memory block based on the decoded row address. In an embodiment, address decoder 130 can decode the column address in the received address ADDR. Address decoder 130 can connect input / output circuit 140 and memory cell array 110 to each other based on the decoded column address.

[0062] According to embodiments of this disclosure, during a read operation, the address decoder 130 can apply a read voltage to a selected word line and apply a read pass voltage with a level higher than the read voltage to an unselected word line.

[0063] Address decoder 130 may include components such as row decoder, column decoder, and address buffer.

[0064] Input / output circuitry 140 may include multiple page buffers. These page buffers can be connected to memory cell array 110 via bit lines. During programming operations, data stored in the multiple page buffers can be provided to a selected physical page via the bit lines, and the provided data can be stored in the memory cells included in the selected physical page. During read operations, data stored in the memory cells included in the selected physical page can be sensed via the bit lines, and the sensed data can be stored in the page buffer.

[0065] Control logic 150 can control address decoder 130, voltage generator 120, and input / output circuitry 140. Control logic 150 can operate in response to a command CMD transmitted from an external device. Control logic 150 can control peripheral circuitry by generating control signals in response to the command CMD and address ADDR.

[0066] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram showing the structure of one of the storage blocks shown.

[0067] Storage block BLKi representation Figure 2 The storage block BLKi is shown among storage blocks BLK1 to BLKi.

[0068] Reference Figure 3 In a memory block BLKi, multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, a memory block BLKi can include multiple string STs connected between bit lines BL1 to BLm and the source line SL. Bit lines BL1 to BLm can be connected to string STs individually, and the source line SL can be connected to string STs collectively. String STs can be configured identically to each other; therefore, a string ST connected to the first bit line BL1 will be described in detail as an example.

[0069] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A string ST may include at least one drain selection transistor DST, and the number of source selection transistors included in a string ST may be greater than the number of source selection transistors SST shown in the figure, and the number of memory cells included in a string ST may be greater than the number of memory cells MC1 to MC16 shown in the figure.

[0070] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistors SST and the drain select transistors DST. The gates of the source select transistors SST included in different strings of ST can be connected to the source select line SSL, and the gates of the drain select transistors DST included in different strings of ST can be connected to the drain select line DSL. The gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells in different strings of ST connected to the same word line can be referred to as a physical page PG. Therefore, the memory block BLKi can include physical pages PG corresponding to the number of word lines WL1 to WL16.

[0071] A memory cell can store one bit of data. This memory cell is usually called a single-level cell (SLC). A physical page (PG) can store one logical page (LPG) of data. The data in an LPG can include data bits corresponding to the number of cells included in a physical page (PG).

[0072] A memory cell can store two or more bits of data. A physical page (PG) can store the data of two or more physical pages (LPGs).

[0073] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 1 The diagram shows a memory controller.

[0074] Reference Figure 1 and Figure 4 The memory controller 200 may include a power management circuit controller 210, a processor 220, RAM 230, an error correction circuit 240, ROM 250, a host interface 260, and a flash memory interface 270.

[0075] The power management circuit controller 210 can control the operation of the power management circuit 300.

[0076] In this embodiment, the power management circuit controller 210 can determine the magnitude of the power voltage supplied from the power management circuit 300. For example, the power management circuit controller 210 can determine the magnitude of the power voltage supplied to the multiple power switching units based on whether the multiple power switching units will supply power to the memory device 100 and the memory controller 200. The power switching units can be modules that control the supply of power to the memory device 100 and the memory controller 200. For example, the power switching units can supply power to the memory device 100 and the memory controller 200 or interrupt the supply of power to the memory device 100 and the memory controller 200 based on the operating mode of the memory device 50. When the operating mode is a normal mode, the multiple power switching units can supply power to the memory device 100 and the memory controller 200. The normal mode can be a mode in which the memory device 50 performs normal operation. When the operating mode is a power-saving mode, the multiple power switching units can interrupt the supply of power to the memory device 100 and the memory controller 200. The power-saving mode can represent various operating modes used to minimize power consumption, such as sleep mode, standby mode, or power-off mode.

[0077] Leakage current may occur due to the miniaturization process of the transistors included in the memory device 100 and the memory controller 200. Power switching units control the power supply, thereby reducing leakage current. However, leakage current may still occur even within the power switching units. Therefore, according to embodiments of this disclosure, the magnitude of the power voltage supplied to the plurality of power switching units is determined based on whether power will be supplied. Thus, leakage current can be reduced, and power efficiency can be improved.

[0078] The processor 220 can control all operations of the memory controller 200. The RAM 230 can be used as a buffer memory, cache memory, working memory, etc. of the memory controller 200.

[0079] Error correction circuit 240 can perform error correction. Error correction circuit 240 can perform error correction code (ECC) encoding on data to be written to the memory device via flash interface 270. ECC-encoded data can be transmitted to the memory device via flash interface 270. Error correction circuit 240 can perform ECC decoding on data received from the memory device via flash interface 270. Error correction circuit 240 can be included as a component of flash interface 270.

[0080] ROM 250 can store various information required for the operation of memory controller 200 in the form of firmware.

[0081] The memory controller 200 can communicate with external devices (e.g., host 400, application processor, etc.) via host interface 260.

[0082] The memory controller 200 can communicate with the memory device 100 via the flash memory interface 270. The memory controller 200 can transmit commands, addresses, control signals, etc., to the memory device 100 and receive data DATA via the flash memory interface 270. The flash memory interface 270 may include a NAND interface.

[0083] In the above embodiments, it has been described that the power management circuit controller 210 is one of the components of the memory controller 200. However, this disclosure is not limited thereto. In some embodiments, the power management circuit controller 210 may be implemented as a component of the processor 220 or as firmware stored in the ROM 250.

[0084] Figure 5 This illustrates an embodiment according to the present disclosure. Figure 1 The diagram shows a power management circuit.

[0085] Reference Figure 5 The power management circuit 300 may include a power controller 310 and an auxiliary power device 320.

[0086] The power controller 310 can select one of external power and auxiliary power and supply the selected power to the memory device 100 and the memory controller 200.

[0087] The power controller 310 can receive external power input from the host 400. The power controller 310 can provide a charging voltage to the auxiliary power device 320. The auxiliary power device 320 can charge its included auxiliary power units using the charging voltage. The power controller 310 can provide external power to the memory device 100 and the memory controller 200. Furthermore, the power controller 310 can provide a charging voltage to the auxiliary power device 320 using external power. When no external power is input or the voltage level of the external power is below a certain voltage level, the power management circuit 300 may not receive external power. In this case, the power controller 310 can provide auxiliary power to the memory device 100 and the memory controller 200 using the voltage charged in the auxiliary power device 320. The auxiliary power can be provided by the auxiliary power units included in the auxiliary power device 320. Therefore, the amount of auxiliary power may be limited.

[0088] External power input to the power management circuit 300 can be supplied to the memory device 100 and the memory controller 200. Optionally, when the voltage level of the external power is lower than a certain voltage level, auxiliary power stored in the power management circuit can be supplied to the memory device 100 and the memory controller 200 for a certain period of time.

[0089] In this embodiment, the power management circuit controller 210 can control the power management circuit 300 to determine the power voltage based on whether the plurality of power switching units will supply power to the memory device 100 and the memory controller 200. The plurality of power switching units can supply power to the memory device 100 and the memory controller 200 or interrupt the power supply based on the operating mode of the memory device 50. The power controller 310 can receive power management circuit control signals from the power management circuit controller 210. These control signals can control the power controller 310 to change the power voltage supplied to the plurality of power switching units.

[0090] For example, when multiple power switching units supply power to the memory device 100 and the memory controller 200, the power management circuit controller 210 can control the power controller 310 to provide a first power voltage to the multiple power switching units. The first power voltage can be the voltage at which the memory device 100 and the memory controller 200 operate.

[0091] In another example, when multiple power switching units interrupt the supply of power to the memory device 100 and the memory controller 200, the power management circuit controller 210 can control the power controller 310 to provide a second power voltage to the multiple power switching units. The second power voltage can be a voltage lower than the first power voltage. In an embodiment, the second power voltage can be the smallest voltage among the voltages at which the multiple power switching units can operate normally. That is, the second power voltage can be the voltage with the lowest level at which the multiple power switching units can operate normally. For example, the second power voltage can be set by taking into account the characteristics of the transistors constituting the multiple power switching units, changes in the processing stages of the multiple power switching units, etc.

[0092] Figure 6A This is a diagram illustrating an example of a power controller according to an embodiment of the present disclosure.

[0093] Reference Figure 6A The power controller 310 can generate a power voltage suitable for the memory device 100 and the memory controller 200 based on external power or auxiliary power.

[0094] The power controller 310 may include a voltage regulator (e.g., a low dropout output (LDO) regulator) 311. The power controller 310 may change the magnitude of the power voltage via the LDO regulator 311. The LDO regulator 311 may be a linear regulator that operates even at low input / output potential differences. The LDO regulator 311 may reduce the output voltage relative to the input voltage.

[0095] In this embodiment, the LDO regulator 311 can receive external or auxiliary power and generate a power voltage with a level available in the memory device 100 and the memory controller 200.

[0096] In this embodiment, when multiple power switching units supply power to the memory device 100 and the memory controller 200, the LDO regulator 311 can generate a first power voltage under the control of the power management circuit controller 210. Furthermore, when the multiple power switching units interrupt the supply of power to the memory device 100 and the memory controller 200, the LDO regulator 311 can generate a second power voltage under the control of the power management circuit controller 210.

[0097] Figure 6B This is a diagram illustrating another example of a power controller according to an embodiment of the present disclosure.

[0098] Reference Figure 6B The power controller 310 may include a buck converter 312. The buck converter 312 is a step-down converter that reduces the output voltage using the input voltage. The power controller 310 can change the magnitude of the power voltage.

[0099] In an embodiment, the buck converter 312 can receive external power or auxiliary power and generate a power voltage with a level available in the memory device 100 and the memory controller 200.

[0100] In this embodiment, when multiple power switching units supply power to the memory device 100 and the memory controller 200, the buck converter 312 can generate a first power voltage under the control of the power management circuit controller 210. Furthermore, when the multiple power switching units interrupt the supply of power to the memory device 100 and the memory controller 200, the buck converter 312 can generate a second power voltage under the control of the power management circuit controller 210.

[0101] Figure 7 This is a diagram illustrating a first operating area and a second operating area according to an embodiment of the present disclosure.

[0102] Reference Figure 7 The memory device 100 and the memory controller 200 may include a first operating area AREA1 and a second operating area AREA2.

[0103] In this embodiment, the first operating area AREA1 may include a plurality of first operating modules 701-1 to 701-n. Power can be supplied to the first operating area AREA1 regardless of the operating mode of the storage device 50.

[0104] The multiple first operation modules 701-1 to 701-n can be modules that are supplied with power regardless of the operating mode. For example, the multiple first operation modules 701-1 to 701-n can be modules included in the power management circuit controller 210, processor 220, host interface 260, flash memory interface 270, etc. of the memory controller 200. The power management circuit controller 210, processor 220, etc. can always operate regardless of the operating mode, thereby controlling the operation of the storage device 50. Since interface devices such as the host interface 260 and flash memory interface 270 receive information from the host 400 or the storage device 100, the interface devices can always operate regardless of the operating mode.

[0105] In this embodiment, the power controller 310 can provide power voltage to a plurality of first operation modules 701-1 to 701-n.

[0106] The second operating area AREA2 may include multiple second operating modules 702-1 to 702-n and multiple power switching units 703-1 to 703-n. Depending on the operating mode of the storage device 50, power can be supplied to the second operating area AREA2 or the supply of power to the second operating area AREA2 can be interrupted.

[0107] Depending on the operating mode, power can be supplied to or interrupted to the multiple second operating modules 702-1 to 702-n. For example, the multiple second operating modules 702-1 to 702-n may be modules included in the error correction circuit 240 of the memory controller 200, the memory device 100, etc.

[0108] Multiple power switching units 703-1 to 703-n can control the supply of power to multiple second operating modules 702-1 to 702-n. Figure 7 In this embodiment, one power switch unit is connected to one second operating module. However, in some embodiments, one power switch unit may be connected to multiple second operating modules.

[0109] In this embodiment, the power controller 310 can provide power voltage to a plurality of power switching units 703-1 to 703-n. The plurality of power switching units 703-1 to 703-n can supply power to a plurality of second operation modules 702-1 to 702-n based on the power voltage control. The plurality of power switching units 703-1 to 703-n can be turned on / off according to the operating mode of the storage device 50. For example, when the operating mode is normal mode, the power switching units 703-1 to 703-n can be turned on. The plurality of power switching units 703-1 to 703-n can supply power to the plurality of second operation modules 702-1 to 702-n. In another example, when the operating mode is power-saving mode, the power switching units 703-1 to 703-n can be turned off. The plurality of power switching units 703-1 to 703-n can interrupt the supply of power to the plurality of second operation modules 702-1 to 702-n.

[0110] The first and second operation modules described above are merely examples. In some embodiments, the modules corresponding to the first and second operation modules may be configured differently.

[0111] Figure 8 This is a diagram illustrating an example of the operation of determining the magnitude of the electrical voltage according to an embodiment of the present disclosure.

[0112] Reference Figure 8 When the operating mode is normal, power switch units 703-1 to 703-n can be turned on. Power management circuit controller 210 can provide power management circuit control signals to power controller 310 for providing a first power voltage. Power controller 310 can provide the first power voltage to multiple power switch units 703-1 to 703-n according to the power management circuit control signals. Multiple power switch units 703-1 to 703-n can supply power to multiple second operating modules 702-1 to 702-n based on the first power voltage.

[0113] Figure 9 This is a diagram illustrating another example of the operation of determining the magnitude of the electrical voltage according to an embodiment of the present disclosure.

[0114] Reference Figure 9 When the operating mode is power-saving mode, power switch units 703-1 to 703-n can be turned off. Multiple power switch units 703-1 to 703-n can interrupt the power supply to multiple second operating modules 702-1 to 702-n. Power management circuit controller 210 can provide power management circuit control signals to power controller 310 for providing a second power voltage. Power controller 310 can provide a second power voltage to multiple power switch units 703-1 to 703-n according to the power management circuit control signals.

[0115] Therefore, according to embodiments of this disclosure, a minimum power voltage is provided required for the operation of a plurality of power switching units 703-1 to 703-n in the off state. This reduces leakage current and improves power efficiency.

[0116] Figure 10 This is a diagram illustrating a method of operating a storage device according to an embodiment of the present disclosure.

[0117] Figure 10 The operation method shown can be performed by Figure 1 The storage device 50 shown is executed.

[0118] Reference Figure 10 During operation S1001, external power can be supplied from the host 400 to the storage device 50.

[0119] In operation S1003, the storage device 50 can determine whether to supply power to the memory device 100 and the memory controller 200 through multiple power switching units. The storage device 50 can change the magnitude of the voltage supplied to the multiple power switching units based on whether power will be supplied. In an embodiment, the storage device 50 can change the magnitude of the power voltage using at least one of an LDO regulator and a buck converter. Subsequently, the storage device 50 can supply the modified power voltage to the multiple power switching units.

[0120] For example, when the operating mode of the storage device 50 is normal mode, the storage device 50 can supply power to the memory device 100 and the memory controller 200. The storage device 50 can change the power voltage to a first power voltage. In operation S1005, the storage device 50 can provide the first power voltage to multiple power switching units.

[0121] Optionally, when the operating mode is power-saving mode, the storage device 50 can interrupt the power supply to the memory device 100 and the memory controller 200. The storage device 50 can change the power voltage to a second power voltage. In operation S1007, the storage device 50 can provide the second power voltage to multiple power switching units.

[0122] Figure 11 This is a block diagram illustrating a memory card system for an application storage device according to an embodiment of the present disclosure.

[0123] Reference Figure 11 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0124] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 can access memory device 2200. For example, memory controller 2100 can control read operations, write operations, erase operations, and background operations of memory device 2200. Memory controller 2100 provides an interface between memory device 2200 and the host computer. Memory controller 2100 drives firmware for controlling memory device 2200. Memory controller 2100 can be used with reference to... Figure 1 The memory controller 200 described is implemented identically. The memory device 2200 can be implemented with reference to... Figure 1 The memory device 100 described is implemented in the same manner.

[0125] The memory controller 2100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and ECC circuitry.

[0126] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to a specific communication protocol. The memory controller 2100 can communicate with external devices via at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. Connector 2300 can be defined using at least one of the aforementioned communication standards or interfaces.

[0127] The memory device 2200 can be implemented using various non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0128] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and memory device 2200 can form memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory (CF) cards, smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC and eMMC), SD cards (SD, mini SD, micro SD and SDHC) and universal flash memory (UFS).

[0129] Figure 12 This is a block diagram illustrating a solid-state drive (SSD) system for an application storage device according to an embodiment of the present disclosure.

[0130] Reference Figure 12 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0131] In this embodiment, the SSD controller 3210 can be used as a reference. Figure 1 The memory controller 200 is described.

[0132] SSD controller 3210 can control multiple flash storage devices 3221 to 322n in response to signals received from host 3100. The signals can be based on the interface between host 3100 and SSD 3200. For example, the signals can be signals defined by at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (MCM), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0133] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can receive power PWR from host 3100 and use the power PWR for charging. When the power supply from host 3100 is unstable, auxiliary power supply 3230 can provide power to SSD 3200. Auxiliary power supply 3230 can be located inside SSD 3200 or externally to SSD 3200. For example, auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to SSD 3200. Auxiliary power supply 3230 can be connected to reference... Figure 5 The auxiliary power unit 320 described is implemented in the same manner.

[0134] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or from multiple flash memories 3221 to 322n, or temporarily store metadata (e.g., mapping tables) of flash memories 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0135] Figure 13 This is a block diagram illustrating a user system of an application storage device according to an embodiment of the present disclosure.

[0136] Reference Figure 13 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0137] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. Application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 can be configured as a system-on-a-chip (SoC).

[0138] The memory module 4200 can operate as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. The application processor 4100 and the memory module 4200 can be packaged in a single semiconductor package using a stacked package (PoP) approach.

[0139] Network module 4300 can communicate with external devices. Network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. Network module 4300 can be included in application processor 4100.

[0140] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Optionally, storage module 4400 can transfer the data stored therein to application processor 4100. Storage module 4400 can be implemented using non-volatile semiconductor memory devices such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional structure. Storage module 4400 can be configured as a removable drive, such as a memory card of user system 4000 or an external drive.

[0141] The storage module 4400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be used in conjunction with a reference. Figure 1 The memory device 100 described operates in the same manner. The memory module 4400 can be compared with the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0142] User interface 4500 may include interfaces for inputting data or commands to application processor 4100 or outputting data to external devices. User interface 4500 may include user input interfaces such as keyboards, keypads, buttons, touch panels, touchscreens, touchpads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements. User interface 4500 may include user output interfaces such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) display devices, active-matrix OLED (AMOLED) display devices, LEDs, speakers, and monitors.

[0143] According to this disclosure, a storage device capable of reducing leakage current and a method of operating the storage device are provided.

[0144] While this disclosure has been shown and described with reference to certain embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0145] In the above embodiments, all operations may be selectively performed, or a portion of the operations may be omitted. In each embodiment, the operations need not be performed in the described order and may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to aid in understanding this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0146] Furthermore, embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, it is only for describing embodiments of this disclosure. Therefore, this disclosure should not be limited to the embodiments described above, but many variations can be made within the spirit and scope of this disclosure. Those skilled in the art will understand that various modifications can be made beyond the embodiments disclosed herein and the claims, based on the technical scope of this disclosure. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A storage device, comprising: Multiple power switching units control the power supply to the memory device and the memory controller, wherein the memory controller controls the memory device; A power management circuit provides a power voltage corresponding to the power supply to the plurality of power switching units; as well as The power management circuit controller controls the power management circuit to determine the magnitude of the power voltage based on whether the plurality of power switching units supply power to the memory device and the memory controller. The power management circuit controller responds to an interrupt by supplying power to the memory device and the memory controller, and controls the power management circuit to reduce the magnitude of the power voltage.

2. The storage device according to claim 1, wherein the plurality of power switching units supply power to the storage device and the storage controller or interrupt the supply of power to the storage device and the storage controller according to the operating mode of the storage device.

3. The storage device according to claim 2, wherein when the operating mode is a normal mode, the plurality of power switching units supply power to the storage device and the storage controller.

4. The storage device according to claim 2, wherein when the operating mode is a power-saving mode, the plurality of power switching units interrupt the supply of power to the storage device and the storage controller.

5. The storage device of claim 1, wherein when the plurality of power switching units supply power to the memory device and the memory controller, the power management circuit controller controls the power management circuit to provide a first power voltage to the plurality of power switching units, and the memory device and the memory controller operate under the first power voltage.

6. The storage device of claim 5, wherein when the plurality of power switching units interrupt the supply of power to the storage device and the storage controller, the power management circuit controller controls the power management circuit to provide a second power voltage to the plurality of power switching units, the second power voltage being lower than the first power voltage.

7. The storage device according to claim 6, wherein the second power voltage is the smallest voltage among the voltages at which the plurality of power switching units operate normally.

8. The storage device of claim 1, wherein the power management circuitry includes a power controller that receives external power supplied from a host and generates the power voltage based on the external power.

9. The storage device of claim 8, wherein the power controller includes a low dropout output regulator, i.e., an LDO regulator, and further modifies the magnitude of the power voltage via the LDO regulator.

10. The storage device of claim 8, wherein the power controller includes a buck converter and further changes the magnitude of the power voltage via the buck converter.

11. The storage device of claim 1, wherein the storage device and the storage controller comprise: The first operating area is supplied with power regardless of the operating mode of the storage device; as well as The second operating area is supplied with power or the power supply to the second operating area is interrupted according to the operating mode of the storage device.

12. The storage device of claim 11, wherein the plurality of power switching units are included in the second operating area and control the supply of power to the second operating area.

13. The storage device of claim 1, wherein the power management circuit controller is included in the memory controller.

14. A method of operating a storage device, the method comprising: Determine whether to supply power to the memory device and memory controller through multiple power switching units; The magnitude of the power voltage corresponding to the power is changed according to the determined result; and Provide the plurality of power switching units with a modified power voltage. The change includes reducing the magnitude of the power voltage in response to determining an interruption in supplying power to the memory device and the memory controller.

15. The method of claim 14, wherein the determination comprises: When the operating mode of the storage device is normal mode, it is determined that power is supplied to the storage device and the memory controller.

16. The method of claim 15, wherein the modification further comprises: Before reducing the magnitude of the power voltage, in response to determining that power is to be supplied to the memory device and the memory controller, the power voltage is changed to a first power voltage, under which the memory device and the memory controller operate.

17. The method of claim 14, wherein the determination comprises: When the operating mode of the storage device is power saving mode, an interrupt is determined to supply power to the storage device and the memory controller.

18. The method of claim 17, wherein the reduction comprises: In response to determining that an interruption is supplying power to the memory device and the memory controller, the power voltage is changed to a second power voltage, which is lower than the first power voltage.

19. The method of claim 18, wherein the second power voltage is the smallest voltage among the voltages at which the plurality of power switching units operate normally.

20. A power supply circuit, comprising: A power circuit that supplies power to components in a first mode and cuts off the power in a second mode; as well as The charging circuit provides a charging voltage to the power circuit in the first mode and reduces the magnitude of the charging voltage provided to the power circuit in the second mode.

21. The power supply circuit of claim 20, wherein the charging voltage having a reduced magnitude has the minimum magnitude required for normal operation of the power switching unit in the power circuit.

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