Method for accessing memory and chip, device and electronic equipment

Abstract

The present disclosure relates to a method for accessing a memory, a chip, a device and an electronic equipment, comprising: determining a first number of beats required by an operation process of a sub-operation of a to-be-executed operation according to a type of the sub-operation; determining a storage unit state according to an operand storage location and an operation result storage location of the sub-operation; determining a second number of beats required by a storage unit access process of the sub-operation according to the storage unit state; and accessing the storage unit based on the storage unit state, the first number of beats, the second number of beats and parameters contained in the to-be-executed operation. Through the method of the present disclosure, read and write data can be arranged at the same time in part of the period according to different storage unit states; the efficiency of accessing the memory is maximized, and the speed and efficiency of the operation are improved as a whole, so as to improve the touch accuracy and sensitivity of intelligent products.

Description

Technical Field

[0001] This disclosure relates to the field of touch display technology, and more particularly to a method, chip, device, and electronic device for accessing memory. Background Technology

[0002] Touch and Display Driver Integration (TDDI) is a unified touch and display solution that integrates touch scanning and display driving into the same chip.

[0003] Depending on the needs of the actual application, the TDDI chip can have multiple independent memory cells built in. Each memory cell can be used to store touch data generated by touch and the calculation results obtained by the Arithmetic and Logic Unit (ALU) from the data.

[0004] To enable smart products to have more sensitive and accurate touch responses, the amount of computation per unit time can usually be increased. This requires the ALU to have higher processing speed and higher processing efficiency. Summary of the Invention

[0005] In view of this, this disclosure proposes a scheme for accessing memory. This disclosure helps to improve the computational accuracy of smart products, increase the computational efficiency of the ALU, and produce more accurate touch effects.

[0006] According to one aspect of this disclosure, a method for accessing memory is provided, comprising:

[0007] Determine the number of first ticks required for the operation process of the sub-operation based on the type of the sub-operation to be executed;

[0008] Based on the storage location of the operand and the storage location of the operation result of the sub-operation, the state of the storage unit is determined. The state is used to characterize whether the operand and the operation result share the storage unit.

[0009] Based on the state of the storage unit, determine the number of second ticks required for the sub-operation to access the storage unit;

[0010] The storage unit is accessed based on the storage unit status, the first number of beats, the second number of beats, and the parameters included in the operation to be performed.

[0011] In one possible implementation, the parameter is the number of sub-operations, and accessing the storage unit based on the storage unit state, the first clock cycle count, the second clock cycle count, and the number of sub-operations includes:

[0012] Based on the storage unit status, the first number of beats, and the second number of beats, a third number of beats is determined. The third number of beats represents the time taken during the execution of the operation to be performed without accessing the storage unit used to store the operands, and / or the time taken during the execution of the operation to store the result.

[0013] Based on the state of the storage unit, determine the order of accessing the storage unit when performing the sub-operation;

[0014] After the operation to be executed begins, the storage unit is accessed according to the access order. Starting from the process of reading operands of the first sub-operation of the operation to be executed, no operation to access the storage unit for the purpose of writing the operation result is performed within the time interval corresponding to the number of the third beats. Also, according to the number of sub-operations, starting from the operation process of the last sub-operation of the operation to be executed, no operation to access the storage unit for the purpose of reading operands is performed within the time interval corresponding to the number of the third beats.

[0015] After the operation to be executed begins, and after the duration of the third cycle ends, the operation result is written to the storage unit.

[0016] In one possible implementation, the operands include a first operand and a second operand, and determining the third tick count based on the storage cell state includes:

[0017] When the storage unit is in a state where the operands and the operation result do not share a storage unit, the third cycle count is set to the first cycle count.

[0018] When the storage unit is in a state where any two or more of the first operand, the second operand, and the operation result share a storage unit, the third beat number is increased by the second beat number for each increase of the first beat number, and the initial value of the third beat number is 0.

[0019] In one possible implementation, the operands include a first operand and a second operand, and determining the access order of the memory unit when performing the sub-operation based on the memory unit state includes:

[0020] Based on the state of the storage unit, determine the first delay cycle number of reading the second operand relative to reading the first operand;

[0021] The access order of the storage units is determined based on the first delay tick number.

[0022] In one possible implementation, the operands include a first operand and a second operand, and the step of determining the access order of the memory cell when performing the sub-operation based on the memory cell state includes:

[0023] Based on the state of the storage unit, determine the second delay cycle number of writing the operation result relative to reading the first operand;

[0024] The memory cell access order is determined based on the second delay clock cycle number.

[0025] In one possible implementation, the step of writing the operation result to the storage unit after the operation to be executed has started and after the duration of the third cycle has ended includes:

[0026] Based on the first number of clock cycles and the state of the storage unit, determine the third delay clock cycle from obtaining the result to writing the result into the storage unit;

[0027] After obtaining the calculation result, the calculation result is written to the storage unit based on the third delay cycle number.

[0028] In one possible implementation, the operands include a first operand and a second operand, and determining the third delay cycle number from obtaining the result to writing the result to the storage unit based on the first cycle number and the storage unit state includes:

[0029] When the storage unit is in a state where the operands and the operation result do not share a storage unit, the third delay cycle number is determined to be 0;

[0030] When the storage unit state is such that the first operand and the second operand do not share a storage unit, or the first operand or the second operand shares a storage unit with the operation result, after execution begins from the start of the operation to be executed and has elapsed for the duration of the sum of the first and second clock cycles, if the storage unit to be accessed is a storage unit used to store the operation result, then the third delay clock cycle number is determined to be 0; if the storage unit to be accessed is a storage unit used to store the operand but not used to store the operation result, then the third delay clock cycle number is determined to be 1.

[0031] When the storage unit state is such that the first operand and the second operand share a storage unit, and the first operand and the operation result do not share a storage unit, after execution starts from the operation to be executed and the execution time is the sum of the first number of clock cycles and the second number of clock cycles, if the storage unit to be accessed is the storage unit used to store the operation result, then the third delay clock cycle number is determined to be 0; if the storage unit to be accessed is the storage unit used to store the operand, then the third delay clock cycle number is determined to be 1.

[0032] When the storage unit is in a state where the first operand, the second operand, and the operation result share a storage unit, after execution begins from the start of the operation to be executed and the execution time is equal to the sum of the first and second clock cycles, if the accessed storage unit is used to store the operation result, then the third delay clock cycle number is determined to be 0; if the accessed storage unit is used to store the first operand, then the third delay clock cycle number is 2; if the accessed storage unit is used to store the second operand, then the third delay clock cycle number is determined to be 1; in the case of reading operands, reading the first operand precedes reading the second operand.

[0033] According to another aspect of this disclosure, a display driver chip is provided, comprising: a first clock cycle number determination unit, a memory cell state determination unit, a second clock cycle number determination unit, and an access control unit to execute a memory access method, the method comprising:

[0034] The first beat count determination unit is used to determine the number of first beats required for the operation process of the sub-operation based on the type of the sub-operation to be executed.

[0035] A storage unit state determination unit is used to determine the storage unit state based on the storage location of the operand and the storage location of the operation result of the sub-operation. The state is used to characterize whether the operand and the operation result share the storage unit.

[0036] The second cycle number determination unit is used to determine the number of second cycles required for the sub-operation to access the storage unit process based on the storage unit state.

[0037] An access control unit is used to access the storage unit based on the storage unit status, the first number of cycles, the second number of cycles, and the parameters included in the operation to be performed.

[0038] In one possible implementation, the parameter is the number of sub-operations, and the access control unit includes:

[0039] The third beat count determination unit, the first beat count, and the second beat count are used to determine the third beat count based on the storage unit state. The third beat count represents the time taken to not access the storage unit used to store the operands during the execution of the operation to be performed, and / or the time taken to not access the storage unit used to store the operation result.

[0040] An access order determination unit is used to determine the access order of the storage unit when performing the sub-operation based on the storage unit state.

[0041] The first timing unit is configured to access the storage unit according to the access order after the execution of the operation to be executed begins, and from the start of the process of reading operands of the first sub-operation of the operation to be executed, within the time interval corresponding to the number of the third beats, not to perform the operation of accessing the storage unit for the purpose of writing the operation result, and according to the number of sub-operations, from the start of the operation process of the last sub-operation of the operation to be executed, within the time interval of the number of the third beats, not to perform the operation of accessing the storage unit for the purpose of reading operands;

[0042] The calculation result writing unit is used to start writing the calculation result to the storage unit after the calculation to be executed has started and after the duration of the third cycle has ended.

[0043] In one possible implementation, the operands include a first operand and a second operand, and the third beat count determination unit includes:

[0044] The third beat quantity first setting unit is used to set the third beat quantity to the first beat quantity when the storage unit state is such that the operands and the operation result do not share the same storage unit.

[0045] The third beat quantity second setting unit is used to, when the storage unit is in a state where any two or more of the first operand, the second operand, and the operation result share a storage unit, increase the third beat quantity by the second beat quantity for each increase of the first beat quantity by the second beat quantity, wherein the initial value of the third beat quantity is 0.

[0046] In one possible implementation, the operands include a first operand and a second operand, and the access order determination unit includes:

[0047] The first delay cycle number determination unit is used to determine the first delay cycle number of reading the second operand relative to reading the first operand based on the state of the storage unit;

[0048] The access order determination first sub-unit is used to determine the access order of the storage unit based on the first delay clock cycle number.

[0049] In one possible implementation, the operands include a first operand and a second operand, and the access order determination unit includes:

[0050] The second delay cycle number determination unit is used to determine the second delay cycle number of writing the operation result relative to reading the first operand based on the state of the storage unit;

[0051] The access order determination second sub-unit is used to determine the access order of the storage unit based on the second delay clock cycle number.

[0052] In one possible implementation, the calculation result writing unit includes:

[0053] The third delay cycle number determination unit is used to determine the third delay cycle number from obtaining the result to writing the result into the storage unit based on the first cycle number and the storage unit state;

[0054] The access order determines the third sub-unit, which is used to write the operation result to the storage unit based on the third delay clock cycle number after obtaining the operation result.

[0055] In one possible implementation, the operands include a first operand and a second operand, and the third delay cycle number determination unit includes:

[0056] The third delay cycle number determines the first sub-unit, which is used to determine the third delay cycle number as 0 when the storage unit state is such that the operand and the operation result do not share the same storage unit;

[0057] The third delay cycle number determination second sub-unit is used when the storage unit state is such that the first operand and the second operand do not share a storage unit, or the first operand or the second operand shares a storage unit with the operation result, after the execution starts from the operation to be executed and has elapsed for the duration of the sum of the first cycle number and the second cycle number, if the storage unit to be accessed is a storage unit used to store the operation result, then the third delay cycle number is determined to be 0; if the storage unit to be accessed is a storage unit used to store the operand but not used to store the operation result, then the third delay cycle number is determined to be 1.

[0058] The third delay cycle number determines the third sub-unit, which is used when the storage unit state is such that the first operand and the second operand share a storage unit, and the first operand and the operation result do not share a storage unit, after the execution starts from the operation to be executed and has elapsed for the duration of the sum of the first cycle number and the second cycle number, if the storage unit to be accessed is the storage unit used to store the operation result, then the third delay cycle number is determined to be 0; if the storage unit to be accessed is the storage unit used to store the operand, then the third delay cycle number is determined to be 1.

[0059] The third delay cycle number determines the fourth sub-unit, which is used when the storage unit state is such that the first operand, the second operand, and the operation result share a storage unit. Starting from the beginning of the operation to be executed, after the duration equal to the sum of the first and second cycle numbers, if the accessed storage unit is used to store the operation result, then the third delay cycle number is determined to be 0; if the accessed storage unit is used to store the first operand, then the third delay cycle number is 2; if the accessed storage unit is used to store the second operand, then the third delay cycle number is determined to be 1. In the case of reading operands, reading the first operand precedes reading the second operand.

[0060] In one possible implementation, the chip is a TDDI chip.

[0061] According to another aspect of this disclosure, an apparatus for accessing memory is provided, comprising: a display; the display having the aforementioned display driver chip; wherein the display driver chip is configured to implement the aforementioned method when executing instructions stored in the memory.

[0062] In one possible implementation, the display is at least one of: a micro light-emitting diode display, a sub-millimeter light-emitting diode display, a quantum dot light-emitting diode display, and an organic light-emitting diode display.

[0063] In one possible implementation, the device for accessing the memory is at least one of a smartphone, smartwatch, smart bracelet, tablet computer, laptop computer, and in-vehicle computer.

[0064] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided that stores computer program instructions thereon, wherein the computer program instructions, when executed by a processor, implement the above-described method.

[0065] According to another aspect of this disclosure, a computer program product is provided, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0066] In this embodiment, the number of first ticks required for the operation of a sub-operation is determined based on the type of the sub-operation to be executed; the storage unit state is determined based on the storage location of the operands and the storage location of the operation result of the sub-operation, the state being used to characterize whether the operands and the operation result share the same storage unit; the number of second ticks required for the sub-operation to access the storage unit is determined based on the storage unit state; and the storage unit is accessed based on the storage unit state, the first tick number, the second tick number, and the parameters included in the operation to be executed. Through the method of this embodiment, read and write data can be simultaneously scheduled during certain time periods according to different storage unit states; under the premise that pipelined operation is proceeding normally, the efficiency of accessing memory is maximized, and the overall speed and efficiency of operation are improved, thereby enhancing the touch accuracy and sensitivity of smart products.

[0067] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0068] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0069] Figure 1 A flowchart illustrating a method for accessing memory according to an embodiment of the present disclosure is shown.

[0070] Figure 2 A schematic diagram of the memory access operation arrangement when the memory cell is in state one is shown.

[0071] Figure 3 A schematic diagram of the memory access operation arrangement when the memory cell is in state two is shown.

[0072] Figure 4 A schematic diagram of the memory access operation arrangement when the memory cell is in state three is shown.

[0073] Figure 5 A schematic diagram of the memory access operation arrangement when the memory cell is in state four is shown.

[0074] Figure 6 A block diagram of an apparatus for accessing memory according to an embodiment of the present disclosure is shown.

[0075] Figure 7 A schematic diagram of the structure of a TDDI chip according to an embodiment of the present disclosure is shown.

[0076] Figure 8 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0077] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0078] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0079] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0080] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0081] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0082] With the rapid development of smart products, in order to facilitate operation, screens have evolved from simply having a display function to being able to both display and complete user interaction with smart products, that is, screens can realize touch functions.

[0083] In this interactive process, if the smart product can provide accurate and rapid feedback after the user touches the screen, it can greatly enhance the user's operating experience. Based on this, on the one hand, the touch reporting rate of the screen can be increased to improve the frequency of touch data acquisition and reduce the probability of missing touch data. On the other hand, it is necessary to improve the computational efficiency of the Arithmetic and Logic Unit (ALU).

[0084] By improving the computational efficiency of the ALU, it can perform more operations per unit of time (e.g., within one minute). For example, regression operations can be performed more times, which helps improve the computational accuracy of smart products and produce more accurate touch effects. Furthermore, improved ALU computational efficiency can shorten the ALU's execution time, thereby increasing the response speed of smart products.

[0085] Generally, the ALU performs operations in three steps: reading operands from the storage unit, performing the operation, and writing the result back to the storage unit. The operands here can be the aforementioned touch data.

[0086] The operations performed by the ALU can include multiple sub-operations. In this case, the ALU can execute these sub-operations in a pipelined manner, improving operational efficiency. However, in practical applications, to avoid memory access conflicts, simultaneous access to two or more memory locations is not scheduled. This reduces memory access efficiency, which in turn reduces the efficiency of the entire pipelined operation. Consequently, the ALU's operation speed and efficiency decrease, which in turn reduces the touch accuracy and sensitivity of smart products.

[0087] To address this issue, this disclosure proposes a memory access scheme that, under the premise that pipelined operations are proceeding normally, arranges for some data to be read / written simultaneously, thereby improving memory access efficiency and thus enhancing the touch accuracy and sensitivity of smart products.

[0088] Figure 1 A flowchart illustrating a method for accessing memory according to an embodiment of the present disclosure is shown. Figure 1 As shown, the method includes:

[0089] S11, determine the number of first ticks required for the operation process of the sub-operation based on the type of the sub-operation to be executed.

[0090] The operation to be performed may include at least one sub-operation. The sub-operation can be an operation that can be performed by an arithmetic unit (e.g., an ALU). The type of the sub-operation may include: the operation type of the sub-operation, and / or, the bit width of the operands used by the sub-operation. The operation type of the sub-operation here may include one or more of the following: arithmetic operations, comparison operations, shift operations, etc. For example, arithmetic operations may include: addition, subtraction, multiplication, division, modulo, etc.; comparison operations may include: greater than, equal to, less than, etc.; shift operations may include: logical shift, arithmetic shift, etc. The above are merely examples, and this disclosure does not limit the type of sub-operation.

[0091] A suboperation can include an operation process and a memory access process. The operation process can be the entire process of a single suboperation from the start of the operation to obtaining the result. The memory access process can be the process of reading all operands of a single suboperation and writing the result of the single suboperation. The memory access process can include an operand reading process and a result writing process. Therefore, a single suboperation can include an operand reading process, an operation process, and a result writing process.

[0092] The operation type of a suboperation and the bit width of its operands can affect the duration of the operation. Therefore, the duration of the suboperation's operation can be determined based on its type. In this embodiment, the duration can be represented using the number of clock cycles of the arithmetic unit. In this embodiment, the number of clock cycles experienced during the operation can be the first number of clock cycles.

[0093] S12, determine the storage unit state based on the storage location of the operand and the storage location of the operation result of the sub-operation. The state is used to characterize whether the operand and the operation result share the storage unit.

[0094] In this embodiment of the disclosure, a single suboperation can have multiple operands, which can be stored in different or the same storage units. The operands and the result of a single suboperation can also be stored in different or the same storage units. In this embodiment of the disclosure, the operand storage location can be a storage unit used to store operands, and the result storage location can be a storage unit used to store the result of the operation. Once the operand storage location and the result storage location are obtained, the storage unit status can be easily obtained. The storage unit status can include: operands and operands, operands and the result do not share storage units; operands and the result share a storage unit; operands and operands share a storage unit, or some operands and the result share a storage unit.

[0095] For example, a suboperation has two operands: a first operand and a second operand; and one operation result. The first operand is stored in storage unit A, the second operand is stored in storage unit B, and the operation result is stored in storage unit A; the storage unit status is: the first operand and the second operand do not share a storage unit, and the first operand and the operation result share storage unit A.

[0096] S13, determine the number of second ticks required for the sub-operation to access the storage unit process based on the storage unit state.

[0097] In this embodiment of the disclosure, the second number of ticks is used to represent the duration of the process of accessing a memory unit in a suboperation.

[0098] When operands do not share storage units with each other, and operands do not share storage units with the operation result, it means that even if multiple operands are read simultaneously, and / or if reading operands and writing operation results are performed simultaneously, no memory access conflict will occur. Therefore, in this storage unit state, the second tick count is 1. That is, the operation of reading all operands and writing operation results can be performed simultaneously.

[0099] When all operands and the result of a single operation share a single storage unit, it means that reading any operand prevents reading other operands and / or writing the result, otherwise a memory access conflict will occur. Furthermore, writing operands also prevents reading any operands, otherwise a memory access conflict will occur. Therefore, in this storage unit state, the second tick count is the sum of the number of operands and the number of operation results.

[0100] When operands share a storage unit, or when some operands share a storage unit with the operation result, a second number of shared storage units is determined. Here, the shared storage unit is defined as the first storage unit, and the number of times the first storage unit is shared needs to be determined. In this storage unit state, the second tick count is the difference between the number of times the first storage unit is shared and the second count, plus 1.

[0101] For example, the first and second operands share storage unit D, the third, fourth, and fifth operands share storage unit E, and the result of the operation is stored in storage unit F. In the first cycle, the first and third operands can be read; in the second cycle, the second and fourth operands can be read; in the third cycle, the fifth operand can be read; and in the fourth cycle, the result of the operation can be written. Therefore, the number of cycles in the second cycle is 4.

[0102] The following explains the process of calculating the number of second beats: Since memory cells D and F are shared memory cells, the number of first cells (the second number) is 2. Because memory cell D is shared 2 times and memory cell F is shared 3 times, the total number of times a memory cell is shared is 5. Therefore, the number of second beats is 5 - 2 + 1 = 4.

[0103] S14, access the storage unit based on the storage unit status, the first number of beats, the second number of beats, and the parameters of the operation to be performed.

[0104] The process of accessing memory units for each sub-operation in the computation to be executed can be parallelized with the computation process to achieve pipelined computing. The parameters of the computation to be executed may include: the number of sub-operations.

[0105] Based on the number of first-cycle ticks and the number of sub-operations, the total duration of each sub-operation in the operation to be executed can be determined, which can be called the first total duration. Based on the number of second-cycle ticks and the number of sub-operations, the total duration of accessing memory units for each sub-operation in the operation to be executed can be determined, which can be called the second total duration. Since executing a single sub-operation usually yields a result, based on the number of sub-operations and the second total duration, the third total duration for accessing memory units to read operands and the fourth total duration for accessing memory units to write the result can be determined.

[0106] After obtaining its operands, a suboperation begins its computation process; however, no result is obtained during this process. Therefore, memory access is not required during computation. Thus, pipelined computation can be scheduled based on the sum of the first, third, and fourth time durations. Furthermore, since the memory cell states are known, the time intervals for simultaneous read and write operations can be determined, improving computational speed and efficiency. Therefore, maximizing memory access efficiency while ensuring normal pipelined computation can improve overall computational speed.

[0107] In this embodiment, the number of first ticks required for the operation of a sub-operation is determined based on the type of the sub-operation to be executed; the storage unit state is determined based on the storage location of the operands and the storage location of the operation result of the sub-operation, the state being used to characterize whether the operands and the operation result share the same storage unit; the number of second ticks required for the sub-operation to access the storage unit is determined based on the storage unit state; and the storage unit is accessed based on the storage unit state, the first tick number, the second tick number, and the parameters of the operation to be executed. Through the method of this embodiment, read and write data can be simultaneously scheduled in certain time periods according to different storage unit states; the efficiency of accessing memory in pipelined operations is improved, and the overall speed and efficiency of operations are improved, thereby enhancing the touch accuracy and sensitivity of smart products.

[0108] In one possible implementation, the parameter is the number of sub-operations, and the step of accessing the storage unit based on the storage unit state, the first number of ticks, the second number of ticks, and the number of sub-operations includes: determining a third number of ticks based on the storage unit state, the first number of ticks, and the second number of ticks, wherein the third number of ticks represents the time occupied by not accessing the storage unit used to store the operands during the execution of the operation to be executed, and / or the time occupied by not accessing the storage unit used to store the operation result; determining the access order of the storage units when executing the sub-operations based on the storage unit state; After the operation to be executed begins, the storage unit is accessed according to the access order. Starting from the process of reading operands of the first sub-operation of the operation to be executed, no operation to access the storage unit for the purpose of writing the operation result is performed within the time interval corresponding to the third number of beats. According to the number of sub-operations, starting from the operation process of the last sub-operation of the operation to be executed, no operation to access the storage unit for the purpose of reading operands is performed within the time interval corresponding to the third number of beats. After the operation to be executed begins and after the duration of the third number of beats ends, the operation result is written to the storage unit.

[0109] During the execution of suboperations, the storage unit for operands is generally accessed first, and the storage unit for storing the operation result is accessed last. Furthermore, if a storage unit is shared, it can be accessed in stages according to the number of times it is shared. Based on this, the access order of the storage units is determined.

[0110] In this embodiment of the disclosure, a mapping relationship between the storage unit state and the number of third beats can be established in advance, and the number of third beats corresponding to the storage unit state can be determined according to the mapping relationship.

[0111] In this embodiment of the disclosure, the number of third beats can be determined based on the number of first beats and the number of second beats. The number of third beats can be the product of the number of second beats included in the number of first beats and the number of second beats. This number and the number of third beats are positive integers. In the operation to be performed, at least two time intervals corresponding to the number of third beats can be set.

[0112] Within the time interval of the third beat, if the storage unit of the operand should be accessed according to the access order, the storage unit of the operand is not accessed, and / or, if the storage unit of the result of the operation should be accessed according to the access order, the storage unit of the result of the operation is not accessed.

[0113] In this embodiment, the first time interval can be determined by starting the first time when the operands are read from the beginning of the first sub-operation. After three time ticks, the first time interval ends. Since the first sub-operation in the pending operation is not yet completed within the first time interval, and the first operation result has not yet been obtained, continuing the write operation according to the access order would result in writing incorrect operation results, causing invalid memory access and wasting energy. Therefore, no operation to access memory units for the purpose of writing operation results is performed within the first time interval; that is, a write-empty operation is set. At the next moment after the first time interval ends, i.e., after the first time interval has elapsed, the access order begins. When the memory unit used to store the operation result should be accessed, the memory unit is accessed and the operation result is written to the memory unit.

[0114] In this embodiment, the last sub-operation to be executed can be determined based on the number of sub-operations. A second timing period begins at the start of the last sub-operation's execution, and ends after a third number of ticks, thus defining a second time interval. Since the operands of each sub-operation in the pending operation have already been acquired before the start of the last sub-operation's execution, if read operations are continued according to the access order, the operands read will be irrelevant to the current operation, resulting in invalid memory access and wasted energy. Therefore, during the second time interval, it is unnecessary to perform operations to access the memory unit for the purpose of reading operands; that is, a read-empty operation is set.

[0115] In this embodiment of the disclosure, by setting a third cycle number, the operation of accessing the memory unit for the purpose of writing the operation result is not performed before the first operation result in the operation to be executed is obtained; after all operands in the operation to be executed have been obtained, the operation of accessing the memory unit for the purpose of reading the operands is not performed, so as to reduce the probability of invalid memory access, thereby reducing the probability of writing incorrect operation results and saving energy consumption.

[0116] In one possible implementation, the operands include a first operand and a second operand. Determining the third tick count based on the storage unit state includes: when the storage unit state is such that the operands and the operation result do not share storage units, setting the third tick count to the first tick count; when the storage unit state is such that any two or more of the first operand, the second operand, and the operation result share storage units, increasing the third tick count by the second tick count for each increment of the first tick count, with the initial value of the third tick count being 0.

[0117] When the first operand, second operand, and operation result do not share storage units, a single sub-operation occupies three storage units. For ease of description, these three storage units are named storage unit A, storage unit B, and storage unit C. The access order can be: access storage units A, B, and C simultaneously. That is, operands can be read and operation results can be written in the same clock cycle. However, from the time the operand of the first sub-operation is obtained until the end of the first sub-operation's operation, continuing to access storage units in the access order will result in writing an incorrect operation result to the storage unit because the operation result of the first sub-operation has not yet been obtained. Therefore, the write operation during the period from the clock cycle of reading operands until the clock cycle before obtaining the operation result can be set to write empty.

[0118] Since this duration is exactly equal to the time taken by the sub-operation, the number of three beats can be set as the number of the first beat.

[0119] The storage unit state is such that any two of the first operand, the second operand, and the operation result share a storage unit. A single sub-operation occupies two storage units. For ease of description, these two storage units are named storage unit A and storage unit B. In this storage unit state, storage unit A can be shared, and storage unit B can be not shared. The access order can be: in the first cycle, storage units A and B are accessed simultaneously, and in the second cycle, storage unit A is accessed. A single sub-operation can complete the storage unit access process in two cycles, so the number of cycles in the second cycle is 2, where accessing the storage unit used to store the operation result occupies one cycle. A single read / write cycle of the operation to be executed is two cycles.

[0120] The operation to be executed continues with read and write operations in a two-beat cycle. Therefore, from the start of the operand reading process of the first sub-operation of the operation to the acquisition of the first result, every time the operation of the first sub-operation increases by two beats (i.e., the number of beats in the first sub-operation increases by a second beat), one beat should be used to perform a write operation, i.e., access the storage unit used to store the operation result. However, since the operation result has not yet been obtained, even accessing the storage unit used to store the operation result is an invalid access. Therefore, before the operation result is obtained, the beat containing the write operation in the read / write cycle is set to write empty. Furthermore, the two beats in the read / write cycle containing the write empty beat are counted into the third beat count, increasing the write empty count by one.

[0121] For example, Table 1 illustrates the method for determining the number of third ticks when the first operand and the second operand do not share a storage unit, and the first operand or the second operand shares a storage unit with the operation result. Table 1 shows the correspondence between the number of first ticks, the number of third ticks, and the number of writes in the first sub-operation when the first operand and the second operand do not share a storage unit, and the first operand or the second operand shares a storage unit with the operation result.

[0122]

[0123] The data in Table 1 is explained below.

[0124] As mentioned earlier, in this storage unit state, a single read / write cycle for an operation to be performed consists of two clock cycles. The first cycle involves reading the first operation and the second operand, while the second cycle involves writing the operation result. Obtaining operands for suboperations requires half a read / write cycle.

[0125] When the first cycle count is 1, the suboperation obtains its result in the cycle following the acquisition of its operand, and the operation process takes one cycle. The first cycle after the suboperation obtains its operand includes a write operation. Therefore, when the first cycle count is 1, the write operation of the result operation in the read-write cycle is not experienced when the result is not obtained. The third cycle count can be set to 0, and the number of write operations is 0.

[0126] When the first cycle count is 2, the sub-operation obtains its result two cycles after acquiring the operand, and the operation process takes two cycles. Acquiring the result involves a read operand operation within a read-write cycle, so a one-cycle delay is needed before writing the result to the memory location. At this point, a write-empty operation occurs, which is equivalent to setting the write operand operation within the read-write cycle to a write-empty operation. This write-empty operation is contained within one read-write cycle, totaling two cycles. Therefore, the third cycle count can be set to 2, and the write-empty operation count can be set to 1.

[0127] When the first cycle count is 3, the sub-operation obtains its result three cycles after acquiring the operand, and the operation process takes three cycles. Obtaining the result is a write operation within a read / write cycle, which can be directly written to the memory location after obtaining the result. At this point, a write-empty operation occurs, meaning the write operand operation within the read / write cycle is set as a write-empty operation. This write-empty operation is contained within one read / write cycle, totaling two cycles. Therefore, the third cycle count can be set to 2, and the write-empty operation count can be set to 1.

[0128] When the first cycle count is 4, the sub-operation obtains its result four cycles after acquiring the operand, and the operation process takes four cycles. Since acquiring the result occurs during the read operand read operation within a read-write cycle, a one-cycle delay is needed before writing the result to the memory location. At this point, two write-to-empty operations occur: one during the read-write cycle where the operand was read, and one during the operation itself. These two write-to-empty operations are contained within two read-write cycles, totaling two cycles. Therefore, the third cycle count can be set to 4, and the number of write-to-empty operations can be set to 2.

[0129] When the first cycle count is 5, the sub-operation obtains its result five cycles after acquiring the operand, and the operation process takes five cycles. Obtaining the result is a write operation within a read / write cycle, which can be directly written to the memory location after obtaining the result. At this point, two write-to-empty operations occur: one during the read / write cycle where the operand is read, and one during the operation itself. These two write-to-empty operations are contained within two read / write cycles, totaling two cycles. Therefore, the third cycle count can be set to 4, and the number of write-to-empty operations can be set to 2.

[0130] Similarly, when the number of beats in the first section is n, the number of beats in the third section can be set to n. Set the number of write empty counts to and Round down to the nearest integer. Also, set the initial value for the third beat count to 0.

[0131] For example, Table 2 illustrates how the number of third ticks is determined when the first operand and the second operand share a storage unit, but the first operand and the operation result do not share a storage unit.

[0132] Table 2 shows the correspondence between the number of first-cycle operations and the number of third-cycle operations, and the number of write operations, when the first operand and the second operand share a storage unit, but the first operand and the operation result do not share a storage unit.

[0133]

[0134] The data in Table 2 is explained below.

[0135] As mentioned earlier, in this storage unit state, a single read / write cycle for the operation to be performed consists of two clock cycles. The first cycle is for reading the first operation and writing the result, and the second cycle is for reading the second operand. Obtaining the operand for a suboperation requires one read / write cycle.

[0136] When the number of beats in the first cycle is 1, the suboperation obtains its result in the cycle following the acquisition of its operand, and the operation process takes one cycle. As mentioned earlier, the first cycle after the suboperation obtains its operand includes a write operation. Therefore, when the number of beats in the first cycle is 1, the read / write cycle experienced before obtaining the result is the same as the read / write cycle used to read the operand. The number of beats in the third cycle can be set to 2, and the number of writes to empty is 1.

[0137] When the first cycle count is 2, the sub-operation obtains its result two cycles after acquiring the operand, and the operation process takes two cycles. As mentioned earlier, the first cycle after acquiring the operand contains a write operation, the second cycle contains a read operation, and the third cycle contains a write operation; that is, the moment the result is obtained is the moment the operand is read in the read-write cycle. Therefore, when the first cycle count is 2, the result needs to be written to the memory unit one cycle later. At this time, two write-empty operations occur. One write-empty operation occurs when reading the operand, and the other occurs during the operation. These two write-empty operations are contained in two read-write cycles, totaling four cycles. The third cycle count can be set to 4, and the number of write-empty operations can be set to 2.

[0138] When the first cycle count is 3, the sub-operation obtains its result three cycles after acquiring the operand, and the operation process takes three cycles. As mentioned earlier, the first cycle after acquiring the operand contains a write operation, the second cycle contains a read operation, and the third cycle contains another write operation; that is, the moment the result is acquired is the moment the result is written in the read-write cycle. Therefore, when the first cycle count is 3, the result can be directly written to the memory unit after acquisition. This involves two write-empty operations: one during operand reading and one during the operation itself. These two write-empty operations are contained within two read-write cycles, totaling four cycles. Therefore, the third cycle count can be set to 4, and the number of write-empty operations can be set to 2.

[0139] Similarly, when the number of beats in the first section is n, the number of beats in the third section can be set to n. Set the number of write empty counts to and Round down to the nearest integer. Also, set the initial value for the third beat count to 2.

[0140] When the storage unit is in a state where the first operand, the second operand, and the operation result share a storage unit, a single sub-operation occupies one storage unit, which is named storage unit A. The access order can be: accessing storage unit A sequentially in three cycles. The second cycle of a single sub-operation has 3 cycles, i.e., three cycles, of which accessing the storage unit used to store the operation result occupies one cycle. A single read / write cycle of the operation to be executed is three cycles.

[0141] After the operand reading process of the first sub-operation of the operation to be executed is completed, the first sub-operation obtains the first operand and the second operand, and begins its operation. At this time, the operation to be executed continues to perform read and write operations in a three-beat cycle. Therefore, when the operation of the first sub-operation increases by three beats (i.e., the number of beats in the first sub-operation increases by the number of beats in the second cycle), one beat should be used to perform a write operation, i.e., access the storage unit used to store the operation result. However, since the operation result has not yet been obtained during the operation, even accessing the storage unit used to store the operation result is an invalid access. Therefore, before the operation result is obtained, the beats in the read / write cycle containing the write operation are set to write empty. Furthermore, the three beats in the read / write cycle containing the write empty beat are counted in the third beat count, increasing the write empty count by one.

[0142] The following example, Table 3, illustrates how the number of third ticks is determined when the first operand, the second operand, and the operation result share a common storage unit.

[0143] Table 3 shows the correspondence between the number of first-cycle operations, the number of third-cycle operations, and the number of write operations when any two of the first operand, second operand, and the result of the operation share a memory unit.

[0144]

[0145]

[0146] The data in Table 3 is explained below.

[0147] As mentioned earlier, in this storage unit state, a single read / write cycle of the operation to be performed is three beats, and the first beat of the read / write cycle is a read operation, the second beat is a read operation, and the third beat is a write operation.

[0148] When the first cycle count is 1, the suboperation obtains its result in the cycle following the acquisition of its operand, and the operation process takes one cycle. As mentioned earlier, the first cycle after the suboperation acquires its operand is a write operation. Therefore, when the first cycle count is 1, there is no need to set a time interval for not accessing the storage unit used to store the operation result. The third cycle count can be set to 0, and the number of write operations is 0.

[0149] When the first cycle count is 2, the sub-operation obtains its result two cycles after acquiring the operand, and the operation process takes two cycles. As mentioned earlier, the first cycle after acquiring the operand contains a write operation, the second cycle contains a read operation, the third cycle contains a read operation, and the fourth cycle contains a write operation. Therefore, when the first cycle count is 2, a two-cycle delay is needed before writing the result to the memory unit. At this point, a write-empty operation has occurred, which is contained within one read-write cycle, totaling three cycles. The third cycle count can be set to 3, and the write-empty operation count can be set to 1.

[0150] When the first cycle count is 3, the sub-operation obtains its result three cycles after acquiring the operand, and the operation process takes two cycles. As mentioned earlier, the first cycle after acquiring the operand contains a write operation, the second cycle contains a read operation, the third cycle contains a read operation, and the fourth cycle contains a write operation. Therefore, when the first cycle count is 3, a one-cycle delay is needed before writing the result to the memory unit. At this point, a write-empty operation occurs, which is contained within one read-write cycle, totaling three cycles. Therefore, the third cycle count can be set to 3, and the write-empty operation count can be set to 1.

[0151] When the first cycle count is 4, the sub-operation obtains its result four cycles after acquiring the operand, and the operation process takes four cycles. As mentioned earlier, the first cycle after acquiring the operand contains a write operation, the second cycle contains a read operation, the third cycle contains a read operation, and the fourth cycle contains a write operation. Therefore, when the first cycle count is 4, there is no need to set a time interval for not accessing the storage unit used to store the operation result; the result can be directly written to the storage unit after acquisition. At this point, a write-empty operation occurs, which is contained within one read-write cycle, totaling three cycles. The third cycle count can be set to 3, and the write-empty operation count can be set to 1.

[0152] When the first cycle count is 5, the sub-operation obtains its result five cycles after acquiring the operand, and the operation process takes five cycles. As mentioned earlier, the first cycle after acquiring the operand contains a write operation, the second cycle contains a read operation, the third cycle contains a read operation, the fourth cycle contains a write operation, the fifth cycle contains a read operation, the sixth cycle contains a read operation, and the fourth cycle contains a write operation. Therefore, when the first cycle count is 5, a two-cycle delay is needed before writing the result to the memory unit. At this point, two write-empty operations have occurred, which are contained within two read / write cycles, totaling six cycles. The third cycle count can be set to 6, and the number of write-empty operations can be set to 2.

[0153] When the first cycle count is 6, the sub-operation obtains its result six cycles after acquiring its operands, and the operation process takes six cycles. As mentioned earlier, the first cycle after acquiring the operands of the sub-operation includes a write operation, the second cycle includes a read operation, the third cycle includes a read operation, the fourth cycle includes a write operation, the fifth cycle includes a read operation, the sixth cycle includes a read operation, and the fourth cycle includes a write operation. Therefore, when the first cycle count is 6, a one-cycle delay is needed before writing the result to the memory unit. At this point, two write-empty operations have occurred, which are contained within two read-write cycles, totaling six cycles. Therefore, the third cycle count can be set to 6, and the number of write-empty operations can be set to 2.

[0154] Similarly, when the number of beats in the first section is n, the number of beats in the third section can be set to n. Set the number of write empty counts to and Round down to the nearest integer.

[0155] In this embodiment, the number of third cycles is determined for each storage unit state to determine the duration of no storage unit access, reducing the probability of invalid memory access and the probability of writing erroneous operation results, while also saving energy. Based on different storage unit states, a mapping relationship can be established between the number of third cycles and the number of first cycles of the first sub-operation, making the method of this embodiment not limited by the operation time of the first sub-operation, thus improving its universality.

[0156] In one possible implementation, the operands include a first operand and a second operand, and determining the access order of the storage unit when performing the sub-operation based on the storage unit state includes: determining a first delay cycle number for reading the second operand relative to reading the first operand based on the storage unit state; and determining the storage unit access order based on the first delay cycle number.

[0157] When the storage unit states that the first operand, second operand, and operation result do not share storage units, reading the first operand and reading the second operand can be performed simultaneously. Therefore, in this storage unit state, the first delay cycle count can be set to 0. The storage unit access order is: simultaneously access the storage unit used to store the first operand and the storage unit used to store the second operand.

[0158] When the storage unit is in a state where any two of the first operand, second operand, and the operation result share a storage unit, if the first operand and second operand share a storage unit, the first delay tick count can be set to 1. The storage unit access order is: first access the storage unit used to store the first operand, then access the storage unit used to store the second operand. If the first operand and second operand do not share a storage unit, the first delay tick count can be set to 0. The storage unit access order is: simultaneously access the storage unit used to store the first operand and the storage unit used to store the second operand.

[0159] When the storage unit is in a state where the first operand, the second operand, and the operation result share a storage unit, it has been determined that the first operand and the second operand share a storage unit, and the first delay cycle number can be set to 1. The storage unit access order is as follows: first access the storage unit used to store the first operand, then access the storage unit used to store the second operand.

[0160] In this embodiment, based on the state of the memory cell, the delay of reading the second operand relative to reading the first operand can be determined to determine the access order of the memory cell. Arranging the access to the memory cell according to this access order can reduce the probability of memory access conflicts. This allows pipelined operations to proceed normally. Furthermore, under the premise that pipelined operations proceed normally, the efficiency of accessing the memory is maximized.

[0161] In one possible implementation, the operands include a first operand and a second operand, and the step of determining the access order of the storage unit when performing the sub-operation based on the storage unit state includes: determining a second delay number of ticks relative to reading the first operand when writing the operation result based on the storage unit state;

[0162] The memory cell access order is determined based on the second delay clock cycle number.

[0163] The second delay time is the delay of the time in which the write operation result is performed relative to the time in which the first operand is read within the same read / write cycle.

[0164] When the storage unit state is such that the first operand, second operand, and operation result do not share storage units, writing the operation result and reading the first operand can be performed simultaneously. Therefore, in this storage unit state, there is no lag between writing the operand and reading the first operand, and the second delay tick count can be set to 0. The storage unit access order is: simultaneously accessing the storage unit used to store the operand and the storage unit used to store the operation result.

[0165] If the storage unit state is any two of the first operand, the second operand, and the operation result that share a storage unit.

[0166] For example, when the first and second operands of the state do not share a storage unit, but the first operand and the operation result share a storage unit, there is no lag in writing the state operation result relative to reading the first operand, and the second delay cycle number can be set to 0. The storage unit access order is as follows: in the first cycle, the storage unit used to store the first operand and the storage unit used to store the operation result are accessed, and in the second cycle, the storage unit used to store the second operand is accessed.

[0167] For example, when the first operand and the second operand do not share a storage unit, the first operand and the second operand can be read simultaneously in the first cycle, and the operation result can be written in the second cycle. Writing the operation result and reading the operand cannot be performed simultaneously. Therefore, in this storage unit state, writing the operation result lags behind reading the first operand by one cycle, and the second delay cycle number can be set to 1. The storage unit access order is as follows: in the first cycle, the storage unit used to store the first operand and the storage unit used to store the second operand are accessed, and in the second cycle, the storage unit used to store the operation result is accessed.

[0168] When the storage unit is in a state where the first operand, the second operand, and the operation result share the same storage unit, the first operand is read in the first cycle, the second operand is read in the second cycle, and the operation result is written in the third cycle. Writing the operation result and reading the operand cannot be performed simultaneously. Therefore, in this storage unit state, writing the operation result lags behind reading the first operand by two cycles, and the second delay cycle number can be set to 2.

[0169] In this embodiment, based on the state of the memory cell, the delay between the write operation result and the read of the first operand can be determined to determine the access order of the memory cell. Arranging the access to the memory cell according to this access order can reduce the probability of memory access conflicts. This allows the pipelined operation to proceed normally. Furthermore, it maximizes the efficiency of memory access while ensuring the pipelined operation proceeds normally.

[0170] In one possible implementation, the step of writing the operation result to the storage unit after the operation to be executed has started and after the duration of the third number of clock cycles has ended includes: determining the third delay clock cycle from obtaining the result to writing the result to the storage unit based on the first number of clock cycles and the state of the storage unit; and writing the operation result to the storage unit based on the third delay clock cycle after obtaining the operation result.

[0171] The access order differs depending on the state of the memory cell. Therefore, the time when the operation result is obtained can be either a clock cycle containing a write operation or a clock cycle without a write operation. If the operation result is obtained in a clock cycle without a write operation, then a third delay clock cycle is needed before the operation result is written to the memory cell. If the operation result is obtained in a clock cycle containing a write operation, then the third delay clock cycle can be set to 0, meaning no delay is needed, and the operation result is written directly to the memory cell.

[0172] In this embodiment of the disclosure, the delay between writing the operation result and obtaining the operation result can be determined based on the state of the memory cell. This ensures that the operation of writing the storage result is performed when the memory cell where the operation result should be accessed is accessed, reducing the probability of memory access conflicts. This allows pipelined operations to proceed normally. Furthermore, it maximizes the efficiency of memory access while ensuring that pipelined operations continue normally.

[0173] In one possible implementation, the operands include a first operand and a second operand. Determining the third delay cycle from obtaining the result to writing the result to the storage unit based on the first cycle count and the storage unit state includes: when the storage unit state is such that the operands and the operation result do not share a storage unit, the third delay cycle count is set to 0; when the storage unit state is such that the first operand and the second operand do not share a storage unit, or the first operand or the second operand shares a storage unit with the operation result, after execution from the start of the operation to be executed for a duration equal to the sum of the first cycle count and the second cycle count, if the storage unit to be accessed is a storage unit used to store the operation result, then the third delay cycle count is set to 0; if the storage unit to be accessed is a storage unit used to store the operands but not the operation result, then the third delay cycle count is set to 1; when the storage unit state is such that the first operand and the second operand share a storage unit, the first operand... When the operand and the operation result do not share a storage unit, after execution begins from the start of the operation to be executed and the duration equal to the sum of the first and second clock cycles, if the storage unit to be accessed is a storage unit used to store the operation result, then the third delay clock cycle count is determined to be 0; if the storage unit to be accessed is a storage unit used to store the operand, then the third delay clock cycle count is determined to be 1. When the storage unit state is such that the first operand, the second operand, and the operation result share a storage unit, after execution begins from the start of the operation to be executed and the duration equal to the sum of the first and second clock cycles, if the storage unit to be accessed is a storage unit used to store the operation result, then the third delay clock cycle count is determined to be 0; if the storage unit to be accessed is a storage unit used to store the first operand, then the third delay clock cycle count is 2; if the storage unit to be accessed is a storage unit used to store the second operand, then the third delay clock cycle count is determined to be 1. In the case of reading operands, reading the first operand precedes reading the second operand.

[0174] In this embodiment, the storage unit state can be divided into four types: State 1, the first operand, the second operand, and the operation result do not share a storage unit. State 2, the first operand and the second operand do not share a storage unit, but the first operand or the second operand and the operation result share a storage unit. State 3, the first operand and the second operand share a storage unit, but the first operand and the operation result do not share a storage unit. State 4, the first operand, the second operand, and the operation result share a storage unit.

[0175] When the storage unit is in state one, both the storage unit for storing operands and the storage unit for storing the operation result can be accessed at any point during the execution of the operation to be performed without causing memory access conflicts. Therefore, in this storage unit state, the third delay cycle number can be set to 0.

[0176] When the storage unit is in state two or three, the second cycle count for a single sub-operation is 2, meaning the sub-operation's access to the storage unit takes two cycles. One cycle is used to access the storage unit used to store the operation result. After the first sub-operation's operand reading process is completed, the operation begins, and the result is obtained after the first cycle count. The moment the result is obtained can be a cycle containing a write operation or a cycle without a write operation. Therefore, as the first cycle count changes, the corresponding read and write operations at the moment the result is obtained will also change. If the moment the result is obtained is a cycle without a write operation, the next cycle contains a write operation, and the third delay cycle count is set to 1. If the moment the result is obtained is a cycle containing a write operation, the result is written directly, and the third delay cycle count is set to 0.

[0177] The following example, Table 4, illustrates how the number of the third delay beats is determined in state two or state three.

[0178] Table 4 shows the correspondence between the number of first clock cycles and the number of third delay clock cycles when the storage cell is in state two or state three.

[0179]

[0180] The data in Table 4 is explained below.

[0181] As mentioned earlier, in this storage unit state, a single read / write cycle for an operation to be performed consists of two clock cycles. Furthermore, a typical sub-operation involves first retrieving the operands and then writing the result. Therefore, one clock cycle contains a read operation, and the other contains a write operation. It should be noted that a single sub-operation includes two operands and one result; therefore, a clock cycle containing a read operation may also include another read operation, and vice versa.

[0182] When the number of clock cycles in the first cycle is 1, the time when the calculation result is obtained is one clock cycle in the read / write cycle that includes the write operation. Therefore, the number of clock cycles in the third delay cycle is set to 0.

[0183] When the number of clock cycles in the first cycle is 2, the result is obtained in a cycle that does not include a write operation, so the next cycle will contain a write operation. Therefore, the number of clock cycles in the third delay is set to 1.

[0184] When the number of clock cycles in the first cycle is 3, the time when the calculation result is obtained is one clock cycle in the read / write cycle that includes the write operation. Therefore, the number of clock cycles in the third delay cycle is set to 0.

[0185] Similarly, when the number of the third delay beats is m, the number of the third delay beats is set as the remainder of the sum of the number of beats and 1 divided by the number of beats in the second period, that is, (m+1)%2, where m is a positive integer m≥1.

[0186] When the storage unit is in state four, the second cycle count for a single sub-operation is 3, meaning the sub-operation's access to the storage unit takes three cycles. One cycle is dedicated to accessing the storage unit used to store the operation result. After the first sub-operation's operand reading process is completed, the operation begins, and the result is obtained after the first cycle count. The moment the result is obtained can be either a cycle containing a write operation or a cycle containing a read operation. Furthermore, in state four, two cycles within a read-write cycle contain read operations. Therefore, as the first cycle count changes, the corresponding read and write operations at the moment the result is obtained also change.

[0187] If the result is obtained in a single clock cycle that does not include a write operation, a third delay clock cycle needs to be set. Since the second clock cycle has 3 clock cycles, if the result is obtained in the first clock cycle containing a read operation, it means the next clock cycle contains a read operation, and the next two clock cycles contain write operations; therefore, the third delay clock cycle number is set to 2. If the result is obtained in the second clock cycle containing a read operation, it means the next clock cycle contains a write operation; therefore, the third delay clock cycle number is set to 1. If the result is obtained in the first clock cycle containing a write operation, the result is written directly, and the third delay clock cycle number is set to 0.

[0188] The following example, Table 5, illustrates how the third delay cycle number is determined when the first operand, the second operand, and the operation result share a common storage unit.

[0189] Table 5 shows the correspondence between the number of first clock cycles and the number of third delay clock cycles when the first operand, the second operand, and the operation result share a common storage unit.

[0190]

[0191] The data in Table 5 is explained below.

[0192] As mentioned earlier, in this storage unit state, a single read / write cycle of the operation to be performed is three beats, and the first beat of the read / write cycle is a read operation, the second beat is a read operation, and the third beat is a write operation.

[0193] When the number of clock cycles in the first cycle is 1, the time when the calculation result is obtained is one clock cycle in the read / write cycle that includes the write operation. Therefore, the number of clock cycles in the third delay cycle is set to 0.

[0194] When the first delay cycle has 2 clock cycles, the result is obtained in the first clock cycle containing the read operation, so the write operation is only included in the next two clock cycles. Therefore, the third delay cycle is set to 2 clock cycles.

[0195] When the first delay cycle has 3 clock cycles, the result is obtained in the second clock cycle containing the read operation, so the write operation will only be included in the next clock cycle. Therefore, the third delay cycle number is set to 1.

[0196] When the number of clock cycles in the first cycle is 4, the time when the calculation result is obtained is one clock cycle in the read / write cycle that includes the write operation. Therefore, the number of clock cycles in the third delay cycle is set to 0.

[0197] When the first delay cycle has 5 clock cycles, the result is obtained in the first clock cycle containing the read operation, so the write operation is only included in the next two clock cycles. Therefore, the third delay cycle is set to 2 clock cycles.

[0198] When the first delay cycle has 6 beats, the result is obtained in the second beat of the read / write cycle, which includes a read operation. Therefore, the write operation is only included in the next beat. Thus, the third delay cycle is set to 1.

[0199] Similarly, when the number of the third delay beats is m, if m = 3 × k - 2, the number of the third delay beats is 0; if m = 3 × k - 1, the number of the third delay beats is 2; if m = 3 × k, the number of the third delay beats is 1; k is a positive integer and k ≥ 1.

[0200] The following examples illustrate the method of accessing memory according to this disclosure, based on the four memory cell states described above.

[0201] Each suboperation has two operands: a first operand and a second operand. Each suboperation has one result. Suboperations in a given operation are the same suboperation. The first tick has 5 ticks and 3 suboperations.

[0202] As mentioned earlier, the state of a storage unit can be divided into four types.

[0203] Figure 2 This diagram illustrates the memory access operation arrangement when the memory cell is in state one. For example... Figure 2As shown, when the storage unit is in state one, the read / write cycle of a single sub-operation is one clock cycle, so the second clock cycle count can be set to 1. Since the first operand, second operand, and operation result do not share the same storage unit, reading the second operand can be performed simultaneously with reading the first operand; therefore, the first delay clock cycle count is set to 0. Furthermore, writing the operation result can also be performed simultaneously with reading the first operand; therefore, the second delay clock cycle count is set to 0. Because two operands can be read within one clock cycle, the sub-operation process begins in the second clock cycle. Figure 2 As can be seen, the third cycle count starts from the read operand and stops counting until the cycle before the result of the first sub-operation is obtained. The time taken for this process is equal to the time taken for the first cycle. Since the first cycle count is 5, the third cycle count can be set to 5. Because write operations can be performed in each cycle when the memory cell is in state one, the third delay cycle count is set to 0.

[0204] Figure 3 This diagram illustrates the memory access operation arrangement when the memory cell is in state two. For example... Figure 3 As shown, when the storage unit is in state two, the read / write cycle of a single sub-operation is two clock cycles, so the number of the second clock cycle is set to 2. Since the first operand and the second operand do not share the same storage unit, reading the second operand can be performed simultaneously with reading the first operand; therefore, the first delay clock cycle is set to 0. However, the write operation result lags behind the reading of the first operand by one clock cycle, so the second delay clock cycle is set to 1. Since two operands can be read within one clock cycle, the sub-operation process begins from the second clock cycle. Because the first clock cycle is 5, the third clock cycle is... The value of , where Round down. Therefore, set the number of beats in the third section to 4. From Figure 3 It can be seen that the write operation from the start of reading operands from the first sub-operation to obtaining the result is set to write empty, which takes two read / write cycles, or four clock cycles. Furthermore, the read operation in the two read / write cycles starting from the last sub-operation's cycle is set to read empty. Also, the moment the first result is obtained is one clock cycle containing a write operation, so the third delay clock cycle is set to 0.

[0205] Figure 4 This diagram illustrates the memory access operation arrangement when the memory cell is in state three. (State)

[0206] like Figure 4As shown, when the storage unit is in state three, the read / write cycle of a single sub-operation is two clock cycles, so the number of the second clock cycle is set to 2. Since the first operand and the second operand share the same storage unit, reading the second operand can be done in two clock cycles as reading the first operand, so the number of the first delay clock cycle is set to 1. Writing the operation result can be done simultaneously with reading the first operand, so the number of the second delay clock cycle is set to 0. Since both operands are read in the second clock cycle, the sub-operation process starts from the third clock cycle. Since the number of the first clock cycle is 5, the number of the third clock cycle is... The value of , where Round down. Therefore, set the number of beats in the third quarter to 6. From Figure 4 It can be seen that the write operation from the start of reading operands from the suboperation to obtaining the result is set to write empty, which takes three read / write cycles, or six clock cycles. Furthermore, the read operation in the three read / write cycles starting from the last suboperation's cycle is set to read empty. Also, the moment the first result is obtained is one clock cycle containing a write operation, so the third delay clock cycle is set to 0.

[0207] Figure 5 A schematic diagram illustrates the memory access operation arrangement when the memory cell is in state four. For example... Figure 5 As shown, when the storage unit is in state four, the read / write cycle of a single sub-operation is three cycles, so the number of cycles in the second cycle is set to 3. Since the first and second operands share the same storage unit, reading the second operand can be done in two cycles compared to reading the first operand; therefore, the number of cycles in the first delay is set to 1. However, the write operation result lags behind the reading of the first operand by two cycles, so the number of cycles in the second delay is set to 2. Both operands are read in the second cycle, so the sub-operation process begins in the third cycle. Since the number of cycles in the first cycle is 5, the number of cycles in the third cycle is... The value of , where Round down. Therefore, set the number of beats in the third quarter to 6. From Figure 5 It can be seen that the write operation from the start of reading operands from the suboperation to obtaining the result is set to write empty, which takes two read-write cycles, or six clock cycles. Furthermore, the read operation in the two read-write cycles starting from the last suboperation's cycle is set to read empty. Also, the moment the first result is obtained is the first clock cycle containing a read operation, so the third delay clock cycle is set to 2.

[0208] Figure 6 A block diagram of an apparatus for accessing memory according to an embodiment of the present disclosure is shown. Figure 6 As shown, the device 50 includes:

[0209] The first beat count determination unit 51 is used to determine the number of first beats required for the operation process of the sub-operation based on the type of the sub-operation to be executed.

[0210] The storage unit state determination unit 52 is used to determine the storage unit state based on the storage location of the operand and the storage location of the operation result of the sub-operation. The state is used to characterize whether the operand and the operation result share the storage unit.

[0211] The second cycle number determination unit 53 is used to determine the number of second cycles required for the sub-operation to access the storage unit process based on the storage unit state.

[0212] Access control unit 54 is used to access the storage unit based on the storage unit status, the first number of beats, the second number of beats, and the parameters included in the operation to be performed.

[0213] In one possible implementation, the parameter is the number of sub-operations, and the access control unit 54 includes:

[0214] The third beat count determination unit is used to determine the third beat count based on the storage unit status, the first beat count, and the second beat count. The third beat count represents the time taken to not access the storage unit used to store the operands and / or the time taken to not access the storage unit used to store the operation result during the execution of the operation to be performed.

[0215] An access order determination unit is used to determine the access order of the storage unit when performing the sub-operation based on the storage unit state.

[0216] The first timing unit is configured to access the storage unit according to the access order after the execution of the operation to be executed begins, and from the start of the process of reading operands of the first sub-operation of the operation to be executed, within the time interval corresponding to the number of the third beats, not to perform the operation of accessing the storage unit for the purpose of writing the operation result, and according to the number of sub-operations, from the start of the operation process of the last sub-operation of the operation to be executed, within the time interval of the number of the third beats, not to perform the operation of accessing the storage unit for the purpose of reading operands;

[0217] The calculation result writing unit is used to start writing the calculation result to the storage unit after the calculation to be executed has started and after the duration of the third cycle has ended.

[0218] In one possible implementation, the operands include a first operand and a second operand, and the third beat count determination unit includes:

[0219] The third beat quantity first setting unit is used to set the third beat quantity to the first beat quantity when the storage unit is in a state where the operands and the operation result do not share the same storage unit.

[0220] The third beat quantity second setting unit is used to, when the storage unit is in a state where any two or more of the first operand, the second operand, and the operation result share a storage unit, increase the third beat quantity by the second beat quantity for each increase of the first beat quantity by the second beat quantity, wherein the initial value of the third beat quantity is 0.

[0221] In one possible implementation, the operands include a first operand and a second operand, and the access order determination unit includes:

[0222] The first delay cycle number determination unit is used to determine the first delay cycle number of reading the second operand relative to reading the first operand based on the state of the storage unit;

[0223] The access order determination first sub-unit is used to determine the access order of the storage unit based on the first delay clock cycle number.

[0224] In one possible implementation, the operands include a first operand and a second operand, and the access order determination unit includes:

[0225] The second delay cycle number determination unit is used to determine the second delay cycle number of writing the operation result relative to reading the first operand based on the state of the storage unit;

[0226] The access order determination second sub-unit is used to determine the access order of the storage unit based on the second delay clock cycle number.

[0227] In one possible implementation, the calculation result writing unit includes:

[0228] The third delay cycle number determination unit is used to determine the third delay cycle number from obtaining the result to writing the result into the storage unit based on the first cycle number and the storage unit state;

[0229] The access order determines the third sub-unit, which is used to write the operation result to the storage unit based on the third delay clock cycle number after obtaining the operation result.

[0230] In one possible implementation, the operands include a first operand and a second operand, and the third delay cycle number determination unit includes:

[0231] The third delay cycle number determines the first sub-unit, which is used to determine the third delay cycle number as 0 when the storage unit state is such that the operand and the operation result do not share the same storage unit;

[0232] The third delay cycle number determination second sub-unit is used when the storage unit state is such that the first operand and the second operand do not share a storage unit, or the first operand or the second operand shares a storage unit with the operation result, after execution from the start of the operation to be executed for the sum of the first cycle number and the second cycle number, if the storage unit to be accessed is a storage unit used to store the operation result, then the third delay cycle number is determined to be 0; if the storage unit to be accessed is a storage unit used to store the operand but not used to store the operation result, then the third delay cycle number is determined to be 1.

[0233] The third delay cycle number determines the third sub-unit, which is used when the storage unit state is such that the first operand and the second operand share a storage unit, and the first operand and the operation result do not share a storage unit, after execution from the start of the operation to be executed for the sum of the first cycle number and the second cycle number, if the storage unit to be accessed is the storage unit used to store the operation result, then the third delay cycle number is determined to be 0; if the storage unit to be accessed is the storage unit used to store the operand, then the third delay cycle number is determined to be 1.

[0234] The third delay cycle number determines the fourth sub-unit, which is used when the storage unit state is such that the first operand, the second operand, and the operation result share a storage unit. Starting from the beginning of the operation to be executed, after the sum of the first cycle number and the second cycle number, if the accessed storage unit is used to store the operation result, then the third delay cycle number is determined to be 0; if the accessed storage unit is used to store the first operand, then the third delay cycle number is 2; if the accessed storage unit is used to store the second operand, then the third delay cycle number is determined to be 1. In the case of reading operands, reading the first operand precedes reading the second operand.

[0235] This disclosure also provides a display driver chip, including: a first clock cycle number determination unit, a memory cell state determination unit, a second clock cycle number determination unit, and an access control unit to execute a memory access method. The method includes: using the first clock cycle number determination unit to determine the first clock cycle number required for the operation of the sub-operation based on the type of the sub-operation to be executed; using the memory cell state determination unit to determine the memory cell state based on the operand storage location and the operation result storage location of the sub-operation, the state being used to characterize whether the operand and the operation result share the same memory cell; using the second clock cycle number determination unit to determine the second clock cycle number required for the sub-operation to access the memory cell based on the memory cell state; and using the access control unit to access the memory cell based on the memory cell state, the first clock cycle number, the second clock cycle number, and the number of sub-operations included in the operation to be executed.

[0236] This disclosure also provides an apparatus for accessing memory, including: a display; the display having the above-described display driver chip; wherein the display driver chip is configured to implement the above-described method when executing instructions stored in the memory.

[0237] In one possible implementation, the display is at least one of: a micro light-emitting diode display, a sub-millimeter light-emitting diode display, a quantum dot light-emitting diode display, and an organic light-emitting diode display.

[0238] In one possible implementation, the device for accessing the memory is at least one of a smartphone, smartwatch, smart bracelet, tablet computer, laptop computer, and in-vehicle computer.

[0239] This disclosure also proposes a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method. The computer-readable storage medium can be volatile or non-volatile.

[0240] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0241] This disclosure also proposes an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute the above-described method.

[0242] For example, the electronic devices in this embodiment include, but are not limited to, desktop computers, televisions, mobile devices with large screens such as mobile phones and tablets, and other common electronic devices that require multiple chips to be cascaded together to achieve driving.

[0243] For example, electronic devices can also be user equipment (UE), mobile devices, user terminals, terminals, handheld devices, computing devices, or in-vehicle devices, etc. Examples of terminals include: displays, smartphones or portable devices, mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, a server can be a local server or a cloud server.

[0244] In one possible implementation, the chip is a TDDI chip.

[0245] Figure 7 A schematic diagram of a TDDI chip according to an embodiment of the present disclosure is shown. As shown, the TDDI chip 700 includes: a touch circuit 710 and a display driving circuit 720. The touch circuit includes: an access memory control unit 711, which is used to control access to a first memory 712, wherein the first memory 712 is the memory in the touch circuit 710.

[0246] Figure 8 A block diagram of an electronic device 800 according to an embodiment of the present disclosure is shown. Figure 8 As shown, the electronic device includes: a control unit 810, a processing unit 820, and a storage unit group 830.

[0247] The control unit 810 sends the type of suboperation to be performed, the storage location of the operands of the suboperation, the storage location of the operation result, and the number of the suboperations to the operation unit 820.

[0248] The arithmetic unit 820 determines the state of the memory cell, the number of first cycles, and the number of second cycles. Based on the state of the memory cell, the number of first cycles, the number of second cycles, and the number of sub-operations, it accesses the memory cell group 830.

[0249] The control unit 810 has access to the storage unit group 830. The storage unit group 830 includes at least one storage unit, and the data stored in the storage unit group 830 can be from an external source.

[0250] The arithmetic unit 820 includes: a read / write timing unit 821, a delay unit 822, a logic operation unit 823, and a planning unit 824. The planning unit 824 determines the delay for reading operands, the delay for writing operation results, and the number of third cycles based on the type of sub-operation to be executed, the storage location of the operands and the storage location of the operation result, and the number of sub-operations. Furthermore, the planning unit 824 inputs the delay for reading operands and the delay for writing operation results to the delay unit 822; and inputs the number of third cycles to the read / write timing unit 821.

[0251] The logic operation unit 823 reads operands from the memory cell group 830 according to the instructions of the delay unit 822, and does not perform a write operation to the memory cell group 830 before obtaining the first operation result according to the instructions of the read-write-empty timing unit 821. Then, the logic operation unit 823 performs operations on the operands to obtain the operation result. The logic operation unit 823 writes the operation result to the memory cell group 830 according to the instructions of the delay unit 822, and does not perform a read operand operation from the memory cell group 830 after obtaining the operand of the last sub-operation according to the instructions of the read-write-empty timing unit 821.

Claims

1. A method for accessing memory, characterized in that, include: Determine the number of first ticks required for the operation process of the sub-operation based on the type of the sub-operation to be executed; The storage unit state is determined based on the storage location of the operand and the storage location of the operation result of the sub-operation. The storage unit state is used to characterize whether the operand and the operation result share the same storage unit. Based on the state of the storage unit, determine the number of second ticks required for the sub-operation to access the storage unit; Access the storage unit based on the storage unit status, the first number of beats, the second number of beats, and the parameters included in the operation to be performed; The parameter is the number of sub-operations. Accessing the storage unit based on the storage unit state, the first clock cycle count, the second clock cycle count, and the number of sub-operations includes: Based on the storage unit status, the first number of beats, and the second number of beats, a third number of beats is determined. The third number of beats represents the time taken during the execution of the operation to be performed without accessing the storage unit used to store the operands, and / or the time taken during the execution of the operation to store the result. Based on the state of the storage unit, determine the order of accessing the storage unit when performing the sub-operation; After the operation to be executed begins, the storage unit is accessed according to the access order. Starting from the process of reading operands of the first sub-operation of the operation to be executed, no operation to access the storage unit for the purpose of writing the operation result is performed within the time interval corresponding to the number of the third beats. Also, according to the number of sub-operations, starting from the operation process of the last sub-operation of the operation to be executed, no operation to access the storage unit for the purpose of reading operands is performed within the time interval corresponding to the number of the third beats. After the operation to be executed begins, and after the duration of the third cycle ends, the operation result is written to the storage unit.

2. The method according to claim 1, characterized in that, The operands include a first operand and a second operand. Determining the third tick count based on the storage cell state includes: When the storage unit is in a state where the operands and the operation result do not share a storage unit, the third cycle count is set to the first cycle count. When the storage unit is in a state where any two or more of the first operand, the second operand, and the operation result share a storage unit, the third beat number is increased by the second beat number for each increase of the first beat number, and the initial value of the third beat number is 0.

3. The method according to claim 1, characterized in that, The operands include a first operand and a second operand. Determining the access order of the memory cells when performing the sub-operation based on the memory cell state includes: Based on the state of the storage unit, determine the first delay cycle number of reading the second operand relative to reading the first operand; The access order of the storage units is determined based on the first delay tick number.

4. The method according to claim 1, characterized in that, The operands include a first operand and a second operand. Determining the access order of the memory cells when performing the sub-operation based on the memory cell state includes: Based on the state of the storage unit, determine the second delay cycle number of writing the operation result relative to reading the first operand; The memory cell access order is determined based on the second delay clock cycle number.

5. The method according to claim 1, characterized in that, The step of writing the calculation result to the storage unit after the execution of the calculation to be executed has begun and after the duration of the third cycle has ended includes: Based on the first number of clock cycles and the state of the storage unit, determine the third delay clock cycle from obtaining the result to writing the result into the storage unit; After obtaining the calculation result, the calculation result is written to the storage unit based on the third delay cycle number.

6. The method according to claim 5, characterized in that, The operands include a first operand and a second operand. Determining the third delay cycle from obtaining the result to writing the result into the storage unit, based on the first cycle count and the storage unit state, includes: When the storage unit is in a state where the operands and the operation result do not share a storage unit, the third delay cycle number is determined to be 0; When the storage unit state is such that the first operand and the second operand do not share a storage unit, or the first operand or the second operand shares a storage unit with the operation result, after execution begins from the start of the operation to be executed and has elapsed for the duration of the sum of the first and second clock cycles, if the storage unit to be accessed is a storage unit used to store the operation result, then the third delay clock cycle number is determined to be 0; if the storage unit to be accessed is a storage unit used to store the operand but not used to store the operation result, then the third delay clock cycle number is determined to be 1. When the storage unit state is such that the first operand and the second operand share a storage unit, and the first operand and the operation result do not share a storage unit, after execution starts from the operation to be executed and the execution time is the sum of the first number of clock cycles and the second number of clock cycles, if the storage unit to be accessed is the storage unit used to store the operation result, then the third delay clock cycle number is determined to be 0; if the storage unit to be accessed is the storage unit used to store the operand, then the third delay clock cycle number is determined to be 1. When the storage unit is in a state where the first operand, the second operand, and the operation result share a storage unit, after execution begins from the start of the operation to be executed and the execution time is equal to the sum of the first and second clock cycles, if the accessed storage unit is used to store the operation result, then the third delay clock cycle number is determined to be 0; if the accessed storage unit is used to store the first operand, then the third delay clock cycle number is 2; if the accessed storage unit is used to store the second operand, then the third delay clock cycle number is determined to be 1; in the case of reading operands, reading the first operand precedes reading the second operand.

7. A chip, characterized in that, The chip includes: The first beat count determination unit is used to determine the number of first beats required for the operation process of the sub-operation based on the type of the sub-operation to be executed. A storage unit state determination unit is used to determine the storage unit state based on the storage location of the operand and the storage location of the operation result of the sub-operation. The state is used to characterize whether the operand and the operation result share the storage unit. The second cycle number determination unit is used to determine the number of second cycles required for the sub-operation to access the storage unit process based on the storage unit state. An access control unit is configured to access the storage unit based on the storage unit status, the first clock cycle number, the second clock cycle number, and the parameters included in the operation to be executed. The parameter is the number of sub-operations, and the access control unit includes: The third beat count determination unit is used to determine the third beat count based on the first beat count, the second beat count, and the storage unit status. The third beat count represents the time taken to not access the storage unit used to store the operands and / or the time taken to not access the storage unit used to store the operation result during the execution of the operation to be performed. An access order determination unit is used to determine the access order of the storage unit when performing the sub-operation based on the storage unit state. The first timing unit is configured to access the storage unit according to the access order after the execution of the operation to be executed begins, and from the start of the process of reading operands of the first sub-operation of the operation to be executed, within the time interval corresponding to the number of the third beats, not to perform the operation of accessing the storage unit for the purpose of writing the operation result, and according to the number of sub-operations, from the start of the operation process of the last sub-operation of the operation to be executed, within the time interval of the number of the third beats, not to perform the operation of accessing the storage unit for the purpose of reading operands; The calculation result writing unit is used to start writing the calculation result to the storage unit after the calculation to be executed has started and after the duration of the third cycle has ended.

8. The chip according to claim 7, characterized in that, The chip is a TDDI chip.

9. A means for accessing a memory, characterized in that, include: A display having the chip as described in claim 7 or 8.

10. The means for accessing a memory according to claim 9, characterized in that, The display is at least one of the following: micro light-emitting diode display, sub-millimeter light-emitting diode display, quantum dot light-emitting diode display, and organic light-emitting diode display.

11. The means for accessing a memory according to claim 9, characterized in that, The device is at least one of the following: smartphone, smartwatch, smart bracelet, tablet computer, laptop computer, and in-vehicle computer.

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