Data transmission processing apparatus, method, control apparatus, and readable storage medium

Abstract

Embodiments of the present application provide a data transmission processing device, method, control device and readable storage medium. The data transmission processing device comprises a main processor, a sub-processor and a DMA controller. The sub-processor is electrically connected to the main processor. The current working state of the execution mechanism can be monitored by the sub-processor, and a state signal can be generated. The state signal can be fed back to the main processor. The DMA controller is electrically connected to the main processor. According to the current task scheduling period of the main processor, the state signal is stored in the corresponding DMA controller. The data received by the main processor per unit time can be reduced, and the load of the main processor can be avoided. In addition, by configuring multiple DMA controllers and configuring different scheduling periods for different DMA controllers, the data acquisition of the main processor at the same node and different periods can be realized.

Description

Technical Field

[0001] This invention relates to the field of vehicle communication technology, and in particular to a data transmission processing apparatus, method, control device, and readable storage medium. Background Technology

[0002] With the rapid development of new energy vehicles, the increasing electrification of vehicles, and the advancement of sensor technology, the requirements for vehicle buses have also increased significantly. One or two CAN buses are gradually no longer sufficient to meet the needs of the controller.

[0003] Because the controller's control algorithm is complex and requires extremely high real-time performance, some functions are delegated to the sub-CPU. Communication between the main CPU and the sub-CPU uses UART. After receiving control commands from the main CPU, the sub-CPU sends the collected status data to the main CPU via UART. If a large number of status data need to be sent, and the transmission frequency is high, the main CPU will be heavily loaded with data reception, making data processing very difficult. Summary of the Invention

[0004] The embodiments of the present invention provide a data transmission processing apparatus, method, control device, and readable storage medium, thereby solving the technical problem of excessive load on the main processor during the process of receiving data from the subprocessor.

[0005] In a first aspect, the present invention provides a data transmission processing apparatus, applied to an actuator, through an embodiment of the present invention, the data transmission processing apparatus comprising:

[0006] The main processor is used to generate a target control signal in response to a target instruction from the upper-level controller, wherein the actuator performs a corresponding action in response to the target control signal;

[0007] A subprocessor, electrically connected to the main processor, is used to monitor the current working state of the actuator to generate a status signal and feed the status signal back to the main processor;

[0008] A DMA controller, electrically connected to the main processor, is used to store the status signal according to the current task scheduling cycle of the main processor.

[0009] As an optional implementation, the DMA controller includes multiple controllers, each of which is configured with a unique scheduling cycle; each DMA controller is configured to store the status signal when its corresponding scheduling cycle matches the current task scheduling cycle of the main processor.

[0010] As an optional implementation, each DMA controller is provided with a corresponding receive array, which is used to store the status signal.

[0011] As an optional implementation, the main processor is further configured to: read the status signal from the corresponding DMA controller according to the current task scheduling cycle, and determine whether to send the target control signal to the actuator based on the status signal.

[0012] As an optional implementation, the data transmission processing apparatus further includes: a universal asynchronous transceiver (UAST) electrically connected to the main processor and the subprocessor, wherein the UAST is used to forward the status signal to the main processor.

[0013] As an optional implementation, the data transmission processing device further includes a battery electrically connected to the main processor, the sub-processor, the DMA controller, and the universal asynchronous transceiver, the battery being used to provide power to the main processor, the sub-processor, the DMA controller, and the universal asynchronous transceiver.

[0014] Secondly, through an embodiment of the present invention, a data transmission processing method is provided, applied to any of the data transmission processing devices described in the first aspect. The method includes: when a target instruction is detected by the upper-level controller, controlling the main processor to generate a target control signal; generating a status signal by monitoring the current working state of the actuator through the sub-processor, and feeding back the status signal to the main processor; and storing the status signal in a corresponding DMA controller according to the current task scheduling cycle of the main processor.

[0015] As an optional implementation, the data transmission processing method further includes: reading the status signal from the corresponding DMA controller according to the current task scheduling cycle of the main processor; and determining whether to control the main processor to send the target control signal to the actuator based on the status signal.

[0016] Thirdly, through an embodiment of the present invention, a control device is provided, which is applied to any of the data transmission processing devices in the first aspect. The control device includes a memory, a controller, and code stored on the controller and executable on the controller. When the controller executes the code, it implements any of the embodiments in the second aspect.

[0017] Fourthly, through one embodiment of the present invention, a readable storage medium is provided having a program stored thereon, which, when executed by a processor, implements any of the embodiments of the second aspect.

[0018] One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0019] The main processor can generate target control signals in response to target instructions from the higher-level controller, and the actuators can execute corresponding actions in response to these target control signals. During this process, since the subprocessor is electrically connected to the main processor, it can monitor the current operating status of the actuators and generate status signals, which can then be fed back to the main processor. Using a DMA (Direct Memory Access) controller electrically connected to the main processor, and based on the main processor's current task scheduling cycle, the status signals are stored in the corresponding DMA controller, thereby reducing the amount of data received by the main processor per unit time and preventing excessive load on the main processor.

[0020] In addition, by configuring multiple DMA controllers and setting different scheduling cycles for different DMA controllers, it is possible to enable the main processor to acquire data at different cycles on the same node. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the data transmission processing device structure in an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the data transmission processing device in one embodiment of the present invention;

[0024] Figure 3 This is a flowchart of the data transmission processing method in an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the control device structure in an embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram of a readable storage medium structure in an embodiment of the present invention. Detailed Implementation

[0027] The embodiments of the present invention provide a data transmission processing apparatus, method, control device, and readable storage medium, thereby solving the technical problem of excessive load on the main processor during the process of receiving data from the subprocessor.

[0028] The technical solution provided by the embodiments of the present invention is to solve the above-mentioned technical problems, and the general idea is as follows:

[0029] A subprocessor monitors the current operating status of the actuator and generates a status signal. This subprocessor is electrically connected to the main processor, feeding the status signal back to the main processor. By configuring a DMA controller and electrically connecting the main processor to it, when the main processor receives the feedback status signal, it stores the signal in the corresponding DMA controller according to the main processor's current task scheduling cycle. This reduces the amount of data received by the main processor per unit time, preventing excessive load on the main processor.

[0030] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0031] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0033] In a first aspect, the present invention provides a data transmission processing device, applied to an actuator, capable of sending control signals to the actuator and continuously monitoring the operating status of the actuator. In a specific implementation, the actuator may be a motor.

[0034] Please see below. Figure 1 As shown, the data transmission processing device may include a main processor 100, a sub-processor 200, and a DMA controller 300, with the main processor 100 electrically connected to the sub-processor 200 and the DMA controller 300.

[0035] The main processor 100 is also electrically connected to a higher-level controller. The main processor 100 is used to generate target control signals in response to target instructions from the higher-level controller. In specific implementations, the higher-level controller can be an ECU (Electronic Control Unit). Since the main processor 100 is also electrically connected to an actuator, when the main processor 100 sends the generated target control signal to the actuator, the actuator will respond to the target control signal and perform the corresponding action.

[0036] The subprocessor 200 is electrically connected not only to the main processor 100, but also to the actuator. The subprocessor 200 can continuously monitor the current working status of the actuator, generate a status signal based on the working status of the actuator, and can also feed the status signal back to the main processor 100 through the electrical connection between the subprocessor 200 and the main processor 100.

[0037] The DMA controller 300 is electrically connected to the main processor 100, and can store status signals according to the current task scheduling cycle of the main processor 100. For more efficient storage or retrieval of status signals, as an optional implementation, please refer to [example description needed]. Figure 2 As shown, DMA controllers 300 may include multiple controllers, and each DMA controller 300 is configured with a unique scheduling cycle.

[0038] Since each DMA controller 300 has a different scheduling cycle, when the scheduling cycle of one of the DMA controllers 300 matches the current task scheduling cycle of the main processor 100, the DMA controller 300 can be used to store the status signal. In this way, by storing the status signal within the task scheduling cycle of the main processor 100 in the matching DMA controller 300, the status signal in different task scheduling cycles can be classified and stored.

[0039] Alternatively, as an optional implementation, please continue to refer to [example...]. Figure 2 As shown, each DMA controller 300 can be configured with a corresponding receive array 301 and store status signals through the receive array 301.

[0040] Correspondingly, the main processor 100 can also read status signals from the corresponding DMA controller 300 according to the current task scheduling cycle, and determine whether to send target control signals to the actuator based on the status signals. In specific implementation, the DMA controller 300 can be initialized first, and the main processor 100 can read the status signals in the corresponding DMA controller 300 by calling the SCI receive function.

[0041] For example, if the current task scheduling cycle of the main processor 100 is A, then the status signal in the DMA controller 300 with the scheduling cycle of A is read; if the current task scheduling cycle of the main processor 100 is B, then the status signal in the DMA controller 300 with the scheduling cycle of B is read.

[0042] As an optional implementation, when there are multiple subprocessors 200, in order to simultaneously receive multiple status signals sent by multiple subprocessors 200, please continue to refer to... Figure 2 As shown, the data transmission processing device may further include a Universal Asynchronous Receiver / Transmitter (UART). One end of the UART is electrically connected to the main processor 100, and the other end of the UART is electrically connected to one or more subprocessors 200. The UART is capable of forwarding status signals to the main processor 100.

[0043] Of course, it is understandable that, in order to ensure the normal operation of the data transmission processing device, the data transmission processing device may also include a battery (not shown). By electrically connecting the battery to the main processor 100, the subprocessor 200, the DMA controller 300, and the universal asynchronous transceiver, the battery can provide power to the main processor 100, the subprocessor 200, the DMA controller 300, and the universal asynchronous transceiver.

[0044] This embodiment of the invention utilizes UART and DMA controller 300 to transform the status signals and other data received by the main processor 100 into a one-to-many interface format, allowing the main processor 100 to read status signals and other data from different interface arrays during different task scheduling cycles. In this way, the main processor 100 can process data with different real-time requirements separately, maintaining the integrity and real-time performance of the data received by the main processor 100 without increasing its load.

[0045] Secondly, based on the same inventive concept, this invention provides a data transmission processing method through an embodiment, which can be applied to any of the data transmission processing devices described in the first aspect. Please refer to... Figure 3 As shown, the data transmission processing method may include the following steps:

[0046] Step S301: When the target instruction from the upper-level controller is detected, the main processor is controlled to generate a target control signal.

[0047] Step S302: The subprocessor monitors the current working state of the actuator, generates a status signal, and feeds the status signal back to the main processor.

[0048] Step S303: Store the status signal in the corresponding DMA controller according to the current task scheduling cycle of the main processor.

[0049] As an optional implementation, the status signal can be read from the corresponding DMA controller 300 according to the current task scheduling cycle of the main processor 100, and the main processor 100 can be controlled to send a target control signal to the actuator based on the status signal.

[0050] For specific implementation methods of the data transmission processing method provided in this invention, please refer to any of the implementation methods in the data transmission processing device described above. For the sake of brevity, they will not be described in detail here.

[0051] Thirdly, based on the same inventive concept, the present invention provides a control device through an embodiment of the present invention, which can be applied to any of the data transmission processing devices in the first aspect.

[0052] refer to Figure 4 As shown, the control device provided in this embodiment of the invention includes: a memory 401, a controller 402, and code stored in the memory 401 and executable on the controller 402. When the controller 402 executes the code, it implements any of the embodiments of the data transmission processing method described above.

[0053] Among them, Figure 4 In this document, a bus architecture (represented by bus 400) is used. Bus 400 may include any number of interconnected buses and bridges, linking various circuits including one or more processors represented by controller 402 and memory represented by memory 401. Bus 400 may also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. Bus interface 405 provides an interface between bus 400 and receiver 403 and transmitter 404. Receiver 403 and transmitter 404 may be the same element, i.e., a transceiver, providing a unit for communicating with various other devices over a transmission medium. Controller 402 is responsible for managing bus 400 and general processing, while memory 401 may be used to store data used by controller 402 during operation.

[0054] Fourthly, such as Figure 5 As shown, based on the same inventive concept, the present invention provides a readable storage medium 500 through an embodiment of the present invention, on which a program 501 is stored, which, when executed by a processor, implements any of the embodiments of the data transmission processing method described above.

[0055] The technical solutions in the above embodiments of the present invention have at least the following technical effects or advantages:

[0056] Since the data transmission processing device includes a main processor 100, a sub-processor 200, and a DMA controller 300, and the sub-processor 200 is electrically connected to the main processor 100, the sub-processor 200 can monitor the current working status of the actuator and generate a status signal, which can then be fed back to the main processor 100. Using the DMA controller 300, which is electrically connected to the main processor 100, and according to the current task scheduling cycle of the main processor 100, the status signal is stored in the corresponding DMA controller 300, thereby reducing the amount of data received by the main processor 100 per unit time and preventing excessive load on the main processor 100. Furthermore, by configuring multiple DMA controllers 300 and configuring different scheduling cycles for different DMA controllers 300, data acquisition by the main processor 100 at different cycles on the same node can be achieved.

[0057] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable code.

[0058] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer instructions. These computer instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0059] These computer instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0060] These computer instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0061] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0062] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A data transmission processing apparatus, characterized in that, Applied to an actuator, the data transmission processing device includes: The main processor is used to generate a target control signal in response to a target instruction from the upper-level controller, wherein the actuator performs a corresponding action in response to the target control signal; A subprocessor, electrically connected to the main processor, is used to monitor the current working state of the actuator to generate a status signal and feed the status signal back to the main processor; A DMA controller, electrically connected to the main processor, is used to store the status signal according to the current task scheduling cycle of the main processor. The DMA controllers include multiple controllers, and each DMA controller is configured with a unique scheduling period. Each of the DMA controllers is configured to store the status signal when its corresponding scheduling period matches the current task scheduling period of the main processor.

2. The apparatus as claimed in claim 1, characterized in that, Each DMA controller is provided with a corresponding receive array, which is used to store the status signals.

3. The apparatus as described in claim 1 or 2, characterized in that, The main processor is also used for: Based on the current task scheduling cycle, the status signal is read from the corresponding DMA controller, and based on the status signal, it is determined whether to send the target control signal to the actuator.

4. The apparatus as described in claim 1 or 2, characterized in that, Also includes: A universal asynchronous transceiver (UAST) is electrically connected to the main processor and the subprocessor, and the UAST is used to forward the status signal to the main processor.

5. The apparatus as described in claim 4, characterized in that, Also includes: A battery is electrically connected to the main processor, the sub-processor, the DMA controller, and the universal asynchronous transceiver, and the battery is used to provide power to the main processor, the sub-processor, the DMA controller, and the universal asynchronous transceiver.

6. A data transmission processing method, characterized in that, Applied to the data transmission processing apparatus as described in any one of claims 1-5, the method comprises: When the target instruction from the upper-level controller is detected, the main processor is controlled to generate a target control signal. The subprocessor monitors the current working state of the actuator, generates a status signal, and feeds the status signal back to the main processor. The status signal is stored in the corresponding DMA controller according to the current task scheduling cycle of the main processor.

7. The method as described in claim 6, characterized in that, Also includes: The status signal is read from the corresponding DMA controller according to the current task scheduling cycle of the main processor; Based on the status signal, determine whether to control the main processor to send the target control signal to the actuator.

8. A control device, characterized in that, Applied to the data transmission processing apparatus as described in any one of claims 1-5, the control apparatus includes a memory, a controller, and code stored on the controller and executable on the controller, wherein the controller executes the code to implement the method of claim 6 or 7.

9. A readable storage medium having a program stored thereon, characterized in that, When the program is executed by the processor, it implements the method of claim 6 or 7.

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