A test method based on serial communication

Abstract

The application discloses a kind of test methods based on serial communication, and at least including SoC chip, FPGA chip and AD chip for the product to be tested, which comprises: the SoC chip is connected with host computer, and host computer sends test instruction to the SoC chip;The SoC chip is connected with FPGA chip, and the SoC chip and FPGA chip realize address space mapping through EMIF bus, the SoC chip receives the test instruction, and according to the content of the test instruction, controls the FPGA chip to execute on-off quantity control and / or gathers the state information of the product to be tested;The SoC chip receives the state information and uploads to host computer.The application does not need additional device, and just with the help of USB to RS422 equipment, the control and monitoring of the product to be tested can be realized, which is simple and convenient, easy to realize, portable, and saves production cost.

Description

Technical Field

[0001] This application relates to the field of aerospace measurement and control technology, and more specifically, to a test method based on serial communication. Background Technology

[0002] With the continuous development of terminal systems, the number and complexity of models are increasing, leading to higher requirements for testing systems. To meet these complex testing needs, current testing systems often adopt a "PC host + communication module + other functional modules + host computer testing software" approach, with the testing software controlling the product testing process. Testing systems designed based on this approach inevitably suffer from high cost and large size, resulting in limited production quantities, inconvenience in portability, and difficulty in meeting the testing and maintenance needs of large-scale products. Summary of the Invention

[0003] To address at least one deficiency or improvement need in the prior art, this invention provides a testing method based on serial communication. It does not require additional devices and can achieve control and monitoring of the product under test using only a USB to RS422 converter. It is simple, convenient, easy to implement, portable, and saves production costs.

[0004] To achieve the above objectives, according to a first aspect of the present invention, a testing method based on serial communication is provided. The product under test includes at least a SoC chip, an FPGA chip, and an AD chip. The method includes:

[0005] The SoC chip is connected to the host computer, and the host computer sends test commands to the SoC chip;

[0006] The SoC chip is connected to the FPGA chip, and the SoC chip and the FPGA chip achieve address space mapping through the EMIF bus. The SoC chip receives the test command and controls the FPGA chip to perform switch control and / or collect the status information of the product under test according to the content of the test command.

[0007] The SoC chip receives the status information and uploads it to the host computer.

[0008] Furthermore, in the above-mentioned test method based on serial communication, the FPGA chip is connected to the AD chip, the FPGA chip controls the AD chip to acquire analog signals, and sends the analog signals to the SoC chip.

[0009] Furthermore, in the above-mentioned test method based on serial communication, the SoC chip controls the FPGA chip to perform corresponding switch quantity closing or opening by writing 0 or writing 1 to a specified address; the SoC chip obtains the status signal and / or analog signal of the specified address by performing a read operation on the specified address.

[0010] Furthermore, in the above-mentioned test method based on serial communication, the host computer is connected to a USB-to-RS422 device, and the USB-to-RS422 device is connected to the SoC chip; the host computer communicates with the SoC chip via serial communication through the USB-to-RS422 device, and the USB-to-RS422 device converts the test instructions into serial command data and sends it to the SoC chip.

[0011] Furthermore, in the above-mentioned test method based on serial communication, the serial communication protocol of the serial command data includes command type and operation type, and the command type includes mode switching and test control command type and switch quantity control command type.

[0012] Furthermore, in the above-mentioned serial communication-based testing method, the mode switching and test control command type values ​​are fixed values, and the operation type values ​​corresponding to the mode switching and test control command types are 0x2C, 0x2D, ​​and 0xCC. 0x2C is used to control the SoC chip to switch from the current state to the serial unit test mode, 0x2D is used to control the SoC chip to switch from the current state to the switch quantity test mode, and 0xCC is used to control the SoC chip to start executing the serial unit test.

[0013] Furthermore, in the above-mentioned test method based on serial communication, the switching control command type has multiple values, which are used to perform corresponding switching control according to the address space mapped by the EMIF bus, including at least ignition timing command control, detonation timing command control, PWM output enable command control, and reset lockout command control.

[0014] Furthermore, in the above-mentioned test method based on serial communication, when the FPGA chip switches to the serial unit test mode, it performs serial communication test, performs on or off operations on the switch quantities in the specified order in the SoC chip, and feeds back the status information of the product under test through serial communication.

[0015] Furthermore, in the above-mentioned serial communication-based testing method, the SoC chip formats the status information of the product under test and feeds it back to the host computer in string form for display.

[0016] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0017] This invention provides a serial communication-based testing method. This method establishes a serial communication protocol between a host computer and the SoC chip of the product under test, parses the test data sent by the host computer into serial data, controls the FPGA chip to switch on and off to control and collect the status information of the product under test. No additional devices are required. Only a USB to RS422 converter is needed to control and monitor the product under test. It is simple, convenient, easy to implement, portable, and saves production costs. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of a serial communication testing method provided in an embodiment of this application;

[0020] Figure 2 A flowchart illustrating the serial communication testing method provided in this application embodiment. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0022] The terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0023] This application provides a testing method based on serial communication. Figure 1 Please refer to the schematic diagram of a serial communication testing method provided in this application embodiment. Figure 1 The product under test includes at least a SoC chip, an FPGA chip, and an AD chip. The host computer communicates with the SoC chip via serial port assistant software, and controls the FPGA chip to acquire status signals and perform switching operations according to a defined communication protocol. This testing method includes the following steps:

[0024] (1) The SoC chip is connected to the host computer, and the host computer sends test commands to the SoC chip;

[0025] Specifically, the host computer includes serial port assistant software, which performs serial communication and converts the received data into text.

[0026] Furthermore, the host computer connects to a USB-to-RS422 adapter, which in turn connects to the SoC chip. The host computer communicates with the SoC chip via serial communication through the USB-to-RS422 adapter, which converts the test commands output by the host computer into serial command data and sends it to the SoC chip.

[0027] In one specific embodiment, the USB to RS422 device is the MOXA UPort1450, but other USB to RS422 devices can also be used as long as they meet the communication requirements.

[0028] (2) The SoC chip is connected to the FPGA chip. The SoC chip and the FPGA chip achieve address space mapping through the EMIF bus. The SoC chip receives test instructions and controls the FPGA chip to perform switch control and / or collect the status information of the product under test according to the content of the test instructions.

[0029] Furthermore, the FPGA chip is also connected to the AD chip. The FPGA chip controls the AD chip to acquire analog signals and sends the analog signals to the SoC chip.

[0030] Specifically, the SoC chip implements address space mapping through the EMIF bus interface to communicate with the FPGA chip. The SoC chip controls the FPGA chip to perform corresponding switch operations by writing 0 or 1 to a specified address, and the SoC chip obtains the status signal and / or analog signal of the specified address by reading from the specified address.

[0031] Furthermore, the serial communication protocol based on serial port command data includes command types and operation types. Command types include mode switching and test control command types and switch quantity control command types. Command types are unsigned 32-bit bits, and operation types are unsigned 8-bit bits. As shown in Table 1, the mode switching and test control command type has a fixed value of 0x405100FF, and the switch quantity control command type has values ​​of 0x40510000, 0x40510002, ..., 0x40510048, and 0x4051004A. These represent the corresponding switch quantity control space addresses mapped by the FPGA through the EMIF bus, including at least ignition timing command control, detonation timing command control, PWM output enable command control, and reset / lockdown command control. The operation type varies depending on the command type. When the command type is a mode switching or test control command, the operation type value can be one of three types: 0x2C, 0x2D, ​​or 0xCC. 0x2C means switching to serial port unit test mode, 0x2D means switching to switch quantity test mode, and 0xCC means starting serial port unit test. When the command type is a switch quantity control command, the data portion can be one of two types: 0x00 or 0x01. 0x00 means switch quantity is off, and 0x01 means switch quantity is on.

[0032] Table 1. Comparison of Serial Communication Protocols

[0033]

[0034] Serial port unit tests can only be executed after switching to serial port unit test mode. This test sequentially performs on / off operations on all switches according to the specified order and combination order in the SOC chip, and feeds back the test results via serial port. Switch quantity tests can only be executed after switching to switch quantity test mode. This test allows any specific switch quantity to be specified for on / off operation, and feeds back the test results via serial port.

[0035] Figure 2 A flowchart illustrating the serial communication testing method provided in this application embodiment. Upon receiving serial port command data, the SoC chip executes the following process:

[0036] Step 1: SoC chip initialization. When serial port command data is received, the serial port data is parsed.

[0037] Step 2: Set the timing period to control the FPGA chip's read digital input retrieval status and analog input acquisition status.

[0038] Step 3: Determine if the command type is mode switching and test control;

[0039] Step 4: Read the fifth byte of the serial port command data;

[0040] Step 5: When the operation type value is 0x2C, switch to serial port unit test mode;

[0041] Step 6: When the operation type value is 0x2D, ​​switch to switch quantity test mode;

[0042] Step 7: When the operation type value is 0x2C, if the current mode is the start serial port unit test mode, then all switch quantities will be opened or closed sequentially according to the given order and combination order in the SoC chip.

[0043] (3) The SoC chip receives the status information and uploads it to the host computer.

[0044] Specifically, the SoC chip formats the status information of the product under test and sends it back to the host computer in string form for display.

[0045] The following are some specific examples.

[0046] Example 1:

[0047] refer to Figure 1 As shown, the present invention provides a test method based on serial communication, which further includes powering the product under test with a 28V DC power supply. The product contains a SoC chip, an FPGA chip, an AD chip, etc. The SoC chip includes an RS422 serial communication interface. The SoC chip and the FPGA chip communicate through an EMIF bus interface. The FPGA chip communicates with the AD chip to collect the product's voltage status values. The FPGA code implements switch control and status acquisition. The host computer is connected to the RS422 serial communication interface of the SoC through a USB to RS422 adapter. The PC transmits data and receives and displays data through serial port assistant software.

[0048] The FPGA software encodes all the switching signals and acquires their status. By responding to write operations on the SoC chip on the EMIF bus (where 0 indicates off and 1 indicates on, distinguished by different addresses), it controls the corresponding output pin of the FPGA chip to be low / high level. By responding to read operations on the SoC chip on the EMIF bus (distinguished by different addresses), it transmits the high / low level status of the corresponding input pin of the FPGA chip to the EMIF bus and feeds it back to the SoC chip. The FPGA chip communicates with the AD chip to acquire analog signals and converts them into the actual voltage value of the product voltage using a calculation formula, which is then transmitted to the EMIF bus for the SoC chip to read periodically.

[0049] After the SoC chip software is powered on, it initializes the EIMF bus and RS422 serial port interface. It connects to the FPGA chip through the EMIF bus and the host computer through the RS422 serial port interface. The software code of the SoC chip implements the serial port receiving data loop query and parsing function, and performs related operations according to the parsed instructions. After the operation is completed, the serial port formats and outputs status information.

[0050] Example 2:

[0051] Referring to the serial communication protocol shown in Table 1, the SoC software parses the received serial command data and finds a complete data frame that conforms to the communication protocol. When the SoC software receives the "0x405100FF" mode switching and test control type command frame, it performs corresponding operations based on the fifth byte data. When the fifth byte is "0x2D", the SoC software switches the working mode to the switch quantity test mode.

[0052] When the SoC software switches to switch quantity test mode, the test steps are as follows:

[0053] The SoC software parses the received serial port data, finding a complete data frame conforming to the communication protocol. The first four bytes form an address mapped to the EMIF bus, and the fifth byte is either "0" or "1," indicating a "close" or "open" operation. Based on the specific content of the received data frame, it communicates with the FPGA via a write operation on the EMIF bus to control the switching quantity to close or open. After the write operation is executed, it waits 200ms for the switch quantity's retrieval status and the analog quantity's status to stabilize before formatting and outputting the status information to the host computer via serial communication.

[0054] The SoC software code implements the function of periodically reading the status of digital and analog signals every 1ms. By setting a timer interrupt, it communicates with the FPGA chip every 1ms through the read operation on the EMIF bus to read the status of digital and analog signals and update the latest status values.

[0055] The SoC software implements the serial port formatted output interface function UART_printf(), which outputs the command count value, write operation information, read switch quantity retrieval status and latest analog quantity status information in string format through the UART_printf() interface.

[0056] The host computer connects to the serial port interface of the SoC chip via a USB to RS422 adapter. The host computer actively sends serial port command data frames to the SoC chip through the serial port assistant software. After the SoC software completes the above serial port data parsing and read / write operations on the EMIF bus, it receives the serial port formatted string data output by the SoC chip and displays it in string form on the host computer's serial port assistant software interface.

[0057] Example 3:

[0058] Referring to the serial communication protocol shown in Table 1, the SoC software parses the received serial data and finds a complete data frame that conforms to the communication protocol. When the SoC software receives the "0x405100FF" mode switching and test control type command frame, it performs corresponding operations based on the fifth byte of data. When the fifth byte is "0x2C", the SoC software switches its working mode to serial unit test mode.

[0059] When the SoC software switches to serial port unit test mode, the test steps are as follows:

[0060] The SoC software parses the received serial port data and finds a complete data frame that conforms to the communication protocol. When the SoC software receives the "0x405100FF" mode switching and test control type command frame and its fifth byte data is 0xCC, it starts executing the unit test.

[0061] During unit testing, the SoC software sequentially performs open or close operations on all switch quantities according to a given order and combination order. Each time an open or close operation is performed, the SoC software outputs the status information of the test process in a formatted manner through the serial port.

[0062] The host computer connects to the SoC serial port interface via a USB to RS422 adapter. It receives the serial port formatted string data output by the SoC through serial port assistant software and displays it as a string on the PC serial port assistant software interface.

[0063] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0064] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0065] The foregoing description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of embodiments of this disclosure upon considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described herein. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

[0066] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A testing method based on serial communication, wherein the product under test includes at least a SoC chip, an FPGA chip, and an AD chip, characterized in that, include: The SoC chip is connected to the host computer, and the host computer sends test commands to the SoC chip; The SoC chip is connected to the FPGA chip, and the SoC chip and the FPGA chip achieve address space mapping through the EMIF bus. The SoC chip receives the test command and controls the FPGA chip to perform switch control and / or collect the status information of the product under test according to the content of the test command. The SoC chip receives the status information and uploads it to the host computer; wherein, after the SoC chip performs a write operation, it waits for a preset time to allow the switch quantity retrieval status and analog quantity status to stabilize before reading and uploading the status information. The host computer is connected to a USB-to-RS422 converter, and the USB-to-RS422 converter is connected to the SoC chip. The host computer communicates with the SoC chip via serial port through the USB-to-RS422 converter, and the USB-to-RS422 converter converts the test instructions into serial port command data and sends it to the SoC chip. The FPGA chip is connected to the AD chip, and the FPGA chip controls the AD chip to acquire analog signals and send the analog signals to the SoC chip. The SoC chip controls the FPGA chip to perform corresponding switch operations by writing 0 or 1 to a specified address; the SoC chip obtains the status signal and / or analog signal of the specified address by reading from the specified address.

2. The test method based on serial communication as described in claim 1, wherein, The serial communication protocol for the serial port command data includes command type and operation type. The command type includes mode switching and test control command type and switch quantity control command type.

3. The test method based on serial communication as described in claim 2, wherein, The mode switching and test control command type values ​​are fixed values. The operation type values ​​corresponding to the mode switching and test control command types are 0x2C, 0x2D and 0xCC. 0x2C is used to control the SoC chip to switch from the current state to the serial port unit test mode. 0x2D is used to control the SoC chip to switch from the current state to the switch quantity test mode. 0xCC is used to control the SoC chip to start executing the serial port unit test.

4. The test method based on serial communication as described in claim 3, wherein, The switching control command type has various values, which are used to perform corresponding switching control according to the address space mapped by the EMIF bus, including at least ignition timing command control, detonation timing command control, PWM output enable command control and reset lockout command control.

5. The test method based on serial communication as described in claim 4, wherein, When the SoC chip switches to the serial port unit test mode, it performs serial communication test, sequentially performs on or off operations on the switch quantities according to the specified order in the SoC chip, and feeds back the status information of the product under test through serial communication.

6. The test method based on serial communication as described in claim 5, wherein, The SoC chip formats the status information of the product under test and sends it back to the host computer in string form for display.

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