A memory access method and apparatus

Abstract

The application discloses a memory access method and device, which can establish a first access mapping relationship between a plurality of processors and a first storage area, and the plurality of processors can access the first storage area through the first access mapping relationship; then, a second access mapping relationship between each processor and a second storage area thereof is established; then, when the processor accesses the first storage area, a first access path is determined according to the first access mapping relationship and the second access mapping relationship; the processor accesses the first storage area according to the first access path; and each second storage area is arranged in a same storage area. On the one hand, the second storage area is arranged in the same storage area, and the second storage area of each processor can be configured according to a data storage amount; on the other hand, the first access path is determined according to the first access mapping relationship and the second access mapping relationship, so that the access speed of the processor accessing the first storage area is improved.

Description

Technical Field

[0001] This application relates to the technical field of memory access, and more particularly to memory access methods and apparatus. Background Technology

[0002] In related technologies, during system software development using multi-core MCUs, core-coupled memory (CCM) is frequently used for fast access via the internal bus. However, the size of the CCM for most CPUs is fixed and non-configurable. This results in situations where one CPU's data area is too large to be used, while another CPU's data volume is too small to be utilized. Because this area is non-configurable, the overflowing data can only be accessed by placing it in static random-access memory (SRAM) at the external bus address, which reduces access speed. Summary of the Invention

[0003] This application provides a memory access method, apparatus, computer-readable storage medium, and electronic device that can solve the problem of non-configurable storage areas and improve memory access speed.

[0004] The technical effect to be achieved in this application is accomplished through the following solution:

[0005] In a first aspect, this application provides a memory access method applied to a multi-core processing system, the multi-core processing system including multiple processors and a first storage area, the multiple processors being able to access the first storage area, and each processor having a second storage area, including:

[0006] A first access mapping relationship is established between the multiple processors and the first storage area, and the multiple processors can access the first storage area through the first access mapping relationship;

[0007] Establish a second access mapping relationship between each processor and its second memory area;

[0008] When the processor accesses the first memory area, it determines the first access path based on the first access mapping relationship and the second access mapping relationship;

[0009] The processor accesses the first storage area according to the first access path;

[0010] When the processor accesses the second memory area, it determines the second access path according to the second access mapping relationship;

[0011] The processor accesses the second storage area according to the second access path;

[0012] Each of the second storage areas is located in the same storage region.

[0013] Optionally, before the step of establishing a second access mapping relationship between each processor and its second memory area, the method includes:

[0014] Each of the second storage areas is located in the same storage region, and each of the second storage areas is communicatively connected to the other.

[0015] Optionally, the step of setting each of the second storage areas in the same storage region and communicating between each of the second storage areas includes:

[0016] Each processor stores data in the same storage area, and when each processor stores data, it establishes a second access mapping relationship with the storage area where the data is stored, and the storage area serves as the second storage area of ​​the processor.

[0017] Optionally, the first storage area and the second storage area are communicatively connected.

[0018] Optionally, the processor is connected to the first storage area via a first communication bus; and / or the processor is connected to the second storage area via a second communication bus.

[0019] Optionally, when the processor accesses the first storage area, determining the first access path based on the first access mapping relationship and the second access mapping relationship includes:

[0020] When the processor accesses the first memory area, it determines the first access address based on the first access mapping relationship;

[0021] The first access path is determined based on the first access address and the second access mapping relationship.

[0022] Optionally, determining the first access path based on the first access address and the second access mapping relationship includes:

[0023] The second access address is determined based on the second access mapping relationship;

[0024] The first access path is determined based on the first access address and the second access address.

[0025] Secondly, this application provides a memory access device, comprising:

[0026] The first establishment unit is used to establish a first access mapping relationship between the plurality of processors and the first storage area, and the plurality of processors can access the first storage area through the first access mapping relationship;

[0027] The second establishment unit establishes a second access mapping relationship between each processor and its second storage area;

[0028] The determining unit is configured to determine a first access path based on the first access mapping relationship and the second access mapping relationship when the processor accesses the first storage area, and / or determine a second access path based on the second access mapping relationship when the processor accesses the second storage area.

[0029] Thirdly, this application provides a computer-readable storage medium including execution instructions, which, when executed by a second processor of an electronic device, cause the electronic device to perform any of the methods described in the first aspect.

[0030] Fourthly, this application provides an electronic device, a second processor;

[0031] Memory used to store instructions executable by the second processor;

[0032] The second processor is configured to read the executable instructions from the memory and execute the instructions to implement any of the methods described in the first aspect.

[0033] This application provides a memory access method and apparatus. A first access mapping relationship is established between multiple processors and a first storage area, allowing the processors to access the first storage area. Next, a second access mapping relationship is established between each processor and a second storage area. Then, when a processor accesses the first storage area, a first access path is determined based on the first and second access mapping relationships; the processor accesses the first storage area according to the first access path. When a processor accesses the second storage area, a second access path is determined based on the second access mapping relationship, and the processor accesses the second storage area according to the second access path. Each second storage area is located in the same storage region. On one hand, by locating the second storage areas in the same storage region, the second storage area of ​​each processor can be configured according to the data storage volume. On the other hand, by determining the first access path based on the first and second access mapping relationships, the access speed of the processor accessing the first storage area is improved.

[0034] The further effects of the aforementioned non-conventional preferred method will be explained below in conjunction with specific embodiments. Attached Figure Description

[0035] To more clearly illustrate the embodiments of this application or the existing technical solutions, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A flowchart illustrating a memory access method provided in one embodiment of this application;

[0037] Figure 2 A flowchart illustrating another memory access method provided in an embodiment of this application;

[0038] Figure 3 This is a schematic diagram of the structure of a memory access device provided in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] In related technologies, during system software development using multi-core MCUs, core-coupled memory (CCM) is frequently used for fast access via the internal bus. However, the size of the CCM for most CPUs is fixed and non-configurable. This results in situations where one CPU's data area is too large to be used, while another CPU's data volume is too small to be utilized. Because this area is non-configurable, the overflowing data can only be accessed by placing it in static random-access memory (SRAM) at the external bus address, which reduces access speed.

[0042] In view of this, this application provides a memory access method applied to a multi-core processing system, the multi-core processing system including multiple processors and a first storage area, the multiple processors being able to access the first storage area, and each processor having a second storage area. In the following embodiments, the first storage area may be a kernel-coupled storage area, and the second storage area may be a static random access memory, but this application does not limit the specific type of memory for the first and second storage areas, and they can be designed according to actual design needs.

[0043] See Figure 1 The image shows a specific embodiment of the memory access method provided in this application. In this embodiment, the method includes steps S01, S03, S04, S05, S06, and S07.

[0044] Step S01: Establish a first access mapping relationship between the plurality of processors and the first storage area, and the plurality of processors can access the first storage area through the first access mapping relationship;

[0045] Step S03: Establish a second access mapping relationship between each processor and its second memory area;

[0046] Step S04: When the processor accesses the first storage area, a first access path is determined according to the first access mapping relationship and the second access mapping relationship;

[0047] Step S05: The processor accesses the first storage area according to the first access path;

[0048] Step S06: When the processor accesses the second memory area, a second access path is determined according to the second access mapping relationship;

[0049] Step S07: The processor accesses the second storage area according to the second access path;

[0050] Each of the second storage areas is located in the same storage region.

[0051] Multiple processors establish a first access mapping relationship with the first storage area. This first access mapping relationship includes a mapping table of access addresses between the processors and the first storage area. In one example, processor 1 corresponds to access address 0x70010000 of its first storage area 1. When processor 1 accesses the first storage area 1, it accesses it based on access address 0x70010000. Similarly, a second access mapping relationship is established between each processor and its second storage area. This second access mapping relationship includes a mapping table of access addresses between the processors and the second storage area. In one example, processor 1 corresponds to access address 0x10010000 of its second storage area 1. When processor 1 accesses the second storage area 1, it accesses it based on access address 0x10010000. The processor accesses the second storage area via an internal bus, which offers high access speed. The processor directly accesses the first memory area via the external bus, which is slow. To improve the access speed of the processor to the first memory area, when the processor needs to access the first memory area, it uses the access address offset in the first access mapping relationship to the access address in the second access mapping relationship. This allows the processor to access the first memory area via the internal bus, thus improving the access speed.

[0052] Each of the second storage areas is located in the same storage region. The configuration of the second storage area for each processor can be based on the amount of data stored. That is, when each processor stores data and / or instructions, it stores them in the same storage region. The region where the data stored by the processor is stored is designated as the processor's second storage area. In one example, processor 1 stores data 1 in the same storage region where all the second storage areas are located. The storage region where data 1 is stored is designated as the processor 1's second storage area, and the second storage area is assigned the access address 0x10010000.

[0053] In some embodiments, before establishing a second access mapping relationship between each processor and its second memory area in step S03, the method includes:

[0054] Step S02: Set each of the second storage areas in the same storage area, and connect each of the second storage areas to each other.

[0055] It should be noted that step S02 is optional and can be omitted. The specific steps of step S02 can be set according to the actual situation. After executing step S01, step S03 can be executed. In this embodiment, after executing step S01, steps S02 and / or step S03 can be executed.

[0056] Setting each of the second storage areas in the same storage region facilitates the configuration of the storage space for each processor, allowing the storage space to be configured according to the storage needs of each processor.

[0057] In some embodiments, step S02, which involves setting each of the second storage areas in the same storage area and communicating between each of the second storage areas, includes:

[0058] Step S021: The data of each processor is stored in the same storage area, and when each processor stores data, it establishes a second access mapping relationship with the storage area where the data is stored, and the storage area is used as the second storage area of ​​the processor.

[0059] The storage area can be a storage unit with a storage capacity of 1MB, and the storage units are arranged consecutively with adjacent storage units connected. The storage unit can be configured as the processor's second memory according to the processor's data volume. In one example, multiple processors are designated as processor 1, processor 2, ..., processor N. Processor 1 has a second storage area 1, processor 2 has a second storage area 2, ..., processor N has a second storage area N. Processor 1 has 6MB of data, so the six connected storage units in the storage area are designated as processor 1's second storage area 1. Similarly, processor 2 has 8MB of data, so the eight connected storage units in the storage area are designated as processor 2's second storage area 2, and so on.

[0060] Furthermore, if data is deleted from a processor, the corresponding second storage area will become a storage area to be configured. In one example, if two storage units of data are deleted from the second storage area 2 of processor 2, then these two storage units will be used as a storage area to be configured and will no longer belong to the second storage area 2. This setting facilitates the configuration of the second storage areas of multiple processors and allows for the rational allocation of storage.

[0061] In some embodiments, the first memory area and the second memory area are communicatively connected. This configuration facilitates the processor's access to the first memory area via an internal bus connected to the second memory area, improving the processor's access speed to the first memory. In one example, processor 1 accesses the first memory area 1, with the access address of the first memory area being 0x70010000. An address offset of 0x6000000 is applied to the access address 0x70010000 to determine the access address of the second memory area 1 as 0x10010000. After accessing the second memory area 1 via access address 0x10010000, processor 1 accesses the first memory area 1 via access address 0x70010000. This allows access to the first memory area 1 via the internal bus, improving access speed.

[0062] Furthermore, the processor is connected to the first memory area via a first communication bus; and / or the processor is connected to the second memory area via a second communication bus. In one example, the second communication bus is an internal bus with fast access and data transmission speeds. The first communication bus is an external bus with slower communication speeds, but it can be used for communication when the second communication bus is not available, thereby improving the overall access speed of the multi-core processing system.

[0063] In some embodiments, step S04, when the processor accesses the first storage area, determines a first access path based on the first access mapping relationship and the second access mapping relationship, including:

[0064] Step S041: When the processor accesses the first memory area, the first access address is determined according to the first access mapping relationship;

[0065] Step S042: Determine the first access path based on the first access address and the second access mapping relationship.

[0066] In one example, when processor 1 accesses the first memory area 1, the first access address 0x70010000 is determined according to the first access mapping relationship. The first access mapping relationship includes a mapping table of access addresses between all processors and all first memory areas. When it is determined that processor 1 needs to access first memory area 1, the access address of the first memory area is found through the mapping table.

[0067] Further, the first access path is determined based on the first access address and the second access mapping relationship, which can be used to determine the second access address based on the second access mapping relationship; then, the first access path is determined based on the first access address and the second access address. To quickly access the first memory area via the internal bus, the access address of the first memory area can be offset to the access address of the second memory area. First, the first access address is determined based on the first access mapping relationship, and the second access address is determined based on the second access mapping relationship. The first access address is then offset to obtain the second access address. Since the first memory area is connected to the second memory area, the first access path is for the processor to access the first memory area where the first access address is located via the second memory area based on the second access address. That is, the internal bus connecting the processor and the second memory area is used to access the first memory area, improving the speed of the processor accessing the first memory.

[0068] like Figure 3 The image shows a specific embodiment of the memory access device described in this application. The device described in this embodiment is used to execute... Figures 1-2The physical apparatus of the method is essentially the same as that in the above embodiments, and the corresponding descriptions in the above embodiments are also applicable to this embodiment. The apparatus in this embodiment includes a first establishing unit, a second establishing unit, and a determining unit.

[0069] The first establishment unit is used to establish a first access mapping relationship between the plurality of processors and the first storage area, and the plurality of processors can access the first storage area through the first access mapping relationship;

[0070] The second establishment unit establishes a second access mapping relationship between each processor and its second storage area;

[0071] The determining unit is configured to determine a first access path based on the first access mapping relationship and the second access mapping relationship when the processor accesses the first storage area, and / or determine a second access path based on the second access mapping relationship when the processor accesses the second storage area.

[0072] Optionally, the memory access device further includes a setting unit, the setting unit being configured to:

[0073] Each of the second storage areas is located in the same storage region, and each of the second storage areas is communicatively connected to the other.

[0074] Optionally, the setting unit is used for:

[0075] Each processor stores data in the same storage area, and when each processor stores data, it establishes a second access mapping relationship with the storage area where the data is stored, and the storage area serves as the second storage area of ​​the processor.

[0076] Optionally, the determining unit is configured to:

[0077] When the processor accesses the first memory area, it determines the first access address based on the first access mapping relationship;

[0078] The first access path is determined based on the first access address and the second access mapping relationship.

[0079] Optionally, the determining unit is configured to:

[0080] The second access address is determined based on the second access mapping relationship;

[0081] The first access path is determined based on the first access address and the second access address.

[0082] Figure 4This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. At the hardware level, the electronic device includes a second processor, and optionally also includes an internal bus, a network interface, and a memory. The memory may include RAM, such as high-speed random-access memory (RAM), or non-volatile memory, such as at least one disk storage device. Of course, the electronic device may also include other hardware required for other services.

[0083] The second processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 4 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0084] Memory is used to store execution instructions. Specifically, execution instructions are computer programs that can be executed. Memory may include main memory and non-volatile memory, and provides execution instructions and data to a second processor.

[0085] In one possible implementation, the second processor reads the corresponding execution instructions from non-volatile memory into memory and then executes them. Alternatively, it may obtain the corresponding execution instructions from other devices to form a memory access device at the logical level. The second processor executes the execution instructions stored in memory to implement the memory access method provided in any embodiment of this application through the executed instructions.

[0086] The above is as stated in this application. Figure 3The method executed by the memory access device provided in the illustrated embodiment can be applied to or implemented by a second processor. The second processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the hardware or by instructions in software within the second processor. The second processor can be a general-purpose second processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose second processor can be a micro-second processor or any conventional second processor.

[0087] The steps of the method disclosed in the embodiments of this application can be directly manifested as hardware decoding by a second processor, or as a combination of hardware and software modules in the second decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the second processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0088] This application also proposes a computer-readable storage medium including executable instructions. When a second processor of an electronic device executes the executable instructions, the electronic device is enabled to perform the memory access method provided in any embodiment of this application, specifically for performing, as... Figure 1 or Figure 2 The method shown.

[0089] The electronic devices described in the foregoing embodiments may be computers.

[0090] Those skilled in the art will understand that the embodiments of this application can be provided as methods or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or a combination of software and hardware.

[0091] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0092] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.

Claims

1. A memory access method applied to a multi-core processing system, the multi-core processing system comprising multiple processors and a first storage area, wherein the multiple processors can access the first storage area, and each processor is provided with a second storage area, characterized in that, include: A first access mapping relationship is established between the multiple processors and the first storage area, and the multiple processors can access the first storage area through the first access mapping relationship; Establish a second access mapping relationship between each processor and its second memory area; When the processor accesses the first memory area, it determines a first access address based on the first access mapping relationship, and obtains a second access address by offsetting the first access address based on the second access mapping relationship; and determines a first access path based on the first access address and the second access address. The first access path is that the processor accesses the first memory area where the first access address is located through the second memory area based on the second access address; The processor accesses the first storage area according to the first access path; When the processor accesses the second memory area, it determines the second access path according to the second access mapping relationship; The processor accesses the second storage area according to the second access path; Each of the second storage areas is located in the same storage region.

2. The memory access method as described in claim 1, characterized in that, Before the step of establishing a second access mapping relationship between each processor and its second storage area, the method includes: Each of the second storage areas is located in the same storage region, and each of the second storage areas is communicatively connected to the other.

3. The memory access method as described in claim 2, characterized in that, The step of setting each of the second storage areas in the same storage region and communicating between each of the second storage areas includes: Each processor stores data in the same storage area, and when each processor stores data, it establishes a second access mapping relationship with the storage area where the data is stored, and the storage area serves as the second storage area of ​​the processor.

4. A memory access method as described in claim 2, characterized in that, The first storage area and the second storage area are communicatively connected.

5. A memory access method as described in claim 4, characterized in that, The processor is connected to the first storage area via a first communication bus; and / or the processor is connected to the second storage area via a second communication bus.

6. A memory access device, characterized in that, include: The first establishment unit is used to establish a first access mapping relationship between multiple processors and a first storage area, and the multiple processors can access the first storage area through the first access mapping relationship; The second establishment unit is used to establish a second access mapping relationship between each processor and its second storage area; The determining unit is configured to, when the processor accesses the first storage area, determine a first access address according to the first access mapping relationship, offset the first access address to obtain a second access address according to the second access mapping relationship, and determine a first access path according to the first access address and the second access address, so that the processor accesses the first storage area according to the first access path; the first access path is that the processor accesses the first storage area where the first access address is located through the second storage area according to the second access address. When the processor accesses the second storage area, it determines a second access path based on the second access mapping relationship, so that the processor accesses the second storage area according to the second access path; wherein each of the second storage areas is located in the same storage region.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes execution instructions that, when executed by a second processor of the electronic device, enable the electronic device to perform the method as described in any one of claims 1-5.

8. An electronic device, characterized in that, The electronic device includes: Second processor; Memory used to store instructions executable by the second processor; The second processor is configured to read the executable instructions from the memory and execute the instructions to implement the memory access method according to any one of claims 1-5.

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