Chip security startup control method and device, electronic equipment and storage medium

Abstract

Embodiments of the present disclosure disclose a chip security startup control method and device, electronic equipment and a storage medium, wherein the method comprises: in a preset stage of a chip startup process, determining, from a decryption result obtained from a hardware security module, first image data to be verified in the preset stage and a first check code corresponding to the first image data; determining a second check code based on the first image data; comparing the second check code with the first check code to obtain a comparison result; determining an integrity check result of the first image data based on the comparison result; and executing a security startup program corresponding to the first image data in the preset stage based on the integrity check result. The embodiments of the present disclosure can ensure the security of the decryption function of the hardware security module and effectively improve the security of the chip startup.

Description

Technical Field

[0001] This disclosure relates to functional safety technology, and in particular to a method, apparatus, electronic device, and storage medium for secure startup control of a chip. Background Technology

[0002] The secure boot of intelligent driving chips is primarily achieved using traditional automotive MCUs (Microcontroller Units). Specifically, it's implemented through HSMs (Hardware Security Modules) to achieve secure boot. Because traditional automotive MCUs use internal embedded Flash memory, the data stored in that Flash only requires verification during the boot process (e.g., signing with the public key if the private key is used for signing). It doesn't involve encryption or decryption of the stored data. Therefore, in traditional MCUs, there's no need to consider Safety Boot, and HSMs have no additional functional safety requirements. However, with the development of intelligent driving technology, intelligent driving chips have begun to widely use advanced manufacturing processes, making it impossible to implement built-in Flash. Therefore, the current mainstream intelligent driving chips use external Flash to achieve non-volatile storage. According to security requirements, the data stored in the external Flash needs to be encrypted. During the secure boot process of the intelligent driving chip, in addition to verifying the stored data, it is also necessary to encrypt and decrypt the stored data. However, during the decryption process, HSM may cause functional safety-related failures in the decrypted data, which can easily lead to poor boot security of the intelligent driving chip.

[0003] To address the technical problems such as poor startup security of intelligent driving chips caused by the aforementioned secure startup process, this disclosure is proposed. Embodiments of this disclosure provide a secure startup control method, apparatus, electronic device, and storage medium for a chip.

[0004] According to one aspect of the present disclosure, a secure boot control method for a chip is provided, comprising: in a preset stage of the chip boot process, determining, from a decryption result obtained from a hardware security module, first image data to be verified in the preset stage and a first verification code corresponding to the first image data; determining a second verification code based on the first image data; comparing the second verification code with the first verification code to obtain a comparison result; determining, based on the comparison result, an integrity verification result of the first image data; and executing a secure boot program corresponding to the first image data in the preset stage based on the integrity verification result.

[0005] According to another aspect of the present disclosure, a secure boot control device for a chip is provided, comprising: a hardware acceleration module connected to a hardware security module, configured to, during a preset stage of the chip boot process, determine, from a decryption result obtained by the hardware security module, first image data to be verified in the preset stage and a first checksum corresponding to the first image data, and determine a second checksum based on the first image data; a first processing module connected to the hardware acceleration module, configured to compare the second checksum with the first checksum to obtain a comparison result; a second processing module, configured to, based on the comparison result, determine an integrity verification result of the first image data; and a third processing module, configured to, based on the integrity verification result, execute a secure boot program corresponding to the first image data during the preset stage.

[0006] According to another aspect of the present disclosure, a computer-readable storage medium is provided, the storage medium storing a computer program for executing the secure boot control method for a chip as described in any of the above embodiments.

[0007] According to another aspect of the present disclosure, an electronic device is provided, the electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory and execute the instructions to implement the secure boot control method for a chip as described in any of the above embodiments; or, the electronic device comprising: a secure boot control device for a chip as described in any of the above embodiments.

[0008] Based on the secure boot control method, apparatus, electronic device, and storage medium for chips provided in the above embodiments of this disclosure, by performing integrity verification on the first image data in the decryption result obtained by the hardware security module in a preset stage of the chip boot process, it can be ensured that the decryption operation of the hardware security module does not damage the first image data, thereby ensuring the functional security of the hardware security module and effectively improving the security of chip boot.

[0009] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0010] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0011] Figure 1This is an exemplary application scenario of the secure boot control method for the chip provided in this disclosure;

[0012] Figure 2 This is a schematic flowchart of a secure boot control method for a chip provided in an exemplary embodiment of this disclosure;

[0013] Figure 3 This is a flowchart illustrating a secure boot control method for a chip provided in another exemplary embodiment of this disclosure;

[0014] Figure 4 This is a schematic diagram of the structure of a secure boot control device for a chip provided in an exemplary embodiment of this disclosure;

[0015] Figure 5 This is a schematic diagram of the structure of a secure boot control device for a chip provided in another exemplary embodiment of this disclosure;

[0016] Figure 6 This is a schematic diagram of the structure of a hardware acceleration module 61 provided in an exemplary embodiment of this disclosure;

[0017] Figure 7 This is a schematic diagram of the structure of a secure boot control device for a chip provided in yet another exemplary embodiment of the present disclosure;

[0018] Figure 8 This is a schematic diagram of the structure of a secure boot control device for a chip provided in yet another exemplary embodiment of this disclosure;

[0019] Figure 9 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed herein. Detailed Implementation

[0020] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0021] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0022] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0023] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0024] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0025] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0026] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0027] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0028] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0029] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0030] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0031] The embodiments disclosed herein can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0032] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0033] This disclosure outlines

[0034] In developing this disclosure, the inventors discovered that secure booting of intelligent driving chips is primarily based on traditional automotive MCUs (Microcontroller Units), specifically, through HSMs (Hardware Security Modules). Because traditional automotive MCUs use internal embedded Flash memory, the data stored in the Flash only requires verification during the boot process (e.g., signing with the public key if the private key is used for signing), without involving encryption or decryption of the stored data. Therefore, in traditional MCUs, there is no need to consider the issue of secure booting, and there are no additional functional safety requirements for HSMs. However, with the development of intelligent driving technology, intelligent driving chips have begun to widely use advanced manufacturing processes, making it impossible to implement built-in Flash. Therefore, the current mainstream intelligent driving chips use external Flash to achieve non-volatile storage. According to security requirements, the data stored in the external Flash needs to be encrypted. During the secure startup process of the intelligent driving chip, in addition to verifying the stored data, it is also necessary to encrypt and decrypt the stored data. However, during the decryption process, HSM may cause functional safety-related failures in the decrypted data, which can easily lead to poor safety of intelligent driving.

[0035] Exemplary Overview

[0036] Figure 1 This is an exemplary application scenario of the secure boot control method for the chip provided in this disclosure.

[0037] In intelligent driving scenarios, when the intelligent driving chip starts up, it first obtains the initial startup program pre-stored in the internal read-only memory and executes the initial startup program to enter the subsequent startup stages. For example, the stage of executing the initial startup program can be called the BL0 stage, and the subsequent startup stages include the BL1 and BL2 stages, which can be set according to actual needs. Each stage that requires loading encrypted image data from an external device can be designated as a preset stage. The encrypted image data is the encrypted result obtained by encrypting the image data executed in the startup stage (which can be called the first image data), used to ensure the security of the image data. To perform subsequent integrity verification of the image data, this disclosure can encrypt the image data together with its first verification code to obtain the corresponding encrypted image data. The first image data refers to the file containing the secure startup program for the corresponding stage. Using the secure boot control method of this disclosure (executed by the secure boot control device of the chip), at any preset stage, encrypted image data loaded from an external storage device is transmitted to a hardware security module (HSM). The HSM decrypts the encrypted image data to obtain a decryption result, which includes the first image data to be verified at that stage and its corresponding first checksum. To verify the integrity of the first image data, a second checksum can be determined based on the first image data. The second checksum is compared with the first checksum to obtain a comparison result. Since the first checksum is the checksum of the first image data before HSM decryption, and the second checksum is the checksum of the first image data after HSM decryption, by comparing the two, if the HSM decryption operation has not damaged the first image data, the second checksum should match the first checksum. If they do not match, it indicates that the HSM decryption operation may have damaged the first image data. Based on this, the integrity verification of the first image data can be completed. Only the first image data that passes the verification will execute its corresponding secure boot program, ensuring the security of the HSM decryption operation function, realizing secure boot of the chip, and thus improving the safety of intelligent driving.

[0038] Exemplary methods

[0039] Figure 2 This is a schematic flowchart illustrating a secure boot control method for a chip provided in an exemplary embodiment of this disclosure. This embodiment can be applied to electronic devices, such as in-vehicle computing platforms, and specifically to chips like intelligent driving chips on those platforms. Figure 2 As shown, it includes the following steps:

[0040] Step 201: In the preset stage of the chip startup process, the first image data to be verified in the preset stage and the first verification code corresponding to the first image data are determined from the decryption results obtained from the hardware security module.

[0041] The chip boot process can be configured into multiple stages according to actual needs, with each stage performing its corresponding boot function. For example, after the chip powers on, the boot process can be divided into three stages. In the first stage, the initial boot program embedded in the internal read-only memory (ROM) is executed. This initial boot program can be called BL0. The functions implemented in the first stage may include initializing the system clock, initializing relevant boot peripherals (such as hardware acceleration modules), determining the hardware boot mode, and loading encrypted image data from BL1 (a boot program used to initialize RAM (Random Access Memory), serial port, allocate stack space, clear the BSS segment, and load BL2 (a boot program used to initialize the hardware used in this stage and load the kernel, etc.). This encrypted image data is then transmitted to the Hardware Security Module (HSM), which decrypts the encrypted image data to obtain the decryption result. The specific decryption operation can be configured according to actual needs, such as using symmetric or asymmetric encryption algorithms for encryption and decryption, which will not be elaborated further. After obtaining the decryption result, the first mirror data to be verified in the preset stage and the first checksum corresponding to the first mirror data are determined from the decryption result. The first checksum is a checksum determined before encryption based on the first mirror data and a preset checksum algorithm, and is used for subsequent integrity verification of the first mirror data. The preset checksum algorithm may include information required to generate the checksum, such as algorithm mode, initial value, and calculation length, and can be set according to actual needs. BL0-BL2 can be set according to actual needs, and this disclosure does not limit them.

[0042] Similarly, after executing the BL1 startup program in the first stage and entering the second stage, the second stage is a preset stage. In the second stage, the encrypted image data of BL2 is loaded and decrypted by HSM to obtain the decryption result. Then, the first image data to be verified in the preset stage and the first verification code corresponding to the first image data are determined from the decryption result. And so on, the method disclosed herein can be executed in each preset stage. It will not be described in detail here. The following only uses one preset stage as an example to explain the subsequent processing flow.

[0043] In practical applications, the specific division of the chip startup process stages can be set according to actual needs, and this disclosure does not impose any restrictions.

[0044] Step 202: Determine the second verification code based on the first mirror data.

[0045] The second verification code is generated based on the first image data and a preset verification algorithm that is consistent with the one used to generate the first verification code after the hardware security module decrypts and obtains the first image data. It is used to verify the integrity of the first image data.

[0046] Step 203: Compare the second check code with the first check code to obtain the comparison result.

[0047] The comparison result may include whether the second check code is the same as or different from the first check code.

[0048] Step 204: Based on the comparison results, determine the integrity verification result of the first mirror data.

[0049] The integrity verification result can include either a pass or a fail. Since the first checksum is the checksum of the first image data before HSM decryption, and the second checksum is the checksum of the first image data after HSM decryption, the two are compared. If the HSM decryption operation did not damage the first image data or no error occurred, the second checksum should be the same as the first checksum. If they are the same, the integrity verification result is a pass. If they are different, it means that the HSM decryption operation may have damaged the first image data, and the integrity verification result is a fail. Based on this, the integrity verification of the first image data can be completed.

[0050] Step 205: Based on the integrity verification result, execute the secure boot procedure corresponding to the first image data in a preset stage.

[0051] Specifically, only the first image data that passes the integrity check will execute its corresponding secure boot procedure to ensure the security of the HSM decryption operation, achieve secure chip boot, and thus improve the safety of autonomous driving. If the integrity check fails, the boot process ends.

[0052] In practical applications, steps 201-202 and steps 203-205 can be implemented by the same processing module or by different processing modules. For example, steps 201-202 can be implemented by a hardware processing module, while steps 203-205 can be implemented by a security core in the chip. The hardware processing module is a hardware circuit independent of the security core, and the specific configuration can be set according to actual needs.

[0053] The secure boot control method for the chip provided in this embodiment verifies the integrity of the first image data in the decryption result obtained by the hardware security module during a preset stage of the chip boot process. This ensures that the decryption operation of the hardware security module does not damage the first image data, thereby guaranteeing the functional security of the hardware security module and effectively improving the security of chip boot.

[0054] Figure 3 This is a flowchart illustrating a secure boot control method for a chip provided in another exemplary embodiment of this disclosure.

[0055] In an optional example, prior to step 201, the method of this disclosure may further include the following steps:

[0056] Step 301: Detect the communication handshake signal between the hardware security module and the first memory.

[0057] The first memory can be internal to the chip, such as RAM or SRAM (Static Random-Access Memory). The decryption result obtained by the hardware security module needs to be stored in the first memory for the chip's corresponding processor (such as the security core) to read and execute. This disclosure determines when the hardware security module transmits the decryption result to the first memory by detecting the communication handshake signal between the hardware security module and the first memory. The communication handshake signal can be determined according to the actual handshake protocol; for example, the communication handshake signal may include a valid signal (VALID) and a ready signal (READY), and there is no specific limitation.

[0058] Step 302: Determine the valid control signal based on the communication handshake signal.

[0059] By detecting the communication handshake signal, it can be determined when the hardware security module starts transmitting the decryption result. Based on this, a valid control signal can be determined, which indicates that the acquisition or retrieval of the decryption result transmitted by the hardware security module can begin. For example, when VALID and READY are detected, it indicates that the hardware security module has successfully handshaked with the first memory and is ready to transmit data, thus determining the valid control signal.

[0060] Step 303: In response to a valid control signal, obtain the decryption result transmitted by the hardware security module from the bus to which the hardware security module is connected.

[0061] Once a valid control signal is detected, indicating that the decryption result can be obtained, the decryption result transmitted by the hardware security module can be obtained from the bus connected to the hardware security module.

[0062] In an optional example, the communication handshake signal between the hardware security module and the first memory can be detected via bus bypass. Bus bypass allows the communication content between the hardware security module and the first memory via the bus to be transmitted simultaneously through this bypass. This bypass is equipped with a corresponding detection component that can receive the communication handshake signal and transmitted data between the hardware security module and the first memory. A valid control signal is used to determine whether to receive and acquire the data transmitted via the data bus. Without a valid control signal, the data sent via the data bus is not received. Once a valid control signal is detected, it indicates that the data bus has started transmitting a valid decryption result. Then, by receiving the data transmitted via the data bus, the transmitted decryption result can be obtained.

[0063] This disclosure detects the communication handshake information between the hardware security module and the first memory. After determining the valid control signal, it obtains the decryption result from the bus connected to the hardware security module without affecting the data transmission from the hardware security module to the first memory. This allows the integrity verification and the storage of the decryption result to be processed in parallel, effectively improving the verification efficiency and reducing the chip startup time.

[0064] In an alternative example, the communication between the hardware security module and the first memory can be bypassed to a hardware processing module (which can be called a hardware acceleration module) via bus bypass. The integrity verification can be implemented in hardware, or the generation of the second verification code can be implemented, thereby further improving the verification efficiency and thus improving the chip startup efficiency.

[0065] In an optional example, before determining the first image data to be verified in the preset stage and the first verification code corresponding to the first image data from the decryption result obtained from the hardware security module in step 201, the method further includes:

[0066] Step 401: Load the encrypted image data corresponding to the preset stage from the external storage device.

[0067] External storage devices are external storage devices used to store encrypted image data. During the chip boot process, only the initial boot program is stored in the chip's internal ROM (Read-Only Memory). Subsequent boot programs need to be loaded from external storage into the internal RAM. To ensure the security of the boot program, it is usually stored as an encrypted image data in the external storage device. Therefore, during the boot process, each stage needs to load the corresponding encrypted image data from the external storage device. To obtain the actual image data, a hardware security module is required for decryption.

[0068] Step 402: The encrypted image data is transmitted to the hardware security module so that the hardware security module can decrypt the encrypted image data and obtain the decryption result.

[0069] Since the hardware security module is required to decrypt the encrypted image data, the encrypted image data must be transmitted to the hardware security module. The hardware security module then obtains the encrypted image data and decrypts it using its hardware implementation to obtain the decryption result.

[0070] In one optional example, the hardware security module can verify the signature of the encrypted image data after obtaining it. Signature verification refers to verifying the legality of the data. For example, when loading and transmitting the encrypted image data, information such as the certificate and digital signature of the encrypted image data are carried to identify its legality. Alternatively, the module can verify the signature of the first image data after obtaining the decryption result. For example, the decryption result may also include information such as the certificate and digital signature of the first image data to identify its legality. The signature of the first image data is verified based on this information. The specific signature verification principle will not be elaborated here.

[0071] This disclosure utilizes a hardware security module to decrypt encrypted image data loaded from an external storage device, effectively ensuring decryption speed and real-time performance, thereby guaranteeing chip startup speed and reducing chip startup time. Furthermore, the external storage device stores encrypted image data, further ensuring chip startup security.

[0072] In one optional example, the methods disclosed herein also include:

[0073] Step 403: Store the decryption result in the first memory.

[0074] The first memory can be RAM or SRAM inside the chip. After the hardware security module completes the decryption process of the encrypted image data, the decryption result can be stored in the first memory for use in the chip boot process.

[0075] Step 203 compares the second check code with the first check code to obtain the comparison result, including:

[0076] Step 2031: Write a completion interrupt signal to the first register.

[0077] The completion interrupt signal is used to notify the relevant processing module (or sub-module) that the generation of the second check code has been completed. After the second check code of the first image data is determined in step 202, the completion interrupt signal can also be written to the first register. The device disclosed herein has a relevant processing module or sub-module for responding to interrupts and detects the status of the first register in real time or periodically.

[0078] Step 2032: In response to detecting a completion interrupt signal in the first register, retrieve the first checksum from the first memory.

[0079] When a completion interrupt signal is detected in the first register, indicating that the second check code has been generated, the first check code can be retrieved from the first memory and used for comparison with the second check code.

[0080] Step 2033: Compare the second check code with the first check code to obtain the comparison result.

[0081] For example, the integrity verification algorithm can be CRC (Cyclic Redundancy Check) or HASH (Hash) algorithm. For instance, in a HASH algorithm, the first checksum and the second checksum are the hash values ​​of the first mirror data before encryption and after decryption, respectively. The second checksum is compared with the first checksum to determine if their values ​​are the same, thus obtaining the comparison result. The specific comparison principle will not be elaborated further.

[0082] In an optional example, step 2033 can be implemented using hardware comparison circuitry to further improve the real-time performance of the verification.

[0083] In an optional example, after determining the first check code, the first check code can also be written into the third register. After obtaining the second check code, the second check code can also be written into the fourth register. The third register and the fourth register are respectively connected to the input of the comparator, serving as the two inputs of the comparator. The comparison between the second check code and the first check code is implemented based on the comparator.

[0084] After generating the second checksum of the first image data, this disclosure allows for comparison of the second checksum with the first checksum via an interrupt signal to complete integrity verification. This enables the generation of the second checksum to be implemented independently of the processor (e.g., a security core), without consuming processor time, thus reducing chip startup latency and improving real-time performance. Alternatively, the comparison of the second checksum with the first checksum can be implemented in hardware, further enhancing real-time performance.

[0085] In an optional example, step 202, determining the second checksum based on the first mirror data, includes:

[0086] Step 2021: Obtain the pre-configured verification configuration information, which includes the verification algorithm information corresponding to the preset stage.

[0087] The verification configuration information can be pre-configured in a certain storage area, such as in a register. The verification algorithm information can include the algorithm mode used for verification, the calculation length, and other relevant information. The specific content can be determined according to the actual verification algorithm, and this disclosure does not limit it. The algorithm mode can be a specific verification algorithm, such as the CRC algorithm, hash algorithm, etc. The CRC algorithm uses the principle of division and remainder to achieve error detection; the specific principle will not be elaborated further. The hash algorithm maps a binary value of arbitrary length to a shorter, fixed-length binary value, called the hash value, which serves as the checksum. The calculation length can refer to the length of the checksum, such as the length of the hash value obtained by the hash algorithm. Different stages of the startup process can correspond to the same or different verification configuration information, which can be set according to actual needs.

[0088] Step 2022: Based on the verification configuration information and the first image data, generate the second verification code for the first image data.

[0089] Specifically, the second verification code is obtained by calculating the first image data according to the corresponding algorithm based on the verification algorithm information in the verification configuration information.

[0090] For example, based on a preset hash algorithm, the first mirror data is hashed, and the hash length is 8 bits, thus obtaining an 8-bit binary hash value as the second check code.

[0091] This disclosure uses pre-configured verification information to generate a second verification code for the first image data, and can support multiple verification algorithms according to actual needs, thereby improving versatility.

[0092] In an optional example, before determining the first image data to be verified in the preset stage and the first verification code corresponding to the first image data from the decryption result obtained from the hardware security module in step 201, the method further includes:

[0093] Step 501: Obtain the initial startup program from the read-only memory.

[0094] The read-only memory is the chip's internal ROM. The initial boot program is a boot program pre-programmed in the read-only memory. After the chip is powered on, the chip starts the relevant processor or processor core (such as the security core) and first executes the initial boot program in the ROM to begin the chip's boot process.

[0095] Step 502: Execute the initial startup program to obtain the initial verification configuration information.

[0096] The initial boot program performs some initialization and configuration tasks. The initial verification configuration information can be information that is stored in the ROM along with the initial boot program. It may include the verification configuration information corresponding to the encrypted image data loaded when the initial boot program is executed.

[0097] Step 503: Based on the initial verification configuration information, perform initial configuration for secure boot of the chip.

[0098] The initial configuration may include configuring the module or sub-module used to generate the second checksum based on the initial verification configuration information, such as configuring the corresponding verification algorithm and calculation length. For example, when the module used to generate the second checksum is a hardware module independent of the security core, the hardware module is configured based on the initial verification configuration information so that it can successfully complete the checksum generation. Specific configurations can be set according to actual needs.

[0099] In an optional example, the initialization configuration completed by executing the initial startup procedure may also include other related initializations and configurations, such as the initialization of related startup peripherals mentioned above, which can be set according to actual needs.

[0100] Step 504: In response to the completion of the initial configuration, the chip startup process enters the preset phase.

[0101] Once the initial configuration is complete, the encrypted image data of the subsequent startup program needs to be loaded. For example, the execution of the initial startup program BL0 mentioned above will load the encrypted image data of BL1, and then the integrity verification of BL1 at this stage will be completed through the method disclosed in this disclosure. If the verification is successful, the secure startup program of BL1 will be executed. During the execution of BL1, the encrypted image data of BL2 will be loaded, and the integrity verification of BL2 will be completed through the method disclosed in this disclosure again. This process continues until all stages of the startup process are completed, that is, the secure startup of the chip is completed.

[0102] This disclosure configures the initial verification information for secure startup of the chip through an initial startup program, enabling the chip startup to perform integrity verification on the decryption results of the hardware security module, thereby ensuring the security of the hardware security module's decryption function and improving the security of chip startup.

[0103] The secure boot control method for any chip provided in this disclosure can be executed by any suitable device with data processing capabilities, including but not limited to terminal devices and servers. Alternatively, the secure boot control method for any chip provided in this disclosure can be executed by a processor, such as by a processor calling corresponding instructions stored in memory to execute the secure boot control method for any chip mentioned in this disclosure. Further details will not be elaborated below.

[0104] Exemplary device

[0105] Figure 4 This is a schematic diagram of a secure boot control device for a chip provided in an exemplary embodiment of this disclosure. The device in this embodiment can be used to implement corresponding method embodiments of this disclosure, such as… Figure 4 The device shown includes: a hardware acceleration module 61, a first processing module 62, a second processing module 63, and a third processing module 64.

[0106] The hardware acceleration module 61, connected to the hardware security module, is used to determine the first image data to be verified in the preset stage and the first checksum corresponding to the first image data from the decryption result obtained by the hardware security module in the preset stage of the chip boot process, and to determine the second checksum based on the first image data; the first processing module 62, connected to the hardware acceleration module, is used to compare the second checksum with the first checksum and obtain the comparison result; the second processing module 63 is used to determine the integrity verification result of the first image data based on the comparison result; and the third processing module 64 is used to execute the secure boot program corresponding to the first image data in the preset stage based on the integrity verification result.

[0107] In an optional example, the first processing module 62, the second processing module 63, and the third processing module 64 can be processor cores used for startup in the chip, such as security cores. The performance of the security core can be set according to actual needs. For example, it can be built based on a low-latency processor core to meet a certain security level (such as ASILD (Automotive Safety Integrity Level D)).

[0108] In one optional example, the hardware acceleration module 61 and / or the first processing module 62 can be either a software module or a hardware circuit module, depending on the actual requirements.

[0109] In an optional example, hardware acceleration module 61 may be connected to first processing module 62, second processing module 63 and third processing module 64 via a bus.

[0110] This disclosure ensures that the decryption operation of the hardware security module does not damage the first image data by performing integrity verification on the first image data in the decryption result obtained by the hardware security module during a preset stage of the chip boot process. This guarantees the functional security of the hardware security module and effectively improves the security of chip boot.

[0111] Figure 5 This is a schematic diagram of the structure of a secure boot control device for a chip provided in another exemplary embodiment of this disclosure.

[0112] In an optional example, the hardware acceleration module 61 includes: a bus monitor 611 and a checksum generator 612; the bus monitor 611 is connected to the hardware security module via a bus bypass, and is used to detect the communication handshake signal between the hardware security module and the first memory, and send a valid control signal to the checksum generator based on the communication handshake signal, the valid control signal being used to notify the checksum generator to start collecting the decryption result transmitted by the hardware security module; the checksum generator 612 is connected to the bus monitor 611 and also connected to the hardware security module via a bus bypass, and is used to collect the decryption result transmitted by the hardware security module from the bus to which the hardware security module is connected in response to the valid control signal of the bus monitor, and determine a second checksum based on the first mirror data in the decryption result.

[0113] Since the communication handshake signal is a control signal, the bus monitor 611 can be connected to the control bus of the bus bypass to monitor the communication handshake signal. The checksum generator 612 is used to collect the decryption result data transmitted, so it can be connected to the data bus of the bus bypass. The specific configuration can be determined according to actual needs, as long as the corresponding function can be achieved. The function of the bus bypass is to allow the communication content between the hardware security module and the first memory to be sent in parallel to the hardware acceleration module 61 through the bus bypass, so as to achieve real-time detection of the communication handshake signal and real-time acquisition of the decryption result. The meaning of the effective control signal is explained in the aforementioned method embodiments and will not be repeated here. The specific operation of the checksum generator 612 after obtaining the decryption result can be found in the aforementioned method embodiments.

[0114] In an optional example, the bus monitor 611 and the checksum generator 612 can be implemented in hardware to further improve real-time performance.

[0115] This disclosure implements the calculation of the checksum of the mirror data to be verified in the decryption result based on bus bypass, which will not affect other circuits on the bus path. Moreover, the checksum of the mirror data to be verified in the decryption result of the hardware security module can be quickly calculated by hardware. Then, the security processing module compares the calculated checksum with the checksum in the decoding result to determine the integrity of the mirror data. This does not require software calculation time and will not cause additional delays on the hardware path. While ensuring that certain security level requirements are met, it effectively reduces the overall startup process time, thereby improving the startup speed.

[0116] In an optional example, the apparatus of this disclosure further includes: a loading module 65 and a hardware security module 66;

[0117] The loading module 65 is used to load encrypted image data corresponding to a preset stage from an external storage device; the hardware security module 66 is connected to the loading module 65 and is used to decrypt the encrypted image data to obtain the decryption result.

[0118] In an optional example, the loading module 65 can be connected to the hardware security module 66 via a bus, or the loading module 65 can be a module in the processor or processor core, connected to the bus via the processor or processor core, and then connected to the hardware security module 66. The specific configuration can be set according to actual needs.

[0119] This disclosure loads the encrypted image data of the secure boot program to be executed, stored on an external storage device, into the chip during a preset stage. This allows the chip to decrypt the encrypted image data through a hardware security module and obtain the image data of the secure boot program to be executed, thus providing external storage functionality for chip startup and reducing the internal storage cost of the chip.

[0120] In an optional example, the apparatus of this disclosure further includes: a first memory 67; and a hardware security module 66, which is also used to store the decryption result in the first memory 67.

[0121] The first memory 67 can be RAM or SRAM inside the chip, and the hardware security module 66 can communicate with the first memory 67 via a bus.

[0122] In an optional example, the hardware acceleration module 61 further includes: a first register 613 connected to the first processing module 62, used to store a completion interrupt signal; the hardware acceleration module 61 is further used to write a completion interrupt signal to the first register 613 after determining the second check code, so as to notify the first processing module 62 that the second check code has been generated; the first processing module 62 is further used to, in response to detecting the completion interrupt signal in the first register 613, retrieve the first check code from the first memory 67, compare the second check code with the first check code, and obtain a comparison result.

[0123] The first register 613 can be any implementable register, such as an existing register in the chip, or an additional register added based on the requirements of this disclosure; the specific configuration can be determined according to actual needs. After generating the second checksum, the hardware acceleration module 61 or the aforementioned checksum generator 612 can write the second checksum into the first register 613 to notify the first processing module 62 that the second checksum has been generated. The first processing module 62 can periodically or in real-time monitor the first register 613 to respond to a completion interrupt signal, and then compare the second checksum with the first checksum to complete the integrity verification.

[0124] In an optional example, the hardware acceleration module 61 may include a comparator to compare the second check code and the first check code. The comparison result may also be stored in a corresponding comparison result register, which may be connected to the first processing module 61 so that the first processing module 62 can directly obtain the comparison result, thereby further improving the real-time performance of the integrity verification.

[0125] This disclosure stores the completion interrupt signal in the first register, thereby enabling the generation of the checksum to be independent of the processor. After the checksum is generated, an interrupt request is sent to the processor through the completion interrupt signal, so that the processor responds to the interrupt request to determine the integrity verification result, further improving real-time performance.

[0126] In an optional example, the apparatus of this disclosure further includes: a second register 68 connected to the hardware acceleration module 61, for storing verification configuration information, the verification configuration information including verification algorithm information corresponding to the stage; the hardware acceleration module 61 is further configured to obtain the verification configuration information from the second register 68, and generate a second verification code of the first image data based on the verification configuration information and the first image data.

[0127] The second register 68 can be any implementable register, and can be set according to actual needs. The content stored in the second register 68 can be configured at any time before the integrity verification of the boot process, and can be set according to actual needs. Optionally, the verification configuration information at each stage can also be pre-stored in the ROM within the chip along with the initial boot code, and there is no specific limitation. The specific content and working principle of the verification configuration information are described in the aforementioned embodiments, and will not be repeated here.

[0128] This disclosure stores the verification configuration information of the preset stage in a second register to support the integrity verification of the first image data decrypted in the preset stage, ensuring the rapid generation of the verification code and further improving real-time performance.

[0129] In an optional example, the apparatus of this disclosure further includes: a second memory 69 and an initial processing module 70; the second memory 69 is used to store an initial startup program and initial verification configuration information of the hardware acceleration module 61; the initial processing module 70 is used to execute the initial startup program stored in the second memory 69, enter the initial startup stage, obtain the initial verification configuration information from the second memory 69 based on the initial startup program, initialize the hardware acceleration module 61 based on the initial verification configuration information, and enter the preset stage of the chip startup process.

[0130] The second memory 69 can be a read-only memory (ROM) in the chip, pre-programmed with an initial startup program. After the chip is powered on, the initial processing module 70 starts working, executing the initial startup program in the ROM. The initial startup program initializes and configures the hardware acceleration module 61, enabling it to function normally. It may also include configuring other related modules or functions of the chip and guiding the chip into a preset stage of the startup process. In this preset stage, the corresponding startup work is completed, including loading encrypted image data from an external storage device and transmitting it to the hardware security module 66 for decryption. The decryption result obtained by the hardware security module 66 is transmitted via the bus and the main circuit. The data is bypassed and transmitted to the first memory 67 and the hardware acceleration module 61. The hardware acceleration module 61 obtains the decryption result, generates a second checksum for the first mirror data in the decryption result based on the verification configuration information for this stage stored in the second register 68, and writes a completion interrupt signal to the first register 613 to notify the first processing module 62. The first processing module 62 retrieves the first checksum from the first memory 67 and the second checksum from the hardware security module, compares the second checksum with the first checksum, obtains the comparison result, and then determines the integrity verification result based on the comparison result. In response to the integrity verification result being successful, the secure boot program corresponding to the first mirror data is executed. For the specific principle, please refer to the aforementioned embodiment, which will not be repeated here.

[0131] This disclosure pre-stores the initial boot program in the chip's read-only memory. When the chip is powered on, the relevant processor core (such as the security core) used for booting can first execute the initial boot program in the read-only memory, thereby entering the chip's initial boot process to guide the chip into the subsequent boot stage and achieve secure booting of the chip.

[0132] In an optional example, hardware acceleration module 61 may further include:

[0133] The fourth register 614, connected to the check code generator 612, is used to store the second check code;

[0134] The check code generator 612 is also used to write the second check code into the fourth register 614.

[0135] The fourth register 614 can be any implementable register, and can be set according to actual needs.

[0136] In one optional example, Figure 6This is a schematic diagram of the structure of a hardware acceleration module 61 provided in an exemplary embodiment of this disclosure. In this example, the hardware acceleration module 61 can be implemented entirely or partially in hardware. The hardware acceleration module 61 may further include a third register 615 and a comparator 616. The third register 615 is used to store a first checksum. The third register 615 and the fourth register 614 can be connected to the input of the comparator 616, thereby implementing the comparison between the second checksum and the first checksum in hardware, further improving the real-time performance of the verification. The comparator 616 is connected to the first register 613, so the completion interrupt signal can carry the comparison result of the comparator 616, thereby transmitting the completion interrupt signal and the comparison result together to the first processing module 62. The first processing module 62 can respond to the interrupt and directly determine the integrity verification result based on the comparison result, further improving the real-time performance of the verification.

[0137] In an optional example, the apparatus disclosed herein may further include: an external storage device 71 for storing encrypted image data.

[0138] Figure 7This is a schematic diagram of the structure of a secure boot control device for a chip provided in another exemplary embodiment of this disclosure. In this example, the first processing module 62, the second processing module 63, the third processing module 64, the loading module 65, and the initial processing module 70 are modules in the safety core of the chip, and the hardware acceleration module 61 is a hardware module independent of the safety core. The safety core, the hardware safety module 66, the hardware acceleration module 61, the first memory 67, the second memory 69, and the external memory 71 are interconnected via a bus. When the chip powers on, the security core starts the initial startup program stored in the second memory 69 to initialize and configure the hardware acceleration module 61, enabling it to operate normally. After the startup process enters a preset stage, the security core loads the encrypted image data corresponding to that preset stage from the external memory 71 and transmits it to the hardware security module 66 via the bus. The hardware security module 66 decrypts the encrypted image data (it can also perform signature verification before decryption), obtains the decryption result, and writes the decryption result to the first memory 67 via the bus. The hardware acceleration module 61 monitors the communication handshake signals between the hardware security module 66 and the first memory 67 via bus bypass, and determines a valid control signal. Afterwards, the decryption result of the bus transmission is obtained, and a second check code for the first image data is generated based on the verification configuration information pre-configured in the second register 68. The second check code is written to the fourth register 614. After generating the second check code, a completion interrupt signal is written to the first register 613 to notify the security core that the second check code has been generated. The security core responds to the completion interrupt signal, retrieves the first check code from the first memory 67 via the bus, and retrieves the second check code from the fourth register 614. The second check code is compared with the first check code to obtain the comparison result. Based on the comparison result, the integrity verification result is determined. In response to the integrity verification result being passed, the secure boot program corresponding to the first image data is executed.

[0139] This disclosure obtains the decryption result of the hardware security module through bus bypass and generates the second check code through hardware. Compared with the second check code being calculated by the security core software, it can greatly reduce the processing time and effectively improve real-time performance. While ensuring the secure startup of the chip, it can effectively improve the secure startup speed of the chip.

[0140] In one optional example, Figure 8This is a schematic diagram of the secure boot control device for a chip provided in another exemplary embodiment of this disclosure. In this example, the hardware acceleration module 61 and the second register 68 can be located within the hardware security module 66. The decryption result of the hardware security module 66 is transmitted to the first memory 67 via the bus and to the hardware acceleration module 61 via the hardware acceleration module 61. The hardware acceleration module 61 generates a second checksum of the first image data and writes it to the fourth register 614, and writes a completion interrupt signal to the first register 613 to notify the security core to perform subsequent comparisons and other related processing. For details, please refer to the foregoing example, which will not be repeated here.

[0141] In one optional example, if the integrity verification result of the first image data in a certain preset stage fails, the chip secure boot fails, and a recovery operation can be performed, such as recovery through software or recovery after notifying the outside world, and a new secure boot process can be started again.

[0142] This disclosure implements integrity verification through bus bypass and hardware acceleration modules, which does not cause additional delays in the chip hardware path and does not affect other circuits. Based on hardware, the checksum calculation can also be performed quickly, further reducing startup time compared to integrity verification performed by processor software. Furthermore, compared to integrity verification of decryption results through redundant hardware security modules (i.e., setting up two hardware security modules to decrypt simultaneously, comparing the decryption results, and considering verification successful if they match, otherwise considering verification unsuccessful), this disclosure effectively reduces hardware costs.

[0143] Exemplary electronic devices

[0144] This disclosure also provides an electronic device, including: a memory for storing computer programs;

[0145] A processor is configured to execute a computer program stored in the memory, and when the computer program is executed, to implement the secure boot control method for the chip described in any of the above embodiments of this disclosure.

[0146] Figure 9 This is a schematic diagram of an application embodiment of the electronic device disclosed herein. In this embodiment, the electronic device 10 includes one or more processors 11 and a memory 12.

[0147] The processor 11 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

[0148] The memory 12 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 11 may execute the program instructions to implement the methods of the various embodiments of this disclosure described above and / or other desired functions. Various contents such as input signals, signal components, and noise components may also be stored in the computer-readable storage medium.

[0149] In one example, the electronic device 10 may also include an input device 13 and an output device 14, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0150] For example, the input device 13 may be the microphone or microphone array described above, used to capture the input signal of the sound source.

[0151] In addition, the input device 13 may also include, for example, a keyboard, a mouse, etc.

[0152] The output device 14 can output various information to the outside, including determined distance information, direction information, etc. The output device 14 may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0153] Of course, for the sake of simplicity, Figure 9 Only some of the components of the electronic device 10 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 10 may include any other suitable components depending on the specific application.

[0154] Exemplary computer program products and computer-readable storage media

[0155] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0156] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0157] Furthermore, embodiments of this disclosure may also be computer-readable storage media having computer program instructions stored thereon, which, when executed by a processor, cause the processor to perform the steps in the methods according to various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0158] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0159] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0160] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0161] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0162] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0163] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0164] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0165] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A secure boot control method for a chip, comprising: In a preset phase of the chip startup process, the first image data to be verified in the preset phase and the first verification code corresponding to the first image data are determined from the decryption results obtained from the hardware security module. The first verification code is the verification code of the first image data before the hardware security module decrypts it; The second verification code is determined based on the first image data; The second verification code is the verification code of the first image data after the hardware security module has decrypted it; Compare the second check code with the first check code to obtain the comparison result; Based on the comparison results, the integrity verification result of the first image data is determined; Based on the integrity verification result, a secure boot procedure corresponding to the first image data is executed in the preset stage.

2. The method according to claim 1, wherein, Before determining the first image data to be verified in the preset stage and the first verification code corresponding to the first image data from the decryption result obtained from the hardware security module, the method further includes: Detect the communication handshake signal between the hardware security module and the first memory; Based on the communication handshake signal, a valid control signal is determined; In response to the valid control signal, the decryption result transmitted by the hardware security module is obtained from the bus to which the hardware security module is connected.

3. The method according to claim 1, wherein, Before determining the first image data to be verified in the preset stage and the first verification code corresponding to the first image data from the decryption result obtained from the hardware security module, the method further includes: Load the encrypted image data corresponding to the preset stage from the external storage device; The encrypted image data is transmitted to the hardware security module, so that the hardware security module can decrypt the encrypted image data and obtain the decryption result.

4. The method according to claim 3, further comprising: The decryption result is stored in the first memory; The step of comparing the second check code with the first check code to obtain a comparison result includes: Write a completion interrupt signal to the first register; In response to detecting the completion interrupt signal in the first register, the first checksum is retrieved from the first memory; The second check code is compared with the first check code to obtain the comparison result.

5. The method according to claim 1, wherein, The step of determining the second verification code based on the first mirror data includes: Obtain pre-configured verification configuration information, which includes verification algorithm information corresponding to the preset stage; Based on the verification configuration information and the first image data, the second verification code of the first image data is generated.

6. The method according to any one of claims 1-5, wherein, Before determining the first image data to be verified in the preset stage and the first verification code corresponding to the first image data from the decryption result obtained from the hardware security module, the method further includes: Retrieve the initial startup program from read-only memory; Execute the initial startup procedure to obtain initial verification configuration information; Based on the initial verification configuration information, the secure boot of the chip is initially configured; In response to the completion of the initial configuration, the chip boot process enters the preset phase.

7. A secure boot control device for a chip, comprising: A hardware acceleration module, connected to a hardware security module, is used to determine, in a preset stage of the chip boot process, the first image data to be verified in the preset stage and the first verification code corresponding to the first image data from the decryption result obtained by the hardware security module, and to determine the second verification code based on the first image data. The first verification code is the verification code of the first image data before the hardware security module decrypts it; The second verification code is the verification code of the first image data after the hardware security module has decrypted it; The first processing module, connected to the hardware acceleration module, is used to compare the second check code with the first check code to obtain a comparison result. The second processing module is used to determine the integrity verification result of the first image data based on the comparison result; The third processing module is used to execute a secure boot program corresponding to the first image data in the preset stage based on the integrity verification result.

8. The apparatus according to claim 7, wherein, The hardware acceleration module includes: a bus monitor and a checksum generator; The bus monitor is connected to the hardware security module via a bus bypass and is used to detect the communication handshake signal between the hardware security module and the first memory. Based on the communication handshake signal, it sends a valid control signal to the checksum generator. The valid control signal is used to notify the checksum generator to start collecting the decryption result transmitted by the hardware security module. The checksum generator is connected to the bus monitor and also connected to the hardware security module via a bus bypass. In response to the valid control signal of the bus monitor, it collects the decryption result transmitted by the hardware security module from the bus to which the hardware security module is connected, and determines the second checksum based on the first mirror data in the decryption result.

9. The apparatus according to claim 7, further comprising: Loading module and the hardware security module; The loading module is used to load the encrypted image data corresponding to the preset stage from an external storage device; The hardware security module is connected to the loading module and is used to decrypt the encrypted image data to obtain the decryption result.

10. The apparatus according to claim 9, further comprising: First memory; The hardware security module is also used to store the decryption result in the first memory; The hardware acceleration module also includes: The first register, connected to the first processing module, is used to store the completion interrupt signal; The hardware acceleration module is further configured to write the completion interrupt signal to the first register after determining the second check code, so as to notify the first processing module that the second check code has been generated. The first processing module is further configured to, in response to detecting the completion interrupt signal in the first register, retrieve the first check code from the first memory, compare the second check code with the first check code, and obtain the comparison result.

11. The apparatus according to claim 7, further comprising: The second register, connected to the hardware acceleration module, is used to store verification configuration information, which includes the verification algorithm information corresponding to this stage. The hardware acceleration module is further configured to obtain the verification configuration information from the second register, and generate the second verification code of the first image data based on the verification configuration information and the first image data.

12. The apparatus according to any one of claims 7-11, further comprising: Second memory and initial processing module; The second memory is used to store the initial startup program and the initial verification configuration information of the hardware acceleration module; The initial processing module is used to execute the initial startup program stored in the second memory, enter the initial startup stage, obtain the initial verification configuration information from the second memory based on the initial startup program, initialize the hardware acceleration module based on the initial verification configuration information, and enter the preset stage of the chip startup process.

13. A computer-readable storage medium storing a computer program for executing the secure boot control method for the chip according to any one of claims 1-6.

14. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the secure boot control method for the chip according to any one of claims 1-6. or, The electronic device includes: The secure boot control device for a chip as described in any one of claims 7-12.

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