A field programmable gate array device and its lookup, set up and initialization method

Abstract

A field programmable gate array device and a lookup, setting and initialization method thereof can quickly configure the connection relationship between the ports and pads of the logic circuit units inside the field programmable gate array device. The device comprises: a plurality of logic circuit units with a connection relationship; the plurality of logic circuit units realize the function of a chip to be verified; any logic circuit unit in the plurality of logic circuit units has at least one port; a plurality of pins for connecting at least one logic circuit unit to an external circuit; a plurality of pads respectively connected to the plurality of pins; and a plurality of selector modules, wherein any selector module is fixedly connected to any port and selectively connected to a plurality of pads, and the ports fixedly connected by the plurality of selector modules are all different.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a field-programmable gate array device and its search, setting and initialization method. Background Technology

[0002] Field Programmable Gate Arrays (FPGAs) are frequently used to test and verify circuit logic designs. The device under test contains multiple logic circuit units. During the verification process, when a logic circuit unit needs to be connected to the outside world through the pins of the FPGA, the port of the logic circuit unit must first be connected to the pad, and then the pad is connected to the package pin, and then connected to the external circuit.

[0003] In existing verification methods, changing the external circuitry connected to a logic circuit unit requires reprogramming the port and pad connection configuration in the configuration file to connect the port to the corresponding pad. This method has the drawback of taking a long time to compile the configuration file, often several hours. Furthermore, the verification process frequently requires adjusting the connection relationships between the logic circuit unit's ports and the external circuitry, thus consuming a significant amount of time.

[0004] Therefore, there is an urgent need for a way to quickly configure the connection between the ports and pads of the logic circuit units inside a field-programmable gate array (FPGA) device. Summary of the Invention

[0005] This application provides a field-programmable gate array (FPGA) device and its search, setup, and initialization method for quickly configuring the connection relationship between the ports and pads of the logic circuit units inside the FPGA device.

[0006] In a first aspect, this application provides a field-programmable gate array (FPGA) device, comprising: a plurality of logic circuit units having interconnected relationships; the plurality of logic circuit units implementing the functions of a chip to be verified; each of the plurality of logic circuit units having at least one port; a plurality of pins for connecting at least one logic circuit unit to an external circuit; a plurality of pads respectively connected to the plurality of pins; and a plurality of selector modules, wherein each selector module is fixedly connected to any port and selectively connected to a plurality of pads, and the ports fixedly connected to the plurality of selector modules are all different.

[0007] In one possible design, the plurality of ports includes a dedicated port, a test port, and a bonding port; the dedicated port and the test port each have their own selector module; the dedicated port is connected to at least one pad of the same type through a corresponding selector module; the test port is connected to any pad through a corresponding selector module; and the bonding port is directly connected to a fixed pad.

[0008] In one possible design, the plurality of selector modules include: a first selector module that is fixedly connected to a first port among the plurality of ports and selectively connected to P pads among the plurality of pads; and a second selector module that is fixedly connected to a second port among the plurality of ports and selectively connected to Q pads among the plurality of pads, wherein P is a positive integer greater than 1, Q is a positive integer greater than 1, and P is not equal to Q.

[0009] In one possible design, the plurality of selector modules include: a first selector module that is fixedly connected to a first port among the plurality of ports and selectively connected to P pads among the plurality of pads; and a second selector module that is fixedly connected to a second port among the plurality of ports and selectively connected to Q pads among the plurality of pads; wherein P is a positive integer greater than 1, Q is a positive integer greater than 1; and the first pad among the P pads is one of the Q pads.

[0010] In one possible design, the field-programmable gate array (FPGA) device further includes: a memory module for storing pads selectively connected to the plurality of selector modules; a serial communication interface module for connecting to a serial communication terminal via a serial communication standard; and a control module connecting the memory module, the serial communication interface module, and the plurality of selector modules, wherein the control module is configured to receive a search command transmitted by the serial communication terminal via the serial communication interface module; read content from the corresponding address in the memory module according to the selector module number in the search command; and transmit the read content back to the serial communication terminal via the serial communication interface module.

[0011] In one possible design, the control module is further configured to: receive a setting instruction transmitted by the serial communication terminal via the serial communication interface module; store the selection signal contained in the setting instruction at the corresponding address in the memory module according to the selector module number in the setting instruction; set the selection signal to the corresponding selector module among the multiple selector modules; and transmit the setting success information back to the serial communication terminal.

[0012] In one possible design, the control module is further configured to: receive an initialization command transmitted by the serial communication terminal through the serial communication interface module; store multiple selection signals in the initialization command into multiple corresponding addresses of the memory module; set the multiple selection signals into corresponding selector modules among the multiple selector modules; and transmit initialization success information back to the serial communication terminal.

[0013] Secondly, embodiments of this application provide a method for finding the connection relationship of a selector module. The method includes: receiving a search instruction transmitted by a serial communication terminal through the serial communication interface module of a field-programmable gate array (FPGA); reading content from the corresponding address of the memory module of the FPGA according to the selector module number in the search instruction; and transmitting the read content back to the serial communication terminal through the serial communication interface module.

[0014] Thirdly, embodiments of this application provide a method for setting the connection relationship of selector modules. The method includes: receiving a setting instruction transmitted by a serial communication terminal through the serial communication interface module of a field-programmable gate array (FPGA); storing the selection signal contained in the setting instruction at the corresponding address of the memory module of the FPGA according to the selector module number in the setting instruction; setting the selection signal to the corresponding selector module among the plurality of selector modules; and transmitting a setting success message back to the serial communication terminal.

[0015] Fourthly, embodiments of this application provide a method for initializing the connection relationship of selector modules. The method includes: receiving an initialization command transmitted by a serial communication terminal through the serial communication interface module of the field-programmable gate array (FPGA); storing multiple selection signals in the initialization command into multiple corresponding addresses of the memory module of the FPGA; setting the multiple selection signals into corresponding selector modules among the multiple selector modules; and transmitting an initialization success message back to the serial communication terminal.

[0016] Fifthly, embodiments of this application also provide a computing device, including:

[0017] Memory, used to store program instructions;

[0018] A processor is configured to invoke program instructions stored in the memory and execute any of the methods described in the second to fourth aspects according to the obtained program instructions.

[0019] Sixthly, embodiments of this application also provide a computer-readable storage medium storing computer-readable instructions that, when read and executed by a computer, cause any one of the methods of the second to fourth aspects described above to be implemented. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic diagram of the structure of a field-programmable gate array device provided in this application embodiment. Figure 1 ;

[0022] Figure 2 A schematic diagram of the structure of a field-programmable gate array device provided in this application embodiment. Figure 2 ;

[0023] Figure 3 A flowchart illustrating a method for finding the connection relationship of a selector module provided in an embodiment of this application;

[0024] Figure 4 A flowchart illustrating a method for setting the connection relationship of a selector module, provided in an embodiment of this application;

[0025] Figure 5 A flowchart illustrating a method for initializing the connection relationship of a selector module provided in an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] In the embodiments of this application, "multiple" refers to two or more. Terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0029] In the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for mutual communication; they can refer to a direct connection or an indirect connection via an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the aforementioned terms in this application according to the specific circumstances.

[0030] Figure 1 An exemplary embodiment of this application provides a field-programmable gate array device, such as... Figure 1 As shown, the field-programmable gate array device includes a connection network 110, a plurality of logic circuit units 120, each logic circuit unit having at least one port 130, a selector module 210, a pad 140, and a pin 150.

[0031] The multiple logic circuit units 120 are interconnected via a connection network 110. These interconnected logic circuit units 120 implement the functions of the chip under test.

[0032] Any of the plurality of logic circuit units 120 has at least one port 130. The port 130 may be an input and / or output port of the logic circuit unit 120, used for signal input and output.

[0033] Any selector module 210 is fixedly connected to any port 130 and selectively connected to a plurality of pads 140. The ports 130 to which the multiple selector modules 210 are fixedly connected are all different. The selector module 210 can select one or more of the multiple pads 140 to be connected to port 130 based on the selection signal 212. Although in Figure 1 In the example shown, only one selector module 210 is shown, but the field programmable gate array device of this application may include multiple selector modules 210 so that they can be connected to multiple ports 130 respectively.

[0034] Understandably, the port 130 inside the programmable gate array device needs to be brought out to the outside for packaging. However, because the wire width is too thin, it cannot withstand the pressure of soldering. It needs to be connected to a large metal block first, and the large metal block is used as a support. This large metal block that withstands the pressure is the pad 140.

[0035] Pin 150 is the packaged pin, and there is a one-to-one correspondence between pad 140 and pin 150. That is, for one port 130 of logic circuit unit 120, it is connected to multiple selected pads 140 through selector module 210. Each pad 140 is then connected to a corresponding pin 150, thus connecting the logic circuit unit 120 to an external circuit. To distribute the input signal of one pin 150 to different logic circuit units 120, one pad 140 can be connected to multiple selector modules 210. When an input signal is needed, multiple selector modules 210 can choose to connect to the same pad 140.

[0036] Understandably, in Figure 1 In the example, selector module 210 is connected to only three pads 140. In practice, selector module 210 can be connected to N pads 140, where N is a positive integer greater than 1. Based on the input of selection signal 212, selector module 210 can select one or more of the N pads 140 and connect them to port 130.

[0037] In the above technical solution, the selector module 210 can connect the port to a specified pad according to the input selection signal 212. The specified pad is one or more of a plurality of pads to which the port is selectively connected. Thus, the external circuitry of the corresponding pin of the port and the specified pad is connected, eliminating the need to re-program the port-pad connection configuration in the configuration file, saving time spent programming the configuration file.

[0038] The selector module 210 can be composed of a cascaded multiplexer structure. Assuming each multiplexer is a two-choice specification, then... Figure 1 The selector module 210 shown can be composed of a double-cascaded structure consisting of two multiplexers. That is, the more pads 140 connected to the selector module 210, the larger and more complex the selector module 210 becomes. Therefore, this application divides the ports into dedicated ports, test ports, and bonding ports. The dedicated port and test port each have their own selector module. The dedicated port is connected to at least one pad of the same type through its corresponding selector module. The test port is connected to any pad through its corresponding selector module. The bonding port is directly connected to a fixed pad.

[0039] exist Figure 1In the example, the rightmost port 130 and pad 140 can maintain a fixed connection, without being connected to selector module 210 in between, thus reducing the number of selector modules. Alternatively, for design consistency, a selector module 210 can be inserted between the bonded port and the pad connection. This selector module 210 is then connected only to the fixed pad. Regardless of the selection signal received by the selector module 210, the connection between the port and the fixed pad remains unchanged.

[0040] In one possible design, to maintain design flexibility of the selector modules, multiple selector modules include a first selector module and a second selector module. The first selector module is fixedly connected to a first port among multiple ports and selectively connected to P pads among multiple pads. The second selector module is fixedly connected to a second port among multiple ports and selectively connected to Q pads among multiple pads, where P is a positive integer greater than 1, Q is a positive integer greater than 1, and P is not equal to Q.

[0041] In one possible design, to allow two ports to connect to the same input signal, multiple selector modules include a first selector module and a second selector module. The first selector module is fixedly connected to a first port among the multiple ports and selectively connected to P pads among a plurality of pads. The second selector module is fixedly connected to a second port among the multiple ports and selectively connected to Q pads among a plurality of pads. Here, P is a positive integer greater than 1, Q is a positive integer greater than 1, and the first pad among the P pads is one of the Q pads.

[0042] In one possible design, to prevent two ports from connecting to the same pad, multiple selector modules include a first selector module and a second selector module. The first selector module is fixedly connected to a first port among the multiple ports and selectively connected to P pads among the multiple pads. The second selector module is fixedly connected to a second port among the multiple ports and selectively connected to Q pads among the multiple pads. Here, P is a positive integer greater than 1, Q is a positive integer greater than 1, and none of the P pads belongs to one of the Q pads.

[0043] In one possible design, such as Figure 2 As shown, the field-programmable gate array device provided in this application also includes a memory module 220, a serial communication interface module 230, and a control module 240.

[0044] Memory module 220 is used to store the pads selectively connected to multiple selector modules. That is, the memory module has a storage space that stores the selection signals of each selector module, indicating which pad the corresponding port of the selector module is currently connected to. This memory can be a volatile register (ROM register). ROM registers have two advantages: first, the contents of the ROM register are easy to modify, as they can be directly written to the ROM register via a serial communication terminal (usually a personal computer) through a serial communication interface; second, ROM registers are volatile, meaning that data is not retained after the field-programmable gate array (FPGA) is powered off. Restarting the FPGA will not affect the normal operation of the chip or other users.

[0045] The serial communication interface module 230 is used to connect to a serial communication terminal via a serial communication standard. The serial communication terminal can be a common desktop calculator, laptop calculator, tablet calculator, etc., and can have human-machine interfaces such as a keyboard, mouse, screen, or touchscreen. Users can issue commands to the control module through this serial communication terminal. Communication is established between the serial communication terminal and the serial communication interface module of the field-programmable gate array (FPGA). The serial communication interface module can be an interface conforming to industry-standard serial communication standards, such as UART or USB.

[0046] The control module 240 is connected to the memory module 220, the serial communication interface module 230, and multiple selector modules 210. The control module is used to receive search instructions transmitted by the serial communication terminal through the serial communication interface module, read the contents from the corresponding address in the memory module according to the selector module number in the search instruction, and transmit the read contents back to the serial communication terminal through the serial communication interface module.

[0047] The control module 240 is also used to receive the setting command transmitted by the serial communication terminal through the serial communication interface module, store the selection signal contained in the setting command at the corresponding address of the memory module according to the selector module number in the setting command, set the selection signal to the corresponding selector module among the multiple selector modules, and transmit the setting success information back to the serial communication terminal.

[0048] The control module 240 is also used to receive initialization instructions transmitted by the serial communication terminal through the serial communication interface module, store multiple selection signals in the initialization instructions into multiple corresponding addresses in the memory module, set the multiple selection signals into the corresponding selector modules in the multiple selector modules, and transmit the initialization success information back to the serial communication terminal.

[0049] Because there's a one-to-one relationship between selector modules and ports—one selector module corresponds to one port—all ports connected to selector modules can be numbered. For example, when there are 256 ports connected to various selector modules, it means there are 256 selector modules. Their port numbers and selector module numbers are 0 to 255, or 0x00 to 0xFF. A space of 256 addresses can be located in memory, with each address storing the selection signal for the corresponding selector module. For example, to find out which pad of the selector module the 128th port is connected to, you can look up the content at address 0x70. Assuming its content is 0b0000011, it indicates the fourth pad. To reconnect the 128th port to the second pad, the content of address 0x70 can be set to 0b00000001, and this content can be used as the selection signal for the 128th selector module.

[0050] In one possible design, a default connection pad can be set for the selector module during configuration. After the FPGA restarts, the selector module is in the default connection state, and the corresponding port of the selector module is connected to the default connection pad. For example, the first pad connected to the selector module can be set as the default connection pad during configuration. After the FPGA restarts, the contents of the memory are also reset to 0b00000000. Therefore, the selector module's selection signal will be consistent with the corresponding memory contents.

[0051] Figure 3 This paper exemplifies a flowchart illustrating a method for finding the connection relationship of a selector module according to an embodiment of this application. This method is applicable to the aforementioned field-programmable gate array (FPGA) device and can be specifically derived from... Figure 2 The control module shown is executed. For example... Figure 3 As shown, the method includes the following steps:

[0052] Step 301: Receive the search command transmitted by the serial communication terminal through the serial communication interface module of the field programmable gate array device.

[0053] The search command contains either the selector module number or the port number you wish to find. Since there is a one-to-one relationship between ports and selector modules, the search command can contain either the selector module number or the port number.

[0054] Step 302: Based on the selector module number in the search instruction, read the contents from the corresponding address of the memory module of the field programmable gate array device.

[0055] Step 303: Transmit the read content back to the serial communication terminal through the serial communication interface module.

[0056] Figure 4 This illustration shows a flowchart of a method for setting the connection relationship of selector modules according to an embodiment of this application, applicable to the above-mentioned field-programmable gate array device, and specifically can be provided by... Figure 2 The control module shown is executed. For example... Figure 4 As shown, the method includes the following steps:

[0057] Step 401: Receive setting instructions transmitted from the serial communication terminal through the serial communication interface module of the field programmable gate array device.

[0058] This configuration command includes the number of the selector module or port to be configured, as well as the selection signal. Since there is a one-to-one relationship between ports and selector modules, this configuration command can include either the selector module's or the port's number.

[0059] Step 402: Based on the selector module number in the setting instruction, store the selection signal contained in the setting instruction at the corresponding address in the memory module of the field programmable gate array device.

[0060] Step 403: Set the selection signal to the corresponding selector module among multiple selector modules.

[0061] This application does not limit the order of steps 402 and 403. After steps 402 and 403 are completed, the process proceeds to step 404.

[0062] Step 404: Send the successful setup message back to the serial communication terminal.

[0063] Figure 5 This application provides an exemplary flowchart illustrating a method for initializing the connection relationship of a selector module, applicable to the aforementioned field-programmable gate array (FPGA) device. Specifically, it can be implemented using... Figure 2 The control module shown is executed. For example... Figure 5 As shown, the method includes the following steps:

[0064] Step 501: Receive the initialization command transmitted by the serial communication terminal through the serial communication interface module of the field programmable gate array device.

[0065] This initialization instruction contains multiple selection signals corresponding to multiple selector modules. These selection signals can be viewed as a long string. For example, when there are 256 selector modules, and each selection signal has 8 bits, the multiple selection signals can be viewed as a long string of 256 bits or bytes.

[0066] Step 502: Store the multiple selection signals in the initialization instruction into multiple corresponding addresses in the memory module of the field programmable gate array device.

[0067] In this embodiment of the application, when these addresses are consecutive, a long string can be stored at the starting address at once without executing multiple storage instructions.

[0068] Step 503: Set the multiple selection signals to the corresponding selector modules in the multiple selector modules respectively.

[0069] This application does not limit the order of steps 502 and 503. After steps 502 and 503 are completed, the process proceeds to step 504.

[0070] Step 504: Send the initialization success message back to the serial communication terminal.

[0071] This application provides a field-programmable gate array (FPGA) device and a method for finding, setting, and initializing the connection relationships of a selector module. By adding a selector module between the ports and pads of the logic circuit units within the FPGA, the connection relationships between the ports and pads of the internal logic circuit units can be quickly configured based on user-issued find, set, and initialization commands. This eliminates the need to rewrite and burn the FPGA configuration file, reducing the time required for reconfiguring ports and pads and accelerating the testing, modulation, and verification process of the chip under test.

[0072] Based on the same technical concept, embodiments of this application provide a computing device, such as... Figure 6 As shown, it includes at least one processor 601 and a memory 602 connected to at least one processor. In this embodiment, the specific connection medium between the processor 601 and the memory 602 is not limited. Figure 6 Taking the connection between the processor 601 and the memory 602 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0073] In this embodiment of the application, the memory 602 stores instructions that can be executed by at least one processor 601. By executing the instructions stored in the memory 602, at least one processor 601 can perform the above-described method for finding, setting, and initializing the connection relationship of the selector module.

[0074] The processor 601 is the control center of the computing device. It can connect to various parts of the computer device through various interfaces and lines, and perform resource settings by running or executing instructions stored in the memory 602 and calling data stored in the memory 602.

[0075] Optionally, processor 601 may include one or more processing units. Processor 601 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into processor 601. In some embodiments, processor 601 and memory 602 may be implemented on the same chip; in some embodiments, they may be implemented separately on independent chips.

[0076] Processor 601 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0077] Memory 602, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 602 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 602 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. In the embodiments of this application, memory 602 may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0078] Based on the same technical concept, embodiments of this application also provide a computer-readable storage medium storing a computer-executable program, which is used to enable a computer to perform any of the above-described methods for finding, setting, and initializing the connection relationships of the selector modules.

[0079] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0080] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0081] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0082] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0083] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0084] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A field-programmable gate array (FPGA) device, characterized in that, include: Multiple logic circuit units that are interconnected; The multiple logic circuit units implement the functions of the chip to be verified; Each of the plurality of logic circuit units has at least one port; Multiple pins used to connect at least one logic circuit unit to an external circuit; Multiple gaskets are connected to the multiple pipe pins respectively; as well as Multiple selector modules, wherein any selector module is fixedly connected to any port and selectively connected to a plurality of pads, wherein the ports fixedly connected to the multiple selector modules are all different; Among them, any selector module is used to select one or more of the plurality of pads and connect them to the port that is fixedly connected to it, according to the selection signal; At least one of the plurality of pads is connected to a plurality of selector modules such that the plurality of selector modules select to be connected to the same pad.

2. The field-programmable gate array device according to claim 1, characterized in that, The multiple ports include dedicated ports, test ports, and bound ports; The dedicated port and the test port each have their own selector module; The dedicated port is connected to at least one gasket of the same type via a corresponding selector module; The test port is connected to any pad through a corresponding selector module; The binding port is directly connected to the fixed pad.

3. The field-programmable gate array device according to claim 1, characterized in that, The plurality of selector modules include: A first selector module is fixedly connected to a first port among the plurality of ports and selectively connected to P pads among the plurality of pads; and The second selector module is fixedly connected to the second port of the plurality of ports and selectively connected to Q pads of the plurality of pads. Where P is a positive integer greater than 1, Q is a positive integer greater than 1, and P is not equal to Q.

4. The field-programmable gate array device according to claim 1, characterized in that, The plurality of selector modules includes: A first selector module is fixedly connected to a first port among the plurality of ports and selectively connected to P pads among the plurality of pads; and The second selector module is fixedly connected to the second port of the plurality of ports and selectively connected to Q of the plurality of pads; Where P is a positive integer greater than 1, and Q is a positive integer greater than 1; The first of the P pads is one of the Q pads.

5. The field-programmable gate array device according to claim 1, characterized in that, Also includes: A memory module is used to store the pads selectively connected to the plurality of selector modules; A serial communication interface module, used to connect to a serial communication terminal via a serial communication standard; as well as A control module is connected to the memory module, the serial communication interface module, and the plurality of selector modules. The control module is used to receive a search command transmitted by the serial communication terminal through the serial communication interface module; and to read content from the corresponding address of the memory module according to the selector module number in the search command. And the read content is transmitted back to the serial communication terminal through the serial communication interface module.

6. The field-programmable gate array device according to claim 5, characterized in that, The control module is also used for: The serial communication interface module receives setting commands transmitted by the serial communication terminal. According to the selector module number in the setting instruction, the selection signal contained in the setting instruction is stored at the corresponding address in the memory module; The selection signal is set to the corresponding selector module among multiple selector modules; and The successful setup message will be sent back to the serial communication terminal.

7. The field-programmable gate array device according to claim 5, characterized in that, The control module is also used for: The serial communication interface module receives the initialization command transmitted by the serial communication terminal. The multiple selection signals in the initialization instruction are stored in the corresponding addresses of the memory module, respectively. The plurality of selection signals are respectively set to the corresponding selector modules in the plurality of selector modules; as well as The initialization success message is sent back to the serial communication terminal.

8. A method for finding the connection relationship of selector modules, applicable to the field-programmable gate array device as described in any one of claims 1 to 4, characterized in that, The method includes: The serial communication interface module of the field-programmable gate array (FPGA) device receives the search command transmitted by the serial communication terminal. Based on the selector module number in the search instruction, the content is read from the corresponding address of the memory module of the field-programmable gate array device; and The read content is transmitted back to the serial communication terminal through the serial communication interface module.

9. A method for setting the connection relationship of selector modules, applicable to the field-programmable gate array device as described in any one of claims 1 to 4, characterized in that, The method includes: The serial communication interface module of the field-programmable gate array device receives setting commands transmitted by the serial communication terminal; According to the selector module number in the setting instruction, the selection signal contained in the setting instruction is stored at the corresponding address in the memory module of the field programmable gate array device; The selection signal is set to the corresponding selector module among the plurality of selector modules; and The successful setup message will be sent back to the serial communication terminal.

10. A method for initializing the connection relationships of a selector module, applicable to the field-programmable gate array device as described in any one of claims 1 to 4, characterized in that, The method includes: The serial communication interface module of the field-programmable gate array (FPGA) receives initialization commands transmitted from the serial communication terminal. The multiple selection signals in the initialization instruction are stored in multiple corresponding addresses of the memory module of the field-programmable gate array device. The plurality of selection signals are respectively set to the corresponding selector modules in the plurality of selector modules; and The initialization success message is sent back to the serial communication terminal.

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