A log-based frequency and precision reconfigurable approximate floating point multiplier

Abstract

This invention discloses a logarithmic frequency and precision reconfigurable approximate floating-point multiplier, belonging to the field of chip design and FPGA technology. It includes: a sign determination module for determining the sign bit of the product of two operands; a mantissa calculation module, including a first adder, where the mantissas of the two operands are input and the output is an approximation of the mantissa of the product; and an exponent calculation module, including an eight-bit adder with carry and a nine-bit subtractor, for calculating the exponent of the product. This multiplier significantly improves the multiplier's operating speed and reduces the circuit area. It also provides different operating modes for varying precision and frequency requirements. In specific cases, the accuracy of the calculation result can be further improved by selecting two error correction modes. It is a high-speed, low-power approximate multiplier, more suitable for large-scale integrated circuit applications.

Description

Technical Field

[0001] This invention belongs to the field of chip design and FPGA technology, and more specifically, relates to an approximate floating-point multiplier with reconfigurable frequency and precision based on logarithms. Background Technology

[0002] In recent years, with the development of artificial intelligence and machine learning, the application of neural networks has become increasingly frequent and its scope has expanded. However, as the scenarios in which neural networks are used become more complex, the amount of computation required for training and using neural networks is also gradually increasing. Therefore, higher demands are being placed on the data processing capabilities of chips. At the same time, the massive computational load also brings about a gradually increasing and increasingly significant power consumption issue, posing new challenges to circuit performance.

[0003] Among them, the multiplier, as the most important and fundamental arithmetic unit, plays a crucial role in neural networks. However, without improvements to the basic circuit components, it has become extremely difficult to further improve the speed of traditional multipliers through simple optimization. Therefore, there is an urgent need to propose a novel multiplier architecture that significantly improves the speed of multiplication operations. This is to ensure the high-speed operation of neural networks to adapt to the more complex and diverse needs of modern society.

[0004] Currently, there are two main basic structures for traditional multipliers: serial multiplier architecture and parallel multiplier architecture. Traditional serial multipliers have the advantages of simple structure and small area, but their characteristic is that the generation and accumulation of partial products are performed in stages. Each cycle generates one partial product, and then an adder is repeatedly used for accumulation. This means that for an n-bit multiplier, n cycles are needed to obtain the final result, resulting in a long operation cycle, which is not conducive to high-speed multiplication. Parallel multipliers, on the other hand, directly and synchronously expand each step of the multiplication operation within the chip, processing the generation and compression of partial products in parallel, thus greatly improving the speed of multiplication. However, their circuitry is very complex, wasting wiring resources, occupying a large area, and consuming a lot of power; it is a space-for-time trade-off.

[0005] In the existing technology, some new multiplier structures have been proposed. Most of them focus on optimizing the traditional multiplier architecture as much as possible, or choose to merge two traditional multiplier structures, or improve the performance of the multiplier through structural optimization. However, these methods are still limited to the structure of traditional multipliers. Although they can optimize the multiplier's operating speed and power consumption to a certain extent, they cannot truly solve the problems of multiplier's operating speed and power consumption.

[0006] Furthermore, with the advancement of technology, in fields such as neural networks and machine learning, which demand higher speed from multipliers but not as stringent accuracy requirements, optimizing traditional multiplier structures is becoming increasingly inadequate. Therefore, there is an urgent need to provide a novel multiplier architecture that is simpler in structure and more suitable for neural network operations. Summary of the Invention

[0007] To address the shortcomings and improvement needs of existing technologies, this invention provides a logarithmic frequency and precision reconfigurable approximate floating-point multiplier. Its purpose is to significantly improve the multiplier's operating speed and reduce the circuit area by slightly sacrificing the precision of the calculation results, making it more suitable for large-scale integrated circuit applications.

[0008] To achieve the above objectives, the present invention provides an approximate floating-point multiplier with reconfigurable frequency and precision based on logarithms, comprising:

[0009] The sign determination module is used to determine the sign bit of the product of two operands, where the two operands are 16-bit floating-point numbers;

[0010] The tail code calculation module includes a first adder. The tail codes of two operands are input into the first adder, and the output result after addition is an approximate value of the tail code of the product of the two operands.

[0011] The exponent calculation module includes an eight-bit adder with carry and a nine-bit subtractor. The exponents of the two operands are input to the eight-bit adder with carry. The most significant bit of the output result of the mantissa calculation module is input to the carry bit of the eight-bit adder with carry. The output result of the eight-bit adder with carry and the nine-bit decimal number 127 are respectively input to the nine-bit subtractor for subtraction. The output of the nine-bit subtractor is the exponent of the product of the two operands.

[0012] Furthermore, the multiplier also includes an error correction module, and the tail code calculation module also includes a second adder;

[0013] The error correction module is used to correct the output of the tail code calculation module;

[0014] The outputs of the first adder and the error correction module are respectively input into the second adder and added together. The output of the second adder is the tail code of the product of the two operands.

[0015] Furthermore, the error correction module includes four parallel 3×3 multipliers, a bit extension unit, two nine-bit adders and one twelve-bit adder, denoted as the third adder and the fourth adder, and the twelve-bit adder as the fifth adder;

[0016] Divide the high 6 bits of the mantissa of the two operands into high 3 bits and low 3 bits. Let the high 3 bits and low 3 bits of one operand be MA[5:3] and MA[2:0], and the high 3 bits and low 3 bits of the other operand be MB[5:3] and MB[2:0], respectively.

[0017] The inputs of the four parallel 3×3 multipliers are MA[5:3] and MB[5:3], MA[5:3] and MB[2:0], MA[2:0] and MB[5:3], MA[2:0] and MB[2:0], respectively. After multiplication by the 3×3 multipliers, the outputs are denoted as MA_53_MB_53, MA_53_MB_20, MA_20_MB_53, and MA_20_MB_20, respectively. The shift operation unit includes first performing bit extension on the corresponding operands and then padding the corresponding bits with 0.

[0018] The bit extension unit is used to pad the low bits of MA_53_MB_53 with 3 bits of 0 and the high bits of MA_53_MB_20 with 3 bits of 0, and then input them to the third adder for addition. The output result is denoted as M1.

[0019] The bit extension unit is also used to pad the low bits of MA_20_MB_53 with 3 bits of 0 and the high bits of MA_20_MB_20 with 3 bits of 0, and then input them to the fourth adder for addition, and the output result is recorded as M2;

[0020] The bit extension unit is also used to pad the low bits of M1 with 3 bits of 0 and the high bits of M2 with 3 bits of 0, and then input them into the fifth adder for addition, and take the high 7 bits of the output result as the high-precision output result M_H of the error correction module.

[0021] Furthermore, the error correction module also includes a low-precision output unit and a second precision selector; the multiplier also includes a clock and a precision control module;

[0022] The low-precision output unit is used to pad MA_53_MB_53 with one bit in the least significant bit and use it as the low-precision output result M_L of the error correction module.

[0023] The clock and precision control module is used to output a control signal to control the second precision selector to select the high precision output result M_H or the low precision output result M_L as the output of the error correction module.

[0024] Furthermore, the 3×3 multiplier includes a partial product generating unit, a first half adder, a second half adder, a one-bit full adder, and a three-bit carry-lookahead adder;

[0025] The partial product generation unit is used to generate nine initial partial products based on the input, which are denoted as x2y2, x2y1, x1y2, x0y2, x1y1, x2y0, x0y1, x1y0, and x0y0 in sequence from the most significant bit to the least significant bit.

[0026] x0y0 is the least significant bit of the output result of the 3×3 multiplier, denoted as S0;

[0027] x0y1 and x1y0 are used as inputs to the first half-adder HA, and the output result obtained by adding them is denoted as S1;

[0028] x0y2, x1y1, and x2y0 are used as inputs to the one-bit full adder, and x2y1 and x1y2 are used as inputs to the second half adder. The carry output of the first half adder and the output of the one-bit full adder are used together as the first input of the three-bit carry-lookahead adder CLA. The output after addition is denoted as S2.

[0029] The carry-out of the one-bit full adder and the output of the second half adder are used together as the second input of the three-bit carry-lookahead adder. The output after addition is denoted as S3.

[0030] The carry-out output of the second half-adder, together with x2y2, serves as the third input of the three-bit carry-lookahead adder A. The result after addition is denoted as S4.

[0031] The carry-out bit output of the three-bit carry-lookahead adder is used as the highest bit of the output result of the 3×3 multiplier, denoted as S5.

[0032] Then S5, S4, S3, S2, S1, and S0 are successively used as the output results of the 3×3 multiplier.

[0033] Furthermore, the tail code calculation module also includes a first precision selector block;

[0034] The clock and precision control module is used to output control signals to control the first precision selector to select the output of the first adder as the tail code of the product of the two operands, or to select the output of the second adder as the tail code of the product of the two operands.

[0035] Furthermore, both the first precision selector and the second precision selector are seven-bit data selectors.

[0036] Furthermore, the clock and precision control module employs a glitch-free clock switching circuit.

[0037] Furthermore, the first adder is a seven-bit adder, and the second adder is an eight-bit adder.

[0038] Furthermore, the sign determination module XORs the sign bits of the two operands to obtain the sign bit of the product of the two operands.

[0039] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0040] (1) The floating-point multiplier designed in this invention is based on logarithmic approximation. It transforms the multiplication operation of two mantissas into a logarithmic operation. Based on the characteristics of floating-point mantissas, a logarithmic approximation is taken, so that the result of multiplying the mantissas of two floating-point numbers can be approximated as the sum of the mantissas of the two floating-point numbers. Although the accuracy of the calculation result is slightly sacrificed, the operating speed of the multiplier is greatly improved and the circuit area is significantly reduced. This new architecture is more suitable for applications such as neural networks and machine learning, which have high requirements for multiplier speed but not very strict requirements for accuracy.

[0041] (2) Considering that different scenarios may have different accuracy requirements, this invention further designs an error correction module to compensate for the approximate calculation results. The output result of the tail code approximation is summed with the error correction coefficient to correct the calculation result, resulting in a more accurate result. Furthermore, depending on the application scenario, different precision outputs can be achieved through a first precision selector. Simultaneously, the error correction module designed in this invention, through its internal structure combined with a second precision selector, can achieve both high-precision and low-precision outputs, further enabling the output of different precisions according to different accuracy requirements, thus achieving precision reconstruction and having a wide range of applications.

[0042] (3) As a further design of the present invention, the error correction module is designed in a serial-parallel combination manner. The four high-speed 3×3 multipliers and the two nine-bit adders all work in parallel, while the high-speed 3×3 multipliers and adders work serially. Compared with the existing serial multipliers, the 3×3 multipliers of the present invention are faster. Compared with the existing parallel multipliers, the 3×3 multipliers of the present invention have a smaller circuit area and are more suitable for large-scale integrated circuits.

[0043] (4) Furthermore, the high-speed 3×3 multiplier designed in this invention adopts a pure parallel structure, which ensures high operation speed while minimizing the consumption of hardware resources through optimized design.

[0044] (5) Furthermore, the clock and precision control module designed in this invention adopts a glitch-free clock switching circuit, which can realize the glitch-free switching of multiple unrelated clock signals, so that the multiplier can work at different frequencies and realize the reconstruction of the multiplier frequency.

[0045] In summary, the logarithmic frequency and precision reconfigurable approximate floating-point multiplier of this invention can significantly improve the operating speed of the multiplier and significantly reduce the circuit area. It also provides different operating modes for different precision and frequency requirements. In specific cases, the accuracy of the calculation results can be further improved by selecting two error correction modes. It is a high-speed, low-power approximate multiplier that is more suitable for large-scale integrated circuit applications. Attached Figure Description

[0046] Figure 1 The diagram shows the structure of a logarithmically reconfigurable frequency and precision approximate floating-point multiplier provided in an embodiment of the present invention.

[0047] Figure 2 This is an architecture diagram of the error correction module provided in an embodiment of the present invention.

[0048] Figure 3 The FECE architecture diagram provided for embodiments of the present invention.

[0049] Figure 4 This is a diagram illustrating the architecture of the clock and precision control module provided in an embodiment of the present invention.

[0050] Figure 5 A timing logic diagram provided for an embodiment of the invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0052] In this invention, the terms "first," "second," etc., used in the invention and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, it is stated that the shift operation mentioned in this invention refers to first extending the original data by bits, and then padding the corresponding bits with zeros.

[0053] like Figure 1 As shown, the present invention provides an approximate floating-point multiplier with reconfigurable frequency and precision based on logarithms. The floating-point multiplier is a 16-bit multiplier and mainly includes: a multiplication core, an error correction module, and a clock and precision control module.

[0054] The multiplication kernel mainly includes: a sign determination module, an exponent calculation module, and a mantissa calculation module;

[0055] The sign determination module is used to determine the sign of the product of two operands. Specifically, it XORs the sign bits of the two operands, and the output is the sign bit of the product. The two operands are 16-bit floating-point numbers.

[0056] The exponent calculation module is used to calculate the exponent of the product of two operands. Specifically, it includes an eight-bit adder with carry and a nine-bit subtractor. The exponents of the two operands are input to the eight-bit adder with carry. The carry bit (most significant bit) of the mantissa calculation result output by the mantissa calculation module is input to the carry bit of the eight-bit adder with carry. After the exponents of the two operands are added, the resulting 9 bits are input to the nine-bit subtractor. The difference between the subtractor and 9'd127 (i.e., the nine-bit decimal number 127) is then calculated. The output of the nine-bit subtractor is the exponent of the product of the two operands.

[0057] The tail code calculation module is used to calculate the tail code of the product of two operands. Specifically, it includes a first adder. The tail codes of the two operands are input into the first adder, and the output after addition is an approximate value of the tail code of the product of the two operands. The highest bit of the final result output by the first adder is the carry bit, and the first adder is a seven-bit adder.

[0058] The outputs of the sign determination module, the exponent calculation module, and the mantissa calculation module constitute the sign bit, exponent, and mantissa of the floating-point multiplier output in sequence.

[0059] To further improve the accuracy of the multiplier calculation results of this invention, the tail code calculation module also includes a second adder, which works in conjunction with the error correction module to improve the accuracy of the calculation results.

[0060] Specifically, in the tail code calculation module, the tail code approximation value output by the first adder and the output of the error correction module are respectively input into the second adder. After addition, the output result of the second adder is the corrected product calculation result. In this embodiment, the second adder is an eight-bit adder.

[0061] Furthermore, a first precision selector is designed in the tail code calculation module. The outputs of the first adder and the second adder are respectively input into the first precision selector to select different precision outputs. According to different precision requirements and application scenarios, based on the control signals output by the clock and precision control module, the first precision selector is controlled to select different precisions. In cases where speed is required but precision is not required, the tail code approximation value of the output of the first adder can be selected as the tail code calculation result of the multiplier of the present invention. In cases where precision is required, the output result of the second adder can be selected as the tail code calculation result of the multiplier of the present invention.

[0062] Specifically, such as Figure 2As shown, the error correction module is used to correct the approximate calculation result of the tail code product in order to improve the accuracy of the calculation result. It mainly includes: four parallel high-speed 3×3 multipliers, bit extension unit, two nine-bit adders and one 12-bit adder; the two nine-bit adders are referred to as the third adder and the fourth adder, and the 12-bit adder is referred to as the fifth adder.

[0063] Four parallel high-speed 3×3 multipliers constitute an ultra-high-speed 3-bit multiplier, denoted as Fast ErrorCorrection Element (FECE).

[0064] Divide the high 6 bits of the mantissa of the two multipliers into high 3 bits and low 3 bits. Let the high 3 bits and low 3 bits of one multiplier be MA[5:3] and MA[2:0], and the high 3 bits and low 3 bits of the other multiplier be MB[5:3] and MB[2:0]. Then the inputs of the four parallel 3×3 multipliers are MA[5:3] and MB[5:3], MA[5:3] and MB[2:0], MA[2:0] and MB[5:3], MA[2:0] and MB[2:0]. The six-bit outputs of the four parallel 3×3 multipliers are denoted as MA_53_MB_53, MA_53_MB_20, MA_20_MB_53, and MA_20_MB_20.

[0065] The bit extension unit is used to pad the low bits of MA_53_MB_53 with 3 bits of 0 and the high bits of MA_53_MB_20 with 3 bits of 0, and then input them into the third adder. After addition, the output result is recorded as M1.

[0066] The bit extension unit is also used to pad the low bits of MA_20_MB_53 with 3 bits of 0 and the high bits of MA_20_MB_20 with 3 bits of 0, and then input them into the fourth adder. After addition, the output result is recorded as M2.

[0067] The bit extension unit is also used to pad the low bits of M1 with 3 bits of 0 and the high bits of M2 with 3 bits of 0, and then input them into the fifth adder. After addition, the high 7 bits of the output result are taken as the high-precision output result M_H of the error correction module.

[0068] As a further design of the present invention, based on the above scheme, by combining a low-precision output unit, a second precision selector, and a clock and precision control module, the present invention can further achieve more refined precision selection and control;

[0069] The low-precision output unit is used to pad the low-order bits of MA_53_MB_53 with 1, which is the low-precision output result M_L of the error correction module;

[0070] Input M_L and M_H into the second precision selector controlled by the SEL signal, where the SEL signal is provided by the clock and precision control module. When the SEL signal is 1'b0, it is in low precision correction mode, and the error correction coefficient Manti_C output by the error correction module is M_L; when the SEL signal is 1'b1, it is in high precision correction mode, and the error correction module outputs Manti_C as M_H.

[0071] The approximate value of the tail code output by the first adder and the output result Manti_C of the error correction module are respectively input into the second adder. After addition, the output result is the corrected product calculation result.

[0072] As a further design of the present invention, based on the above scheme, by combining a low-precision output unit, a second precision selector, and a clock and precision control module, the present invention can further achieve more refined precision selection and control;

[0073] Specifically, the low-precision output unit is used to pad MA_53_MB_53 with a 1 at the end, serving as the low-precision output result M_L of the error correction module. The high-precision output result M_H and the low-precision output result M_L of the error correction module are respectively input to the second precision selector to select different precision outputs. Depending on the application scenario with different precision requirements, the SEL control signal output by the clock and precision control modules controls the second precision selector to select different precisions. In situations where precision requirements are not very high, the low-precision output result M_L can be selected. In this case, the error correction module only needs to run the 3*3 result once, which can improve the multiplier's operating speed while maintaining a certain level of precision. In this embodiment, the second precision selector is a seven-bit data selector.

[0074] As a further design of the present invention, a specific structure for a high-speed 3×3 multiplier is also designed, such as... Figure 3 Each high-speed 3×3 multiplier includes: a partial product generation unit, two one-bit half-adders HA, one one-bit full adder FA, and a three-bit carry-lookahead adder CLA. The two one-bit half-adders HA are denoted as the first half-adder HA and the second half-adder HA, respectively. The inputs of each high-speed 3×3 multiplier are x and y, both of which are 3-bit numbers.

[0075] The partial product generation unit is used to generate 9 initial partial products based on the inputs x and y of each high-speed 3×3 multiplier, which are denoted as x2y2, x2y1, x1y2, x0y2, x1y1, x2y0, x0y1, x1y0, and x0y0 in order from the most significant bit to the least significant bit.

[0076] The least significant partial product x0y0 is directly used as the least significant bit S0 of the output of the high-speed 3×3 multiplier; x0y1 and x1y0 are used as inputs to the first half-adder HA, and the output of the first half-adder HA is denoted as S1; x0y2, x1y1, and x2y0 are used as inputs to the one-bit full adder FA; x2y1 and x1y2 are used as inputs to the second half-adder HA; the carry-out output of the first half-adder HA and the output of the one-bit full adder FA are used together as the first input of the three-bit carry-lookahead adder CLA, and its output is denoted as S2. The carry-out bit output of a full adder FA and the output of a second half adder HA are used together as the second input of a three-bit carry-lookahead adder CLA, and its output is denoted as S3. The carry-out bit output of the second half adder HA and x2y2 are used together as the third input of a three-bit carry-lookahead adder CLA, and its output is denoted as S4. The carry-out bit output of a three-bit carry-lookahead adder CLA is denoted as S5. Then S5, S4, S3, S2, S1, and S0 are used as the output of a high-speed 3×3 multiplier in sequence, where S5 is the most significant bit and S0 is the least significant bit.

[0077] The high-speed 3×3 multiplier designed in this invention adopts a pure parallel structure, which ensures high operation speed while minimizing hardware resource consumption through optimized design.

[0078] Specifically, such as Figure 4 As shown, the clock and precision control module of this invention employs a glitch-free clock switching circuit, which includes a series of three-input AND gates, two-input AND gates, three-input OR gates, and a series of D flip-flops. This circuit eliminates glitches or metastabilities in multiple input clocks, enabling glitch-free switching of multiple unrelated clock signals. It can output multiple clocks of different frequencies as the operating clock frequencies of the multiplier, allowing the multiplier to operate at different frequencies and achieving frequency reconfiguration. Simultaneously, the clock and precision control module provides control signals to control the first precision selector and the second precision selector, enabling the multiplier to output different precisions. In this embodiment, the clock and precision control module eliminates glitches or metastabilities in the three input clocks, selects the output clock signal free of glitches and metastabilities according to the control signals, and transmits precision control signals to the multiplication core and error correction module through a mode register, thus achieving reconfigurable precision and clock operation.

[0079] The working method of the 16-bit fast floating-point multiplier designed in this invention specifically includes:

[0080] After initialization and receiving the reset signal, on the rising edge of the clock, the 16-bit multiplier A and the 16-bit multiplicand B are input into the input registers respectively, and the result of the multiplication operation is stored in register P.

[0081] The multiplication core is a pure combinational logic circuit. The most significant bits of A and B are input to the sign determination module, and the output result is directly used as the sign bit of the product of the two operands and output to the most significant bit of register P.

[0082] The lower 7 bits of A and B (i.e., the tail bits of the two operands, corresponding to...) Figure 1 The Manti[7:1] bits are input into the first adder in the tail code calculation module and added together to obtain the output result M_ADDER, which is the tail code approximation of the product of the two operands. The 6th to 1st bits of A and B are input into the error correction module according to the above grouping. At the same time, under the control of the MODE signal output by the clock and precision control module, the error correction module outputs the error correction coefficient Manti_C (that is, M_H or M_L mentioned above). Then, the lower 7 bits of the output result M_ADDER obtained by the first adder and the error correction coefficient Manti_C are input into the second adder. The output result of the second adder is the corrected product result M_Ptemp.

[0083] The highest bit of M_ADDER and M_Ptemp is ORed to obtain the carry signal Exp_Carry of the exponent pair. Exp_Carry is then input into the carry bit of the eight-bit adder with carry in the exponent calculation module. Bits 15 to 7 of A and B (i.e., the exponent bits of the two operands) are input into the eight-bit adder with carry in the exponent calculation module to obtain the output result E_P_temp1. E_P_temp1 and 9'd127 are input into the nine-bit subtractor. After subtraction, the output result is the exponent operation result E_P of the product of the two operands.

[0084] In the error correction module, bits 6 to 4 of A (denoted as MA[5:3]) and bits 6 to 4 of B (denoted as MB[5:3]), bits 6 to 4 of A and bits 3 to 1 of B (denoted as MB[2:0]), bits 3 to 1 of A (denoted as MA[2:0]) and bits 6 to 3 of B, bits 3 to 1 of A and bits 3 to 1 of B are respectively input into four 3×3 multipliers, and the output results are denoted as MA_53_MB_53, MA_53_MB_20, MA_20_MB_53, MA_20_MB_20; after padding the low bits of MA_53_MB_53 with 3 bits of 0 and the high bits of MB_53_MB_20 with 3 bits of 0, they are input into the third adder, and the output result is denoted as M1.

[0085] After padding the low-order bits of MA_20_MB_53 with 3 bits of 0 and the high-order bits of MA_20_MB_20 with 3 bits of 0, input them into the fourth adder. After adding them together, the output result is recorded as M2.

[0086] After padding the low-order bits of M1 with 3 bits of 0 and the high-order bits of M2 with 3 bits of 0, input them into the fifth adder respectively. After adding them together, take the high 7 bits of the output result (i.e., bits 11 to 5) to get the high-precision output result M_H of the error correction module.

[0087] Add 1 bit to the low-order bits of MA_53_MB_53 to get the low-precision output result M_L from the error correction module;

[0088] The second data selector, controlled by the MODE signal, selects either M_H or M_L as the error correction coefficient Manti_C output by the error correction module.

[0089] In the clock and precision control module, the clock for the multiplier is selected via MODE, and the characteristics of the D flip-flop are used to eliminate clock signal glitches and metastability. The specific working process is as follows: Figure 4 The diagram illustrates a glitch-free switching solution for related clock sources. A falling-edge-activated D flip-flop is inserted into the selection path of each clock source. On each falling edge of the clock, the register select control signal MODE is active, and the selection of a new clock is enabled after the selection of other clocks is released. The selection of one clock feeds back to the other two clocks, causing the gating switch to cancel the current clock's output selection before selecting the next clock, thus avoiding any potential glitches.

[0090] Specifically, for the three input clock signals, one-hot encoding is used for control, because only one of the three clocks will be selected at any given time, which is the same as the nature of one-hot encoding. The 2-bit MODE signal is selected by the one-hot encoder, and the encoded signals (sel1~sel3) are input to the mode register to control the calculation accuracy of the multiplier core. In addition, in this application, the output clock signal is used to drive the one-hot encoder, which not only eliminates the metastability of the MODE signal, but also further improves the system stability. Because when the clock speeds up, the critical path needs to be switched first, and when the clock speeds down, the clock signal needs to be switched first, this structure synchronizes the accuracy control signal with the clock of the multiplier core. All switching occurs on the rising edge of the clock before the clock gap time, thus solving the timing problem when switching between fast and slow clocks. The final runtime sequence is as follows. Figure 5 As shown. When the input MODE signal is 2'b00 or 2'b01, the output is clk_1; when the input MODE signal is 2'b10, the output is clk_2; when the input MODE signal is 2'b11, the output is clk_3.

[0091] The floating-point multiplier designed in this invention is based on logarithmic approximation. It transforms the multiplication operation of two mantissas into a logarithmic operation. Based on the characteristics of floating-point mantissas, a logarithmic approximation is taken, ultimately resulting in the product of the mantissas of two floating-point numbers being approximately the sum of their mantissas. Although this slightly sacrifices the accuracy of the calculation result, it greatly improves the multiplier's operating speed and significantly reduces the circuit area. This new architecture is more suitable for applications such as neural networks and machine learning, where high multiplier speed is required but accuracy is not a critical factor.

[0092] Considering that different scenarios impose different accuracy requirements, this invention further designs an error correction module to compensate for the approximate calculation results. It sums the approximate output result with the error correction coefficient to correct the result, obtaining a more accurate calculation result. Furthermore, depending on the application scenario, a first precision selector enables outputs of different precisions. Simultaneously, the error correction module of this invention, through its designed internal structure combined with a second precision selector, can also achieve high-precision and low-precision outputs, further enabling the output of different precisions according to different accuracy requirements, thus achieving precision reconstruction and broad applicability.

[0093] Furthermore, the error correction module in the design adopts a serial-parallel combination approach. The four high-speed 3×3 multipliers and two nine-bit adders all operate in parallel, while the high-speed 3×3 multipliers and adders operate serially. Compared with existing serial multipliers, the 3×3 multiplier of the present invention is faster, and compared with existing parallel multipliers, the 3×3 multiplier of the present invention has a smaller circuit area.

[0094] Furthermore, the designed clock and precision control module adopts a glitch-free clock switching circuit, which can realize glitch-free switching of multiple unrelated clock signals, enabling the multiplier to operate at different frequencies and realize the reconstruction of the multiplier frequency.

[0095] Furthermore, compared to existing multipliers that use high-order truncation for direct multiplication, the method of this invention, which first performs approximate calculation and then corrects errors through an error correction module, is faster because only one adder is needed during the approximate calculation process. Moreover, the approximation based on logical deduction in this invention has higher accuracy compared to the approach of direct hard truncation.

[0096] In summary, the multiplier architecture designed in this invention transforms floating-point multiplication into logarithmic addition, significantly improving computational efficiency while reducing circuit area and overall power consumption, making it more suitable for large-scale integrated circuit applications. The clock and precision control module enables glitch-free switching of multiple unrelated clock signals, as well as reconfigurable precision and frequency.

[0097] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A logarithmic frequency and precision reconfigurable approximate floating-point multiplier, characterized in that, include: The sign determination module is used to determine the sign bit of the product of two operands, where the two operands are 16-bit floating-point numbers; The tail code calculation module includes a first adder. The tail codes of two operands are input into the first adder, and the output result after addition is an approximate value of the tail code of the product of the two operands. The exponent calculation module includes an eight-bit adder with carry and a nine-bit subtractor. The exponents of the two operands are input to the eight-bit adder with carry. The most significant bit of the output result of the mantissa calculation module is input to the carry bit of the eight-bit adder with carry. The output result of the eight-bit adder with carry and the nine-bit decimal number 127 are respectively input to the nine-bit subtractor for subtraction. The output of the nine-bit subtractor is the exponent of the product of the two operands. The multiplier also includes an error correction module, and the tail code calculation module also includes a second adder; The error correction module is used to correct the output of the tail code calculation module; The output of the first adder and the output of the error correction module are respectively input into the second adder and added together. The output of the second adder is the tail code of the product of the two operands. The error correction module includes four parallel 3×3 multipliers, a bit extension unit, two nine-bit adders and one twelve-bit adder. The two nine-bit adders are referred to as the third adder and the fourth adder, and the twelve-bit adder is referred to as the fifth adder. Divide the high 6 bits of the mantissa of the two operands into high 3 bits and low 3 bits. Let the high 3 bits and low 3 bits of one operand be MA[5:3] and MA[2:0], and the high 3 bits and low 3 bits of the other operand be MB[5:3] and MB[2:0], respectively. The inputs of the four parallel 3×3 multipliers are MA[5:3] and MB[5:3], MA[5:3] and MB[2:0], MA[2:0] and MB[5:3], and MA[2:0] and MB[2:0]. After multiplication by the 3×3 multipliers, the outputs are denoted as MA_53_MB_53, MA_53_MB_20, MA_20_MB_53, and MA_20_MB_20, respectively. The bit extension unit includes first extending the corresponding operands and then padding the corresponding bits with 0. The bit extension unit is used to pad the low bits of MA_53_MB_53 with 3 bits of 0 and the high bits of MA_53_MB_20 with 3 bits of 0, and then input them to the third adder for addition. The output result is denoted as M1. The bit extension unit is also used to pad the low bits of MA_20_MB_53 with 3 bits of 0 and the high bits of MA_20_MB_20 with 3 bits of 0, and then input them to the fourth adder for addition. The output result is denoted as M2. The bit extension unit is also used to pad the low bits of M1 with 3 bits of 0 and the high bits of M2 with 3 bits of 0, and then input them to the fifth adder for addition, and take the high 7 bits of the output result as the high-precision output result M_H of the error correction module.

2. The multiplier according to claim 1, characterized in that, The error correction module also includes a low-precision output unit and a second precision selector; the multiplier also includes a clock and a precision control module. The low-precision output unit is used to pad MA_53_MB_53 with one bit in the least significant bit and use it as the low-precision output result M_L of the error correction module. The clock and precision control module is used to output a control signal to control the second precision selector to select the high precision output result M_H or the low precision output result M_L as the output of the error correction module.

3. The multiplier according to claim 2, characterized in that, The 3×3 multiplier includes a partial product generating unit, a first half adder, a second half adder, a one-bit full adder, and a three-bit carry-lookahead adder. The partial product generation unit is used to generate nine initial partial products based on the input, which are denoted as x2y2, x2y1, x1y2, x0y2, x1y1, x2y0, x0y1, x1y0, and x0y0 in sequence from the most significant bit to the least significant bit. x0y0 is the least significant bit of the output result of the 3×3 multiplier, denoted as S0; x0y1 and x1y0 are used as inputs to the first half-adder HA, and the output result obtained by adding them is denoted as S1; x0y2, x1y1, and x2y0 are used as inputs to the one-bit full adder, and x2y1 and x1y2 are used as inputs to the second half adder. The carry output of the first half adder and the output of the one-bit full adder are used together as the first input of the three-bit carry-lookahead adder CLA. The output after addition is denoted as S2. The carry-out of the one-bit full adder and the output of the second half adder are used together as the second input of the three-bit carry-lookahead adder. The output after addition is denoted as S3. The carry-out output of the second half-adder, together with x2y2, serves as the third input of the three-bit carry-lookahead adder A. The result after addition is denoted as S4. The carry-out bit output of the three-bit carry-lookahead adder is used as the highest bit of the output result of the 3×3 multiplier, denoted as S5. Then S5, S4, S3, S2, S1, and S0 are successively used as the output results of the 3×3 multiplier.

4. The multiplier according to claim 3, characterized in that, The tail code calculation module also includes a first precision selector block; The clock and precision control module is used to output control signals to control the first precision selector to select the output of the first adder as the tail code of the product of the two operands, or to select the output of the second adder as the tail code of the product of the two operands.

5. The multiplier according to claim 4, characterized in that, Both the first precision selector and the second precision selector are seven-bit data selectors.

6. The multiplier according to claim 4 or 5, characterized in that, The clock and precision control module uses a glitch-free clock switching circuit.

7. The multiplier according to claim 1, characterized in that, The first adder is a seven-bit adder, and the second adder is an eight-bit adder.

8. The multiplier according to claim 1, characterized in that, The sign determination module XORs the sign bits of the two operands and outputs the sign bit of the product of the two operands.

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