Data output control circuit and semiconductor device including the same

Abstract

The present disclosure relates to a data output control circuit and a semiconductor device including the same. The data output control includes a decoder adapted to generate a preheat period information by decoding a preheat period preliminary information, a first data output control circuit adapted to generate a first latched read enable signal and a first data output control timing signal based on a first read enable signal, an internal enable signal, and the preheat period information, and generate a first data output control signal using the first latched read enable signal masked with one or more pulses in response to the first data output control timing signal, and a second data output control circuit adapted to generate a second latched read enable signal and a second data output control timing signal based on a second read enable signal, the internal enable signal, and the preheat period information, and generate a second data output control signal using the second latched read enable signal masked with one or more pulses in response to the second data output control timing signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0121081, filed on September 10, 2021, the entirety of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure generally relate to a semiconductor circuit, and more specifically, to a data output control circuit and a semiconductor device including the same. Background Technology

[0004] Recently, the paradigm of the computing environment has shifted to ubiquitous computing, where computer systems can be used anytime, anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. Typically, these portable electronic devices use memory systems that utilize semiconductor memory devices (i.e., data storage devices). Data storage devices are used as either primary or secondary storage devices in portable electronic devices.

[0005] For example, semiconductor memory devices can store externally supplied data in their memory area and output data from the memory area to the outside of the semiconductor memory device. To improve the high-speed operation and operational reliability of semiconductor memory devices, controlling the timing of data input / output is crucial. Summary of the Invention

[0006] Various embodiments of this disclosure relate to data output control circuits and semiconductor devices including [missing information], for improving data output timing control performance.

[0007] In embodiments of this disclosure, a data output control may include: a decoder adapted to generate preheating cycle information indicating different preheating cycles by decoding preliminary preheating cycle information for setting one of different preheating cycles; a first data output control circuit adapted to generate a first latch read enable signal and a first data output control timing signal based on a first read enable signal, an internal enable signal, and the preheating cycle information, and in response to the first data output control timing signal, generate a first data output control signal using the first latch read enable signal, wherein one or more pulses of the first latch read enable signal are masked according to the preheating cycle information; and a second data output control circuit adapted to generate a second latch read enable signal and a second data output control timing signal based on a second read enable signal complementary to the first read enable signal, an internal enable signal, and the preheating cycle information, and in response to the second data output control timing signal, generate a second data output control signal using the second latch read enable signal, wherein one or more pulses of the second latch read enable signal are masked according to the preheating cycle information.

[0008] In embodiments of this disclosure, a semiconductor device may include: a memory cell array including a plurality of memory cells; data input / output circuitry adapted to output data provided from the memory cell array in response to a pair of data output control signals; and data output control circuitry adapted to: generate a pair of latch read enable signals and a pair of data output control timing signals based on a pair of complementary read enable signals, an internal enable signal, and preheating cycle information indicating different preheating cycles; and output a pair of data output control signals using the pair of latch read enable signals according to the pair of data output control timing signals, wherein one or more pulses of each of the pair of latch read enable signals are masked according to the preheating cycle information.

[0009] In embodiments of this disclosure, a semiconductor device may include: a first circuit and a second circuit, each configured to: enable a timing signal based on an edge of a corresponding clock of a first input clock and a second input clock, the edge corresponding to an enabled information signal in an information signal representing a respective warm-up cycle, the first input clock and the second input clock being complementary to each other; generate an internal clock by masking one or more cycles of the input clock based on the enabled timing signal; and generate a corresponding output clock of a first output clock and a second output clock based on an edge of the internal clock, the first output clock and the second output clock having frequencies half that of the input clock and having different phases relative to each other. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating the configuration of a semiconductor system according to an embodiment of the present disclosure.

[0011] Figure 2 This is a diagram illustrating the timing of data output according to the preheating cycle of a semiconductor device, based on an embodiment of the present disclosure.

[0012] Figure 3 This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 4 This is a diagram illustrating the configuration of a data output control circuit according to an embodiment of the present disclosure.

[0014] Figure 5 This is an operation timing diagram of a data output control circuit according to an embodiment of the present disclosure.

[0015] Figure 6 This is a diagram illustrating the configuration of a data output control circuit according to another embodiment of the present disclosure.

[0016] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 6A diagram showing the configuration of the first timing signal generation circuit.

[0017] Figure 8 This illustrates an embodiment according to the present disclosure. Figure 6 A diagram showing the configuration of the first control signal generation circuit.

[0018] Figure 9 This illustrates an embodiment according to the present disclosure. Figure 8 The diagram shows the configuration of the eleventh trigger.

[0019] Figure 10 This illustrates an embodiment according to the present disclosure. Figure 6 A diagram showing the configuration of the second timing signal generation circuit.

[0020] Figure 11 This illustrates an embodiment according to the present disclosure. Figure 6 A diagram showing the configuration of the second control signal generation circuit.

[0021] Figure 12A and Figure 12B This is an operation timing diagram of a data output control circuit according to another embodiment of the present disclosure. Detailed Implementation

[0022] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be exhaustive and complete, and will fully convey the scope of the disclosure to those skilled in the art. Throughout this disclosure, the same reference numerals denote the same components in the various figures and embodiments of the present disclosure.

[0023] Figure 1 This is a diagram illustrating the configuration of a semiconductor system 10 according to an embodiment of the present disclosure.

[0024] Reference Figure 1 The semiconductor system 10 may include a semiconductor device 100 and a controller 101. The semiconductor device 100 may operate based on the control of the controller 101. In response to a write command provided from the controller 101, the semiconductor device 100 may write data into the memory cell array 110. When the controller 101 receives a write command, an address, and data, the semiconductor device 100 may write data into the memory cell corresponding to the address.

[0025] In response to a read command provided by controller 101, semiconductor device 100 can perform a read operation. When it receives a read command and an address from controller 101, semiconductor device 100 can read data from the memory cell corresponding to the address and output the read data to controller 101.

[0026] Semiconductor device 100 may include NAND flash memory, vertical NAND (hereinafter referred to as "VNAND"), NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin-torque random access memory (STT-RAM). In embodiments, semiconductor device 100 may be implemented with a three-dimensional array structure. In embodiments, semiconductor device 100 may be applied to flash memory devices having a charge storage layer including a conductive floating gate and charge-trapped flash memory (CTF) having a charge storage layer including an insulating layer.

[0027] The controller 101 can be coupled between the semiconductor device 100 and a host computer. The host computer may include a central processing unit (CPU), a graphics processing unit (GPU), etc. The controller 101 can be configured to connect the host computer and the semiconductor device 100. Based on host computer control, the controller 101 can provide write commands and read commands to the semiconductor device 100.

[0028] Signal lines configured to transmit data DQ[7:0], signal lines configured to transmit data strobe signals DQS, and signal lines configured to transmit read enable signals RE can be coupled between controller 101 and semiconductor device 100. The read enable signal RE can be provided from controller 101. The read enable signal RE may include complementary signals and may be referred to as an external clock signal. Figure 1 The data DQ[7:0] with 8 bits is shown; however, the data may include 16 bits, 32 bits, etc.

[0029] The data strobe signal DQS can be a bidirectional signal. During data output operation of the semiconductor device 100, the data strobe signal DQS can be provided from the semiconductor device 100 to the controller 101. When data is input to the semiconductor device 100, the data strobe signal DQS can be provided from the controller 101 to the semiconductor device 100.

[0030] After the read enable signal RE is provided to the semiconductor device 100, data DQ[7:0] can be output based on the data strobe signal DQS. When data is transmitted between the controller 101 and the semiconductor device 100, the data transmission timing can be adjusted by the warm-up period defined in the operating specifications of the semiconductor device 100. According to the operating specifications of the semiconductor device 100, data should be output after the warm-up period has elapsed, referring to the read enable signal RE.

[0031] The warm-up period can be set to one of "0", "1", "2", and "4". When the warm-up period is set to "0", data can be output in the first cycle of the read enable signal RE without performing warm-up. When the warm-up period is set to "1", the data output can be delayed in the first cycle of the read enable signal RE, and the data can be output in the second cycle of the read enable signal RE. When the warm-up period is set to "2", the data output can be delayed in the first and second cycles of the read enable signal RE, and the data can be output in the third cycle of the read enable signal RE. When the warm-up period is set to "4", the data output can be delayed in the first to fourth cycles of the read enable signal RE, and the data can be output in the fifth cycle of the read enable signal RE.

[0032] Figure 2 This is a diagram illustrating the timing of data output according to the preheating cycle of a semiconductor device, based on an embodiment of the present disclosure. Figure 2 The read enable signal RE_N, data DQ[7:0], and data strobe signal DQS are shown. The read enable signal RE_N can include a complementary form of the signal as described above, and Figure 2 The read enable signal RE_N is shown as one of the complementary forms of the signal.

[0033] When the preheating cycle is set to "2", such as Figure 2 As shown, the data output can be delayed in the first and second cycles ("cycle 0" and "cycle 1") of the read enable signal RE_N, and the data DQ[7:0] can be output based on the data strobe signal DQS in the third cycle ("cycle 2") of the read enable signal RE_N.

[0034] According to embodiments of this disclosure, the semiconductor device 100 can internally adjust the timing of the read enable signal RE_N to output data based on the warm-up cycle.

[0035] Figure 3 This is a diagram illustrating the configuration of a semiconductor device 100 according to an embodiment of the present disclosure.

[0036] Reference Figure 3 The semiconductor device 100 may include a memory cell array 110, peripheral circuitry 120, and control circuitry 130. Peripheral circuitry 120 may include an address decoder 121, a voltage generation circuit 122, a read / write circuit 123, and a data input / output circuit 124.

[0037] The memory cell array 110 can be coupled to the address decoder 121 via row lines RL and to the read / write circuitry 123 via bit lines BL1 to BLm. The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. The multiple memory cells may be non-volatile memory cells. Each of the multiple memory blocks BLK1 to BLKz may include multiple pages. Among the multiple memory cells, the memory cell coupled to a single row line may be defined as a single page.

[0038] The storage unit can be configured with one or more of a single-level cell (SLC) capable of storing a single data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, and a four-level cell (QLC) capable of storing four data bits.

[0039] The peripheral circuit 120 can drive the memory cell array 110 to perform programming, reading and erasing operations.

[0040] Address decoder 121 can be coupled to memory cell array 110 via row lines RL. Address decoder 121 can be configured to operate based on control of control circuitry 130. Address decoder 121 can receive address ADDR from control circuitry 130.

[0041] Address decoder 121 can decode block addresses within address ADDR. Address decoder 121 can select at least one of a plurality of memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode row addresses within address ADDR. Based on the decoded row address, address decoder 121 can select at least one of the row lines RL coupled to the selected memory block by applying a voltage provided by voltage generation circuit 122 to at least one row line RL.

[0042] Address decoder 121 can perform programming operations by applying a programming voltage Vpgm to the selected row line and a pass voltage Vpass, which is lower than the programming voltage Vpgm, to the unselected row line.

[0043] Address decoder 121 can perform a read operation by applying a read voltage Vread to the selected row line and a pass voltage Vpass, which is higher than the read voltage Vread, to the unselected row line.

[0044] Erasure operations can be performed on a block-by-block basis within the semiconductor device 100. The address decoder 121 can decode the block address and select an individual memory block based on the decoded block address. The address decoder 121 can perform the erase operation by applying a ground voltage to the row line RL coupled to the selected memory block and applying an erase voltage Vers to form the body region of the selected memory block.

[0045] Voltage generation circuit 122 can generate various voltages required for the operation of semiconductor device 100. Voltage generation circuit 122 can generate read voltage Vread, pass voltage Vpass, programming voltage Vpgm, erase voltage Vers, etc., and provide them to address decoder 121. In an embodiment, voltage generation circuit 122 may include multiple pump capacitors, and multiple pump capacitors can be selectively activated based on the control of control circuit 130 to generate multiple voltages.

[0046] The read / write circuit 123 may include multiple page buffers, such as first page buffer PB1 to m-th page buffer PBm. First page buffer PB1 to m-th page buffer PBm may be coupled to the memory cell array 110 via bit line BL1 to m-th bit line BLm, respectively. First page buffer PB1 to m-th page buffer PBm may be operated in response to a control signal CTRL provided from the control circuit 130.

[0047] Page buffers PB1 through PBm can perform data communication with the data input / output circuit 124. Page buffers PB1 through PBm can perform programming operations by transferring data to be stored from the data input / output circuit 124 and data lines DL to the memory cell array 110. The read / write circuit 123 can perform a read operation by reading data from the memory cells of the selected page via bit lines BL1 through BLm and by providing the read data to the data input / output circuit 124. The read / write circuit 123 can perform an erase operation by floating bit lines BL1 through BLm.

[0048] Data input / output circuit 124 can be coupled to the first page buffer PB1 to the m-th page buffer PBm via data line DL. In response to the control signal CTRL provided from control circuit 130, data input / output circuit 124 can perform data input / output operations. During a read operation, data input / output circuit 124 can output data provided from the first page buffer PB1 to the m-th page buffer PBm to controller 101 at a timing based on the aforementioned warm-up period.

[0049] Control circuit 130 can be coupled to address decoder 121, voltage generation circuit 122, read / write circuit 123, and data input / output circuit 124. Control circuit 130 can be configured to control the overall operation of semiconductor device 100. Control circuit 130 can operate in response to a command CMD provided from an external device. During a read operation, control circuit 130 can generate a data output control signal by internally adjusting the timing of the read enable signal RE_N, and can output the generated data output control signal as one of the control signals CTRL, thereby outputting data based on a warm-up cycle. Control circuit 130 can output a timed signal as the data output control signal, at which pulses corresponding to the warm-up cycle in the pulses of the read enable signal RE_N are masked.

[0050] Figure 4 This is a diagram illustrating the configuration of a data output control circuit 131 according to an embodiment of the present disclosure. Figure 5 This is an operation timing diagram of the data output control circuit 131 according to an embodiment of the present disclosure.

[0051] In the following text, refer to Figure 4 and Figure 5 The configuration and operation of the data output control circuit 131 according to embodiments of the present disclosure will be described.

[0052] According to embodiments of this disclosure, the data output control circuit 131 may be included in, by way of example only. Figure 3 The arrangement of the data output control circuit 131 is not limited to that in the control circuit 130.

[0053] According to embodiments of this disclosure, such as Figure 4 As shown, the data output control circuit 131 may include a decoder 210, a timing signal generation circuit 220, and a control signal generation circuit 230.

[0054] Decoder 210 can decode the preliminary preheating cycle information LTC<0:1> used to set the preheating cycle to generate preheating cycle information LTC00, LTC01, LTC10, and LTC11. Preheating cycle information LTC00 can correspond to preheating cycle "0", preheating cycle information LTC01 can correspond to preheating cycle "1", preheating cycle information LTC10 can correspond to preheating cycle "2", and preheating cycle information LTC11 can correspond to preheating cycle "4". For example, when only preheating cycle information LTC00 among preheating cycle information LTC00, LTC01, LTC10, and LTC11 has a high level, the preheating cycle of semiconductor device 100 can be set to "0". When only preheating cycle information LTC01 among preheating cycle information LTC00, LTC01, LTC10, and LTC11 has a high level, the preheating cycle can be set to "1". When only preheating cycle information LTC10 among LTC00, LTC01, LTC10, and LTC11 is high, the preheating cycle can be set to "2". When only preheating cycle information LTC11 among LTC00, LTC01, LTC10, and LTC11 is high, the preheating cycle can be set to "4".

[0055] The timing signal generation circuit 220 can generate preliminary timing signals LTEN10, LTEN20, LTEN30, and LTEN40 based on the read enable signal RE_N, and can output one of the preliminary timing signals LTEN10, LTEN20, and LTEN40 as the timing signal LTEN based on the warm-up period information LTC00, LTC01, LTC10, and LTC11. The timing signal generation circuit 220 may include logic gate 221, shift register 222, and multiplexer (MUX) 223.

[0056] Logic gate 221 can invert the read enable signal RE_N to generate an inverted read enable signal RE_N_B.

[0057] Shift register 222 can shift the power supply voltage VCCD based on the inverted read enable signal RE_N_B to generate preliminary timing signals LTEN10, LTEN20, LTEN30, and LTEN40. Shift register 222 may include multiple flip-flops, such as first flip-flop 222-1 to fourth flip-flop 222-4. First flip-flop 222-1 to fourth flip-flop 222-4 can collectively receive the inverted read enable signal RE_N_B as a reference signal (i.e., a clock signal) for the shift operation. First flip-flop 222-1 can latch the level of the power supply voltage VCCD in response to the transition of the inverted read enable signal RE_N_B, and can output the latched signal as the preliminary timing signal LTEN10. Second flip-flop 222-2 can latch the preliminary timing signal LTEN10 in response to the transition of the inverted read enable signal RE_N_B, and can output the latched signal as the preliminary timing signal LTEN20. The third flip-flop 222-3 can latch the initial timing signal LTEN20 in response to the transition of the inverted read enable signal RE_N_B, and can output the latched signal as the initial timing signal LTEN30. The fourth flip-flop 222-4 can latch the initial timing signal LTEN30 in response to the transition of the inverted read enable signal RE_N_B, and can output the latched signal as the initial timing signal LTEN40.

[0058] Reference Figure 5 You can input a pair of read enable signals RE_N and RE_C. The phases of the read enable signals RE_N and RE_C can be opposite to each other. The inverted read enable signal RE_N_B can have the same phase as the read enable signal RE_C.

[0059] Based on the rising edge of the inverted read enable signal RE_N_B, the preliminary timing signals LTEN10, LTEN20, LTEN30 and LTEN40 can sequentially transition to a high level.

[0060] Based on the warm-up period information LTC00, LTC01, LTC10, and LTC11, multiplexer 223 can output one of the preliminary timing signals LTEN10, LTEN20, and LTEN40 as the timing signal LTEN. Here, Figure 4Since the semiconductor device 100 is sufficient to support the warm-up cycles "0", "1", "2", and "4" as defined in the previously described operating specifications, the data output control circuit 131 is not shown as inputting the preliminary timing signal LTEN30 to the multiplexer 223. When the warm-up cycle information LTC01 among the warm-up cycle information LTC00, LTC01, LTC10, and LTC11 is high, the multiplexer 223 can output the preliminary timing signal LTEN10 as the timing signal LTEN. When the warm-up cycle information LTC10 among the warm-up cycle information LTC00, LTC01, LTC10, and LTC11 is high, the multiplexer 223 can output the preliminary timing signal LTEN20 as the timing signal LTEN. When the warm-up period information LTC11 among the warm-up period information LTC00, LTC01, LTC10, and LTC11 is at a high level, the multiplexer 223 can output the initial timing signal LTEN40 as the timing signal LTEN. When the warm-up period information LTC00 among the warm-up period information LTC00, LTC01, LTC10, and LTC11 is at a high level (i.e., when no warm-up period is applied), the multiplexer 223 can output the timing signal LTEN that becomes high at the timing point before the initial timing signal LTEN10 becomes high.

[0061] The control signal generation circuit 230 can generate data output control signals RE_RDP and RE_FDP based on the timing signal LTEN by using a signal masked by a pulse corresponding to the warm-up period in the pulse of the read enable signal RE_N. Of the data output control signals RE_RDP and RE_FDP, RE_RDP can be referred to as the first data output control signal RE_RDP, and RE_FDP can be referred to as the second data output control signal RE_FDP.

[0062] The control signal generation circuit 230 may include a delay unit 231, logic gates 232 and 233, and oscillators 234 and 235.

[0063] Delay unit 231 can delay the read enable signal RE_N by a predetermined amount of time so that the read enable signal RE_N is driven after the predetermined amount of time. Delay unit 231 can be configured to compensate for the delay in signal processing of timing signal generation circuit 220. That is, delay unit 231 can be designed to have a delay amount corresponding to the delay in signal processing of timing signal generation circuit 220.

[0064] The first logic gate 232 can perform a NAND operation on the output signal of the delay unit 231 and the timing signal LTEN to output the signal RE_N_LT. The second logic gate 233 can invert the signal RE_N_LT output from the first logic gate 232.

[0065] Reference Figure 5 When the warm-up period is set to "0", the signal RE_N_LT output from the first logic gate 232 can have the same waveform as the read enable signal RE_N. When the warm-up period is set to "1", the signal RE_N_LT can have a waveform that masks the first cycle of the read enable signal RE_N. When the warm-up period is set to "2", the signal RE_N_LT can have waveforms that mask the first and second cycles of the read enable signal RE_N. When the warm-up period is set to "4", the signal RE_N_LT can have waveforms that mask the first to fourth cycles of the read enable signal RE_N.

[0066] The first oscillator 234 can perform an oscillation operation in response to the output signal of the second logic gate 233 to generate the first data output control signal RE_RDP in the data output control signals RE_RDP and RE_FDP. The first oscillator 234 may include a flip-flop 234-1 and a logic gate 234-2. The flip-flop 234-1 can generate the first data output control signal RE_RDP by repeatedly receiving the output signal of the second logic gate 233 as a clock signal and receiving an inverted signal of the output level as a feedback signal from the logic gate 234-2 in response to the transition of the output signal of the second logic gate 233. The logic gate 234-2 inverts the output level to generate an inverted signal.

[0067] Reference Figure 5 The first data output control signal RE_RDP can begin its transition based on the rising edge of the corresponding preheating cycle reference signal RE_N_LT "0", "1", "2" and "4", and its frequency can be half the frequency of the signal RE_N_LT.

[0068] The second oscillator 235 can perform an oscillation operation in response to the output signal of the first logic gate 232 to generate the second data output control signal RE_FDP in the data output control signals RE_RDP and RE_FDP. The second oscillator 235 may include a flip-flop 235-1 and a logic gate 235-2. The flip-flop 235-1 can generate the second data output control signal RE_FDP by repeatedly receiving the output signal of the first logic gate 232 as a clock signal and receiving an inverted signal of the output level as a feedback signal from the logic gate 235-2 in response to the transition of the output signal of the first logic gate 232. The logic gate 235-2 inverts the output level to generate an inverted signal.

[0069] Reference Figure 5 The second data output control signal RE_FDP can begin its transition based on the falling edge of the corresponding preheating cycle reference signal RE_N_LT "0", "1", "2" and "4", and can have half the frequency of signal RE_N_LT.

[0070] As described above, according to the embodiment, the data output control circuit 131 can generate data output control signals RE_RDP and RE_FDP based on the pulse of the masked read enable signal RE_N to support the preheating cycle signal.

[0071] Therefore, when the preheating cycle is set to "0" (i.e., when no preheating cycle is applied), the semiconductor device 100 can output data based on the data output control signals RE_RDP and RE_FDP, starting from the first cycle of the read enable signal RE_N.

[0072] When the preheating cycle is set to "1", the semiconductor device 100 can output data based on the data output control signals RE_RDP and RE_FDP, starting from the second cycle of the read enable signal RE_N.

[0073] When the preheating cycle is set to "2", the semiconductor device 100 can output data based on the data output control signals RE_RDP and RE_FDP, starting from the third cycle of the read enable signal RE_N.

[0074] When the preheating cycle is set to "4", the semiconductor device 100 can output data based on the data output control signals RE_RDP and RE_FDP, starting from the fifth cycle of the read enable signal RE_N.

[0075] In the following text, refer to Figure 6 and Figure 12B The configuration and operation of the data output control circuit 132 will be described according to another embodiment of the present disclosure.

[0076] According to another embodiment of this disclosure, the data output control circuit 132 may be included in, by way of example only. Figure 3In the control circuit 130. The arrangement of the data output control circuit 132 is not limited thereto. According to another embodiment of the present disclosure, the data output control circuit 132 can output a timing signal as a data output control signal, at which pulses corresponding to the warm-up period in the pulses of the read enable signal RE_N are masked based on a multi-phase clock signal generated by dividing the read enable signals RE_N and RE_C. Therefore, under low voltage conditions (i.e., conditions where the operating voltage is low) and high-speed operating conditions (i.e., conditions where the operating frequency is high), the data output control circuit 132 can operate stably by ensuring that the timing margin is twice that of the data output control circuit 131, which is configured based on a reference. Figure 4 The read enable signal RE_N described performs a masking operation.

[0077] Figure 6 This is a diagram illustrating the configuration of a data output control circuit 132 according to another embodiment of the present disclosure. Figure 7 This illustrates another embodiment according to the present disclosure. Figure 6 A diagram showing the configuration of the first timing signal generation circuit. Figure 8 This illustrates another embodiment according to the present disclosure. Figure 6 A diagram showing the configuration of the first control signal generation circuit.

[0078] Figure 9 This illustrates another embodiment according to the present disclosure. Figure 8 The diagram shows the configuration of the eleventh trigger. Figure 10 This illustrates another embodiment according to the present disclosure. Figure 6 A diagram showing the configuration of the second timing signal generation circuit. Figure 11 This illustrates another embodiment according to the present disclosure. Figure 6 A diagram showing the configuration of the second control signal generation circuit. Figure 12A and 12B This is an operation timing diagram of a data output control circuit according to another embodiment of the present disclosure.

[0079] According to another embodiment of this disclosure, such as Figure 6 As shown, the data output control circuit 132 may include a decoder 310, a first data output control circuit 320, and a second data output control circuit 330.

[0080] Decoder 310 can decode the preliminary preheating cycle information LTC<0:1> used to set the preheating cycle to generate preheating cycle information LTC00, LTC01, LTC10 and LTC11.

[0081] LTC00, LTC01, LTC10, and LTC11 correspond to preheating cycles set to “0”, “1”, “2”, and “4”, respectively.

[0082] For example, if LTC00 among the preheating cycle information LTC00, LTC01, LTC10, and LTC11 is high, it indicates that the preheating cycle of semiconductor device 100 is set to "0". If LTC01 among the preheating cycle information LTC00, LTC01, LTC10, and LTC11 is high, it indicates that the preheating cycle of semiconductor device 100 is set to "1". If LTC10 among the preheating cycle information LTC00, LTC01, LTC10, and LTC11 is high, it indicates that the preheating cycle of semiconductor device 100 is set to "2". If LTC11 among the preheating cycle information LTC00, LTC01, LTC10, and LTC11 is high, it indicates that the preheating cycle of semiconductor device 100 is set to "4".

[0083] The first data output control circuit 320 can generate a first latch read enable signal RE_N_D and a first data output control timing signal MASK_LTC_N based on the first read enable signal RE_N, the internal enable signal ENABLE, and the preheating cycle information LTC00, LTC01, LTC10, and LTC11. It can also generate a first data output control signal RE_RDP based on the masking signal of the pulse corresponding to the preheating cycle information LTC00, LTC01, LTC10, and LTC11 in the pulse of the first data output control timing signal MASK_LTC_N and the pulse of the first latch read enable signal RE_N_D.

[0084] The second data output control circuit 330 can generate a second latch read enable signal RE_C_D and a second data output control timing signal MASK_LTC_C based on a second read enable signal RE_C that is complementary to the first read enable signal RE_N, an internal enable signal ENABLE, and preheating cycle information LTC00, LTC01, LTC10, and LTC11. It can also generate a second data output control signal RE_FDP based on a masking signal of the pulse corresponding to the preheating cycle information LTC00, LTC01, LTC10, and LTC11 in the pulse of the second data output control timing signal MASK_LTC_C and the pulse of the second latch read enable signal RE_C_D.

[0085] Here, the internal enable signal ENABLE is a signal that is enabled when a read command (not shown) is applied, and after the internal enable signal ENABLE is applied, the first read enable signal RE_N and the second read enable signal RE_C are input.

[0086] Reference Figure 6 and 7 The first data output control circuit 320 may include a first timing signal generation circuit 400 and a first control signal generation circuit 600.

[0087] The first timing signal generation circuit 400 can generate a first latch read enable signal RE_N_D and a first inverted read enable signal RE_N_B based on the first read enable signal RE_N and the internal enable signal ENABLE. Furthermore, it can generate a first data output control timing signal MASK_LTC_N based on the first inverted read enable signal RE_N_B and the warm-up cycle information LTC00, LTC01, LTC10, and LTC11 by selectively combining the preliminary timing signals LTE10_N, LTE20_N, LTE40_N, LTE10_C, LTE20_C, and LTE50_C.

[0088] The first timing signal generation circuit 400 may include a first logic gate group 410, a first shift register 420, and a first multiplexer 430.

[0089] The first logic gate group 410 may include a first NAND gate 411, a first inverter 412, and a second inverter 413.

[0090] The first NAND gate 411 can output the result of the NAND logic operation between the first read enable signal RE_N and the internal enable signal ENABLE.

[0091] The first inverter 412 can generate the first latch read enable signal RE_N_D by inverting the result of the NAND logic operation of the first NAND gate 411.

[0092] The second inverter 413 can generate the first inverted read enable signal RE_N_B by inverting the first latch read enable signal RE_N_D.

[0093] The first shift register 420 can generate the first preliminary timing signal to the fifth preliminary timing signal LTE10_N, LTE20_N, LTE30_N, LTE40_N and LTE50_N by shifting the power supply voltage VCCD according to the first inverted read enable signal RE_N_B.

[0094] The first shift register 420 may include first flip-flops 421 through fifth flip-flops 425.

[0095] The first flip-flop 421 to the fifth flip-flop 425 can all receive the first inverted read enable signal RE_N_B as the clock signal CLK, which is a reference signal used for shift operations.

[0096] The first flip-flop 421 can latch the voltage level of the power supply voltage VCCD in response to the transition of the first inverted read enable signal RE_N_B, and output the first preliminary timing signal LTEN10_N as the latched voltage level.

[0097] The second trigger 422 can latch the first preliminary timing signal LTEN10_N in response to the transition of the first inverted read enable signal RE_N_B and output the second preliminary timing signal LTEN20_N as the latched first preliminary timing signal.

[0098] The third trigger 423 can latch the second preliminary timing signal LTEN20_N in response to the transition of the first inverted read enable signal RE_N_B and output the third preliminary timing signal LTEN30_N as the latched second preliminary timing signal.

[0099] The fourth trigger 424 can latch the third preliminary timing signal LTEN30_N in response to the transition of the first inverted read enable signal RE_N_B and output the fourth preliminary timing signal LTEN40_N as the latched third preliminary timing signal.

[0100] The fifth trigger 425 can latch the fourth preliminary timing signal LTEN40_N in response to the transition of the first inverted read enable signal RE_N_B and output the fifth preliminary timing signal LTEN50_N as the latched fourth preliminary timing signal.

[0101] Reference Figure 12A The first preliminary timing signal to the fifth preliminary timing signal LTEN10_N, LTE20_N, LTE30_N, LTE40_N and LTE50_N are sequentially switched to high level according to the rising edge of the first inverted read enable signal RE_N_B.

[0102] The first multiplexer 430 can output a first data output control timing signal MASK_LTC_N and a power supply voltage VCCD as one of the preliminary signals LTE10_N, LTE20_N and LTE40_N, based on the preheating cycle information LTC00, LTC01, LTC10, LTC11.

[0103] Here, Figure 7 The example shown is of the first multiplexer 430 designed to be used without inputting a third preliminary timing signal LTEN30_N.

[0104] Reference Figure 7 and Figure 12AIf LTC01 among the warm-up period information LTC00, LTC01, LTC10, and LTC11 is high, then the first multiplexer 430 outputs the first data output control preliminary timing signal MASK_LTC_N as the first preliminary timing signal LTEN10_N. If LTC10 among the warm-up period information LTC00, LTC01, LTC10, and LTC11 is high, then the first multiplexer 430 outputs the first data output control preliminary timing signal MASK_LTC_N as the second preliminary timing signal LTEN20_N. If LTC11 among the warm-up period information LTC00, LTC01, LTC10, and LTC11 is high, then the first multiplexer 430 outputs the first data output control preliminary timing signal MASK_LTC_N as the fourth preliminary timing signal LTEN40_N.

[0105] Furthermore, if LTC00 among the preheating cycle information LTC00, LTC01, LTC10 and LTC11 is at a high level, that is, if no preheating cycle is applied, the first multiplexer 430 outputs the first data output control preliminary timing signal MASK_LTC_N as a power supply voltage VCCD with a high voltage level at the timing point before the transition timing of the first preliminary timing signal LTEN10_N.

[0106] Reference Figure 6 and Figure 8 The first control signal generation circuit 600 can generate the first data output control signal RE_RDP based on the masking signal of the pulse corresponding to the preheating cycle information LTC00, LTC01, LTC10 and LTC11 in the pulse of the first data output control timing signal MASK_LTC_N and the pulse of the first latch read enable signal RE_N_D.

[0107] The first control signal generation circuit 600 may include a first delay unit 610, a second logic gate group, a first frequency divider circuit 640, and a third logic gate group.

[0108] The first delay unit 610 can output a first latch compensation read enable signal RE_N_DD by delaying the first latch read enable signal RE_N_D for a predetermined time. The first delay unit 610 can be configured to compensate for the signal processing delay of the first timing signal generation circuit 400. That is, the first delay unit 610 can be designed to delay by the same amount of time as the signal processing delay of the first timing signal generation circuit 400.

[0109] The second logic gate group may include a second NAND gate 620 and a third inverter 630.

[0110] The second NAND gate 620 can output the result of the NAND logic operation of the first latch compensation read enable signal RE_N_DD and the first data output control timing signal MASK_LTC_N.

[0111] The third inverter 630 can output the first clock signal RE_N_CLK by inverting the NAND logic operation result of the second NAND gate 620.

[0112] When the first read enable signal RE_N is not high, i.e., when the first latch compensation read enable signal RE_N_DD is not high, the first clock signal RE_N_CLK is applied to the first frequency divider circuit 640 at a low level. In other words, leakage current can be prevented by controlling the timing signal MASK_LTC_N with the first data output.

[0113] Reference Figure 12B When the warm-up period is set to "0" (0 warm-up periods), the waveform of the first clock signal RE_N_CLK is the same as the waveform of the first read enable signal RE_N. When the warm-up period is set to "1" (1 warm-up period), the first clock signal RE_N_CLK has a waveform masked by the first period of the first read enable signal RE_N. When the warm-up period is set to "2" (2 warm-up periods), the first clock signal RE_N_CLK has a waveform masked by the first and second periods of the first read enable signal RE_N. When the warm-up period is set to "4" (4 warm-up periods), the first clock signal RE_N_CLK has waveforms masked by the first to fourth periods of the first read enable signal RE_N.

[0114] The first frequency divider circuit 640 can receive the third-phase clock signal ICLKB as a non-inverting input signal and the first-phase clock signal ICLK as an inverting input signal. The first frequency divider circuit 640 can output the first-phase clock signal ICLK as a non-inverting output signal and the third-phase clock signal ICLKB as an inverting output signal, based on the first clock signal RE_N_CLK.

[0115] In other words, the first frequency divider circuit 640 can receive and divide the first clock signal RE_N_CLK and generate the first phase clock signal ICLK and the third phase clock signal ICLKB among the multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB.

[0116] The multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB can have half the frequency of the first read enable signal RE_N and the first clock signal RE_N_CLK.

[0117] The first frequency divider circuit 640 may include an eleventh flip-flop. In response to the transition of the first clock signal RE_N_CLK, the eleventh flip-flop can generate the first phase clock signal ICLK and the third phase clock signal ICLKB by latching the third clock signal ICLKB and the first phase clock signal ICLK.

[0118] Reference Figure 9 The eleventh flip-flop can be configured to have a cross-coupled structure. The NMOS transistor included in the tail region 642 of the eleventh flip-flop can be a high-threshold transistor. Other transistors besides the NMOS transistor in the tail region 642 can be low-threshold transistors. Here, since the first clock signal RE_N_CLK remains at a low voltage level except during the trigger time, the NMOS transistor in the tail region 642 is turned off, preventing leakage current. Since flip-flops with cross-coupled structures are well known to those skilled in the art, a detailed description of flip-flops with cross-coupled structures will be omitted.

[0119] The third logic gate group may include a third NAND gate 650 and a fourth inverter 660.

[0120] The third NAND gate 650 can output the NAND logic operation result of the power supply voltage VDD based on the first phase clock signal ICLK.

[0121] The fourth inverter 660 can generate and output the first data output control signal RE_RDP by inverting the result of the NAND logic operation of the third NAND gate 650.

[0122] Reference Figure 12B The first data output control signal RE_RDP can change based on the rising edge of the first clock signal RE_N_CLK, according to warm-up cycles 0, 1, 2, and 4. The first data output control signal RE_RDP can have half the frequency of the first clock signal RE_N_CLK.

[0123] Reference Figure 6 and Figure 10 The second data output control circuit 330 may include a second timing signal generation circuit 500 and a second control signal generation circuit 700.

[0124] The second timing signal generation circuit 500 can generate a second latch read enable signal RE_C_D and a second inverted read enable signal RE_C_B based on the second read enable signal RE_C and the internal enable signal ENABLE. Furthermore, it can generate a second data output control timing signal MASK_LTC_C based on the second inverted read enable signal RE_C_B and the warm-up cycle information LTC00, LTC01, LTC10, and LTC11 by selectively combining the preliminary timing signals LTE10_N, LTE20_N, LTE40_N, LTE10_C, LTE20_C, and LTE50_C.

[0125] The second read enable signal RE_C may have an opposite phase to the first read enable signal RE_N, and may have the same phase as the first inverted read enable signal RE_N_C. The second inverted read enable signal RE_C_B may have the same phase as the first read enable signal RE_N.

[0126] The second timing signal generation circuit 500 may include a fourth logic gate group 510, a second shift register 520, and a second multiplexer 530.

[0127] The fourth logic gate group 510 may include a fourth NAND gate 511, a fifth inverter 512, and a sixth inverter 513.

[0128] The fourth NAND gate 511 can output the result of the NAND logic operation between the second read enable signal RE_C and the internal enable signal ENABLE.

[0129] The fifth inverter 512 generates the second latch read enable signal RE_C_D by inverting the result of the NAND logic operation of the fourth NAND gate 511. Here, the second latch read enable signal RE_C_D is held high until the external clock signal is triggered, as shown below. Figure 12A The area marked "A" is shown.

[0130] The sixth inverter 513 can generate the second inverted read enable signal RE_C_B by inverting the second latch read enable signal RE_C_D.

[0131] The second shift register 520 can generate the sixth to tenth preliminary timing signals LTE10_C, LTE20_C, LTE30_C, LTE40_C and LTE50_C by shifting the power supply voltage VCCD according to the second inverted read enable signal RE_C_B.

[0132] The second shift register 520 may include the sixth flip-flop 521 through the eleventh flip-flop 525.

[0133] The sixth flip-flop 521 to the eleventh flip-flop 525 can all receive the second inverted read enable signal RE_C_B as the clock signal CLK, which is a reference signal used for shift operations.

[0134] The sixth flip-flop 521 can latch the voltage level of the power supply voltage VCCD in response to the transition of the second inverted read enable signal RE_C_B and output the sixth preliminary timing signal LTEN10_C as the latch voltage signal.

[0135] The seventh trigger 522 can latch the sixth preliminary timing signal LTEN10_C in response to the transition of the second inverted read enable signal RE_C_B and output the seventh preliminary timing signal LTEN20_C as the latched sixth preliminary timing signal.

[0136] The eighth flip-flop 523 can latch the seventh preliminary timing signal LTEN20_C in response to the transition of the second inverted read enable signal RE_C_B and output the eighth preliminary timing signal LTEN30_C as the latched seventh preliminary timing signal.

[0137] The ninth trigger 524 can latch the eighth preliminary timing signal LTEN30_C in response to the transition of the second inverted read enable signal RE_C_B and output the ninth preliminary timing signal LTEN40_C as the latched eighth preliminary timing signal.

[0138] The tenth trigger 525 can latch the ninth preliminary timing signal LTEN40_C in response to the transition of the second inverted read enable signal RE_C_B and output the tenth preliminary timing signal LTEN50_C as the latched ninth preliminary timing signal.

[0139] Reference Figure 12A The sixth preliminary timing signal to the tenth preliminary timing signal LTEN10_C, LTE20_C, LTE30_C, LTE40_C and LTE50_C sequentially change to high level according to the rising edge of the second inverted read enable signal RE_C_B.

[0140] The second multiplexer 530 can output a second data output control timing signal MASK_LTC_N as one of the preliminary signals LTE10_C, LTE20_C, LTE30_C, and LTE50_C based on the preheating cycle information LTC00, LTC01, LTC10, and LTC11.

[0141] Here, Figure 10 The second multiplexer 530 shown is an example designed for the case where no ninth preliminary timing signal LTEN40_C is input.

[0142] Reference Figure 10 and Figure 12A If LTC01 among the warm-up period information LTC00, LTC01, LTC10, and LTC11 is high, then the second multiplexer 530 outputs the second data output control preliminary timing signal MASK_LTC_C as the seventh preliminary timing signal LTEN20_C. If LTC10 among the warm-up period information LTC00, LTC01, LTC10, and LTC11 is high, then the second multiplexer 530 outputs the second data output control preliminary timing signal MASK_LTC_C as the eighth preliminary timing signal LTEN30_C. If LTC11 among the warm-up period information LTC00, LTC01, LTC10, and LTC11 is high, then the second multiplexer 530 outputs the second data output control preliminary timing signal MASK_LTC_C as the tenth preliminary timing signal LTEN50_C.

[0143] Furthermore, if LTC00 among the warm-up cycle information LTC00, LTC01, LTC10 and LTC11 is high, that is, if no warm-up cycle is applied, the second multiplexer 530 outputs the second data output control preliminary timing signal MASK_LTC_C as the sixth preliminary timing signal LTEN10_C at the timing point before the transition timing of the seventh preliminary timing signal LTEN20_C.

[0144] Reference Figure 6 and Figure 11 The second control signal generation circuit 700 can generate the second data output control signal RE_FDP by using the masking signal of the pulse corresponding to the preheating cycle information LTC00, LTC01, LTC10 and LTC11 in the pulse of the second latch read enable signal RE_C_D based on the second data output control timing signal MASK_LTC_C.

[0145] The second control signal generation circuit 700 may include a second delay unit 710, a fifth logic gate group 720 and 730, a second frequency divider circuit 740, and a sixth logic gate group 750 and 760.

[0146] The second delay unit 710 can output a second latch compensation read enable signal RE_C_DD by delaying the second latch read enable signal RE_C_D by a predetermined time. The second delay unit 710 can be configured to compensate for the signal processing delay of the second timing signal generation circuit 500. That is, the second delay unit 710 can be designed to delay by the same amount of time as the signal processing delay of the second timing signal generation circuit 500.

[0147] The fifth logic gate group 720 and 730 may include a fifth NAND gate 720 and a seventh inverter 730.

[0148] The fifth NAND gate 720 can output the result of the NAND logic operation of the second latch compensation read enable signal RE_C_DD and the second data output control timing signal MASK_LTC_C.

[0149] The seventh inverter 730 can output the second clock signal RE_C_CLK by inverting the result of the NAND logic operation of the fifth NAND gate 720.

[0150] When the second read enable signal RE_C is not high, i.e., when the second latch compensation read enable signal RE_C_DD is not high, the second clock signal RE_C_CLK, which is at a low level, is applied to the second frequency divider circuit 740. In other words, the timing signal MASK_LTC_C can be controlled by the second data output to prevent leakage current.

[0151] Reference Figure 12B When the warm-up period is set to "0" (0 warm-up cycles), the waveform of the second clock signal RE_C_CLK is the same as the waveform of the second read enable signal RE_C. When the warm-up period is set to "1" (1 warm-up cycle), the second clock signal RE_C_CLK has a waveform masked by the first cycle of the second read enable signal RE_C. When the warm-up period is set to "2" (2 warm-up cycles), the second clock signal RE_C_CLK has waveforms masked by the first and second cycles of the second read enable signal RE_C. When the warm-up period is set to "4" (4 warm-up cycles), the second clock signal RE_C_CLK has waveforms masked by the first to fourth cycles of the second read enable signal RE_C.

[0152] The second frequency divider circuit 740 can receive the fourth phase clock signal QCLKB as a non-inverting input signal and the second phase clock signal QCLK as an inverting input signal. The second frequency divider circuit 740 can output the second phase clock signal QCLK as a non-inverting output signal and the fourth phase clock signal QCLKB as an inverting output signal, based on the second clock signal RE_C_CLK.

[0153] In other words, the second frequency divider circuit 740 can receive and divide the second clock signal RE_C_CLK, and generate the second phase clock signal QCLK and the fourth phase clock signal QCLKB among the multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB.

[0154] The multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB can have half the frequency of the second read enable signal RE_C and the second clock signal RE_C_CLK.

[0155] The second frequency divider circuit 740 may include a twelfth flip-flop. Since the twelfth flip-flop has the same configuration as the eleventh flip-flop of the first frequency divider circuit 640, a detailed description of the twelfth flip-flop will be omitted.

[0156] The sixth logic gate group 750 and 760 may include a sixth NAND gate 750 and an eighth inverter 760.

[0157] The sixth NAND gate 750 can output the NAND logic result of the power supply voltage VCCD based on the fourth phase clock signal QCLKB.

[0158] The eighth inverter 760 can generate and output the second data output control signal RE_FDP by inverting the result of the NAND logic operation of the sixth NAND gate 750.

[0159] Reference Figure 12B The second data output control signal RE_FDP can change based on the rising edge of the second clock signal RE_C_CLK, according to warm-up cycles 0, 1, 2, and 4. The second data output control signal RE_FDP can have half the frequency of the second clock signal RE_C_CLK.

[0160] Therefore, the semiconductor device 100 can stably generate the first data output control signal RE_RDP and the second data output control signal RE_FDP, regardless of the operating conditions of the semiconductor device 100, namely low voltage and high frequency operating conditions.

[0161] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that many changes and modifications can be made without departing from the spirit and scope of this disclosure as defined by the appended claims. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A data output control circuit, comprising: The decoder is adapted to generate preheating cycle information indicating the different preheating cycles by decoding preliminary preheating cycle information for setting one of the different preheating cycles. A first data output control circuit is adapted to generate a first latch read enable signal and a first data output control timing signal based on a first read enable signal, an internal enable signal and the preheating cycle information, and in response to the first data output control timing signal, to generate a first data output control signal using the first latch read enable signal, wherein one or more pulses of the first latch read enable signal are masked according to the preheating cycle information. as well as The second data output control circuit is adapted to generate a second latch read enable signal and a second data output control timing signal based on a second read enable signal complementary to the first read enable signal, the internal enable signal, and the preheating cycle information, and in response to the second data output control timing signal, to generate a second data output control signal using the second latch read enable signal, wherein one or more pulses of the second latch read enable signal are masked according to the preheating cycle information.

2. The data output control circuit according to claim 1, wherein, The first data output control circuit includes: a first timing signal generation circuit, adapted to generate a first latch read enable signal and a first inverted read enable signal based on the first read enable signal and the internal enable signal, and to selectively combine a preliminary timing signal based on the preheating cycle information and the first inverted read enable signal to generate the first data output control timing signal; and The first control signal generation circuit is adapted to generate the first data output control signal using the masked first latch read enable signal.

3. The data output control circuit according to claim 2, wherein, The first timing signal generation circuit includes: The first logic gate group is adapted to generate the first latch read enable signal by inverting the result signal of the NAND logic operation of the first read enable signal and the internal enable signal, and to generate the first inverted read enable signal by inverting the first latch read enable signal. A first shift register is adapted to generate a first to a fifth preliminary timing signal by shifting the power supply voltage according to the first inverted read enable signal; and A first multiplexer is adapted to output, based on the preheating cycle information, a first data output control timing signal and the power supply voltage as one of the first preliminary timing signals to the fifth preliminary timing signals.

4. The data output control circuit according to claim 3, wherein, The first logic gate group includes: The first NAND gate is adapted to output the NAND logic operation result signal according to the internal enable signal and the first read enable signal; A first inverter, adapted to generate the first latch read enable signal by inverting the result signal of the NAND operation; and The second inverter is adapted to generate the first inverted read enable signal by inverting the first latch read enable signal.

5. The data output control circuit according to claim 3, wherein, The first shift register includes: A first trigger is adapted to output the first preliminary timing signal by latching the voltage level of the power supply voltage in response to a change in the first inverted read enable signal; The second trigger is adapted to output the second preliminary timing signal by latching the first preliminary timing signal in response to a change in the first inverted read enable signal; The third trigger is adapted to output the third preliminary timing signal by latching the second preliminary timing signal in response to a change in the first inverted read enable signal; A fourth trigger, adapted to output the fourth preliminary timing signal by latching the third preliminary timing signal in response to a transition of the first inverted read enable signal; and The fifth trigger is adapted to output the fifth preliminary timing signal by latching the fourth preliminary timing signal in response to a transition of the first inverted read enable signal.

6. The data output control circuit according to claim 2, wherein, The first control signal generation circuit includes: The first delayer is adapted to generate a first latch compensation read enable signal by delaying the first latch read enable signal for a predetermined time. The second logic gate group is adapted to generate a first clock signal by inverting the NAND logic operation result signal of the first latch compensation read enable signal and the first data output control timing signal; A first frequency divider circuit is adapted to generate a multi-phase clock signal by dividing the phase of the first clock signal, and to generate a first-phase clock signal and a third-phase clock signal of the multi-phase clock signal; and The third logic gate group is adapted to output the first data output control signal by inverting the result signal of the NAND logic operation of the power supply voltage output according to the first phase clock signal.

7. The data output control circuit according to claim 6, wherein, The first frequency divider circuit includes an eleventh flip-flop, which has a cross-coupled structure and is adapted to prevent leakage current.

8. The data output control circuit according to claim 6, wherein, The first data output control signal changes based on the rising edge of the first clock signal according to the preheating cycle.

9. The data output control circuit according to claim 1, wherein, The second data output control circuit includes: The second timing signal generation circuit is adapted to generate a second latch read enable signal and a second inverted read enable signal based on the second read enable signal and the internal enable signal, and to generate a second data output control timing signal by selectively combining a preliminary timing signal based on the preheating cycle information and the second inverted read enable signal; and The second control signal generation circuit is adapted to generate the second data output control signal using a masked second latch read enable signal.

10. The data output control circuit according to claim 9, wherein, The second timing signal generation circuit includes: The fourth logic gate group is adapted to generate the second latch read enable signal by inverting the result signal of the NAND logic operation of the second read enable signal and the internal enable signal, and to generate the second inverted read enable signal by inverting the second latch read enable signal. The second shift register is adapted to generate a sixth to a tenth preliminary timing signal by shifting the power supply voltage according to the second inverted read enable signal; and The second multiplexer is adapted to output, based on the preheating cycle information, a second data output control timing signal and the power supply voltage as one of the sixth to tenth preliminary timing signals.

11. The data output control circuit according to claim 10, wherein, The fourth logic gate group includes: The fourth NAND gate is adapted to output the NAND logic operation result signal according to the internal enable signal and the second read enable signal; A fifth inverter, adapted to generate the second latch read enable signal by inverting the result signal of the NAND operation; and The sixth inverter is adapted to generate the second inverted read enable signal by inverting the second latch read enable signal.

12. The data output control circuit according to claim 10, wherein, The second shift register includes: The sixth trigger is adapted to output the sixth preliminary timing signal by latching the voltage level of the power supply voltage in response to a change in the second inverted read enable signal; A seventh flip-flop is adapted to output the seventh preliminary timing signal by latching the sixth preliminary timing signal in response to a transition of the second inverted read enable signal; The eighth flip-flop is adapted to output the eighth preliminary timing signal by latching the seventh preliminary timing signal in response to a transition of the second inverted read enable signal; A ninth flip-flop, adapted to output the ninth preliminary timing signal by latching the eighth preliminary timing signal in response to a transition of the second inverted read enable signal; and The tenth flip-flop is adapted to output the tenth preliminary timing signal by latching the ninth preliminary timing signal in response to a transition of the second inverted read enable signal.

13. The data output control circuit according to claim 9, wherein, The second control signal generation circuit includes: The second delayer is adapted to generate a second latch compensation read enable signal by delaying the second latch read enable signal for a predetermined time. The fifth logic gate group is adapted to generate a second clock signal by inverting the result signal of the NAND logic operation of the second latch compensation read enable signal and the second data output control timing signal; The second frequency divider circuit is adapted to generate a multi-phase clock signal by dividing the phase of the second clock signal, and to generate a second-phase clock signal and a fourth-phase clock signal of the multi-phase clock signal; and The sixth logic gate group is adapted to output the second data output control signal by inverting the result signal of the NAND logic operation of the power supply voltage output according to the fourth phase clock signal.

14. The data output control circuit according to claim 13, wherein, The second data output control signal changes according to the preheating cycle based on the rising edge of the second clock signal and at a frequency half that of the second clock signal.

15. A semiconductor device, comprising: A storage cell array, comprising multiple storage cells; A data input / output circuit is adapted to output data provided from the memory cell array in response to a pair of data output control signals; as well as The data output control circuit is adapted to: generate a pair of latch read enable signals and a pair of data output control timing signals based on a pair of complementary read enable signals, an internal enable signal, and preheating cycle information indicating different preheating cycles; Based on the pair of data output control timing signals, the pair of latch read enable signals are used to output the pair of data output control signals, and one or more pulses of each of the pair of latch read enable signals are masked according to the preheating cycle information.

16. The semiconductor device according to claim 15, wherein, The data output control circuit includes: A decoder adapted to generate the preheating cycle information by decoding preliminary preheating cycle information used to set one of the preheating cycles; A first data output control circuit is adapted to generate a first latch read enable signal in a pair of latch read enable signals and a first data output control timing signal in a pair of data output control timing signals based on a first read enable signal in the complementary read enable signals, the internal enable signal, and the warm-up cycle information; and in response to the first data output control timing signal, to generate a first data output control signal in the pair of data output control signals using the first latch read enable signal, wherein one or more pulses of the first latch read enable signal are masked according to the warm-up cycle information; and The second data output control circuit is adapted to generate a second latch read enable signal in the pair of latch read enable signals and a second data output control timing signal in the pair of data output control timing signals based on a second read enable signal complementary to the first read enable signal in the complementary read enable signals, the internal enable signal, and the warm-up cycle information; and in response to the second data output control timing signal, to generate a second data output control signal in the pair of data output control signals using the second latch read enable signal, wherein one or more pulses of the second latch read enable signal are masked according to the warm-up cycle information.

17. The semiconductor device of claim 16, wherein, The first data output control circuit includes: A first timing signal generation circuit is adapted to generate a first latch read enable signal and a first inverted read enable signal based on the first read enable signal and the internal enable signal, and to generate a first data output control timing signal by selectively combining a preliminary timing signal based on the preheating cycle information and the first inverted read enable signal; and The first control signal generation circuit is adapted to generate the first data output control signal using the masked first latch read enable signal.

18. The semiconductor device according to claim 17, wherein, The first timing signal generation circuit includes: The first logic gate group is adapted to generate the first latch read enable signal by inverting the result signal of the NAND logic operation of the first read enable signal and the internal enable signal, and to generate the first inverted read enable signal by inverting the first latch read enable signal. A first shift register is adapted to generate a first to a fifth preliminary timing signal by shifting the power supply voltage according to the first inverted read enable signal; and A first multiplexer is adapted to output, based on the preheating cycle information, a first data output control timing signal and the power supply voltage as one of the first preliminary timing signals to the fifth preliminary timing signals.

19. The semiconductor device according to claim 17, wherein, The first control signal generation circuit includes: The first delayer is adapted to generate a first latch compensation read enable signal by delaying the first latch read enable signal for a predetermined time. The second logic gate group is adapted to generate a first clock signal by inverting the NAND logic operation result signal of the first latch compensation read enable signal and the first data output control timing signal; A first frequency divider circuit is adapted to generate a multi-phase clock signal by dividing the phase of the first clock signal, and to generate a first-phase clock signal and a third-phase clock signal of the multi-phase clock signal; and The third logic gate group is adapted to output the first data output control signal by inverting the result signal of the NAND logic operation of the power supply voltage output according to the first phase clock signal.

20. The semiconductor device of claim 16, wherein, The second data output control circuit includes: The second timing signal generation circuit is adapted to generate a second latch read enable signal and a second inverted read enable signal based on the second read enable signal and the internal enable signal, and to generate a second data output control timing signal by selectively combining a preliminary timing signal based on the preheating cycle information and the second inverted read enable signal; and The second control signal generation circuit is adapted to generate the second data output control signal using a masked second latch read enable signal.

21. A semiconductor device, comprising: The first circuit and the second circuit, each of which: A timing signal is enabled based on the edge of a corresponding input clock from one of the first and second input clocks, where the edge corresponds to an enable signal in an information signal representing a respective warm-up cycle. The first and second input clocks are complementary to each other. An internal clock is generated by masking one or more cycles of the corresponding input clock according to an enabled timing signal, and A corresponding output clock, one of a first output clock and a second output clock, is generated based on the edge of the internal clock. The first output clock and the second output clock have frequencies that are half of the corresponding input clock and have different phases with each other.

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