Operating method and apparatus for flash memory

Abstract

This invention provides a method and apparatus for operating a flash memory. The method includes: writing an operation command to the flash memory when performing data operations on it; the operation command includes at least address information; the address information includes a data address and a compensation feature value; the flash memory includes peripheral circuitry and a memory cell array; the peripheral circuitry adjusts data operation parameters according to the compensation feature value and performs the data operation on the data at the data address in the memory cell array. This invention sets the compensation feature value in the address information when performing data operations on the flash memory, eliminating the need for an additional feature value setting sequence, thereby significantly saving flash memory data operation time and improving device performance.

Description

[0001] This application is a divisional application of the patent filed on January 25, 2021, with application number 202110093103.7, entitled "Operation Method and Apparatus for Flash Memory". Technical Field

[0002] This invention relates to the field of integrated circuit design, and in particular to a method and apparatus for operating a flash memory. Background Technology

[0003] Based on the difference in the number of bits that can be stored in a single storage cell in NAND flash memory, it can be divided into different types such as Single-Level Cell (SLC), Multi-Level Cell (MLC), Three-Level Cell (TLC), and Quadruple-Level Cell (QLC). Data operations on different storage cells require adjustments to corresponding data operation parameters. For example, when performing data read operations on NAND flash memory, different read offset features need to be selected for different types of storage cells or pages with different read speeds to optimize the flash memory's read operation performance and ensure the stability of stored data.

[0004] Currently, when setting read compensation characteristic values ​​and other features of NAND flash memory, it is generally possible to write feature value setting commands through a dedicated feature value setting sequence according to the feature value table of the ONFi 4.1 protocol. This changes the feature values ​​set in the feature register of the NAND flash memory, ensuring that the NAND flash memory operates in an optimal state during various data operations. For example, in NAND flash memory with both SLC and TLC cells, different read compensation characteristic values ​​are set separately for pages in SLC and pages in TLC with different operating speeds, thereby adjusting parameters such as read level resolution and scan range to maintain good read operation performance.

[0005] However, when setting characteristic values ​​such as read compensation characteristic values ​​using the above method, an additional characteristic value setting sequence needs to be introduced. This will cause the NAND flash memory to consume additional operation time when performing data operations, which is not conducive to improving the operating speed of the device.

[0006] Therefore, it is necessary to propose a new operating method and apparatus for flash memory to solve the above problems. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an operation method and apparatus for flash memory, which solves the problem that setting feature values ​​requires an additional feature value setting sequence and consumes additional operation time in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a method for operating a flash memory, the method comprising:

[0009] When performing data operations on the flash memory, an operation command is written to the flash memory; the operation command includes at least address information; the address information includes a data address and a compensation feature value;

[0010] The flash memory includes peripheral circuitry and a storage cell array; the peripheral circuitry adjusts data operation parameters according to the compensation feature value and performs the data operation on the data at the data address in the storage cell array.

[0011] As an optional embodiment of the present invention, the data operation includes data reading, data writing, or data erasure.

[0012] As an optional embodiment of the present invention, when the data operation is data reading, the compensation feature value includes reading compensation feature value, and the data operation parameters include reading level and its resolution and scanning range.

[0013] As an optional embodiment of the present invention, the storage units in the storage unit array include single-level units and three-level units; the three-level units include lower-level page storage units, middle-level page storage units, and upper-level page storage units.

[0014] As an optional embodiment of the present invention, the reading of the compensation feature value includes:

[0015] A single-layer read compensation feature value that adjusts the data operation parameters read by the single-level unit;

[0016] The first read compensation feature value and the fifth read compensation feature value are used to adjust the data operation parameters read from the lower-level page storage unit;

[0017] The second read compensation feature value, the fourth read compensation feature value, and the sixth read compensation feature value are used to adjust the data operation parameters read from the middle-level page storage unit.

[0018] The third and seventh read compensation feature values ​​are used to adjust the data operation parameters read from the upper-level page storage unit.

[0019] As an optional embodiment of the present invention, the read compensation feature values ​​are sequentially arranged into a first compensation interval, a second compensation interval, and a third compensation interval during the address write cycle; the first compensation interval is used to write the single-layer read compensation feature value, the first read compensation feature value, the second read compensation feature value, and the third read compensation feature value; the second compensation interval is used to write the fourth read compensation feature value, the fifth read compensation feature value, and the seventh read compensation feature value; and the third compensation interval is used to write the sixth read compensation feature value.

[0020] As an optional embodiment of the present invention, a reserved interval is further provided after the third compensation interval.

[0021] As an optional embodiment of the present invention, the data address includes a row address and a column address; during the address writing cycle, the sequence of the address information is arranged in the order of column address, row address and compensation feature value.

[0022] The present invention also provides a flash memory device, the device comprising: peripheral circuitry and a memory cell array;

[0023] The peripheral circuitry includes a data register and a feature register;

[0024] When the flash memory performs data operations, it writes an operation command to the peripheral circuit. The operation command includes at least address information, which includes a data address and a compensation feature value.

[0025] The data register is used to store the data address; the feature register is used to store the compensation feature value;

[0026] The peripheral circuit adjusts the data operation parameters according to the compensation feature value and performs the data operation on the data at the data address in the storage cell array.

[0027] As an optional embodiment of the present invention, the peripheral circuit further includes a first data selector and a second data selector;

[0028] The first data selector has its input terminal connected to a data input clock signal and a feature value input clock signal, and its output terminal connected to an operation command clock signal; the second data selector has its input terminal connected to a data signal and a feature value signal, and its output terminal connected to an operation command signal.

[0029] As described above, the present invention provides a method and apparatus for operating a flash memory, which has the following beneficial effects:

[0030] This invention sets compensation feature values ​​in the address information when performing data operations on flash memory, eliminating the need to introduce an additional feature value setting sequence, thereby significantly saving flash memory data operation time and improving device performance. Attached Figure Description

[0031] Figure 1 This is a timing diagram of the address write cycle before performing the read operation in Embodiment 1 of the present invention.

[0032] Figure 2 The diagram shows the timing of writing and reading compensation feature values ​​in Embodiment 1 of the present invention.

[0033] Figure 3 The diagram shows the signal connection of the first data selector provided in Embodiment 2 of the present invention.

[0034] Figure 4 The diagram shows the signal connection of the second data selector provided in Embodiment 2 of the present invention.

[0035] Component designation explanation

[0036] 101 First Data Selector

[0037] 102 Second data selector. Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] Please see Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0040] Example 1

[0041] Please see Figures 1 to 2 This embodiment provides an operation method for a flash memory, the operation method including:

[0042] When performing data operations on the flash memory, an operation command is written to the flash memory; the operation command includes at least address information; the address information includes a data address and a compensation feature value;

[0043] The flash memory includes peripheral circuitry and a storage cell array; the peripheral circuitry adjusts data operation parameters according to the compensation feature value and performs the data operation on the data at the data address in the storage cell array.

[0044] In the flash memory operation method provided in this embodiment, when performing data operations on the flash memory, compensation feature values ​​are set in the address information and written into the flash memory cache through the address information sequence, thus eliminating the need to introduce an additional feature value setting sequence. This significantly saves data operation time of the flash memory and improves device performance.

[0045] As an example, the data operations include data reading, data writing, or data erasure. In this embodiment, the data operation is data reading, that is, when the host connected to the flash memory issues a read command to the flash memory, the peripheral circuitry of the flash memory reads data from the memory cell array by applying a read level. The compensation feature value includes a read offset feature, and the data operation parameters include the read level, its resolution, and the scan range. By changing the read offset feature value in the flash memory's feature register, the data operation parameters used to read data from the memory cell array are adjusted to appropriate values ​​through compensation, thereby increasing the read operation success rate and ensuring that the memory maintains good read operation performance.

[0046] As an example, in this embodiment, the storage cells in the storage cell array include single-level cells (SLC) and trinary-level cells (TLC); the trinary-level cells include lower page storage cells, middle page storage cells, and upper page storage cells. NAND flash memory using trinary-level cells as storage cells has the advantages of small size and low cost, but it also has the disadvantage of slower read / write speeds. In contrast, single-level cells have the characteristics of fast read / write speeds but large size and high cost. Existing NAND flash memory generally uses trinary-level cells as the main storage cells and sets some single-level cells as cache to improve short-term burst write speeds. Therefore, existing NAND flash memory generally combines single-level cells and trinary-level cells, and it is necessary to adjust data operation parameters such as read levels according to different types of storage cells. Optionally, in order to further reduce the size and cost of NAND flash memory, the three-level cell can also be replaced by the four-level cell (QLC). In this case, the storage cells in such a storage cell array will include both single-level cells and four-level cells.

[0047] In a three-level cell, a single storage unit needs to store 3 bits of data. Its binary information corresponds to 8 states, requiring 7 reference voltages (denoted as P1 to P7) to isolate and distinguish these 8 states. A single storage unit will change within these 8 states during data operations. Based on the speed of data operations in different storage units, the three-level cell can be further divided into lower page, middle page, and upper page storage units. The lower page storage unit is the fastest, followed by the middle page storage unit, and the upper page storage unit is the slowest. Furthermore, when the three-level cell is replaced with a four-level cell storing 4 bits of data, the binary information corresponds to 16 states, and the reference voltage and the number of pages will also change accordingly.

[0048] As an example, such as Figure 1 As shown, in this embodiment, reading the compensation feature value includes:

[0049] Single-level read compensation feature (SLClevel) that adjusts the data operation parameters read by the single-level unit;

[0050] The first read compensation feature value (P1 offset) and the fifth read compensation feature value (P5 offset) are used to adjust the data operation parameters read from the lower-level page storage unit.

[0051] The second read compensation feature value (P2 offset), the fourth read compensation feature value (P4 offset), and the sixth read compensation feature value (P6 offset) are used to adjust the data operation parameters read from the middle-level page storage unit.

[0052] The third read compensation feature value (P3 offset) and the seventh read compensation feature value (P7 offset) are used to adjust the data operation parameters read from the upper-level page storage unit.

[0053] When reading data from a flash memory, the host first writes the address of the data to be read to the external circuitry and sets the read compensation characteristic value. For example... Figure 1 The diagram shown is a timing diagram of the address write cycle before the read operation in this embodiment. The flash memory performs address write operations within multiple clock signal intervals between 00h and 30h. Figure 1 In the process, the column address (CA) is written in interval A1; the row address (RA) is written in interval A2; and the compensation feature value is written in interval A3. The data address and compensation feature value are written to the peripheral circuit cache sequentially according to the order of A1 to A3. Specifically, in interval A3, the compensation feature value is sequentially arranged as the first compensation interval (offset1), the second compensation interval (offset2), and the third compensation interval (offset3) during the address write cycle. Figure 1 As shown in the table, the first compensation interval (offset1) is used to write the single-layer read compensation feature value (SLC level), the first read compensation feature value (P1 offset), the second read compensation feature value (P2 offset), and the third read compensation feature value (P3 offset); the second compensation interval (offset2) is used to write the fourth read compensation feature value (P4 offset), the fifth read compensation feature value (P5 offset), and the seventh read compensation feature value (P7 offset); and the third compensation interval (offset3) is used to write the sixth read compensation feature value (P6 offset). Furthermore, Figure 1The read compensation feature value corresponding to the address in the feature register can be adjusted through the feature address (FA), such as A0h to A3h. Since different regions and types of storage cells in the flash memory can share the read compensation feature value setting in the feature register when performing data read operations, the operation method provided in this embodiment can also keep the system resource consumption at a low level.

[0054] As an example, a reserved interval is set after the third compensation interval (offset3). Since this embodiment uses a three-level unit as the main storage unit, the three compensation intervals of offset1 to 3 are sufficient to accommodate all read compensation feature values, and unused space (NU) is also reserved in the table.

[0055] Furthermore, when subsequent products are replaced with four-level cells, there will be 16 states in a single memory cell, corresponding to 15 reference voltages. Therefore, the three compensation intervals (offsets 1-3) and the reserved intervals set in this embodiment are sufficient to accommodate the writing of the read compensation characteristic values ​​of the four-level cell. Similarly, if five-level cells (FLC) or more layers of memory cells are further used to replace the four-level cells in newly developed flash memory, the number of reserved intervals can be increased accordingly.

[0056] like Figure 2 The diagram shown is a timing schematic for writing and reading the compensation feature value. Figure 2 In this diagram, the DQ signal represents the input / output signal; R / B represents the ready / busy signal, during which the peripheral circuit writes data into the memory cell; the three signals roic_offset1[7:0], roic_offset2[7:0], and roic_offset3[7:0] are the read compensation feature value data input and written to the feature register during the OA1, OA2, and OA3 phases of the DQ signal, respectively. The OA1, OA2, and OA3 phases of the DQ signal correspond to... Figure 1The offsets 1, 2, and 3 are defined in the DQ signal. In roic_offset1[7:0], roic_offset2[7:0], and roic_offset3[7:0], 8'h0 represents no data, while OA1, OA2, and OA3 represent the read compensation feature values ​​of OA1, OA2, and OA3 in the input DQ signal, respectively. The wefeat_clk_sw signal represents the clock signal used to synchronously write the above three signals into the feature register. Within the OA3 to 30h interval of the DQ signal, the wefeat_clk_sw signal is used as the clock signal to synchronously write the three signals roic_offset1[7:0], roic_offset2[7:0], and roic_offset3[7:0] into the feature register.

[0057] After completing the address write operation between 00h and 30h, the peripheral circuit of the flash memory will read data from the memory cell array according to the data address, and the data operation parameters used to read the data will also be adjusted according to the read compensation feature value.

[0058] In this embodiment, when performing data operations on the flash memory, the compensation feature value is set in the address information, eliminating the need to introduce an additional feature value setting sequence, thereby significantly saving the data operation time of the flash memory and improving device performance.

[0059] Example 2

[0060] Please see Figures 2 to 4 This embodiment provides a flash memory device, which includes: peripheral circuitry and a memory cell array; the peripheral circuitry includes a data register and a feature register.

[0061] The storage cell array includes storage cells for storing data, and the peripheral circuit includes CMOS logic circuits that can control the storage cell array to perform data operations such as reading, writing, or erasing.

[0062] When the flash memory performs data operations, it writes operation commands to the peripheral circuitry. These operation commands include at least address information, which includes a data address and a compensation feature value. Specifically, the operation commands include read, write, or erase commands. When the flash memory device receives the data operation commands from the host, the peripheral circuitry performs read, write, or erase operations on the memory cell array according to the data operation commands containing the address.

[0063] The peripheral circuitry includes at least a data register and a feature register. The data register stores the data address, and the feature register stores the compensation feature value. The peripheral circuitry adjusts data operation parameters according to the compensation feature value and performs the data operation on the data at the data address in the storage cell array.

[0064] As an example, such as Figure 3 and Figure 4 As shown, the peripheral circuit also includes a first data selector 101 for selecting a clock signal and a second data selector 102 for selecting a data signal.

[0065] like Figure 3 The diagram shows the signal connections of the first data selector 101. The input terminals of the first data selector 101 are connected to a data input clock signal and a feature value input clock signal, and the output terminal is connected to an operation command clock signal. Specifically, the first data selector 101 is used to control the switching of different clock signals in the peripheral circuit. The address input terminal of the first data selector 101 is the wefeat_clk_sw signal, the input terminals are the WEB clock signal and the set_feat_lat_clk signal, and the output terminal is the we_feat_clk signal. According to the control of the wefeat_clk_sw signal, the output we_feat_clk signal can select one signal from the WEB clock signal and the set_feat_lat_clk signal for output.

[0066] like Figure 4 The diagram shows the signal connections of the second data selector 102. The input of the second data selector 102 is connected to a data signal and a feature value signal, and the output is connected to an operation command signal. Specifically, the second data selector 102 is used to control the switching of different data signals in the peripheral circuit. The address input of the second data selector 102 is the wefeat_clk_sw signal, the inputs are the roic_offset<31:0> signal and the db_io2lg<31:0> signal, and the output is the roic_db_io2lg<31:0> signal. According to the control of the wefeat_clk_sw signal, the output roic_db_io2lg<31:0> signal can select one signal from the roic_offset<31:0> signal and the db_io2lg<31:0> signal for output.

[0067] Combination Figures 2 to 4It can be seen that when the webfeat_clk_sw signal is 1, the input of the first data selector 101 switches to the WEB clock signal, and the input of the second data selector 102 switches to the roic_offset<31:0> signal. The peripheral circuit uses the WEB clock signal as the clock signal and transmits the roic_offset<31:0> signal, which contains the read compensation feature value, to the web clock signal. Figure 2 The values ​​roic_offset1[7:0], roic_offset2[7:0], and roic_offset3[7:0] are written into the feature register.

[0068] In summary, this invention provides an operation method and apparatus for a flash memory. The operation method includes: writing an operation command to the flash memory when performing data operations on the flash memory; the operation command includes at least address information; the address information includes a data address and a compensation feature value; the flash memory includes peripheral circuitry and a memory cell array; the peripheral circuitry adjusts data operation parameters according to the compensation feature value and performs the data operation on the data at the data address in the memory cell array. This invention sets the compensation feature value in the address information when performing data operations on the flash memory, eliminating the need for an additional feature value setting sequence, thereby significantly saving flash memory data operation time and improving device performance.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of operating a flash memory device, characterized in that, The operation method includes: The system receives an operation command sent by a memory controller coupled to the flash memory device, the operation command including address information of the memory cell of the flash memory device to be operated; the address information includes a data address and a compensation feature value; Adjust the data operation parameters corresponding to the operation command according to the compensation feature value to obtain the adjusted data operation parameters; Data operations are performed on the storage unit determined based on the data address based on the adjusted data operation parameters; wherein the data operations include one of the following: data reading, data writing, and data erasure.

2. The operating method according to claim 1, characterized in that, The operation method further includes: During the address writing cycle, the data address and compensation feature value contained in the address information are received sequentially.

3. The operating method according to claim 2, characterized in that, The operation method further includes: The received data address and the compensation feature value are stored in the data register and feature register included in the corresponding flash memory device via the data input clock signal and feature value input clock signal, respectively.

4. The operating method according to claim 1, characterized in that, When the data operation is data reading, the compensation feature value includes the read compensation feature value, and the data operation parameters include the read level, resolution, and scan range.

5. The operating method according to claim 4, characterized in that, The storage units in the flash memory device include single-level units and three-level units; the three-level units include lower-level page storage units, middle-level page storage units, and upper-level page storage units.

6. The operating method according to claim 5, characterized in that, The read compensation feature value includes: A single-layer read compensation feature value that adjusts the data operation parameters read by the single-level unit; The first read compensation feature value and the fifth read compensation feature value are used to adjust the data operation parameters read from the lower-level page storage unit; The second read compensation feature value, the fourth read compensation feature value, and the sixth read compensation feature value are used to adjust the data operation parameters read from the middle-level page storage unit. The third and seventh read compensation feature values ​​are used to adjust the data operation parameters read from the upper-level page storage unit.

7. The operating method according to claim 6, characterized in that, The read compensation feature values ​​are sequentially arranged as a first compensation interval, a second compensation interval, and a third compensation interval during the address write cycle; the first compensation interval is used to write the single-layer read compensation feature value, the first read compensation feature value, the second read compensation feature value, and the third read compensation feature value; the second compensation interval is used to write the fourth read compensation feature value, the fifth read compensation feature value, and the seventh read compensation feature value; The third compensation interval is used to write the sixth read compensation feature value.

8. The operating method according to claim 7, characterized in that, A reserved interval is also set after the third compensation interval.

9. The operating method according to claim 1, characterized in that, The data address includes a row address and a column address; during the address writing cycle, the column address, row address, and compensation feature value are received sequentially.

10. A flash memory device, characterized in that, include: Peripheral circuits and memory cell arrays, wherein; The peripheral circuit is configured to receive an operation command sent by a memory controller coupled to the flash memory device, the operation command including address information of the memory cells of the memory cell array to be operated; The address information includes a data address and a compensation feature value; the data operation parameters corresponding to the operation command are adjusted according to the compensation feature value to obtain adjusted data operation parameters; data operations are performed on the storage unit determined based on the data address based on the adjusted data operation parameters; wherein, the data operation includes one of the following: data reading, data writing, and data erasure.

11. The flash memory device according to claim 10, characterized in that, The peripheral circuitry includes a data register and a feature register; wherein... The data register is configured to store the data address; The feature register is configured to store the compensation feature value.

12. The flash memory device according to claim 10, characterized in that, The peripheral circuit includes a first data selector and a second data selector; The first data selector receives a data input clock signal and a feature value input clock signal at its input terminal, and selects to output either the data input clock signal or the feature value input clock signal according to the control signal wefeat_clk_sw at its output terminal; the second data selector receives a data signal and a feature value signal at its input terminal, and selects to output either the data signal or the feature value signal according to the control signal wefeat_clk_sw at its output terminal; wherein, the data signal includes the data address; and the feature value signal includes the compensation feature value.

13. A memory controller, characterized in that, The memory controller is coupled to the flash memory device; the memory controller is configured to send an operation command to the flash memory device; the operation command includes address information of the memory cell of the flash memory device to be operated; the address information includes a data address and a compensation feature value; the data address is used to locate the memory cell; the compensation feature value is used to adjust the data operation parameters corresponding to the operation command; wherein the data operation includes one of the following: data reading, data writing, and data erasure.

14. The memory controller according to claim 13, characterized in that, When the operation command is data reading, the compensation feature value includes reading compensation feature value, and the data operation parameters include reading level, resolution, and scanning range.

15. The memory controller according to claim 13, characterized in that, The data address includes a row address and a column address; during the address write cycle, the column address, row address, and compensation feature value are sent to the flash memory device.

16. A flash memory, characterized in that, The flash memory includes the flash memory device according to any one of claims 10 to 12 and the memory controller according to any one of claims 13 to 15.

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