Semiconductor memory device

Abstract

This invention provides a semiconductor memory device. The semiconductor memory device includes: a substrate; a plurality of first word lines; a plurality of second word lines; a plurality of first dummy word lines; a plurality of second dummy word lines; a first select gate line; a second select gate line; and a driver. During a write operation, the driver applies a first voltage to the first select gate line, applies a second voltage lower than the first voltage to the second select gate line, applies a third voltage higher than the first voltage to the uppermost first dummy word line, applies a fourth voltage different from the third voltage and higher than the second voltage to the uppermost second dummy word line, applies a fifth voltage higher than the third voltage to the lowermost first dummy word line, and applies a sixth voltage different from the fifth voltage and higher than the fourth voltage to the lowermost second dummy word line.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-148135 (filed on September 10, 2021). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] NAND (Not AND) type flash memory is known as a non-volatile semiconductor memory device. Summary of the Invention

[0005] The purpose of this implementation is to provide a semiconductor memory device with improved reliability.

[0006] A semiconductor memory device according to an embodiment includes: a substrate; memory pillars extending from the substrate in a first direction; a plurality of first word lines on the substrate, separated from the substrate in the first direction, disposed parallel to a substrate surface of the substrate, and facing a first side of the memory pillars; a plurality of second word lines on the substrate, separated from the substrate in the first direction, disposed parallel to the substrate surface of the substrate, and positioned in the first direction at the same positions as the plurality of first word lines, and facing a second side of the memory pillars; a plurality of first dummy word lines on the first word lines, disposed parallel to the substrate surface of the substrate, and facing a first side of the memory pillars; a plurality of second dummy word lines on the second word lines, disposed parallel to the substrate surface of the substrate, and positioned in the first direction at the same positions as the plurality of first dummy word lines, and facing a second side of the memory pillars; and a first select gate line extending from the substrate in a first direction. A dummy word line is disposed above the substrate surface of the substrate, parallel to the substrate surface, and facing the first side of the memory pillar; a second select gate line is disposed above the second dummy word line, parallel to the substrate surface of the substrate, and is positioned in the first direction at the same location as the first select gate line, facing the second side of the memory pillar; and a driver capable of supplying voltage; during a write operation, the driver applies a first voltage to the first select gate line, applies a second voltage lower than the first voltage to the second select gate line, applies a third voltage higher than the first voltage to the uppermost first dummy word line, applies a fourth voltage different from the third voltage and higher than the second voltage to the uppermost second dummy word line, applies a fifth voltage higher than the third voltage to the lowermost first dummy word line, and applies a sixth voltage different from the fifth voltage and higher than the fourth voltage to the lowermost second dummy word line. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the configuration of a memory system including the semiconductor memory device of the first embodiment.

[0008] Figure 2 This is a schematic diagram showing the circuit configuration of the memory cell array in the semiconductor memory device of the first embodiment.

[0009] Figure 3 This is a schematic diagram showing the planar layout of the selected gate line, bit line, and memory pillars in the first embodiment.

[0010] Figure 4 This is a schematic diagram showing the planar layout of the word lines and memory pillars in the first embodiment.

[0011] Figure 5 yes Figure 3 and Figure 4 The diagram shows the end face of the B1-B2 cut-off section of the semiconductor memory device.

[0012] Figure 6 yes Figure 3 and Figure 4 The diagram shows the end face of the A1-A2 cut-off portion of the semiconductor memory device.

[0013] Figure 7 yes Figure 5 The diagram shows the end face of the C1-C2 cut-off portion of the memory cell transistor.

[0014] Figure 8 yes Figure 7 The diagram shows the cut-off section (D1-D2) of the memory cell transistor.

[0015] Figure 9 It means Figure 7 The cut-off end face view of a variation example of a memory cell transistor is shown.

[0016] Figure 10 yes Figure 9 The diagram shows the E1-E2 cut-off section end face of the memory cell transistor.

[0017] Figure 11 This is a diagram showing the equivalent circuit of a memory column (two adjacent NAND strings) in a semiconductor memory device according to the first embodiment.

[0018] Figure 12 This is a diagram used to illustrate the electrical connections of the voltage generation circuit, driver group, and select gate line or word line in the first embodiment.

[0019] Figure 13 This is a diagram used to illustrate the electrical connections of the voltage generation circuit, driver group, and select gate line or word line in the first embodiment.

[0020] Figure 14 This is a schematic diagram illustrating the electrical connection between the even-side driver and the line decoder in the first embodiment.

[0021] Figure 15 This is a schematic diagram illustrating the electrical connection between the odd-side driver and the line decoder in the first embodiment.

[0022] Figure 16 This is a schematic diagram illustrating the electrical connection between the voltage generation circuit 27 and the even-side driver 28 in the first embodiment.

[0023] Figure 17 This is a schematic diagram illustrating the electrical connection between the voltage generation circuit 27 and the odd-side driver 28 in the first embodiment.

[0024] Figure 18This is a schematic diagram illustrating a method for applying voltage to a selection transistor and a memory cell transistor in a semiconductor memory device according to a first comparative embodiment.

[0025] Figure 19 This is a schematic diagram illustrating a method for applying voltage to a selection transistor and a memory cell transistor in a semiconductor memory device according to a second comparative embodiment.

[0026] Figure 20 (a) to (d) are schematic diagrams illustrating the method by which the semiconductor memory device of the first embodiment applies voltage to the selection transistor and the memory cell transistor.

[0027] Figure 21 This diagram schematically illustrates the voltage applied to the select transistors in the memory pillars (two adjacent NAND strings) via the select gate line, and the voltage applied to the memory cell transistors in the memory pillars via the word line and the dummy word line in a semiconductor memory device according to a comparative embodiment.

[0028] Figure 22 This diagram schematically illustrates the voltage applied to the select transistors in the memory pillars (two adjacent NAND strings) via the select gate line, and the voltage applied to the memory cell transistors in the memory pillars via the word line and the dummy word line in the semiconductor memory device of the first embodiment.

[0029] Figure 23 This diagram schematically illustrates the voltage applied to the select transistors in the memory pillars (two adjacent NAND strings) via the select gate line, and the voltage applied to the memory cell transistors in the memory pillars via the word line and the dummy word line in the semiconductor memory device of the second embodiment.

[0030] Figure 24 This diagram schematically illustrates the voltage applied to the select transistors in the memory pillars (two adjacent NAND strings) via the select gate line, and the voltage applied to the memory cell transistors in the memory pillars via the word line and the dummy word line in the semiconductor memory device of the third embodiment.

[0031] Figure 25 This diagram schematically illustrates the voltage applied to the select transistors in the memory pillars (two adjacent NAND strings) via the select gate line and the voltage applied to the memory cell transistors in the memory pillars via the word line and the dummy word line in the semiconductor memory device of the fourth embodiment. Detailed Implementation

[0032] The embodiments will now be described using the accompanying drawings. Furthermore, in the drawings, the same or similar parts are labeled with the same or similar symbols.

[0033] (First Embodiment)

[0034] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system 3 including the semiconductor memory device 1 of the first embodiment. The configuration of the memory system 3 including the semiconductor memory device 1 of the first embodiment is not limited to... Figure 1 The structure shown.

[0035] like Figure 1 As shown, the memory system 3 includes a semiconductor storage device 1 and a memory controller 2. The memory system 3 may be, for example, a memory card such as an SSD (Solid State Drive) or an SDTM card. The memory system 3 may also include a host device (not shown in the diagram).

[0036] Semiconductor memory device 1 is connected to and controlled by memory controller 2, for example. Memory controller 2 receives commands from host device required for the operation of semiconductor memory device 1 and sends these commands to semiconductor memory device 1. Memory controller 2 sends these commands to semiconductor memory device 1 to control data reading from, writing to, or erasing from semiconductor memory device 1. In this embodiment, semiconductor memory device 1 is, for example, a NAND flash memory.

[0037] like Figure 1 As shown, the semiconductor memory device 1 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a sequencer 24, a register 25, a ready / busy control circuit 26, a voltage generation circuit 27, a driver assembly 28, a line decoder 29, a sense amplifier 70, an input / output pad assembly 71, and a logic control pad assembly 72. The semiconductor memory device 1 performs various operations, such as a write operation to store write data DAT into the memory cell array 21 and a read operation to read read data DAT from the memory cell array 21. The configuration of the semiconductor memory device 1 in this embodiment is not limited to... Figure 1 The structure shown.

[0038] The memory cell array 21 is connected, for example, to the sense amplifier 70, the line decoder 29, and the driver group 28. The memory cell array 21 contains blocks BLK1, BLK0, ..., BLKn (n is an integer greater than or equal to 1). Each block BLK contains multiple string components SU (SU0, SU1, SU2, ...), details of which will be described below. Each string component SU contains multiple non-volatile memory cells associated with bit lines and word lines. The block BLK is, for example, a data erasure unit. The memory cell transistors MT contained within the same block BLK (… Figure 2 The data stored was erased in one go.

[0039] Semiconductor memory device 1 can, for example, employ a TLC (Triple-Level Cell) or QLC (Quadruple-Level Cell) architecture. In TLC, each memory cell stores 3 bits of data, while in QLC, each memory cell stores 4 bits of data. Furthermore, each memory cell can store less than 2 bits of data or more than 5 bits of data.

[0040] Input / output circuit 22 is connected, for example, to register 25, logic control circuit 23, and sense amplifier 70. Input / output circuit 22 controls the transmission and reception of data signal DQ<7:0> between memory controller 2 and semiconductor storage device 1.

[0041] The data signal DQ<7:0> is an 8-bit signal. The data signal DQ<7:0> is the entity that transmits and receives data between the semiconductor memory device 1 and the memory controller 2, and includes instructions (CMD), data (DAT), address information (ADD), and status information (STS). The instructions (CMD) include, for example, commands used to execute commands sent from the host device (memory controller 2) to the semiconductor memory device 1. The data (DAT) includes data written to or read from the semiconductor memory device 1. The address information (ADD) includes, for example, column and row addresses used to select multiple non-volatile memory cells associated with bit lines and word lines. The status information (STS) includes, for example, information related to the status of the semiconductor memory device 1, which is related to write and read operations.

[0042] More specifically, the input / output circuit 22 includes an input circuit and an output circuit, which perform the following processing: The input circuit receives write data DAT, address information ADD, and instruction CMD from the memory controller 2. The input circuit sends the received write data DAT to the sense amplifier 70 and sends the received address information ADD and instruction CMD to the register 25. On the other hand, the output circuit receives status information STS from the register 25 and read data DAT from the sense amplifier 70. The output circuit sends the received status information STS and read data DAT to the memory controller 2.

[0043] Logic control circuit 23 is connected, for example, to memory controller 2 and sequencer 24. Logic control circuit 23 receives from memory controller 2, for example, chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn, and write protection signal WPn. Based on the received signals, logic control circuit 23 controls input / output circuit 22 and sequencer 24.

[0044] The chip enable signal CEn is used to enable (activate) the semiconductor memory device 1. The instruction latch enable signal CLE is used to notify the input / output circuit 22 that the signal DQ input to the semiconductor memory device 1 is the instruction CMD signal. The address latch enable signal ALE is used to notify the input / output circuit 22 that the signal DQ input to the semiconductor memory device 1 is the address information ADD signal. The write enable signal WEn and the read enable signal REn are, for example, signals used to command the input / output circuit 22 to input and output the data signal DQ, respectively. The write protection signal WPn is used to instruct the semiconductor memory device 1 to prohibit data writing and erasure.

[0045] The sequencer 24 is connected, for example, to the ready / busy control circuit 26, the sense amplifier 70, and the driver group 28. The sequencer 24 controls the overall operation of the semiconductor memory device 1 based on the instruction CMD stored in the instruction register. For example, the sequencer 24 controls the sense amplifier 70, the line decoder 29, the voltage generation circuit 27, and the driver group 28 to perform various operations such as write operations and read operations.

[0046] Register 25 includes, for example, a status register (not shown in the diagram), an address register (not shown in the diagram), and an instruction register (not shown in the diagram). The status register receives and stores status information STS from the sequencer 24, and sends the status information STS to the input / output circuit 22 based on the instructions of the sequencer 24. The address register receives and stores address information ADD from the input / output circuit 22. The address register sends the column address in the address information ADD to the sense amplifier 70, and sends the row address in the address information ADD to the row decoder 29. The instruction register receives and stores the instruction CMD from the input / output circuit 22, and sends the instruction CMD to the sequencer 24.

[0047] The ready / busy control circuit 26 generates a ready / busy signal R / Bn under the control of the sequencer 24, and sends the generated ready / busy signal R / Bn to the memory controller 2. The ready / busy signal R / Bn is used to notify the semiconductor memory device 1 that it is in a ready state or a busy state. In the ready state, commands from the memory controller 2 can be accepted; in the busy state, commands cannot be accepted.

[0048] The voltage generation circuit 27 is connected, for example, to the driver assembly 28. Based on the control of the sequencer 24, the voltage generation circuit 27 generates voltages for write and read operations, and supplies the generated voltages to the driver assembly 28.

[0049] Drive group 28, for example, includes even-numbered side drives 28A ( Figure 12 ) and odd-side driver 28B ( Figure 12Driver group 28 is connected to memory cell array 21, sense amplifier 70, and line decoder 29. Driver group 28 generates select gate line SGD based on the voltage supplied from voltage generation circuit 27, for various operations such as read and write operations. Figure 2 ), Word line WL ( Figure 2 ) and source line SL ( Figure 2 Various voltages are applied by the driver group 28. The generated voltage is supplied to the even-side driver 28A, the odd-side driver 28B, the sense amplifier 70, the line decoder 29, the source line SL, etc.

[0050] The row decoder 29 receives the row address from the address register and decodes the received row address. Based on the decoding result, the row decoder 29 selects the target block BLK to perform various operations such as read and write operations. The row decoder 29 can supply the voltage supplied from the driver group 28 to the selected block BLK.

[0051] The sense amplifier 70 receives a column address from an address register and decodes the received column address. Based on the decoding result, the sense amplifier 70 performs data transmission and reception operations (DAT) between the memory controller 2 and the memory cell array 21. The sense amplifier 70 includes, for example, a sense amplifier component (not shown) configured for each bit line. The sense amplifier 70 can supply voltage to the bit line BL using the sense amplifier component. For example, the sense amplifier 70 can supply voltage to the bit line using the sense amplifier component. Furthermore, the sense amplifier 70 senses data read from the memory cell array 21, generates read data DAT, and sends the generated read data DAT to the memory controller 2 via the input / output circuit 22. Additionally, the sense amplifier 70 receives write data DAT from the memory controller 2 via the input / output circuit 22 and sends the received write data DAT to the memory cell array 21.

[0052] The input / output pad group 71 sends the data signal DQ<7:0> received from the memory controller 2 to the input / output circuit 22.

[0053] The logic control pad group 72 transmits the chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn received from the memory controller 2 to the logic control circuit 23. The logic control pad group 72 transmits the ready / busy signal R / Bn received from the ready / busy control circuit 26 to the memory controller 2.

[0054] Figure 2 yes Figure 1An example of the circuit configuration of the storage cell array 21 shown. Figure 2 This is a diagram showing the circuit configuration of one block BLK among the multiple blocks BLK contained in the memory cell array 21. For example, each of the multiple blocks BLK contained in the memory cell array 21 has... Figure 2 The circuit configuration is shown. The configuration of the memory cell array 21 in this embodiment is not limited to... Figure 2 The structure shown. Figure 2 In the description, sometimes the terms "and" are omitted. Figure 1 Description of identical or similar structures.

[0055] like Figure 2 As shown, block BLK contains multiple string components SU (SU0, SU1, SU2, SU3). In this embodiment, write and read operations are performed on a per-string component SU (page). Each string component SU contains multiple NAND strings 50. For example, string components SU0 and SU2 contain multiple NAND strings 50e, and string components SU1 and SU3 contain multiple NAND strings 50o. Furthermore, Figure 2 The example shown illustrates that each block BLK contains four string components SU0, SU1, SU2, and SU3. However, the number of string components contained in each block is not limited to four. For example, each block BLK can also contain more than six string components.

[0056] Each NAND string 50 includes, for example, eight memory cell transistors MT (MT0 to MT7), four dummy transistors DT0, DT1, DT2, and DT3, and select transistors ST1 and ST2. The memory cell transistors MT have a control gate and a charge storage layer, non-volatilely storing data. The dummy transistors DT are connected in series between the source of select transistor ST1 and the drain of select transistor ST2. The memory cell transistors MT are connected in series between the drain of dummy transistor DT1 and the source of dummy transistor DT2.

[0057] The gates of the selection transistors ST1 in each string assembly SU are connected to the selection gate lines SGD (SGD0, SGD1, ...). The selection gate lines SGD are independently controlled using the line decoder 29. Additionally, the gates of the selection transistors ST2 in each even-numbered string assembly SUe (SU0, SU2, ...) are connected, for example, to the even-numbered selection gate line SGSe, and the gates of the selection transistors ST2 in each odd-numbered string assembly SUo (SU1, SU3, ...) are connected, for example, to the odd-numbered selection gate line SGSo. The even-numbered selection gate lines SGSe and the odd-numbered selection gate lines SGSo can be interconnected and controlled in the same way, or they can be set and controlled independently.

[0058] Within the same block BLK, the control gates of the memory cell transistors MT (MT0 to MT7) contained in the serial component SUE are all connected to word lines WLe (WLe0 to WLe7). Within the same block BLK, the control gates of the memory cell transistors MT (MT0 to MT7) contained in the serial component SUo are all connected to word lines WLo (WLo0 to WLo7). The select gate lines WLe and WLo are independently controlled by the line decoder 29.

[0059] The control gates of the dummy transistors DT0, DT1, DT2, and DT3 contained in the serial component SUE within the same block BLK are commonly connected to the dummy word lines WLDSe0, WLDSe1, WLDDe0, and WLDDe1, respectively. The control gates of the dummy transistors DT0, DT1, DT2, and DT3 contained in the serial component SUE within the same block BLK are commonly connected to the dummy word lines WLDSo0, WLDSo1, WLDDo0, and WLDDo1, respectively. The dummy word lines WLDSo0, WLDSo1, WLDDo0, and WLDDo1 are independently controlled by the line decoder 29.

[0060] Within the memory cell array 21, the drains of the select transistors ST1 of the NAND strings 50 in the same column are commonly connected to the bit line BL (BL0 to BL(L-1), where (L-1) is a natural number greater than 2). That is, the bit line BL connects the NAND strings 50 across multiple string components SU. The sources of multiple select transistors ST2 are commonly connected to the source line SL. The source line SL is electrically connected to the driver group 28, for example, and voltage is supplied to the source line SL from the voltage generation circuit 27 or the driver group 28 by controlling the voltage generation circuit 27 and the driver group 28 using the sequencer 24. Alternatively, the semiconductor memory device 1 in one embodiment may also have multiple source lines SL. For example, the multiple source lines SL may each be electrically connected to the driver group 28, and different voltages are supplied to the multiple source lines SL from the voltage generation circuit 27 or the driver group 28 by controlling the voltage generation circuit 27 and the driver group 28 using the sequencer 24.

[0061] String components SU are connected to different bit lines BL and contain multiple NAND strings 50 connected to the same select gate line SGD. Block BLK contains multiple string components SU sharing a word line WL. Memory cell array 21 contains multiple blocks BLK sharing a bit line BL. In memory cell array 21, the aforementioned select gate line SGS, dummy word line WLDS, word line WL, dummy word line WLDD, and select gate line SGD are stacked above the source line layer, and memory cell transistors MT are stacked in three dimensions.

[0062] Figure 3This is a diagram showing the planar layout of the select gate line (SGD) in the plane (XY plane) parallel to the source line layer of a certain block of BLK. For example... Figure 3 As shown, the semiconductor memory device 1 of this embodiment includes, for example, four select gate lines (SGDs) within one block BLK. The planar layout of the select gate lines (SGDs) in one embodiment is not limited to... Figure 3 The layout shown. Figure 3 In the description, sometimes the terms "and" are omitted. Figure 1 and Figure 2 Description of identical or similar structures.

[0063] like Figure 3 As shown, in the semiconductor memory device 1 of this embodiment, for example, a first connection portion 10-0d extending in the Y direction is used to connect three wiring layers 10-0a, 10-0b, and 10-0c extending in the X direction. Wiring layers 10-0a and 10-0c are located at both ends in the Y direction. Wiring layers 10-0a and 10-0b are adjacent in the Y direction, separated by another wiring layer (wiring layer 10-1a). The first connection portion 10-0d is located at one end in the X direction. The three wiring layers 10-0a, 10-0b, and 10-0c function as a select gate line SGDO. In this embodiment, for example, the Y direction is orthogonal or substantially orthogonal to the X direction.

[0064] A second connection portion 10-1d extending in the Y direction is used to connect wiring layers 10-1a and 10-1b extending in the X direction. Wiring layer 10-1a is located between wiring layers 10-0a and 10-0b. Wiring layer 10-1b is located between wiring layer 10-0b and another wiring layer (wiring layer 10-2a). The second connection portion 10-1d is located at the opposite end of the first connection portion 10-0d in the X direction. The two wiring layers 10-1a and 10-1b function as the select gate line SGD1.

[0065] A first connecting portion 10-2d extending in the Y direction connects to wiring layers 10-2a and 10-2b extending in the X direction. Similarly, a second connecting portion 10-3d extending in the Y direction connects to wiring layers 10-3a and 10-3b extending in the X direction. Wiring layer 10-2a is located between wiring layers 10-1b and 10-3a. Wiring layer 10-3a is located between wiring layers 10-2a and 10-2b. Wiring layer 10-2b is located between wiring layers 10-3a and 10-3b. Wiring layer 10-3b is located between wiring layers 10-2b and 10-0c. The first connecting portion 10-2d is located at one end on the same side as the first connecting portion 10-0d in the X direction. The second connection portion 10-3d is located at the opposite end of the first connection portion 10-0d in the X direction. The two wiring layers 10-2a and 10-2b function as the select gate line SGD2. The two wiring layers 10-3a and 10-3b function as the select gate line SGD3.

[0066] This embodiment illustrates a configuration in which the first connecting portions 10-0d and 10-2d or the second connecting portions 10-1d and 10-3d are used to connect the various wiring layers, but it is not limited to this configuration. For example, control can be performed in such a way that each wiring layer is independent of the others, the same voltage is supplied to wiring layers 10-0a, 10-0b, and 10-0c, the same voltage is supplied to wiring layers 10-1a and 10-1b, the same voltage is supplied to wiring layers 10-2a and 10-2b, and the same voltage is supplied to wiring layers 10-3a and 10-3b.

[0067] The string assembly SU containing the memory cylinder MP adjacent to wiring layers 10-0a, 10-0b, and 10-0c, of NAND string 50e, is referred to as SU0. The string assembly SU containing the memory cylinder MP adjacent to wiring layers 10-1a and 10-1b, of NAND string 50o, is referred to as SU1. The string assembly SU containing the memory cylinder MP adjacent to wiring layers 10-2a and 10-2b, of NAND string 50e, is referred to as SU2. The string assembly SU containing the memory cylinder MP adjacent to wiring layers 10-3a and 10-3b, of NAND string 50o, is referred to as SU3.

[0068] In block BLK, adjacent wiring layers 10 in the Y direction are insulated. The region that insulates adjacent wiring layers 10 is called slot SLT2. In slot SLT2, for example, an insulating film (not shown) is embedded in the region from the surface parallel to the source line layer to the layer where at least wiring layer 10 is provided. In addition, within the memory cell array 21, for example, multiple [missing information] are arranged in the Y direction. Figure 3The block BLK is shown. Within block BLK, similarly to the adjacent wiring layer 10 in the Y direction, an insulating film (not shown) is embedded between adjacent blocks BLK in the Y direction, thus insulating adjacent blocks BLK in the Y direction as well. The region that insulates adjacent blocks BLK is called slit SLT1. Similar to slit SLT2, in slit SLT1, an insulating film is embedded in the region from the surface parallel to the source line layer to the layer where at least the wiring layer 10 is located.

[0069] Multiple memory pillars MP (MP0 to MP15) are disposed between adjacent wiring layers 10 in the Y direction. The multiple memory pillars MP are disposed in the memory cell section. Each of the multiple memory pillars MP is disposed along the Z direction. In one embodiment, for example, the Z direction is a direction orthogonal or substantially orthogonal to the XY direction, and is a direction perpendicular or substantially perpendicular to the source line layer. The Z direction is an example of a first direction. The Y direction is an example of a second direction.

[0070] Specifically, memory pillars MP4 and MP12 are installed between wiring layers 10-0a and 10-1a. Memory pillars MP0 and MP8 are installed between wiring layers 10-1a and 10-0b. Memory pillars MP5 and MP13 are installed between wiring layers 10-0b and 10-1b. Memory pillars MP1 and MP9 are installed between wiring layers 10-1b and 10-2a. Memory pillars MP6 and MP14 are installed between wiring layers 10-2a and 10-3a. Memory pillars MP2 and MP10 are installed between wiring layers 10-3a and 10-2b. Memory pillars MP7 and MP15 are installed between wiring layers 10-2b and 10-3b. Memory pillars MP3 and MP11 are installed between wiring layers 10-3b and 10-0c.

[0071] The memory column MP is the structure that forms the select transistors ST1, ST2, dummy transistors DT0, DT1, DT2, DT3, and the memory cell transistor MT. The detailed structure of the memory column MP will be described below.

[0072] Memory cylinders MP0 to MP3 are arranged along the Y direction. Memory cylinders MP8 to MP11 are arranged along the Y direction at positions adjacent to memory cylinders MP0 to MP3 in the X direction. In other words, memory cylinders MP0 to MP3 are arranged side by side with memory cylinders MP8 to MP11.

[0073] Memory cylinders MP4-MP7 and memory cylinders MP12-MP15 are arranged along the Y direction. Memory cylinders MP4-MP7 are located between memory cylinders MP0-MP3 and memory cylinders MP8-MP11 in the X direction. Memory cylinders MP12-MP15 are located in the X direction, separated from memory cylinders MP4-MP7 by memory cylinders MP8-MP11. In other words, memory cylinders MP4-MP7 and memory cylinders MP12-MP15 are arranged side by side.

[0074] Above memory cylinders MP0 to MP3, two bit lines BL0 and BL1 are provided. Bit line BL0 is connected to memory cylinders MP1 and MP3. Bit line BL1 is connected to memory cylinders MP0 and MP2. Above memory cylinders MP4 to MP7, two bit lines BL2 and BL3 are provided. Bit line BL2 is connected to memory cylinders MP5 and MP7. Bit line BL3 is connected to memory cylinders MP4 and MP6.

[0075] Above memory cylinders MP8 to MP11, two bit lines BL4 and BL5 are provided. Bit line BL4 is connected to memory cylinders MP9 and MP11. Above memory cylinders MP12 to MP15, two bit lines BL6 and BL7 are provided. Bit line BL6 is connected to memory cylinders MP13 and MP15. Bit line BL7 is connected to memory cylinders MP12 and MP14.

[0076] As described above, the memory pillars MP are positioned across two wiring layers 10 in the Y direction, and are embedded in a portion of any one of the multiple slits SLT2. Additionally, one slit SLT2 is positioned between adjacent memory pillars MP in the Y direction.

[0077] Furthermore, no memory pillar MP is provided between the adjacent wiring layers 10-0a and 10-0b separated by the slit SLT1.

[0078] Figure 4 This is a diagram showing the planar layout of the letter lines WL on the XY plane. Figure 4 The layout shown corresponds to Figure 3 The layout of a single block is set up in a way that is more than... Figure 3 The layout of the wiring layer 11 below the wiring layer 10 is shown. The planar layout of the word line WL in one embodiment is not limited to... Figure 4 The layout shown. Figure 4 In the description, sometimes the terms "and" are omitted. Figures 1-3 Description of identical or similar structures.

[0079] like Figure 4As shown, nine wiring layers 11 (wiring layers 11-0 to 11-7, where wiring layer 11-0 includes wiring layers 11-0a and 11-0b) extending in the X direction are arranged along the Y direction. Each wiring layer 11-0 to 11-7 is arranged in the Z direction below each wiring layer 10-0 to 10-7. An insulating film is provided between wiring layers 11-0 to 11-7 and wiring layers 10-0 to 10-7, and wiring layers 11-0 to 11-7 are mutually insulated from each other.

[0080] Each wiring layer 11 functions as word line WL7. Other word lines WL0 to WL6 also have the same structure and function as word line WL7. Figure 4 In the example shown, wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b function as word lines WLe7. Wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are connected using a first connection portion 11-8 extending in the Y direction. The first connection portion 11-8 is located at one end in the X direction. Wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are connected to the line decoder 29 via the first connection portion 11-8. In one embodiment, the first connection portion 11-8 and wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are sometimes collectively referred to as wiring layer 11e.

[0081] Additionally, wiring layers 11-1, 11-3, 11-5, and 11-7 function as word lines WLo7. A second connection portion 11-9 extending in the Y direction connects wiring layers 11-1, 11-3, 11-5, and 11-7. The second connection portion 11-9 is located in the X direction at the opposite end to the first connection portion 11-8. Wiring layers 11-1, 11-3, 11-5, and 11-7 are connected to the line decoder 29 via the second connection portion 11-9. In one embodiment, the second connection portion 11-9 and wiring layers 11-1, 11-3, 11-5, and 11-7 are sometimes collectively referred to as wiring layer 11o.

[0082] The storage cell section is disposed between the first connection section 11-8 and the second connection section 11-9. In the storage cell section, adjacent wiring layers 11 in the Y direction are... Figure 3 The slit SLT2 shown is used for isolation. Additionally, the wiring layer 11 between adjacent blocks BLK in the Y direction is similarly isolated by slit SLT1, just like slit SLT2. The memory cell section and... Figure 3 Similarly, it includes memory columns MP0 to MP15.

[0083] Select gate line SGS, word lines WL0~WL6, and dummy word lines WLDS0, WLDS1, WLDD0, and WLDD1 to have the same characteristics as... Figure 4The character line WL7 shown has the same structure.

[0084] Figure 5 It means Figure 4 The diagram shows the end faces of the cut-off portions B1-B2. The end faces of the cut-off portions of block BLK in this embodiment are not limited to... Figure 5 The cut-off end face shown. Figure 5 In the description, sometimes the terms "and" are omitted. Figures 1-4 Description of identical or similar structures.

[0085] like Figure 5 As shown, the wiring layer 12 is disposed above the source line layer 13 along the Z direction. The source line layer 13 functions as the source line SL. Alternatively, the wiring layer 12 may not be disposed above the source line layer 13. Figure 5 Instead of the source line layer 13 shown, it is disposed on the p-type well region of the semiconductor substrate. In this case, the source line SL is electrically connected to the p-type well region of the semiconductor substrate. The wiring layer 12 functions as the select gate line SGS. A 12-layer wiring layer 11 is stacked on top of the wiring layer 12 along the Z direction. The wiring layer 12 functions as the dummy word lines WLDS, WL, and WLDD. Furthermore, the 12-layer wiring layer 11 corresponds one-to-one with the dummy word lines WLDS0, WLDS1, WL0 to WL7, WLDD0, and WLDD1. Figure 4 This is a diagram showing the planar layout of the wiring layer 11, which functions as the word line WL. Figure 3 This is a planar layout diagram showing the wiring layer 10 that functions as the Select Gate Line (SGD). The planar layout of the wiring layer 12 that functions as the Select Gate Line (SGS) is, for example, [the following diagram is shown]. Figure 3 The wiring layer 10 shown, which functions as the select gate line SGD, is replaced with a wiring layer 12, which functions as the select gate line SGS.

[0086] Wiring layer 12 functions as either an even-numbered gate selection line SGSe or an odd-numbered gate selection line SGSo. The even-numbered gate selection line SGSe and the odd-numbered gate selection line SGSo are alternately arranged in the Y direction, separated by a slit SLT2. Memory pillars MP are positioned between adjacent even-numbered gate selection lines SGSe and odd-numbered gate selection lines SGSo in the Y direction.

[0087] Wiring layer 11 functions as even-numbered dummy word lines WLDSe, odd-numbered dummy word lines WLDSo, even-numbered word lines WLe, odd-numbered word lines WLo, even-numbered dummy word lines WLDDe, or odd-numbered dummy word lines WLDDo. Even-numbered dummy word lines WLDSe and odd-numbered dummy word lines WLDSo are alternately arranged in the Y direction, separated by slits SLT2. Memory cylinders MP are positioned between adjacent even-numbered dummy word lines WLDSe and odd-numbered dummy word lines WLDSo in the Y direction. Memory cells (described later) are positioned between memory cylinders MP and even-numbered dummy word lines WLDSe, and between memory cylinders MP and odd-numbered dummy word lines WLDSo. Even-numbered word lines WLe and odd-numbered word lines WLo are alternately arranged in the Y direction, separated by slits SLT2. Memory cylinders MP are positioned between adjacent word lines WLe and WLo in the Y direction. Memory cells (described later) are positioned between memory cylinders MP and word lines WLe, and between memory cylinders MP and word lines WLo. Even-numbered dummy word lines WLDDe and odd-numbered dummy word lines WLDDo are alternately arranged in the Y direction, separated by a slit SLT2. Memory cylinders MP are disposed between adjacent even-numbered dummy word lines WLDDe and odd-numbered dummy word lines WLDDo in the Y direction. Memory cells, described later, are disposed between memory cylinders MP and even-numbered dummy word lines WLDDe, and between memory cylinders MP and odd-numbered dummy word lines WLDDo.

[0088] A slit SLT1 is provided between adjacent blocks BLK in the Y direction. As described above, an insulating layer is provided in the slit SLT1. However, a contact plug or a groove-shaped structure formed using a conductor may also be provided within the slit SLT1, which serves as an insulator. When a contact plug or a groove-shaped structure formed using a conductor is provided within the slit SLT1, a voltage can be applied to the source line layer 13. Furthermore, the width of the slit SLT1 in the Y direction is greater than the width of the slit SLT2 in the Y direction.

[0089] like Figure 3 and such Figure 5 As shown, memory cylinders MP are electrically connected to bit lines BL. For example, memory cylinder MP0 is connected to bit line BL1 via contact plug 16. Additionally, memory cylinders MP1, MP2, and MP3 are connected to bit line BL0 via contact plug 16. Similarly, memory cylinders MP4 to MP7 are each connected to bit line BL2 or BL3, memory cylinders MP8 to MP11 are connected to bit line BL4 or BL5, and memory cylinders MP12 to MP15 are connected to bit line BL6 or BL7.

[0090] Figure 6 It means Figure 3 The diagram shows the cut-off end face of the semiconductor memory device, specifically the A1-A2 section. In one embodiment, the cut-off end face of block BLK is not limited to... Figure 6 The cut-off end face shown. Figure 6 In the description, sometimes the terms "and" are omitted. Figures 1-5 Description of similar or identical configurations. The stacked structure of source line layer 13, wiring layer 12, wiring layer 11, and wiring layer 10, and the configuration of the memory cell section are as follows. Figure 5 The explanation is already provided, therefore it is omitted here. Furthermore, Figure 6 In the diagram, dashed lines are used to depict the structure in the depth direction of the cut-off end face of section A1-A2.

[0091] like Figure 6 As shown, in the first connection region, wiring layers 10, 11, and 12 are, for example, stepped and led out from the source line layer 13. That is, when viewed in the XY plane, the upper surfaces of the ends of wiring layers 10, 11, and 12 are exposed in the first connection region. Contact plugs 17 are provided on the upper surfaces of the ends of wiring layers 10, 11, and 12 exposed in the first connection region. Contact plugs 17 are connected to the metal wiring layer 18. For example, using the metal wiring layer 18, wiring layer 10, which functions as even-numbered select gate lines SGD0 and SGD2, wiring layer 11, which functions as even-numbered dummy word lines WLDSe, WLDDe, and WLe, and wiring layer 12, which functions as even-numbered select gate line SGSe, are connected via the line decoder 29. Figure 1 It is electrically connected to the even-numbered side driver 28A.

[0092] Similar to the first connection region, in the second connection region, wiring layers 10, 11, and 12 are, for example, stepped and led out from the source line layer 13. When viewed in the XY plane, the upper surfaces of the ends of wiring layers 10, 11, and 12 are exposed in the second connection region. Contact plugs 19 are provided on the upper surfaces of the ends of wiring layers 10, 11, and 12 exposed in the second connection region. The contact plugs 19 are connected to the metal wiring layer 20. For example, using the metal wiring layer 20, the odd-numbered select gate lines SGD1 and SGD3, wiring layer 11 functioning as the odd-numbered line WLo, and wiring layer 12 functioning as the odd-numbered select gate line SGSo are connected via the line decoder 29 ( Figure 1 It is electrically connected to the odd-side driver 28B.

[0093] The wiring layer 10 can also be electrically connected to the line decoder 29 or the even-side driver 28A and the odd-side driver 28B via the second connection area instead of the first connection area, or it can be electrically connected to the line decoder 29 or the even-side driver 28A and the odd-side driver 28B via both the first connection area and the second connection area.

[0094] Figure 7 This is a diagram showing the C1-C2 cut-off end face of the memory cell transistor in this embodiment. Figure 8 It means Figure 7 The diagram shows the cut-off end face of the D1-D2 section of the memory cell transistor. Figure 7 and Figure 8 This is a cut-off end-face view of a region containing two memory cell transistors MT. In the first example, the charge storage layer included in the memory cell transistor MT is an insulating film. The first example of the memory cell transistor in this embodiment is not limited to... Figure 7 and Figure 8 The structure shown. Figure 7 and Figure 8 In the description, sometimes the terms "and" are omitted. Figures 1-6 Description of identical or similar structures.

[0095] like Figure 7 and such Figure 8 As shown, the memory column MP includes an insulating layer 30 (an example of an insulator), a semiconductor layer 31, and insulating layers 32-34 disposed along the Z direction. The insulating layer 30 is formed, for example, using a silicon oxide film. The semiconductor layer 31 is disposed around the insulating layer 30 and functions as a region for forming channels of memory cell transistors MT. The semiconductor layer 31 (an example of a first channel and a second channel) is formed, for example, using a polysilicon layer. Between memory cell transistors MT located within the same memory column MP, the semiconductor layer 31 is disposed continuously without separation. Therefore, the channels formed in each of the two memory cell transistors MT share a portion of the memory column MP.

[0096] As described above, the semiconductor layer 31 is continuous between two opposing memory cell transistors MT. Therefore, the channels formed in each of the two opposing memory cell transistors MT share a portion of the memory pillar MP. Specifically, Figure 7 and Figure 8 In this configuration, the left and right memory cell transistors MT, which are facing each other, share a portion of a memory pillar MP with the channel formed in the first memory cell and the channel formed in the second memory cell. Here, "two channels sharing a portion of a memory pillar MP" means that the two channels are formed on the same memory pillar MP, and a portion of the two channels overlaps. In one embodiment, this configuration is sometimes referred to as "two memory cell transistors MT sharing a channel" or "two memory cell transistors MT facing each other."

[0097] An insulating layer 32 is disposed around the semiconductor layer 31 and functions as a gate insulating film for the memory cell transistor MT. The insulating layer 32 is formed, for example, using a laminated structure of silicon oxide and silicon nitride films. An insulating layer 33 is disposed around the semiconductor layer 31 and functions as a charge storage layer for the memory cell transistor MT. The insulating layer 33 is formed, for example, using a silicon nitride film. An insulating layer 34 is disposed around the insulating layer 33 and functions as a block insulating film for the memory cell transistor MT. The insulating layer 34 is formed, for example, using a silicon oxide film. An insulating layer 37 is embedded within the slit SLT2, excluding the memory pillar MP portion. The insulating layer 37 is formed, for example, using a silicon oxide film. The insulating layers 33 of the left and right memory cell transistors MT, facing each other, are connected, for example, by an insulating layer 33 containing a silicon nitride film.

[0098] In the first embodiment, an AlO layer 35 is provided around the memory pillar MP, for example. A barrier metal layer 36 is provided around the AlO layer 35, for example. The barrier metal layer 36 is formed using a TiN film, for example. A wiring layer 11, which functions as a word line WL, is provided around the barrier metal layer 36. The wiring layer 11 is formed using a tungsten film, for example.

[0099] Therefore, the position of one memory column MP on the Z-axis includes two memory cell transistors MT and MT, or two selection transistors ST1 and ST2 along the Y direction.

[0100] <Example 2>

[0101] Figure 9 It means Figure 7 The diagram showing an example of a change in the memory cell transistor is an illustration. Figure 5 A diagram of the C1-C2 cut-off end face of the memory cell transistor. Figure 10 It means Figure 9 The diagram shows the E1-E2 cut-off end face of the memory cell transistor. Figure 9 and Figure 10 This is a cut-off end-face view of a region containing two memory cell transistors MT. In the second example, the charge storage layer included in the memory cell transistor MT is a conductive film. The second example of the memory cell transistor in one embodiment is not limited to... Figure 10 and Figure 11 The structure shown. Figure 10 and Figure 11 In the description, sometimes the terms "and" are omitted. Figures 1-9 Description of identical or similar structures.

[0102] like Figure 10 and Figure 11As shown, the memory cylinder MP includes insulating layers 48 and 43, a semiconductor layer 40, an insulating layer 41, a conductive layer 42, and insulating layers 46a-46c disposed along the Z direction. The insulating layer 48 is formed, for example, using a silicon oxide film. The semiconductor layer 40 is disposed to surround the insulating layer 48. The semiconductor layer 40 functions as a channel region for forming the memory cell transistor MT. The semiconductor layer 40 is formed, for example, using a polysilicon layer. The semiconductor layer 40 and... Figure 8 Similarly, in the first example of the memory column MP shown, the memory cell transistors MT located within the same memory column MP are arranged continuously without separation.

[0103] An insulating layer 41 is disposed around the semiconductor layer 40, serving as a gate insulating film for each memory cell transistor MT. The insulating layer 41... Figure 10 The XY plane shown is divided into two regions. The insulating layer 41 of the two regions each functions as the gate insulating film of two memory cell transistors MT within the same memory pillar MP. The insulating layer 41 is formed, for example, using a laminated structure of silicon oxide film and silicon nitride film.

[0104] A conductive layer 42 is disposed around an insulating layer 41 and is separated into two regions along the Y direction by an insulating layer 43. Each of the two separated conductive layers 42 functions as a charge storage layer for the two memory cell transistors MT. The conductive layer 42 is formed, for example, using a polysilicon layer.

[0105] The insulating layer 43 is formed, for example, using a silicon oxide film. Around the conductive layer 42, insulating layers 46a, 46b, and 46c are sequentially disposed from near to far from the conductive layer 42. Insulating layers 46a and 46c are formed, for example, using silicon oxide films, and insulating layer 46b is formed, for example, using a silicon nitride film. Insulating layers 46a, 46b, and 46c function as block insulating films for the memory cell transistor MT. Insulating layers 46a, 46b, and 46c are separated into two regions along the Y direction. An insulating layer 43 is disposed between the two separated regions of insulating layer 46c. Furthermore, the insulating layer 43 is embedded within the slit SLT2. The insulating layer 43 is formed, for example, using a silicon oxide film.

[0106] In the second example of this embodiment, an AlO layer 45 is provided around the memory cylinder MP, for example. A barrier metal layer 47 is provided around the AlO layer 45, for example. The barrier metal layer 47 is formed using a TiN film, for example. A wiring layer 11, which functions as a word line WL, is provided around the barrier metal layer 47. Similar to the first example of the memory cylinder MP of this embodiment, the wiring layer 11 of the second example of the memory cylinder MP of this embodiment is formed using a film made of tungsten, for example.

[0107] In the second example of the memory column MP in this embodiment, similar to the first example, one memory column MP, located on the Z-axis, includes two memory cell transistors MT and MT, or two select transistors ST1 and ST2, along the Y-direction. Furthermore, an insulating layer is provided between adjacent memory cell transistors in the Z-direction (not shown in the figure). Through this insulating layer and insulating layers 43 and 46, the conductive layer 42 is insulated between the individual memory cell transistors.

[0108] Figure 11 This is an equivalent circuit diagram of the memory columns (two adjacent NAND strings) of the semiconductor memory device 1 according to this embodiment. The equivalent circuit diagram of the memory columns in this embodiment is not limited to... Figure 11 The equivalent circuit diagram is shown. Figure 11 In the description, sometimes the terms "and" are omitted. Figures 1-10 Description of identical or similar structures.

[0109] like Figure 11 As shown, two NAND strings 50e and 50o are formed in one memory column MP. NAND strings 50e and 50o each have a select transistor ST1, dummy transistors DT0 and DT1, memory cell transistors MT0 to MT7, dummy transistors DT2 and DT3, and a select transistor ST2 connected in series. NAND strings 50e and 50o are arranged in a mutually opposing (opposite) manner. Therefore, the select transistor ST1, dummy transistors DT0 and DT1, memory cell transistors MT0 to MT7, dummy transistors DT2 and DT3, and select transistor ST2 included in NAND string 50e are arranged in a one-to-one opposing (opposite) manner as those included in NAND string 50o. Specifically, the select transistor ST1 included in NAND string 50e is configured opposite to the select transistor ST1 included in NAND string 50o; the dummy transistors DT0 and DT1 included in NAND string 50e are configured one-to-one opposite to the dummy transistors DT0 and DT1 included in NAND string 50o; the memory cell transistors MT0 to MT7 included in NAND string 50e are configured one-to-one opposite to the memory cell transistors MT0 to MT7 included in NAND string 50o; the dummy transistors DT2 and DT3 included in NAND string 50e are configured one-to-one opposite to the dummy transistors DT2 and DT3 included in NAND string 50o; and the select transistor ST2 included in NAND string 50e is configured opposite to the select transistor ST2 included in NAND string 50o.

[0110] The following description primarily focuses on the memory column MP (e.g., the first memory column). Figure 4 MP4) and the second memory column MP adjacent to the first memory column MP (e.g. Figure 4 Examples of the two memory columns MP0).

[0111] The select transistor ST1 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP is connected to the common select gate line SGD0, for example. The select transistor ST1 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP is connected to the select gate line SGD1, for example. The dummy transistors DT2 and DT3 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP are connected to the common dummy word lines WLDDe0 and WLDDe1, respectively. The dummy transistors DT2 and DT3 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP are connected to the common dummy word lines WLDDo0 and WLDDo1, respectively. The memory cell transistors MT0 to MT7 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP are connected to the common word lines WLe0 to WLe7, respectively. The memory cell transistors MT0 to MT7 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP are respectively connected to the common word lines WLo0 to WLo7. The dummy transistors DT0 and DT1 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP are respectively connected to the common dummy word lines WLDSe0 and WLDSe1. The dummy transistors DT0 and DT1 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP are respectively connected to the common dummy word lines WLDSo0 and WLDSo1. The select transistor ST2 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP is, for example, connected to the even-numbered select gate line SGSe. The select transistor ST2 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP is, for example, connected to the odd-numbered select gate line SGSo.

[0112] As described above, the select transistor ST1, dummy transistors DT2 and DT3, memory cell transistors MT0-7, dummy transistors DT0 and DT1, and select transistor ST2 included in NAND string 50e correspond to the select transistor ST1, dummy transistors DT2 and DT3, memory cell transistors MT0-7, dummy transistors DT0 and DT1, and select transistor ST2 included in NAND string 50o. In the two opposing transistors, the sources are electrically connected to each other, and the drains are electrically connected to each other. Specifically, in NAND strings 50e and 50o, the sources and drains of opposing select transistors ST1 are electrically connected to each other; the sources and drains of opposing dummy transistors DT3 and DT2 are electrically connected to each other; the sources and drains of opposing memory cell transistors MT0-7 are electrically connected to each other; the sources and drains of opposing dummy transistors DT1 and DT0 are electrically connected to each other; and the sources and drains of opposing select transistors ST2 are electrically connected to each other. This is because the channels formed in the opposing transistors share a portion of the memory column MP.

[0113] Two NAND strings 50e and 50o within the same memory cylinder MP are connected to the same bit line BL and the same source line SL.

[0114] use Figure 3 and Figure 4 The selection gate line SGD is explained below. When any one of the selection gate lines SGD0 to SGD3 is selected, a voltage is supplied to one wiring layer 10-0 to 10-3 corresponding to each selection gate line to turn on the selection transistor ST1. For example, when wiring layer 10-1 is selected, the eight selection transistors ST1 located in memory pillars MP0, MP1, MP4, MP5, MP8, MP9, MP12, and MP13 are turned on. This selects the eight memory cell transistors MT belonging to those memory pillars. In other words, one page is formed by these eight memory cell transistors MT. The operation when wiring layers other than wiring layer 10-1 are selected is the same as above, so the explanation is omitted.

[0115] In this embodiment, the writing method for the memory cell transistor MT is, for example, TLC. Multiple memory cell transistors MT using the TLC method form eight threshold distributions (write levels). These eight threshold distributions are, for example, named in ascending order of threshold voltage as "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level. Each of the "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level is assigned a different 3-bit data.

[0116] The semiconductor memory device 1 of this embodiment repeatedly executes a programming cycle during the write operation. The programming cycle includes, for example, a programming operation and a verification operation. The programming operation is as follows: by injecting electrons into the charge storage layer of the selected memory cell transistor MT, the threshold voltage of the selected memory cell transistor MT is increased. Alternatively, the programming operation is as follows: by preventing the injection of electrons into the charge storage layer, the threshold voltage of the selected memory cell transistor MT is maintained. The verification operation is as follows: after the programming operation, a verification voltage is used for reading to confirm whether the threshold voltage of the selected memory cell transistor MT has reached a target level. Once the threshold voltage of the selected memory cell transistor MT reaches the target level, it is set to disable writing.

[0117] In the semiconductor memory device 1 of this embodiment, the threshold voltage of the selected memory cell transistor MT is raised to the target level by repeatedly executing the programming cycle that includes programming and verification operations as described above.

[0118] Electrons stored in the charge storage layer can sometimes be stored in an unstable state. Therefore, sometimes, starting from the end of the programming operation, electrons stored in the charge storage layer of the memory cell transistor MT may leak out over time. If electrons leak out of the charge storage layer, the threshold voltage of the memory cell transistor MT will decrease. Therefore, to address the possibility of the threshold voltage of the memory cell transistor decreasing over time, a read voltage lower than the verification voltage is used during the read operation after the write operation is completed. The read operation may also include a verification operation.

[0119] Figure 12 and Figure 13 This diagram illustrates the electrical connections of the sequencer 24, voltage generation circuit 27, driver group 28, line decoder 29, and select gate line SGD or word line WL in this embodiment. The electrical connections of the sequencer 24, voltage generation circuit 27, driver group 28, line decoder 29, and select gate line SGD or word line WL in this embodiment are not limited to... Figure 12 face shown. Figure 12 and Figure 13 In the description, sometimes the terms "and" are omitted. Figures 1 to 11 Description of similar or identical configurations. The circuit including sequencer 24, voltage generation circuit 27, driver group 28 and line decoder 29 is an example of a control circuit.

[0120] like Figure 12 As shown, wiring layer 11, which functions as the even-number line WLe, can be connected to the even-side driver 28A, and wiring layer 11, which functions as the odd-number line WLo, can be electrically connected to the odd-side driver 28B. As described above, the even-side driver 28A and the odd-side driver 28B are included in driver assembly 28. Driver assembly 28 is electrically connected to voltage generation circuit 27. Figure 12 and Figure 13 As shown, even-side driver 28A and odd-side driver 28B can also generate various voltages using the voltage supplied from voltage generation circuit 27. Furthermore, even-side driver 28A can supply the generated voltage to the even-numbered lines WLe of each block BLK via line decoder 29A. Additionally, odd-side driver 28B can supply the generated voltage to the odd-numbered lines WLo of each block BLK via line decoder 29B. Line decoders 29A and 29B are included in line decoder 29.

[0121] like Figure 13 As shown and as described above, the sequencer 24 can control the driver group 28 and other devices to perform various actions such as writing and reading.

[0122] Figure 14 This is a schematic diagram illustrating the electrical connection between the even-side driver 28A and the line decoder 29A in this embodiment.

[0123] On the even-numbered side driver 28A, signal lines SGe0, SGe1, SGe2, CGDe0, CGDe1, CGDe2, CGDe3, and signal lines CGe0…CGe7 (which are signal lines CGe) are connected. Furthermore, regarding signal lines CGe, for example, the number of connected signal lines CGe is the same as the number of even-numbered lines WL arranged in the Z direction within block BLK.

[0124] Signal line SGe0 is connected to the even-numbered select gate line SGSe in each block BLK via transistor TR_SGe0. Transistor TR_SGe0 functions as a switch, used by the block decoder 29A1 to turn the signal from signal line SGe0 on or off.

[0125] Signal lines CGDe0 and CGDe1 are connected to the even-numbered dummy word lines WLDSe0 and WLDSe1 in each block BLK via transistors TR_CGDe0 and TR_CGDe1. Transistors TR_CGDe0 and TR_CGDe1 function as switches, used by the block decoder 29A1 to turn the signals from signal lines CGDe0 and CGDe1 on or off.

[0126] Signal lines CGe0…CGe7 are connected to even-numbered lines WLe0…WLe7 in each block BLK via transistors TR_CGe0…TR_CGe7. Transistor TR_CGe0…TR_CGe7 functions as a switch, used by block decoder 29A1 to turn the signal from signal lines CGe0…CGe7 on or off.

[0127] Signal lines CGDe2 and CGDe3 are connected to the even-numbered dummy word lines WLDDe0 and WLDDe1 in each block BLK via transistors TR_CGDe2 and TR_CGDe3. Transistors TR_CGDe2 and TR_CGDe3 function as switches, which are used to turn the signals from signal lines CGDe2 and CGDe3 on or off via the block decoder 29A1.

[0128] Signal line SGe1 is connected to the select gate line SGD0 in each block BLK via transistor TR_SGe1. Transistor TR_SGe1 functions as a switch, used to turn the signal from signal line SGe1 on or off via block decoder 29A1.

[0129] Signal line SGe2 is connected to the select gate line SGDe2 in each block BLK via transistor TR_SGe2. Transistor TR_SGe2 functions as a switch, which is used to turn the signal from signal line SGe2 on or off via block decoder 29A1.

[0130] Figure 15 This is a schematic diagram illustrating the electrical connection between the odd-side driver 28B and the line decoder 29B in this embodiment.

[0131] On the odd-numbered side driver 28, signal lines SGo0, SGo1, SGo2, CGDo0, CGDo1, CGDo2, CGDo3, and signal lines CGo0…CGo7 (which are signal lines CGo) are connected. Furthermore, regarding signal lines CGo, for example, the number of connected signal lines CGo is the same as the number of odd-numbered lines WL configured in the Z direction within block BLK.

[0132] Signal line SGo0 is connected to the odd-numbered select gate line SGSo in each block BLK via transistor TR_SGo0. Transistor TR_SGo0 functions as a switch, used by block decoder 29B1 to turn the signal from signal line SGo0 on or off.

[0133] Signal lines CGDo0 and CGDo1 are connected to the odd-numbered dummy word lines WDLSo0 and WLDSo1 in each block BLK via transistors TR_CGDo0 and TR_CGDo1. Transistors TR_CGDo0 and TR_CGDo1 function as switches, used by the block decoder 29B1 to turn the signals from signal lines CGDo0 and CGDo1 on or off.

[0134] Signal lines CGo0…CGo7 are connected to the odd-numbered lines WLo0…WLo7 in each block BLK via transistors TR_CGo0…TR_CGo7. Transistor TR_CGo0…TR_CGo7 functions as a switch, used by block decoder 29B1 to turn the signal from signal lines CGo0…CGo7 on or off.

[0135] Signal lines CGDo2 and CGDo3 are connected to the odd-numbered dummy word lines WLDDo0 and WLDDo1 in each block BLK via transistors TR_CGDo2 and TR_CGDo3. Transistors TR_CGDo2 and TR_CGDo3 function as switches, which are used to turn the signals from signal lines CGDo2 and CGDo3 on or off via the block decoder 29B1.

[0136] Signal line SGo1 is connected to the select gate line SGD1 in each block BLK via transistor TR_SGo1. Transistor TR_SGo1 functions as a switch, used to turn the signal from signal line SGo1 on or off via block decoder 29B1.

[0137] Signal line SGo2 is connected to the select gate line SGD3 in each block BLK via transistor TR_SGo2. Transistor TR_SGo1 functions as a switch, used to turn the signal from signal line SGo2 on or off via block decoder 29B1.

[0138] Figure 16 This is a schematic diagram illustrating the electrical connection between the voltage generation circuit 27 and the even-side driver 28A in this embodiment.

[0139] The voltages Vpgm, Vpass, VSGD1, and VSGD2, described later, are generated, for example, by the first charge pump circuit 27A, the second charge pump circuit 27B, the third charge pump circuit 27C, and the fourth charge pump circuit 27D within the voltage generation circuit 27, respectively. Furthermore, Vpgm, Vpass, VSGD1, and VSGD2 are stored by the first regulator circuit 28A1, the second regulator circuit 28A2, the third regulator circuit 28A3, and the fourth regulator circuit 28A4 within the even-numbered-side driver 28A, respectively. Subsequently, Vpgm, Vpass, VSGD1, and VSGD2 are appropriately summed and supplied to CGe0…CGe7.

[0140] Figure 17 This is a schematic diagram illustrating the electrical connection between the voltage generation circuit 27 and the odd-side driver 28B in this embodiment.

[0141] Vpgm, Vpass, VSGD1, and VSGD2 are stored by the first regulator circuit 28B1, the second regulator circuit 28B2, the third regulator circuit 28B3, and the fourth regulator circuit 28B4 within the odd-side driver 28B, respectively. Subsequently, Vpgm, Vpass, VSGD1, and VSGD2 are appropriately summed and supplied to signal lines CGo0…CGo7.

[0142] Figure 18 This is a schematic diagram illustrating a method for applying voltage to a selection transistor ST and a memory cell transistor MT in a semiconductor memory device according to a first comparative embodiment.

[0143] Here, we examine a semiconductor memory device with two NAND strings 50e and 50o within a single memory column MP. This semiconductor memory device does not contain a dummy transistor DT.

[0144] Figure 18 The diagram shows two memory cylinders (MPs), each with two NAND strings 50e and 50o. Here, the gate of the select transistor ST1 for each NAND string 50e in each memory cylinder (MP) is connected to a common select gate line SGD, and the gate of the select transistor ST1 for each NAND string 50o in each memory cylinder (MP) is also connected to a common select gate line SGD. Furthermore, the gate of the cell transistor MT7 for each NAND string 50e in each memory cylinder (MP) is connected to a common word line WL7e, and the gate of the cell transistor MT7 for each NAND string 50o in each memory cylinder (MP) is connected to a common word line WL7o. Similarly, the gate of the cell transistor MT6 for each NAND string 50e in each memory cylinder (MP) is connected to a common word line WL6e, and the gate of the cell transistor MT6 for each NAND string 50o in each memory cylinder (MP) is connected to a common word line WL6o.

[0145] Here, we examine the NAND string 50e connected to the bit line BL, which is subjected to 0 V. In other words, we examine the NAND string 50e connected to the "selected bit line BL". In this case, VSGD is applied to the gate of the selection transistor ST1 from the select gate line SGD, and 0 V is applied to the drain (or source) of the selection transistor ST1 from the bit line BL. As a result, the selection transistor ST1 is turned on. VSGD is a voltage higher than VSS. VSGD is, for example, 2.5 V. VSS is, for example, ground voltage. VSS is, for example, 0 V. However, VSGD and VSS are not particularly limited to these. In addition, Vpgm is applied to the gate of the memory cell transistor MT7 from the word line WLe7. Vpgm is, for example, 20 V. As a result, the memory cell transistor MT7 is subjected to a high electric field and "0" data is written to it. On the other hand, Vpass is applied to the gate of the memory cell transistor MT6 from the word line WLe6. Vpass is, for example, 10 V. Therefore, the memory cell transistor MT6 is not subjected to a high electric field and no data is written to it. Vpass is also applied to the memory cell transistors MT5 to MT0 from word lines WLe5 to WLe0 respectively. Figure 18 Not shown in the diagram. Memory cell transistors MT5 through MT0 also do not write data. In other words, in the NAND string 50e connected to the "selected bit line BL", only the memory cell transistor MT7 corresponding to the selected word line WLe7 is written with "0" data.

[0146] Next, consider the NAND string 50e connected to the bit line BL to which VDDSA is applied. In other words, consider the NAND string 50e connected to the "non-select bit line BL". In this case, VSGD is applied to the gate of the select transistor ST1 from the select gate line SGD, and VDDSA is applied to the drain (or source) of the select transistor ST1 from the bit line BL. As a result, the select transistor ST1 is turned off. That is, when a voltage VSGD is applied to the selected common select gate line SGD, VDDSA is the voltage that turns the select transistor ST1 off. Conversely, the voltage VSGD is the voltage that turns the select transistor ST1 on or off according to the voltage applied to the bit line BL. VDDSA is, for example, 2.5 V. However, VDDSA is not particularly limited to this. As described above, the NAND string 50e in each memory cylinder MP is connected to the common select gate line SGD, the common word line WLe7, and the common word line WLe6. Therefore, in the NAND string 50e connected to the "non-select bit line BL", the gates of the select transistor ST1, the memory cell transistor MT7, and the memory cell transistor MT6 are also subjected to VSGD, Vpgm, and Vpass, respectively. Here, for the NAND string 50e connected to the non-select bit line BL which is subjected to VDDSA, the select transistor ST1 is required to be turned off. However, the memory cell transistor MT7 is adjacent to the select transistor ST1. When a relatively high voltage, such as Vpgm, is applied to the gate of the memory cell transistor MT7 adjacent to the select transistor ST1, the potential of the channel in the select transistor ST1 of the NAND string 50e, closer to the memory cell transistor MT7, may sometimes rise transitionally to Vpgm. In this case, the select transistor ST1 of the NAND string 50e connected to the "non-select bit line BL" may not be able to be turned off smoothly due to the voltage withstand limit of the select transistor ST1. Furthermore, the channel potential of the select transistor ST1 may decrease due to GIDL (Gate-Induced Drain Leakage), potentially causing erroneous writes to the memory cell transistor MT connected to the NAND string 50e on the "non-select bit line BL". In other words, when writing to the memory cell transistor MT7 connected to the topmost word line (WLe7) in the NAND string 50e on the "selected bit line BL", the select transistor ST1 and the corresponding memory cell transistor MT7 connected to the word line (WLe7) in the NAND string 50e on the "non-select bit line BL" may malfunction unexpectedly.

[0147] Figure 19This is a schematic diagram illustrating a method for applying voltage to the select transistor and the memory cell transistor in the semiconductor memory device of the second comparative embodiment. Here, a semiconductor memory device in which two NAND strings 50e and 50o are disposed within a single memory column MP is examined. A bit line BL, to which 0 V is applied, is connected to the two NAND strings 50e and 50o disposed within the same memory column MP. A bit line BL, to which VDDSA is applied, is also connected to the two NAND strings 50e and 50o disposed within the same memory column MP. Furthermore, in each NAND string 50e and 50o, dummy transistors DT2 and DT3 are disposed between the select transistor ST1 and the memory cell transistor MT7.

[0148] The following example illustrates the process: In each memory cylinder MP, data is written to the memory cell transistor MT7 of the NAND string 50e corresponding to the selected word line WLe7. First, consider the NAND string 50e connected to the bit line BL, which is applied with 0 V. VSGD is applied to the gate of the select transistor ST1 from the select gate line SGD, thus turning on the select transistor ST1. Data is written by applying Vpgm to the memory cell transistor MT7 from the selected word line WLe7 in this state. Additionally, Vpass is applied to the gate of the dummy transistor DT2, and VSGD is applied to the gate of the dummy transistor DT3. Here, for example, Vpgm > Vpass > VSGD > 0 V. Figure 18 Unlike the previous example, a dummy transistor DT3 is disposed adjacent to the selection transistor ST1. A VSGD is applied to the gate of the dummy transistor DT3 adjacent to the selection transistor ST1. Therefore, in the second comparative embodiment, the potential of the channel of the selection transistor ST1 near the dummy transistor DT3 is less likely to become high. This suppresses the occurrence of GIDL. Furthermore, because a Vpass is applied to the gate of the dummy transistor DT2 adjacent to the dummy transistor DT3, the potential change between the selection transistor ST1 and the memory cell transistor MT7 is gradual. This prevents the selection transistor ST1 from being subjected to a voltage exceeding its withstand voltage limit.

[0149] Next, we examine the NAND string 50e connected to bit line BL, where VDDSA is applied. A voltage VSGD is also applied to the gate of the select transistor ST1 of the NAND string 50e connected to bit line BL, where VDDSA is applied. Additionally, Vpgm is applied to the memory cell transistor MT7. However, Vpass is applied to the gate of the dummy transistor DT2, and VSGD is applied to the gate of the dummy transistor DT3. Therefore, similar to the NAND string 50e connected to bit line BL, where 0 V is applied, GIDL can be suppressed. Furthermore, it is possible to prevent the select transistor ST1 from being subjected to a voltage exceeding its withstand voltage limit.

[0150] Figure 20 This is a schematic diagram illustrating the method of applying voltage to the select transistor ST and the memory cell transistor MT of the semiconductor memory device according to this embodiment. In the first and second comparative embodiments, the following situation was considered: the same voltage was applied to the gate of the dummy transistors DT2 and DT3 in NAND string 50e and NAND string 50o. However, in this embodiment, different voltages are applied to the dummy transistors DT2 and DT3 in NAND string 50e and NAND string 50o.

[0151] Figure 20 In the schematic shown in (a), bit line BL is applied with 0 V. VSGD is applied to the gate of the select transistor ST1 of NAND string 50e from the select gate line SGD (an example of the first select gate line). 0 V is applied to the gate of the select transistor ST1 of NAND string 50o using the select gate line SGD (an example of the second select gate line SGD). VSGD is applied to the gate of the dummy transistor DT3 of NAND string 50e from the dummy word line (an example of the topmost first dummy word line). VSGD / 2 is applied to the gate of the dummy transistor DT3 of NAND string 50o from the dummy word line (an example of the topmost second dummy word line). Vpass is applied to the gate of the dummy transistor DT2 of NAND string 50e from the dummy word line (an example of the bottommost first dummy word line). VSGD is applied to the gate of the dummy transistor DT2 of NAND string 50o from the dummy word line (an example of the bottommost second dummy word line). Vpgm is applied to the gate of the memory cell transistor MT7 of NAND string 50e from the word line (an example of the topmost first word line). Vpass is applied to the gate of the memory cell transistor MT7 of NAND string 50o from the word line (an example of the topmost second word line).

[0152] In other words, in the NAND string 50o that is not being written to, the gate voltage of the dummy transistor DT3 is VSGD / 2, which is higher than... Figure 19 The situation shown (VSGD) becomes even lower. Therefore, the potential of the channel of the select transistor ST1 in the NAND string 50o that is not being written to is lower than that of the dummy transistor DT3. Figure 19 The second comparative embodiment is further miniaturized. Therefore, GIDL occurrence can be suppressed more reliably in NAND strings 50o that are not intended for writing. In addition, it is possible to more reliably prevent the select transistor ST1 from being subjected to a voltage exceeding its withstand voltage limit. As a result, a semiconductor memory device with improved reliability can be provided.

[0153] Figure 20In the schematic diagram shown in (b), 0 V is applied to the gate of the selection transistor ST of NAND string 50e using the select gate line SGD (an example of the third select gate line). Additionally, 0 V is applied to the gate of the selection transistor ST of NAND string 50o using the select gate line SGD (an example of the fourth select gate line). Furthermore, Figure 20 (b) The selection transistor ST1 of the NAND string 50e shown is... Figure 20 (a) shows that the select transistor ST1 of the NAND string 50e is connected to different select gate lines. That is, Figure 20 (a) shows the NAND string 50e and Figure 20 (b) shows NAND strings 50e belonging to different string components. Additionally, Figure 20 (b) The selection transistor ST1 of the NAND string 50o shown is... Figure 20 (a) shows that the select transistor ST1 of the NAND string 50o is connected to different select gate lines. That is, Figure 20 (a) shows the NAND string 50o and Figure 20 (b) shows NAND strings 50o belonging to different string components. Other aspects are similar to... Figure 20 The schematic diagram shown in (a) is the same. In this case, the voltage applied to the gate of the dummy transistor DT3 of the NAND string 50o that is not being written to is also VSGD / 2. Therefore, the potential of the channel of the select transistor ST1 in the NAND string 50o that is not being written to is the same as that of the dummy transistor DT3. Figure 19 The second comparative implementation is further miniaturized. Therefore, GIDL occurrence can be suppressed more reliably in NAND strings 50o that are not intended for writing. In addition, it is possible to more reliably prevent the select transistor ST1 from being subjected to a voltage exceeding its withstand voltage limit. Therefore, a semiconductor memory device with improved reliability can be provided.

[0154] Figure 20 In the schematic diagram shown in (c), VDDSA is applied to the bit line BL. Figure 20 (c) The selection transistor ST1 of the NAND string 50e shown is... Figure 20 (a) shows that the select transistor ST1 of the NAND string 50e is connected to the common select gate line (the first select gate line). That is, Figure 20 (a) shows the NAND string 50e and Figure 20 (c) shows NAND string 50e belonging to the same string component. Additionally, Figure 20 (c) The selection transistor ST1 of the NAND string 50o shown is... Figure 20(a) The select transistor ST1 of the NAND string 50o shown is connected to the common select gate line (the second select gate line). That is, Figure 20 (a) shows the NAND string 50o and Figure 20 (c) shows NAND string 50o belonging to the same string component. Therefore, except for the voltage of bit line BL, the others are the same as... Figure 20 The schematic diagram shown in (a) is the same. In this case, the voltage applied to the gate of the dummy transistor DT3 of the NAND string 50o that is not being written to is also VSGD / 2. Therefore, the potential of the channel of the select transistor ST1 in the NAND string 50o that is not being written to is the same as that of the dummy transistor DT3. Figure 19 The second comparative implementation is further miniaturized. Therefore, GIDL occurrence can be suppressed more reliably in NAND strings 50o that are not intended for writing. In addition, it is possible to more reliably prevent the select transistor ST1 from being subjected to a voltage exceeding its withstand voltage limit. Therefore, a semiconductor memory device with improved reliability can be provided.

[0155] Figure 20 In the schematic diagram shown in (d), VDDSA is applied to the bit line BL. Figure 20 (d) shows the selection transistor ST1 of the NAND string 50e. Figure 20 (b) The select transistor ST1 of the NAND string 50e shown is connected to the common select gate line (the third select gate line). That is, Figure 20 (b) shows the NAND string 50e and Figure 20 (d) shows NAND string 50e belonging to the same string component. Additionally, Figure 20 (d) shows the selection transistor ST1 of the NAND string 50o. Figure 20 (b) The select transistor ST1 of the NAND string 50o shown is connected to the common select gate line (the 4th select gate line). That is, Figure 20 (b) The NAND string 50o shown is Figure 20 (d) shows NAND string 50o belonging to the same string component. Therefore, except for the voltage of bit line BL, the others are the same as... Figure 20 The schematic diagram shown in (b) is the same. In this case, the voltage applied to the gate of the dummy transistor DT3 of the NAND string 50o that is not being written to is also VSGD / 2. Therefore, the potential of the channel of the select transistor ST1 in the NAND string 50o that is not being written to is the same as that of the dummy transistor DT3. Figure 19The second comparative implementation is further miniaturized. Therefore, GIDL occurrence can be suppressed more reliably in NAND strings 50o that are not intended for writing. In addition, it is possible to more reliably prevent the select transistor ST1 from being subjected to a voltage exceeding its withstand voltage limit. Therefore, a semiconductor memory device with improved reliability can be provided.

[0156] Figure 21 This diagram schematically illustrates the voltage applied to the select transistors within the memory pillar MP (two adjacent NAND strings) via the select gate line, and the voltage applied to the memory cell transistors within the memory pillar via the word line and dummy word line in a semiconductor memory device according to a comparative embodiment. Here, it is assumed that... Figure 5 The memory cell transistor MT7 with NAND string 50e of select gate line SGD0 in the memory column MP3 shown is the write target.

[0157] First, assume that between time t1 and t2, the voltage of the selected gate line SGD0 (SGDe sel), dummy word line WLDDe1, dummy word line WLDDe0, selected gate line SGD2 (SGDe usel), selected gate line SGD1 and selected gate line SGD3 (SGDousel), selected gate line SGSe, selected gate line SGSo, word line WLe7 (WLe sel), word lines WLe0 to WLe6 (WLeusel), WLo0 to WLo7 (WLo usel), dummy word line WLDDe0, dummy word line WLDDe1, bit line BL1 (Inhibit BL), and bit line BL0 (Program BL) is VSS.

[0158] At time t2, a precharge voltage VSGPCH is applied to the select gate line SGD0 (SGDe sel), dummy word lines WLDDe1, WLDDo1, select gate line SGD2 (SGDe usel), select gate line SGD1, and select gate line SGD3 (SGDo usel). Additionally, a precharge voltage VCHPCH is applied to word lines WLe7 (WLe sel), WLe0 to WLe6 (WLe usel), WLo0 to WLo7 (WLousel), dummy word lines WLDDe0, and WLDDo0. The precharge voltages VSGPCH and VCHPCH are, for example, higher than VSS.

[0159] At time t3, VDDSA is applied to bit line BL1 (Inhibit BL).

[0160] At time t4, the precharge voltage VSGPCH applied to the select gate line SGD0 (SGDe sel), dummy word line WLDDe1, dummy word line WLDDo1, select gate line SGD2 (SGDe usel), select gate line SGD1, and select gate line SGD3 (SGDo usel) is restored to VSS. Additionally, the precharge voltage VCHPCH applied to word line WLe7 (WLe sel), word lines WLe0 to WLe6 (WLeusel), WLo0 to WLo7 (WLo usel), dummy word line WLDDe0, and dummy word line WLDDo0 is restored to VSS.

[0161] At time t5, VSG is applied to the select gate line SGD0 (SGDe sel), dummy word line WLDDe1, and dummy word line WLDDo1. Additionally, Vpass is applied to word line WLe7 (WLe sel), word lines WLe0 to WLe6 (WLe usel), WLo0 to WLo7 (WLousel), dummy word line WLDDe0, and dummy word line WLDDo0. Then, at time t6, Vpgm is applied to word line WLe7 (WLesel).

[0162] At time t7, VSS is applied to the select gate line SGD0 (SGDe sel), dummy word line WLDDe1, dummy word line WLDDo1, word line WLe7 (WLe sel), word lines WLe0 to WLe6 (WLe usel), WLo0 to WLo7 (WLo usel), dummy word line WLDDe0, and dummy word line WLDDo0.

[0163] exist Figure 21 In the illustrated embodiment, as described above, the memory cell transistor MT7 of the NAND string 50e in memory column MP3, which has a select gate line SGD0, becomes the write target. On the other hand, Vpgm is also applied to the gates of the memory cell transistor MT7 of the NAND string 50e in memory columns MP0, MP1, and MP2. However, they are not the write targets.

[0164] Figure 22 This diagram schematically illustrates the voltage applied to the select transistors within the memory pillars (two adjacent NAND strings) via the select gate line, and the voltage applied to the memory cell transistors within the memory pillars via the word line and dummy word line in the semiconductor memory device of this embodiment. Here, it is assumed that the voltage applied to the dummy word line WLDDe1 is different from the voltage applied to the dummy word line WLDDo1. Furthermore, it is assumed that the voltage applied to the dummy word line WLDDe0 is different from the voltage applied to the dummy word line WLDDo0.

[0165] The voltage applied to dummy word lines WLDDe1 and WLLDe0 is related to... Figure 21 The same applies to the semiconductor memory device shown. On the other hand, the dummy word line WLDDo1 is applied at time t5 with a voltage lower than VSG / 2. Additionally, the dummy word line WLDDo0 is applied at time t5 with a voltage lower than Vpass. Therefore, GIDL occurrence can be more reliably suppressed in NAND strings 50o that are not intended for writing. Furthermore, it is more reliable to prevent the select transistor ST1 from being applied a voltage exceeding its withstand voltage limit. Thus, a semiconductor memory device with improved reliability can be provided.

[0166] (Second Implementation)

[0167] Figure 23 This diagram schematically illustrates the voltage applied to the selection transistor via the selection gate line and the voltage applied to the memory cell transistors within the memory cylinder via the word line and dummy word line in the semiconductor memory device of this embodiment. This embodiment illustrates the operation of the semiconductor memory device when the memory cell transistor MT connected to word lines other than the uppermost word line WL (WLe7) becomes the target of a write operation. Specifically, it illustrates the operation of the memory cell transistor MT1 connected to the word line WLe1 of the NAND string 50e within the memory cylinder MP3 when it becomes the target of a write operation. Furthermore, Figure 23 The voltage recorded corresponds to the voltage applied at time t6.

[0168] Apply VSG to the dummy word line WLDDo1. Apply Vpass / 2 to the dummy word lines WLDDe1, WLDDe0, and WLDDo1. Apply Vpgm to WLe1. On the other hand, apply Vpass to word lines WLe0, WLe2 to WLe7, and WLo0 to WLo7.

[0169] In the semiconductor memory device of this embodiment, the voltages applied to the dummy word lines WLDDo1 and WLDDe1 are different. Furthermore, the voltages applied to the dummy word lines WLDDo0 and WLDDe0 are also different. Therefore, GIDL occurrence can be more reliably suppressed in NAND strings 50o that are not intended for writing. Additionally, it is more reliable to prevent the select transistor ST1 from being subjected to voltages exceeding its withstand voltage limit. Thus, a semiconductor memory device with improved reliability can be provided.

[0170] (Third Implementation)

[0171] Figure 24This diagram schematically illustrates the voltage applied to the selection transistor via the selection gate line and the voltage applied to the memory cell transistors within the memory cylinder via the word line and dummy word line in the semiconductor memory device of this embodiment. This embodiment illustrates the operation of the semiconductor memory device when the memory cell transistor MT7 connected to the uppermost word line WL (WLe7) becomes the write target. Specifically, it illustrates the operation of the memory cell transistor MT7 connected to the word line WLe7 of the NAND string 50e within the memory cylinder MP3 when it becomes the write target. Furthermore, Figure 24 The voltage recorded corresponds to the voltage applied at time t6.

[0172] Apply (1 / 3) Vpass to dummy word line WLDDo1. Apply (2 / 3) Vpass to dummy word line WLDDo0. Apply (1 / 2) (Vpass) to dummy word line WLDDe1. Apply Vpass to dummy word line WLDDe0. Apply Vpgm to WLe7. On the other hand, apply Vpass to word lines WLe0~WLe6 and WLo0~WLo7.

[0173] In the semiconductor memory device of this embodiment, the voltages applied to the dummy word lines WLDDo1 and WLDDe1 are different. Furthermore, the voltages applied to the dummy word lines WLDDo0 and WLDDe0 are also different. Therefore, GIDL occurrence can be more reliably suppressed in NAND strings 50o that are not intended for writing. Additionally, it is more reliable to prevent the select transistor ST1 from being subjected to voltages exceeding its withstand voltage limit. Thus, a semiconductor memory device with improved reliability can be provided.

[0174] (Fourth implementation)

[0175] Figure 25 This diagram schematically illustrates the voltage applied to the select transistor via the select gate line and the voltage applied to the memory cell transistors within the memory cylinder via the word line and dummy word lines, according to the semiconductor memory device of this embodiment. This embodiment illustrates the operation of the semiconductor memory device when the memory cell transistor MT7 connected to the uppermost word line WL (WLe7) becomes the write target. Specifically, it illustrates the operation when the memory cell transistor MT7 connected to the word line WLe7 of the NAND string 50e within the memory cylinder MP3 becomes the write target. Furthermore, in the semiconductor memory device of this embodiment, each NAND string 50 is provided with four dummy word lines WLD. Additionally, Figure 25 The voltage recorded corresponds to the voltage applied at time t6.

[0176] Apply (1 / 5) Vpass to dummy word line WLDDo3. Apply (2 / 5) Vpass to dummy word line WLDDo2. Apply (3 / 5) Vpass to dummy word line WLDDo1. Apply (4 / 5) Vpass to dummy word line WLDDo0. Apply (2 / 4) (Vpass) to dummy word line WLDDe3. Apply (2 / 4) (Vpass) to dummy word line WLDDe2. Apply (3 / 4) (Vpass) to dummy word line WLDDe1. Apply (4 / 4) (Vpass) to dummy word line WLDDe0.

[0177] In the semiconductor memory device of this embodiment, the occurrence of GIDL can be more reliably suppressed in NAND string 50o that is not intended for writing. Furthermore, it is more reliable to prevent the select transistor ST1 from being subjected to a voltage exceeding its withstand voltage limit. Therefore, a semiconductor memory device with improved reliability can be provided.

[0178] Several embodiments and examples of the present invention have been described, but these embodiments and examples are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the invention as set forth in the claims and its equivalents.

[0179] [Explanation of Symbols]

[0180] 1 Semiconductor memory device

[0181] 2 Memory Controller

[0182] 3 Memory System

[0183] 10 wiring layers

[0184] 11 wiring layers

[0185] 12 wiring layers

[0186] 13 source line layers

[0187] 16-Contact Plug

[0188] 17 Contact Plug

[0189] 18 metal wiring layers

[0190] 19 Contact plugs

[0191] 20 metal wiring layers

[0192] 21-cell array

[0193] 22 Input / Output Circuit

[0194] 23 Logic Control Circuit

[0195] 24 Sequencer

[0196] 25 registers

[0197] 26 Ready / Busy Control Circuit

[0198] 27 Voltage Generation Circuit

[0199] 27A First Charge Pump Circuit

[0200] 27B Second Charge Pump Circuit

[0201] 27C Third Charge Pump Circuit

[0202] 27D 4th charge pump circuit

[0203] 28 drive group

[0204] 28A Even-Side Driver

[0205] 28A1 First Regulator Circuit

[0206] 28A2 Second Regulator Circuit

[0207] 28A3 Third Regulator Circuit

[0208] 28A4 Fourth Regulator Circuit

[0209] 28B Odd-Side Driver

[0210] 28B1 First Regulator Circuit

[0211] 28B2 Second Regulator Circuit

[0212] 28B3 Third Regulator Circuit

[0213] 28B4 Fourth Regulator Circuit

[0214] 29-line decoder

[0215] 29A line decoder

[0216] 29B line decoder

[0217] 30 insulation layers

[0218] 31 semiconductor layers

[0219] 32 insulation layers

[0220] 33 Insulation Layer

[0221] 34 insulation layers

[0222] 35AlO layer

[0223] 36 barrier metal layers

[0224] 37 insulation layers

[0225] 40 semiconductor layers

[0226] 41 Insulation Layer

[0227] 42 conductive layers

[0228] 43 Insulation Layer

[0229] 45AlO layer

[0230] 46 insulation layers

[0231] 47 Barrier Metal Layer

[0232] 48 insulation layers

[0233] 50NAND string

[0234] 70 Sensing Amplifier

[0235] 71 Input / Output Pads

[0236] 72 Logic Control Pads

[0237] BL bit line

[0238] BLK Block

[0239] C binding capacity

[0240] CEn chip enable signal

[0241] CG signal line

[0242] CLE instruction latch enable signal

[0243] CMD commands

[0244] DAT data

[0245] DQ signal

[0246] SU string component

[0247] MP Same memory column

[0248] MT memory cell transistor

[0249] R resistance ingredients

[0250] REn reads the enable signal

[0251] SG signal line

[0252] SGD Select Gate Line

[0253] SGS Select Gate Line

[0254] SL source line

[0255] SL slit

[0256] ST select transistor

[0257] STS Status Information

[0258] WLD Dummy Word Line

[0259] WLe even number line

[0260] WLoqi Number Line

[0261] WPn write protection signal.

Claims

1. A semiconductor memory device comprising: Substrate; Memory pillars extending from the substrate in a first direction; Multiple first word lines are provided on the substrate, separated from the substrate in the first direction, arranged parallel to the substrate surface of the substrate, and facing the first side of the memory pillar; Multiple second word lines are disposed on the substrate, separated from the substrate in the first direction, parallel to the substrate surface of the substrate, and at the same position as the multiple first word lines in the first direction, facing the second side of the memory pillar; Multiple first dummy word lines are disposed above the first word lines, parallel to the substrate surface of the substrate, and facing the first side of the memory pillar; Multiple second dummy word lines are disposed above the second word lines, parallel to the substrate surface of the substrate, and are positioned in the first direction at the same position as the multiple first dummy word lines, facing the second side of the memory pillar; The first selected gate line is disposed above the first dummy word line, parallel to the substrate surface of the substrate, and facing the first side of the memory pillar; The second select gate line is disposed above the second dummy word line, parallel to the substrate surface of the substrate, and is positioned in the first direction at the same location as the first select gate line, facing the second side of the memory pillar; and The driver is capable of supplying voltage; During a write operation, the driver... A first voltage is applied to the first selected gate line. A second voltage lower than the first voltage is applied to the second selected gate line. A third voltage, greater than the first voltage, is applied to the topmost first dummy word line. A fourth voltage, different from the third voltage and higher than the second voltage, is applied to the topmost second dummy word line. A fifth voltage, greater than the third voltage, is applied to the first dummy word line at the bottom layer. A sixth voltage, which is different from the fifth voltage and is higher than the fourth voltage, is applied to the second dummy word line at the bottom layer.

2. The semiconductor memory device according to claim 1, wherein The third voltage is equal to the sixth voltage.

3. The semiconductor memory device according to claim 1, wherein... The driver during the write operation A seventh voltage, higher than the fifth voltage and higher than the sixth voltage, is applied to the topmost first word line. An eighth voltage, lower than the seventh voltage but higher than the sixth voltage, is applied to the topmost second word line. The first voltage is equal to the third voltage and the sixth voltage. The fifth voltage is equal to the eighth voltage.

4. The semiconductor memory device according to claim 1, wherein The driver during the write operation A seventh voltage, higher than the fifth voltage and higher than the sixth voltage, is applied to the topmost first word line. An eighth voltage, lower than the seventh voltage but higher than the sixth voltage, is applied to the topmost second word line. The first dummy word line and the second dummy word line are each provided with n layers. n is a natural number greater than 2. The fourth voltage is 1 / (n+1) of the eighth voltage. The sixth voltage is n / (n+1) of the eighth voltage.

5. The semiconductor memory device according to claim 1, wherein... The driver during the write operation A seventh voltage, higher than the fifth voltage and higher than the sixth voltage, is applied to the topmost first word line. An eighth voltage, higher than the fifth voltage and higher than the sixth voltage, is applied to the topmost second word line. The first voltage is equal to the fourth voltage. The third voltage is equal to the fifth voltage and the sixth voltage.

6. The semiconductor memory device according to claim 5, wherein The driver during the write operation A ninth voltage, higher than the seventh voltage, is applied to the first word lines other than the topmost first word line. A 10th voltage is applied to the second word lines other than the topmost second word line, which is higher than the fifth voltage, higher than the sixth voltage, and lower than the ninth voltage.

Images