A programming method and a testing method of a flash memory chip

Abstract

The application discloses a programming method and a testing method of a flash memory chip. The flash memory chip comprises a flash memory array, and the flash memory array comprises a memory and computing unit. The programming method comprises at least two memory and computing programming processes. One memory and computing programming process comprises the following steps: writing a first programming voltage into all to-be-programmed memory and computing units; reading a current of each to-be-programmed memory and computing unit; calculating a first difference between the current of each to-be-programmed memory and computing unit and a corresponding first target current; taking the to-be-programmed memory and computing unit with a first difference greater than or equal to a first preset value as a to-be-programmed memory and computing unit in a next memory and computing programming process, and taking a second programming voltage as a first programming voltage in the next memory and computing programming process; and the second programming voltage is a voltage adjusted on the basis of the first programming voltage in the current memory and computing programming process. The technical scheme of the embodiment of the application reduces the interference on the programmed memory and computing unit.

Description

Technical Field

[0001] This invention relates to the field of flash memory technology, and in particular to a programming method and a testing method for a flash memory chip. Background Technology

[0002] Flash memory is a type of non-volatile memory that retains data even when power is off, and it has a wide range of applications. Flash memory chips include flash memory arrays. Figure 1 This is a schematic diagram of the structure of a flash memory array in the prior art, such as... Figure 1 As shown, the flash array contains multiple flash cells. Flash cell 10 is, for example, a target cell. The target cell is a flash cell that has been programmed or erased. The cells adjacent to the flash cell 10 in the same row are flash cells 11 and flash cells 12.

[0003] Figure 2 It is a working curve diagram of the storage unit, such as Figure 2 As shown, the horizontal axis represents the control gate voltage, and the vertical axis represents the current of the memory cell. The operating current of the memory cell is relatively small, at the nanoampere level. Therefore, when the state of the memory cell changes, such as when the floating gate potential changes slightly during memory programming, the rate of change of the current of the memory cell is relatively large. That is, the ratio of the change in the current of the memory cell to the current before programming is relatively large.

[0004] If flash memory cells 11 and 12 are in-memory computing units, when the flash array is programmed randomly, there is a possibility that flash memory cell 10 will finish programming first, followed by programming of flash memory cells 11 and 12. Conversely, when the flash array is programmed sequentially, flash memory cell 10 will finish programming first, followed by programming of flash memory cell 12. Since flash memory cells 11 and 12 are adjacent to the target cell, and the coupling capacitance between the floating gates of flash memory cells 11 and 12 and the floating gate of the target cell is relatively large, significant changes in the current (floating gate potential) of flash memory cells 11 and 12 will lead to significant changes in the current of the target cell. Therefore, both programming methods will interfere with the programmed flash memory cells. Summary of the Invention

[0005] This invention provides a programming method and a testing method for a flash memory chip to reduce interference to the programmed flash memory cells.

[0006] According to one aspect of the present invention, a method for programming a flash memory chip is provided, the flash memory chip including a flash memory array, the flash memory array including in-memory computing units; the programming method includes at least two in-memory programming processes, one of the in-memory programming processes including:

[0007] Write the first programming voltage to all memory cells to be programmed;

[0008] Read the current current of each of the programmed memory units;

[0009] Calculate the first difference between the current current of each of the programmed memory units and the corresponding first target current;

[0010] The memory cell to be programmed with the first difference being greater than or equal to the first preset value is used as the memory cell to be programmed in the next memory programming process, and the second programming voltage is used as the first programming voltage in the next memory programming process; wherein, the second programming voltage is the voltage after the first programming voltage is adjusted in the current memory programming process.

[0011] Optionally, during one programming process, if the first programming voltage reaches a voltage limit, the second programming voltage is equal to the first programming voltage.

[0012] Optionally, during one programming process, if the first programming voltage is less than the voltage limit, then the second programming voltage is greater than the first programming voltage.

[0013] Optionally, the flash memory array further includes storage units; the programming method further includes storing the programming process;

[0014] Before executing the in-memory programming process, the storage programming process is executed; the storage programming process includes:

[0015] A third programming voltage is written to the memory cell to be programmed, so that each of the memory cells to be programmed reaches the corresponding second target current.

[0016] Optionally, after performing the memory programming procedure and before performing the memory-based programming procedure, the method further includes:

[0017] The memory cells to be programmed are initially programmed so that the current of each memory cell reaches its initial programming current.

[0018] Optionally, the initial programming operation performed on the memory-to-computer unit to bring the current of each memory-to-computer unit to its initial programming current includes:

[0019] According to the address order of the memory cells to be programmed, the current of the memory cells to be programmed is programmed to the corresponding initial programming current in sequence.

[0020] Optionally, the initial programming operation of the in-memory computing unit to be programmed includes at least two initial programming processes, one of which includes:

[0021] Write the first initial programming voltage to all the programmed memory units;

[0022] Read the current initial current of each of the programmed memory units;

[0023] Calculate the second difference between the current initial current and the initial programming current of each of the programmed memory cells;

[0024] The programmable memory unit whose second difference is greater than or equal to the first preset value is used as the programmable memory unit for the next initial programming process, and the second initial programming voltage is used as the first initial programming voltage for the next initial programming process; wherein, the second initial programming voltage is the voltage after the first initial programming voltage is adjusted in the current initial programming process.

[0025] Optionally, before performing the in-memory programming process, the following steps are also included:

[0026] An erase operation is performed on the flash memory array.

[0027] According to another aspect of the present invention, a testing method for a flash memory chip is provided, the testing method comprising the programming method described in any embodiment of the present invention, and the testing method further comprising:

[0028] If the number of executions of the in-memory programming process is less than a preset number, and the first difference between the current current of all in-memory computing units to be programmed and the corresponding first target current is less than the first preset value, then the flash memory chip is qualified.

[0029] Optionally, the test method further includes:

[0030] If the number of executions of the in-memory programming process is greater than or equal to the preset number, and there is still a first difference between the current current of the in-memory unit to be programmed and the corresponding first target current that is greater than or equal to the first preset value, then the flash memory chip is unqualified.

[0031] The technical solution of this invention provides a flash memory chip programming method that includes at least two in-memory programming processes. By cyclically executing at least two in-memory programming processes, the programming voltage written to the in-memory cell to be programmed is gradually increased, or the programming time for writing the programming voltage to the in-memory cell to be programmed is gradually increased. This allows each in-memory cell to gradually reach its corresponding first target current. In each in-memory programming process, the difference between the first programming voltage written to the in-memory cell to be programmed and the first programming voltage written in the previous process is small, thereby minimizing the change in current (floating gate potential) of each in-memory cell to be programmed. Therefore, the interference of the in-memory cell to be programmed with the first programming voltage written later on to the in-memory cell to be programmed with the first programming voltage written later is smaller, thus reducing interference to the already programmed in-memory cells and improving programming accuracy.

[0032] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the structure of a flash memory array in the prior art;

[0035] Figure 2 This is a graph showing the working curves of the storage unit;

[0036] Figure 3 This is a flowchart of a flash memory chip programming method provided in an embodiment of the present invention;

[0037] Figure 4 This is a flowchart of another flash memory chip programming method provided in an embodiment of the present invention;

[0038] Figure 5 This is a flowchart of another flash memory chip programming method provided in an embodiment of the present invention;

[0039] Figure 6 This is a flowchart of another flash memory chip programming method provided in an embodiment of the present invention;

[0040] Figure 7 This is a flowchart of a testing method for a flash memory chip provided in an embodiment of the present invention;

[0041] Figure 8 This is a flowchart of another testing method for flash memory chips provided in an embodiment of the present invention. Detailed Implementation

[0042] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0043] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the term "comprising" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0044] Figure 3 This is a flowchart illustrating a programming method for a flash memory chip according to an embodiment of the present invention. The flash memory chip includes a flash memory array, and the flash memory array includes in-memory computing units. The programming method includes at least two in-memory programming processes. Figure 3 As shown, the programming methods for flash memory chips include:

[0045] S101. Write the first programming voltage to all memory cells to be programmed.

[0046] The flash memory array comprises multiple flash memory cells arranged in an array. These flash memory cells can function as either in-memory computing units or storage units. The in-memory computing unit to be programmed is the in-memory computing unit that needs to be programmed.

[0047] Specifically, according to the address order of the memory-to-memory units to be programmed, a first programming voltage is written sequentially to each memory-to-memory unit, thereby writing the first programming voltage to all memory-to-memory units. The difference between the first programming voltage written in each memory-to-memory programming process and the first programming voltage written in the previous memory-to-memory programming process is small, resulting in a small change in the current (potential of the floating gate) of each memory-to-memory unit to be programmed, thus reducing the coupling voltage between adjacent memory-to-memory units. Therefore, memory-to-memory units to which the first programming voltage is written later have less interference with memory-to-memory units to which the first programming voltage has already been written, thereby reducing interference to already programmed memory-to-memory units.

[0048] S102, Read the current current of each memory cell to be programmed.

[0049] Specifically, the current current of the in-memory computing unit to be programmed refers to the current channel current of the in-memory computing unit to be programmed. By reading the current current of each in-memory computing unit to be programmed, it can be determined whether each in-memory computing unit to be programmed has reached its corresponding first target current.

[0050] S103. Calculate the first difference between the current current of each memory cell to be programmed and the corresponding first target current.

[0051] Specifically, the first target current for each programmable memory cell can be the same or different, meaning some programmable memory cells may reach their corresponding first target current first. The first difference between the current of each programmable memory cell and its corresponding first target current is subtracted, and the magnitude of this first difference determines whether the programmable memory cell has reached its corresponding first target current.

[0052] S104. Determine whether all the first differences are less than the first preset value. If yes, end; otherwise, proceed to step S105.

[0053] Specifically, when all the first differences are less than the first preset value, it indicates that all the memory-based computing units to be programmed have reached the target state of programming, and programming ends. If not all the first differences are less than the first preset value, that is, there are memory-based computing units to be programmed with a first difference greater than or equal to the first preset value, then programming needs to continue for the memory-based computing units to be programmed with a first difference greater than or equal to the first preset value.

[0054] S105. The programmable storage unit with a first difference greater than or equal to a first preset value is selected as the programmable storage unit for the next storage programming process, and the second programming voltage is selected as the first programming voltage for the next storage programming process; wherein, the second programming voltage is the voltage after the first programming voltage is adjusted in the current storage programming process.

[0055] Specifically, the first programming voltage in the current in-memory programming process is adjusted, for example, by increasing the first programming voltage, decreasing the first programming voltage, or maintaining the first programming voltage, to obtain a second programming voltage. The in-memory unit to be programmed with a first difference greater than or equal to a first preset value is selected as the in-memory unit to be programmed in the next in-memory programming process, and the second programming voltage is used as the first programming voltage in the next in-memory programming process. Then, the process returns to continue executing step S101 to enter the next in-memory programming process.

[0056] It should be noted that a single in-memory programming process includes steps S101 to S105. Through cyclic operation, after step S105 is executed, step S101 is returned to be executed, thus achieving at least two executions of the in-memory programming process. This allows each in-memory unit to be programmed to gradually reach its corresponding first target current. After each programming, the change in the current (potential of the floating gate) of the in-memory unit to be programmed is small. Therefore, the interference of the in-memory unit to be programmed with the first programming voltage written later on to the in-memory unit to be programmed with the first programming voltage written later is small, thereby reducing the interference to the programmed in-memory unit.

[0057] The technical solution of this embodiment describes a flash memory chip programming method that includes at least two in-memory programming processes. By cyclically executing at least two in-memory programming processes, the programming voltage written to the in-memory unit to be programmed is gradually increased, or the programming time for writing the programming voltage to the in-memory unit to be programmed is gradually increased, so that each in-memory unit to be programmed gradually reaches its corresponding first target current. In each in-memory programming process, the difference between the first programming voltage written to the in-memory unit to be programmed and the first programming voltage written in the previous process is small, thereby making the change in current (floating gate potential) of each in-memory unit to be programmed small. Therefore, the interference of the in-memory unit to be programmed with the first programming voltage written later on to the in-memory unit to be programmed with the first programming voltage written later is smaller, thereby reducing interference to the programmed in-memory units and improving programming accuracy.

[0058] Based on the above technical solution, optionally, during a programming process, if the first programming voltage reaches the voltage limit, the second programming voltage is equal to the first programming voltage.

[0059] Specifically, the voltage limit is, for example, the maximum programming voltage of the memory cell to be programmed. If the first programming voltage reaches the voltage limit, it cannot be increased further. The second programming voltage is equal to the first programming voltage, that is, the first programming voltage before adjustment is equal to the voltage after adjustment. By increasing the programming time, the memory cell to be programmed gradually reaches its corresponding first target current.

[0060] Optionally, during a programming process, if the first programming voltage is less than the voltage limit, then the second programming voltage is greater than the first programming voltage.

[0061] Specifically, if the first programming voltage is less than the voltage limit, the first programming voltage can be increased to obtain the second programming voltage, that is, the second programming voltage is greater than the first programming voltage, which makes it easier to control the memory cell to be programmed to reach its corresponding first target current.

[0062] In some other implementations, if the difference between the current of the memory-based computing unit to be programmed and its corresponding first target current is small after a memory-based programming process is completed, the first programming voltage of the previous memory-based programming process can be maintained, and the next memory-based programming process can be continued, increasing the programming time; if the difference between the current of the memory-based computing unit to be programmed and its corresponding first target current is large after a memory-based programming process is completed, the first programming voltage of the previous memory-based programming process can be increased, and the next memory-based programming process can be continued based on the increased first programming voltage, so that the memory-based computing unit to be programmed can reach its first target current more quickly.

[0063] Based on the above technical solutions, the flash memory array also includes storage cells, and the programming method includes a storage programming process. The storage programming process is performed before the computational programming process, thereby programming all flash memory cells that need to be programmed. The programming method including the storage programming process is described below, but is not limited thereto.

[0064] Figure 4 This is a flowchart of another flash memory chip programming method provided in an embodiment of the present invention. Optionally, refer to... Figure 4 The programming methods for flash memory chips include:

[0065] S201. Write a third programming voltage to the memory cell to be programmed so that each memory cell to be programmed reaches the corresponding second target current.

[0066] Specifically, before programming, the operating current of a memory cell is typically in the microamplitude range. When the state of a memory cell changes, the compute unit has not yet been programmed, and changes in the state of adjacent memory cells do not affect the target programmed compute state of the compute unit. Moreover, the operating current of the compute unit is relatively small, typically in the nanoamplitude range, so the impact of fine-tuning the programmed compute unit on the already programmed compute units is also minimal. Therefore, all memory cells to be programmed can be directly programmed to their corresponding second target current first, and then the compute units to be programmed can be fine-tuned, thereby enabling all flash memory cells that need to be programmed to reach the target state and completing the programming of all flash memory cells that need to be programmed.

[0067] S202. Write the first programming voltage to all memory cells to be programmed.

[0068] S203, Read the current current of each memory cell to be programmed.

[0069] S204. Calculate the first difference between the current current of each memory cell to be programmed and the corresponding first target current.

[0070] S205. Determine whether all the first differences are less than the first preset value. If yes, end; otherwise, proceed to step S206.

[0071] S206. The programmable storage unit whose first difference is greater than or equal to the first preset value is selected as the programmable storage unit for the next storage programming process, and the second programming voltage is selected as the first programming voltage for the next storage programming process. Then, the process returns to step S202. The second programming voltage is the voltage after the first programming voltage is adjusted in the current storage programming process.

[0072] The technical solution of this embodiment first executes a memory programming process, directly programming all memory cells to be programmed to their corresponding second target current, and then executes a memory computing programming process. This ensures that all flash memory cells requiring programming reach the target state, and also reduces programming time. Furthermore, when the state of a memory cell changes, the memory computing unit has not yet been programmed, and changes in the state of adjacent memory cells do not affect the target programming state of the memory computing unit. Moreover, the operating current of the memory computing unit is relatively small, typically in the nanoamplitude range, so the impact of fine-tuning the programming of the memory computing unit on the already programmed memory computing units is also minimal.

[0073] In another implementation, after performing the stored programming process and before performing the in-memory programming process, an initial programming operation can be performed on the in-memory units to be programmed. This ensures that the current of each in-memory unit reaches its corresponding initial programming current. Since the difference between the initial programming current of each in-memory unit and its corresponding first target current is small, performing the in-memory fine-tuning programming process after the current of the in-memory unit reaches its corresponding initial programming current can reduce current variations in each in-memory unit, thereby reducing interference to the already programmed in-memory units. The programming method involving initial programming operations is described below, but is not limited to it.

[0074] Figure 5 This is a flowchart of another flash memory chip programming method provided in an embodiment of the present invention. Optionally, refer to... Figure 5 The programming methods for flash memory chips include:

[0075] S301. Write a third programming voltage to the memory cell to be programmed so that each memory cell to be programmed reaches the corresponding second target current.

[0076] S302. Perform initial programming operations on the memory units to be programmed so that the current of each memory unit to be programmed reaches its initial programming current.

[0077] Specifically, the current of each in-memory unit to be programmed is programmed to its corresponding initial programming current. The initial programming current of each in-memory unit is greater than its corresponding first target current. After the current of a subsequently programmed in-memory unit reaches its initial programming current, the state changes in subsequent in-memory fine-tuning programming have a smaller impact on the state of already programmed in-memory units during the current in-memory programming process, thus reducing interference to already programmed in-memory units. Furthermore, the difference between the initial programming current of each in-memory unit and its corresponding first target current is small. Therefore, performing the in-memory programming process after the current of each in-memory unit reaches its corresponding initial programming current can reduce current changes in each in-memory unit, thereby reducing interference to already programmed in-memory units.

[0078] Furthermore, by ensuring that the current of all memory-in-memory units (MIMs) reaches their corresponding initial programming current, the programming time can be reduced. This reduces the time during which the programming voltage written by later-programmed MMIs interferes with the programming voltage of non-adjacent MMIs already programmed in the same row. Therefore, the programming method using this technical solution not only reduces the interference caused by the programming voltage written by later-programmed MMIs to adjacent MMIs already programmed, but also reduces the time during which non-adjacent MMIs already programmed interfere, further reducing interference with already programmed MMIs.

[0079] For example, such as Figure 1 As shown, in a single memory programming process, flash memory cell 10 is, for example, the memory cell to be programmed that first writes the first programming voltage, and flash memory cell 13 is the memory cell to be programmed that subsequently writes the first programming voltage. Flash memory cells 10 and 13 are located in the same row, but are not adjacent to each other. Since a row of flash memory cells shares one control gate line and one select gate line, when writing the first programming voltage to flash memory cell 13 after writing the first programming voltage to flash memory cell 10, the control gate voltage and select gate voltage of the entire row also need to be written, which may interfere with the already programmed flash memory cell 10. However, after the current of all memory cells to be programmed reaches the corresponding initial programming current, the memory programming time can be reduced, thereby reducing the interference time of flash memory cell 13 to flash memory cell 10, and thus reducing the interference with the already programmed memory cells.

[0080] S303: Write the first programming voltage to all memory cells to be programmed.

[0081] S304. Read the current current of each memory cell to be programmed.

[0082] S305. Calculate the first difference between the current current of each memory cell to be programmed and the corresponding first target current.

[0083] S306. Determine whether all the first differences are less than the first preset value. If yes, end; otherwise, proceed to step S307.

[0084] S307. The programmable storage unit whose first difference is greater than or equal to the first preset value is selected as the programmable storage unit for the next storage programming process, and the second programming voltage is selected as the first programming voltage for the next storage programming process. Then, the process returns to step S303. The second programming voltage is the voltage after the first programming voltage is adjusted in the current storage programming process.

[0085] The technical solution of this embodiment performs an initial programming operation before executing the memory programming process. This programm the current of all memory-based computing units to be programmed to the initial programming current. Since the difference between the initial programming current of each memory-based computing unit and its corresponding first target current is small, performing the memory programming process after the current of each unit reaches the corresponding initial programming current reduces current variations in each unit, thereby reducing interference with already programmed units. Furthermore, it reduces the time of the memory programming process, thus minimizing the time during which a later-programmed memory-based computing unit writes its programming voltage, interfering with non-adjacent memory-based computing units already programmed in the same row.

[0086] Based on the above technical solution, the initial programming operation of the memory cell to be programmed can be performed by directly programming the current of the memory cell to be programmed to the corresponding initial programming current, or by gradually programming the current of the memory cell to be programmed to the corresponding initial programming current. The two initial programming operations are described below, but are not limited thereto.

[0087] In one embodiment, optionally, S302, performing an initial programming operation on the memory-to-be-programmed units to bring the current of each memory-to-be-programmed unit to its initial programming current, includes:

[0088] According to the address order of the memory cells to be programmed, the current of the memory cells to be programmed is programmed to the corresponding initial programming current in sequence.

[0089] Specifically, following the address order of the memory-based computing units to be programmed, the current of the first unit is programmed to its corresponding initial programming current. Then, the next unit is programmed, and so on, until all units are programmed to their corresponding initial programming currents. The first unit to be programmed is, for example, the one with the smallest address value among those to be programmed, i.e., the one with the smallest row and column number. After the current of a later-programmed unit reaches its initial programming current, subsequent state changes in fine-tuning have minimal impact on the already programmed units. Therefore, even if the units are programmed sequentially, programming the current of one unit to its corresponding initial programming current before programming the next, it will not significantly affect the state of the already programmed units in subsequent fine-tuning.

[0090] In another embodiment, optionally, S302, performing an initial programming operation on the memory-to-computer unit to be programmed so that the current of each memory-to-computer unit reaches its initial programming current, includes:

[0091] Step a1: Write the first initial programming voltage to all memory cells to be programmed.

[0092] Specifically, according to the address order of the memory cells to be programmed, a first initial programming voltage is written to each memory cell sequentially, thereby writing the first initial programming voltage to all memory cells to be programmed. The difference between the first initial programming voltage written each time and the first initial programming voltage written in the previous time is small, thus resulting in a small change in the current (potential of the floating gate) of each memory cell to be programmed. Therefore, memory cells to be programmed with a later first initial programming voltage have less interference with memory cells to be programmed with a first initial programming voltage already written, thereby reducing interference to the already programmed memory cells.

[0093] Step a2: Read the current initial current of each memory cell to be programmed.

[0094] Specifically, the current initial current of the in-memory unit to be programmed refers to the current channel initial current of the in-memory unit to be programmed. By reading the current initial current of each in-memory unit to be programmed, it can be determined whether each in-memory unit to be programmed has reached its corresponding initial programming current.

[0095] Step a3: Calculate the second difference between the current initial current and the initial programming current of each memory cell to be programmed.

[0096] Specifically, the initial programming current for each programmable memory cell can be the same or different, meaning some cells may reach their initial programming current first. The second difference between the current initial current and the corresponding initial programming current of each programmable memory cell is calculated. The magnitude of this second difference determines whether the programmable memory cell has reached its initial programming current.

[0097] Step a4: Determine whether all second differences are less than the first preset value. If yes, end; otherwise, proceed to step a5.

[0098] Specifically, when all the second differences are less than the first preset value, it indicates that all the memory-based computing units to be programmed have reached the target initial state for programming, and the initial programming operation ends. If not all the second differences are less than the first preset value, that is, there are memory-based computing units to be programmed with second differences greater than or equal to the first preset value, then the initial programming of the memory-based computing units to be programmed with second differences greater than or equal to the first preset value needs to continue.

[0099] Step a5: Select the storage unit to be programmed with a second difference greater than or equal to the first preset value as the storage unit to be programmed in the next initial programming process, and use the second initial programming voltage as the first initial programming voltage in the next initial programming process, and return to execute step a1; wherein, the second initial programming voltage is the voltage after the first initial programming voltage is adjusted in the current initial programming process.

[0100] Specifically, the first initial programming voltage in the current initial programming process is adjusted, for example, by increasing, decreasing, or maintaining the first initial programming voltage, to obtain a second initial programming voltage. The memory cell to be programmed with a second difference greater than or equal to a first preset value is selected as the memory cell to be programmed in the next initial programming process, and the second initial programming voltage is used as the first initial programming voltage for the next initial programming process. The process then returns to step S101 to continue executing and enter the next initial programming process.

[0101] It should be noted that an initial programming process includes steps a1-a5. Through a loop, after executing step a5, the process returns to execute step a1, achieving at least two executions of the initial programming process. This ensures that each in-memory unit to be programmed gradually reaches its corresponding initial programming current, and the change in current (floating gate potential) of the in-memory unit after each programming is relatively small. Therefore, the interference of in-memory units that have already been programmed with the first initial programming voltage is smaller, thus reducing interference with already programmed in-memory units.

[0102] Figure 6 This is a flowchart of another flash memory chip programming method provided in an embodiment of the present invention. Optionally, refer to... Figure 6 The programming methods for flash memory chips include:

[0103] S401, Perform an erase operation on the flash memory array.

[0104] Specifically, an erase operation is first performed on the entire flash array, so that all flash cells are in an erased state, which can erase the voltage written in the last programming. Then, the computing and storage cells that need to be programmed are programmed, so that the state of the flash cells after programming is consistent with the target state, which helps to improve the programming effect.

[0105] S402. Write a third programming voltage to the memory cell to be programmed so that each memory cell to be programmed reaches the corresponding second target current.

[0106] S403: Write the first programming voltage to all memory cells to be programmed.

[0107] S404: Read the current current of each memory cell to be programmed.

[0108] S405. Calculate the first difference between the current current of each memory cell to be programmed and the corresponding first target current.

[0109] S406. Determine whether all the first differences are less than the first preset value. If yes, end; otherwise, proceed to step S407.

[0110] S407. The programmable storage unit whose first difference is greater than or equal to the first preset value is selected as the programmable storage unit for the next storage programming process, and the second programming voltage is selected as the first programming voltage for the next storage programming process. Then, the process returns to step S403. The second programming voltage is the voltage after the first programming voltage is adjusted in the current storage programming process.

[0111] The technical solution of this embodiment performs an erase operation, first performing an erase operation on the entire flash memory array, so that all flash memory cells are in an erased state, which can erase the voltage written in the last programming, and can ensure that the state of the flash memory cells after programming is consistent with the target state.

[0112] The technical solution of this invention also provides a method for testing flash memory chips, which includes the programming method for flash memory chips provided in any of the above embodiments. Figure 7 This is a flowchart of a testing method for a flash memory chip provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the testing methods for flash memory chips include:

[0113] S501. Write a third programming voltage to the memory cell to be programmed so that each memory cell to be programmed reaches the corresponding second target current.

[0114] S502: Write the first programming voltage to all memory cells to be programmed.

[0115] S503: Read the current current of each memory cell to be programmed.

[0116] S504. Calculate the first difference between the current current of each memory cell to be programmed and the corresponding first target current.

[0117] S505. Determine whether all the first differences are less than the first preset value. If yes, proceed to step S506; otherwise, proceed to step S507.

[0118] Specifically, if all the first differences are less than the first preset value, it indicates that all the memory cells to be programmed have reached the target programming state, and the flash memory chip is qualified, and it indicates that the programming method of performing at least two programming processes provided by the above implementation scheme is feasible.

[0119] S506. Confirm that the flash memory chip is qualified.

[0120] S507. Determine whether the number of times the stored-computer programming process has been executed is less than the preset number. If yes, proceed to step S508; otherwise, proceed to step S509.

[0121] Specifically, if not all first differences are less than the first preset value, meaning there are programmable memory cells with first differences greater than or equal to the first preset value, then programming needs to continue for these programmable memory cells. If the number of executions of the memory programming process is less than a preset number, then return to step S507, select the next programmable memory cell for the next memory programming process, determine the second programming voltage, and continue programming the programmable memory cells with first differences greater than or equal to the first preset value. If the number of executions of the memory programming process is greater than or equal to the preset number, and there are still programmable memory cells with first differences greater than or equal to the first preset value, then the flash memory chip is defective.

[0122] S508. The programmable storage unit whose first difference is greater than or equal to the first preset value is selected as the programmable storage unit for the next storage programming process, and the second programming voltage is selected as the first programming voltage for the next storage programming process. Then, the process returns to step S502. The second programming voltage is the voltage after the first programming voltage is adjusted in the current storage programming process.

[0123] S509. The flash memory chip is determined to be defective.

[0124] Specifically, if the number of times the in-memory programming process is executed is greater than or equal to the preset number, and there are still in-memory units to be programmed with a first difference greater than or equal to the first preset value, then the flash memory chip is unqualified.

[0125] The technical solution of this embodiment determines whether the flash memory chip is qualified by judging whether all the memory-to-be-programmed units can reach the corresponding first target current within a preset number of times. If all the memory-to-be-programmed units reach the corresponding first target current within the preset number of times, the flash memory chip is qualified, proving that the flash memory chip programming method that performs at least two programming processes in the above implementation scheme is feasible.

[0126] Figure 8 This is a flowchart of another testing method for a flash memory chip provided in an embodiment of the present invention, referred to [reference]. Figure 8 The testing methods for flash memory chips include:

[0127] S601. Write a third programming voltage to the memory cell to be programmed, so that each memory cell to be programmed reaches the corresponding second target current.

[0128] S602. Perform initial programming operations on the memory units to be programmed so that the current of each memory unit to be programmed reaches its initial programming current.

[0129] S603: Write the first programming voltage to all memory cells to be programmed.

[0130] S604: Read the current current of each memory cell to be programmed.

[0131] S605. Calculate the first difference between the current current of each memory cell to be programmed and the corresponding first target current.

[0132] S606. Determine whether all the first differences are less than the first preset value. If yes, proceed to step S607; otherwise, proceed to step S608.

[0133] Specifically, if all the first differences are less than the first preset value, it indicates that all the memory cells to be programmed have reached the target state of programming, and the flash memory chip is qualified. This also indicates that the programming method provided by the above implementation scheme, which involves performing an initial programming operation first and then performing at least two programming processes, is feasible.

[0134] S607. Confirm that the flash memory chip is qualified.

[0135] S608. Determine whether the number of times the stored-computer programming process has been executed is less than the preset number. If yes, proceed to step S609; otherwise, proceed to step S610.

[0136] S609. The programmable storage unit whose first difference is greater than or equal to the first preset value is selected as the programmable storage unit for the next storage programming process, and the second programming voltage is selected as the first programming voltage for the next storage programming process. Then, the process returns to step S603. The second programming voltage is the voltage after the first programming voltage is adjusted in the current storage programming process.

[0137] S610, The flash memory chip is determined to be defective.

[0138] The technical solution of this embodiment determines whether the flash memory chip is qualified by judging whether all the memory-to-be-programmed units can reach the corresponding first target current within a preset number of times. If all the memory-to-be-programmed units reach the corresponding first target current within a preset number of times, the flash memory chip is qualified, and this proves that the programming method in the above implementation scheme, which involves performing an initial programming operation first and then performing at least two programming processes, is feasible.

[0139] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0140] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for programming a flash memory chip, characterized in that, The flash memory chip includes a flash memory array, and the flash memory array includes a storage and computing unit; The programming method includes at least two in-memory programming processes, one of which includes: Write the first programming voltage to all memory cells to be programmed; Read the current current of each of the programmed memory units; Calculate the first difference between the current current of each of the programmed memory units and the corresponding first target current; The memory cell to be programmed with the first difference being greater than or equal to the first preset value is used as the memory cell to be programmed in the next memory programming process, and the second programming voltage is used as the first programming voltage in the next memory programming process; wherein, the second programming voltage is the voltage after the first programming voltage is adjusted in the current memory programming process; in one programming process, if the first programming voltage reaches the voltage limit, the second programming voltage is equal to the first programming voltage; in one programming process, if the first programming voltage is less than the voltage limit, the second programming voltage is greater than or equal to the first programming voltage.

2. The programming method according to claim 1, characterized in that, The flash memory array further includes storage units; the programming method further includes a storage programming process; The storage programming process is executed before the in-memory programming process is executed. The storage programming process includes: A third programming voltage is written to the memory cell to be programmed, so that each of the memory cells to be programmed reaches the corresponding second target current.

3. The programming method according to claim 2, characterized in that, After executing the memory programming procedure and before executing the memory computation procedure, the method further includes: The memory cells to be programmed are initially programmed so that the current of each memory cell reaches its initial programming current.

4. The programming method according to claim 3, characterized in that, The initial programming operation for each memory cell to be programmed, so that the current of each memory cell reaches its initial programming current, includes: According to the address order of the memory cells to be programmed, the current of the memory cells to be programmed is programmed to the corresponding initial programming current in sequence.

5. The programming method according to claim 4, characterized in that, The initial programming operation of the in-memory computing unit to be programmed includes at least two initial programming processes, one of which includes: Write the first initial programming voltage to all the programmed memory units; Read the current initial current of each of the programmed memory units; Calculate the second difference between the current initial current and the initial programming current of each of the programmed memory cells; The programmable memory unit whose second difference is greater than or equal to the first preset value is used as the programmable memory unit for the next initial programming process, and the second initial programming voltage is used as the first initial programming voltage for the next initial programming process; wherein, the second initial programming voltage is the voltage after the first initial programming voltage is adjusted in the current initial programming process.

6. The programming method according to claim 2 or 3, characterized in that, Before performing the in-memory programming process, the following is also included: An erase operation is performed on the flash memory array.

7. A testing method for a flash memory chip, characterized in that, The testing method includes the programming method according to any one of claims 1-6, and the testing method further includes: If the number of executions of the in-memory programming process is less than a preset number, and the first difference between the current current of all in-memory computing units to be programmed and the corresponding first target current is less than the first preset value, then the flash memory chip is qualified.

8. The test method according to claim 7, characterized in that, Also includes: If the number of executions of the in-memory programming process is greater than or equal to the preset number, and there is still a first difference between the current current of the in-memory unit to be programmed and the corresponding first target current that is greater than or equal to the first preset value, then the flash memory chip is unqualified.

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