Chip and method of manufacturing the same

Abstract

The application discloses a chip and a manufacturing method thereof. The method comprises the following steps: growing a first sacrificial layer on an original substrate, and growing an AlN insertion layer with a thickness of 0-100 nm on the first sacrificial layer; growing a second sacrificial layer on the AlN insertion layer, and growing an AlN buffer layer with a thickness of 0-100 nm on the second sacrificial layer, and growing a functional material layer on the AlN buffer layer to form a GaN wafer; bonding the GaN wafer and a first surface of a temporary carrier, and removing the first sacrificial layer, the AlN insertion layer, the second sacrificial layer and the original substrate; transferring the remaining material after the first sacrificial layer, the AlN insertion layer, the second sacrificial layer and the original substrate are removed to a target substrate, and removing the temporary carrier from the remaining material to form a GaN chip. Through the scheme of the application, the crystal quality of the GaN wafer and the heat dissipation capacity and output power of the GaN chip are improved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a chip and its manufacturing method. Background Technology

[0002] With the development of semiconductor technology, high electron mobility transistors (HEMTs) based on GaN materials have been widely used in the communication field due to their excellent power output capabilities. However, conventional GaN power devices have low output power density, reaching only -5W / mm². To overcome the problem of low output power density in GaN power devices, CN113270358A discloses a method for fabricating GaN chips. The method involves sequentially forming an Nb₂N sacrificial layer, a GaN insertion layer, a Ta₂N sacrificial layer, and a semiconductor layer on a SiC substrate to form a GaN wafer. Then, the Nb₂N and Ta₂N sacrificial layers are removed from the GaN wafer to remove the high thermal conductivity substrate, thereby forming a GaN chip and improving the output power of the GaN chip. However, due to the lattice mismatch between the SiC substrate and the semiconductor layer, although the introduction of the Nb2N / GaN / Ta2N sandwich structure has alleviated the lattice mismatch between the SiC substrate and the semiconductor layer, the mitigation effect is not significant. As a result, the output power of the formed GaN chip is only slightly improved. Therefore, a solution is urgently needed to significantly improve the output power of the GaN chip. Summary of the Invention

[0003] In view of this, the present invention proposes a chip and its fabrication method, which generates a functional material layer on a SiC substrate through a Nb2N, AlN, Ta2N, AlN stacked structure, thereby alleviating the lattice mismatch and thermal mismatch between the SiC substrate and the functional material layer generated on the upper layer, improving the crystal quality of the GaN wafer, and significantly improving the heat dissipation capability and output power of the GaN chip.

[0004] To achieve the above objectives, one aspect of the present invention provides a chip manufacturing method, specifically including the following steps:

[0005] A first sacrificial layer is grown on the original substrate, and an AlN insertion layer with a thickness of 0-100 nm is grown on the first sacrificial layer;

[0006] A second sacrificial layer is grown on the AlN insertion layer, and an AlN buffer layer with a thickness of 0-100 nm is grown on the second sacrificial layer. A functional material layer is grown on the AlN buffer layer to form a GaN wafer.

[0007] The first surfaces of the GaN wafer and the temporary carrier are bonded together, and the first sacrificial layer, the AlN insertion layer, the second sacrificial layer and the original substrate are removed.

[0008] The remaining material after removing the first sacrificial layer, the AlN insertion layer, the second sacrificial layer, and the original substrate is transferred to the target substrate, and the temporary wafer is removed from the remaining material to form a GaN chip, the GaN chip including the target substrate, the AlN buffer layer, and the functional material layer.

[0009] In some embodiments, growing a second sacrificial layer on the AlN insertion layer includes:

[0010] A second sacrificial layer with a thickness of 0-50 nm is grown on the AlN insertion layer.

[0011] In some implementations, the first sacrificial layer includes an Nb2N sacrificial layer; and the second sacrificial layer includes a Ta2N sacrificial layer.

[0012] In some embodiments, growing a functional material layer on the AlN buffer layer includes:

[0013] A high mobility layer is formed on the upper surface of the AlN buffer layer;

[0014] A barrier layer is formed on the upper surface of the high mobility layer;

[0015] A capping layer is formed on the upper surface of the barrier layer.

[0016] In some embodiments, the original substrate includes a SiC substrate.

[0017] In another aspect of this invention, a chip is also provided, manufactured based on the following method:

[0018] A first sacrificial layer is grown on the original substrate, and an AlN insertion layer with a thickness of 0-100 nm is grown on the first sacrificial layer;

[0019] A second sacrificial layer is grown on the AlN insertion layer, and an AlN buffer layer with a thickness of 0-100 nm is grown on the second sacrificial layer. A functional material layer is grown on the AlN buffer layer to form a GaN wafer.

[0020] The first surfaces of the GaN wafer and the temporary carrier are bonded together, and the first sacrificial layer, the AlN insertion layer, the second sacrificial layer and the original substrate are removed.

[0021] The remaining material after removing the first sacrificial layer, the AlN insertion layer, the second sacrificial layer, and the original substrate is transferred to the target substrate, and the temporary wafer is removed from the remaining material to form a GaN chip, the GaN chip including the target substrate, the AlN buffer layer, and the functional material layer.

[0022] In some embodiments, growing a second sacrificial layer on the AlN insertion layer includes:

[0023] A second sacrificial layer with a thickness of 0-50 nm is grown on the AlN insertion layer.

[0024] In some implementations, the first sacrificial layer includes an Nb2N sacrificial layer; and the second sacrificial layer includes a Ta2N sacrificial layer.

[0025] In some embodiments, growing a functional material layer on the AlN buffer layer includes:

[0026] A high mobility layer is formed on the upper surface of the AlN buffer layer;

[0027] A barrier layer is formed on the upper surface of the high mobility layer;

[0028] A capping layer is formed on the upper surface of the barrier layer.

[0029] In some embodiments, the original substrate includes a SiC substrate.

[0030] The present invention has at least the following beneficial technical effects: by generating a functional material layer on a SiC substrate through a Nb2N, AlN, Ta2N, AlN stacked structure, the lattice mismatch and thermal mismatch between the SiC substrate and the functional material layer generated on the upper layer are alleviated, the crystal quality of GaN wafers is improved, and the heat dissipation capability and output power of GaN chips are significantly improved. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0032] Figure 1 A flowchart of an embodiment of the chip fabrication method provided by the present invention;

[0033] Figure 2 A schematic diagram of the structure of a chip manufactured by the chip manufacturing method provided by the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0035] The following describes embodiments of this disclosure. However, it should be understood that the disclosed embodiments are merely examples, and other embodiments may take various alternative forms. The drawings are not necessarily drawn to scale; certain functions may be exaggerated or minimized to show detail of particular components. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art to use this application in various ways. As will be understood by those skilled in the art, various features shown and described with reference to any of the drawings may be combined with features shown in one or more other drawings to produce embodiments not explicitly shown or described. The combinations of features shown provide representative embodiments for typical applications. However, various combinations and modifications of features consistent with the teachings of this disclosure may be desirable for certain particular applications or implementations.

[0036] In this application, relational terms, such as "first" and "second," are used only to distinguish one entity or action from another, and do not necessarily require or imply any actual such relationship or order between such entities or actions. The term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not necessarily include only those elements, but may also include other elements not expressly listed or inherent to such a process, method, article, or apparatus. Without further constraints, an element preceded by "comprising" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element. The term "and / or," when used to enumerate two or more items, means that it may include any one of the listed items, or any combination of two or more of the listed items.

[0037] In the prior art, a "sandwich" structure sacrificial layer is introduced between the GaN functional material and the SiC substrate to peel the GaN device off the SiC substrate and transplant it onto other high thermal conductivity substrates, thereby achieving the transfer of GaN devices and improving the quality of GaN chips.

[0038] To further improve GaN chip quality and enable the stripping and transfer of GaN devices from SiC substrates to target substrates, a first aspect of this invention proposes an embodiment of a chip fabrication method. For example... Figure 1 As shown, it includes the following steps:

[0039] S10. Grow a first sacrificial layer on the original substrate, and grow an AlN insertion layer with a thickness of 0-100 nm on the first sacrificial layer;

[0040] S20. A second sacrificial layer is grown on the AlN insertion layer, and an AlN buffer layer with a thickness of 0-100 nm is grown on the second sacrificial layer, and a functional material layer is grown on the AlN buffer layer to form a GaN wafer.

[0041] S30. Bond the first side of the GaN wafer and the temporary carrier, and remove the first sacrificial layer, the AlN insertion layer, the second sacrificial layer and the original substrate;

[0042] S40. Transfer the remaining material after removing the first sacrificial layer, the AlN insertion layer, the second sacrificial layer and the original substrate to the target substrate, and remove the temporary wafer from the remaining material to form a GaN chip, the GaN chip including the target substrate, the AlN buffer layer and the functional material layer.

[0043] In one specific embodiment, combined with Figure 1 and Figure 2 The fabrication process of GaN chips is described below. The initial substrate is a substrate with high conductivity, including but not limited to SiC. A first sacrificial layer is grown on the initial substrate. An AlN insertion layer with a thickness of 0-100 nm is grown on the first sacrificial layer. A second sacrificial layer is grown on the AlN insertion layer. An AlN buffer layer with a thickness of 0-100 nm is grown on the second sacrificial layer. Finally, a functional material layer is grown on the AlN buffer layer to form a GaN wafer, hereinafter referred to as a GaN device. Using an AlN insertion layer, compared to traditional GaN insertion layers, can alleviate the lattice mismatch between the SiC substrate and the functional material layer, improving the quality of the GaN wafer. Simultaneously, the lattice matching between the AlN insertion layer and the AlN buffer layer facilitates the growth of a high-quality AlN buffer layer. The AlN buffer layer effectively alleviates the lattice and thermal mismatch between the SiC substrate and the functional material layer, achieving a higher quality GaN wafer. Next, the first surfaces of the GaN wafer and the temporary substrate are bonded together, and the first sacrificial layer, AlN insertion layer, second sacrificial layer, and original substrate are removed. The remaining material after removing the first sacrificial layer, AlN insertion layer, second sacrificial layer, and original substrate is transferred to the target substrate, and the temporary substrate is removed from the remaining material to form a GaN chip, as shown below. Figure 2 As shown, the GaN chip includes a target substrate, an AlN buffer layer, and a functional material layer, which enables the peeling of the manufactured GaN wafer from the original substrate to finally form a GaN chip. The AlN buffer layer alleviates the lattice mismatch and thermal mismatch between the target substrate and the functional material layer, thereby significantly improving the heat dissipation capability and output power of the GaN chip.

[0044] The present invention generates a functional material layer on a SiC substrate through a Nb2N, AlN, Ta2N, and AlN stacked structure, which alleviates the lattice mismatch and thermal mismatch between the SiC substrate and the functional material layer generated on top, improves the crystal quality of the GaN wafer, and enhances the heat dissipation capability and output power of the formed GaN chip.

[0045] In one specific embodiment, the first sacrificial layer includes an Nb2N sacrificial layer.

[0046] SiC (silicon carbide) material with hexagonal crystal structure symmetry was selected as the original substrate. A Nb2N sacrificial layer with a thickness of 0-50 nm was grown by thin film deposition. An AlN insertion layer with a thickness of 0-100 nm was then grown on the Nb2N sacrificial layer. By adding an AlN insertion layer between the Nb2N sacrificial layer and the Ta2N sacrificial layer, the lattice mismatch and thermal mismatch between the SiC substrate and the functional material layer generated on top were alleviated, thereby improving the crystal quality of the GaN wafer and thus improving the heat dissipation capability and output power of the GaN chip.

[0047] In some embodiments, growing a second sacrificial layer on the AlN insertion layer includes:

[0048] A second sacrificial layer with a thickness of 0-50 nm is grown on the AlN insertion layer.

[0049] In one specific embodiment, the first sacrificial layer includes a Ta2N sacrificial layer. A Ta2N sacrificial layer with a thickness of 0-50 nm is grown on the AlN insertion layer, and an AlN buffer layer with a thickness of 0-100 nm is grown on the Ta2N sacrificial layer. By adding an AlN insertion layer between the Nb2N and Ta2N sacrificial layers, the lattice and thermal mismatch between the SiC substrate and the upper functional material layer is alleviated, improving the crystal quality of the GaN wafer. The AlN buffer layer is formed on the Ta2N sacrificial layer. The AlN buffer layer facilitates the nucleation of the upper GaN material and further alleviates the lattice and thermal mismatch between SiC and GaN materials, further improving the crystal quality of the GaN wafer, thereby enhancing the heat dissipation capability and output power of the GaN chip.

[0050] In some implementations, the first sacrificial layer includes an Nb2N sacrificial layer; and the second sacrificial layer includes a Ta2N sacrificial layer.

[0051] In some embodiments, growing a functional material layer on the AlN buffer layer includes:

[0052] A high mobility layer is formed on the upper surface of the AlN buffer layer;

[0053] A barrier layer is formed on the upper surface of the high mobility layer;

[0054] A capping layer is formed on the upper surface of the barrier layer.

[0055] In some embodiments, the original substrate includes a SiC substrate.

[0056] In one specific embodiment, the original substrate includes, but is not limited to, SiC, and may also be Si, GaN, Sapphire, Diamond, Ga2O3, and AlN, etc.

[0057] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a chip manufactured using the following method:

[0058] A first sacrificial layer is grown on the original substrate, and an AlN insertion layer with a thickness of 0-100 nm is grown on the first sacrificial layer;

[0059] A second sacrificial layer is grown on the AlN insertion layer, and an AlN buffer layer with a thickness of 0-100 nm is grown on the second sacrificial layer. A functional material layer is grown on the AlN buffer layer to form a GaN wafer.

[0060] The first surfaces of the GaN wafer and the temporary carrier are bonded together, and the first sacrificial layer, the AlN insertion layer, the second sacrificial layer and the original substrate are removed.

[0061] The remaining material after removing the first sacrificial layer, the AlN insertion layer, the second sacrificial layer, and the original substrate is transferred to the target substrate, and the temporary wafer is removed from the remaining material to form a GaN chip, the GaN chip including the target substrate, the AlN buffer layer, and the functional material layer.

[0062] In some embodiments, growing a second sacrificial layer on the AlN insertion layer includes:

[0063] A second sacrificial layer with a thickness of 0-50 nm is grown on the AlN insertion layer.

[0064] In some implementations, the first sacrificial layer includes an Nb2N sacrificial layer; and the second sacrificial layer includes a Ta2N sacrificial layer.

[0065] In some embodiments, growing a functional material layer on the AlN buffer layer includes:

[0066] A high mobility layer is formed on the upper surface of the AlN buffer layer;

[0067] A barrier layer is formed on the upper surface of the high mobility layer;

[0068] A capping layer is formed on the upper surface of the barrier layer.

[0069] In some embodiments, the original substrate includes a SiC substrate.

Claims

1. A chip manufacturing method, characterized in that, include: An Nb2N sacrificial layer is grown on a SiC substrate, and an AlN insertion layer is grown on the Nb2N sacrificial layer; A Ta2N sacrificial layer is grown on the AlN insertion layer, an AlN buffer layer is grown on the Ta2N sacrificial layer, and a functional material layer is grown on the AlN buffer layer to form a GaN wafer. Growing the functional material layer on the AlN buffer layer includes: forming a high mobility layer on the upper surface of the AlN buffer layer; forming a barrier layer on the upper surface of the high mobility layer; and forming a capping layer on the upper surface of the barrier layer. The first surfaces of the GaN wafer and the temporary carrier are bonded together, and the Nb2N sacrificial layer, the AlN insertion layer, the Ta2N sacrificial layer and the SiC substrate are removed. The remaining material after removing the Nb2N sacrificial layer, the AlN insertion layer, the Ta2N sacrificial layer, and the SiC substrate is transferred to the target substrate, and the temporary wafer is removed from the remaining material to form a GaN chip, which is composed of a target substrate, an AlN buffer layer, and a functional material layer stacked sequentially.

2. A chip, characterized in that, It is made based on the method as described in claim 1.

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