Chip packaging method

Abstract

This invention provides a chip packaging method, the method comprising: bonding at least one chip to a first substrate and forming a first multi-layer wiring package on the chip; forming a second multi-layer wiring package on a second substrate according to the position of the chip on the first substrate; and connecting the first multi-layer wiring package and the second multi-layer wiring package to achieve chip packaging. The chip packaging method provided by this invention can effectively reduce the number of substrate layers used in the packaging process and effectively reduce warpage deformation generated during the packaging process.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a chip packaging method. Background Technology

[0002] With the continuous development of electronic technology and the increasing sophistication of electronic devices, high-end chips are demanding higher integration and more complex input / output interfaces (I / O), leading to a continuous increase in the number of substrate layers and structural complexity. Multilayer substrate technology faces challenges in terms of process difficulty, cost, and yield. Current technologies employ fan-out wafer-level packaging (FLP) processes to fabricate intermediate layers and reduce the number of packaging substrate layers. However, since current chip packaging typically requires a large number of redistribution layers, the reduction in packaging substrate layers achieved through fan-out FLP processes is limited. Furthermore, fan-out FLP processes are prone to substrate warping during secondary packaging, resulting in significant yield losses. Summary of the Invention

[0003] The chip packaging method provided by this invention can effectively reduce the number of substrate layers used in the packaging process and effectively reduce warpage deformation generated during the packaging process.

[0004] This invention provides a chip packaging method, the method comprising:

[0005] At least one chip is bonded to the first carrier board, and a first rewiring encapsulation layer is formed on the chip;

[0006] Based on the position of the chip on the first substrate, a second rewiring encapsulation layer is formed on the second substrate;

[0007] The first and second multiple wiring packaging layers are connected to achieve chip packaging.

[0008] Optionally, after connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer, the following steps are included:

[0009] Remove the second carrier plate;

[0010] The surface of the second rewiring encapsulation layer exposed after the removal of the second carrier board is planarized;

[0011] Pins are fabricated on the surface of the second rewiring package layer.

[0012] Optionally, before connecting the first multi-layer wiring encapsulation layer and the second multi-layer wiring encapsulation layer, the following steps are included:

[0013] Remove the second carrier plate;

[0014] Based on the correspondence between the second wiring package layer and the chip, the second wiring package layer is cut to form multiple second wiring package layer individual modules that correspond one-to-one with the chip.

[0015] Optionally, after connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer, the method further includes:

[0016] The gaps between the individual modules of the second wiring encapsulation layer are backfilled and encapsulated to form an intermediate package.

[0017] The intermediate package is planarized to expose the surface of the second rewiring package layer unit module;

[0018] Pins are fabricated on the surface of each second rewiring package layer unit module.

[0019] Optionally, after connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer, the following steps are included:

[0020] The first and second carrier boards are removed, and the first and second rewiring encapsulation layers are cut to form a package unit.

[0021] Optionally, connecting the first multi-layer wiring encapsulation layer and the second multi-layer wiring encapsulation layer includes:

[0022] Apply a filler to the surface of the first or second wiring encapsulation layer;

[0023] The first and second wiring encapsulation layers are bonded together.

[0024] Solder the connection points corresponding to the first and second wiring encapsulation layers.

[0025] Optionally, connecting the first multi-layer wiring encapsulation layer and the second multi-layer wiring encapsulation layer includes:

[0026] In a vacuum environment, a solid film made of thermosetting composite material is pressed onto the surface of one of the first and second rewiring encapsulation layers;

[0027] The solid film is heated so that it wets the surface of the corresponding redistribution packaging layer;

[0028] The first and second wiring encapsulation layers are bonded together;

[0029] Solder the connection points corresponding to the first and second wiring encapsulation layers.

[0030] Optionally, depending on the position of the chip on the first carrier, before forming the second rewiring package layer on the second carrier, the method further includes: bonding at least one chip to the second carrier.

[0031] Optionally, the number of the second rewiring encapsulation layers is one or more;

[0032] Connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer includes:

[0033] Connect the current second wiring encapsulation layer to the first wiring encapsulation layer;

[0034] Expose the surface of the current second wiring encapsulation layer;

[0035] Connect the next second-level routing layer to the current second-level routing layer.

[0036] Optionally, the first carrier board has multiple chip regions, each chip region corresponding to a chip combination, and each chip combination including at least one chip.

[0037] In the technical solution provided by this invention, a first rewiring encapsulation layer is fabricated on the chip on a first substrate, and a second rewiring encapsulation layer is fabricated on a second substrate. The final encapsulation structure connects the first and second rewiring encapsulation layers. This structure utilizes rewiring encapsulation layers entirely for chip rewiring, effectively reducing the number of substrate layers. Furthermore, because the properties of the first and second rewiring encapsulation layers are similar in this invention, warping and deformation can be effectively avoided when connecting them, improving the chip packaging yield. Attached Figure Description

[0038] Figure 1 This is a flowchart of a chip packaging method according to an embodiment of the present invention;

[0039] Figure 2 This is a flowchart illustrating the pin fabrication process of a chip packaging method according to another embodiment of the present invention;

[0040] Figure 3 This is a flowchart illustrating the cutting of the second rewiring packaging layer in a chip packaging method according to another embodiment of the present invention;

[0041] Figure 4 This is a flowchart illustrating the pin fabrication process of a chip packaging method according to another embodiment of the present invention;

[0042] Figure 5 This is a flowchart illustrating the connection between a first rewiring packaging layer and a second rewiring packaging layer in a chip packaging method according to another embodiment of the present invention.

[0043] Figure 6 This is a flowchart illustrating the chip packaging method of another embodiment of the present invention, showing the welding of a first rewiring packaging layer and a second rewiring packaging layer;

[0044] Figure 7 This is a flowchart illustrating the connection between a first rewiring packaging layer and a second rewiring packaging layer in a chip packaging method according to another embodiment of the present invention.

[0045] Figure 8 This is a structural diagram of the first redistribution packaging layer prepared by a chip packaging method according to another embodiment of the present invention;

[0046] Figure 9 This is a structural diagram of a chip packaging method according to another embodiment of the present invention for preparing a second rewiring packaging layer;

[0047] Figure 10 This is a structural diagram of a chip packaging method according to another embodiment of the present invention, showing the connection between a first rewiring packaging layer and a second rewiring packaging layer;

[0048] Figure 11 This is a structural diagram of a chip packaging method for removing a second carrier board according to another embodiment of the present invention;

[0049] Figure 12 This is a structural diagram of a chip packaging method according to another embodiment of the present invention, after removing the first carrier board;

[0050] Figure 13 This is a structural diagram of cutting the first rewiring packaging layer and the second rewiring packaging layer according to another embodiment of the chip packaging method of the present invention;

[0051] Figure 14 A diagram illustrating the fabrication of a first rewiring packaging layer structure according to another embodiment of the chip packaging method of the present invention;

[0052] Figure 15 This is a structural diagram of a chip packaging method according to another embodiment of the present invention for preparing a second rewiring packaging layer;

[0053] Figure 16 This is a structural diagram of a chip packaging method for removing a second carrier board according to another embodiment of the present invention;

[0054] Figure 17 This is a structural diagram of cutting the second rewiring packaging layer in a chip packaging method according to another embodiment of the present invention;

[0055] Figure 18 This is a structural diagram of a chip packaging method according to another embodiment of the present invention, showing the connection between a first rewiring packaging layer and a second rewiring packaging layer;

[0056] Figure 19 A structural diagram illustrating the method for filling the gaps between individual modules in the second wiring packaging layer according to another embodiment of the present invention;

[0057] Figure 20 This is a structural diagram of a chip packaging method according to another embodiment of the present invention, after removing the first carrier board;

[0058] Figure 21 This is a structural diagram of cutting the first rewiring encapsulation layer and the second rewiring encapsulation layer in a chip packaging method according to another embodiment of the present invention. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] This invention provides a chip packaging method, such as... Figure 1 As shown, the method includes:

[0061] Step 100: At least one chip is bonded to the first carrier board and a first rewiring package layer is formed on the chip;

[0062] In some embodiments, when bonding the chip to the first substrate, the back side of the chip needs to be fixed to the first substrate. Before forming the first multi-layer wiring package on the chip, the gaps between the chips need to be filled, encapsulated, and planarized. Based on the planarized structure, a dielectric material is formed on the surface, and wiring patterns are formed on the dielectric layer by developing, exposing, and etching. Copper metal is formed within the pattern by electroplating, thus forming the first multi-layer wiring package.

[0063] Step 200: Based on the position of the chip on the first substrate, a second rewiring encapsulation layer is formed on the second substrate;

[0064] In some embodiments, when forming a second rewiring package layer on a second substrate of a chip, since there is no chip on the second substrate, a dielectric layer can be formed on the substrate, and a wiring pattern can be formed on the dielectric layer by developing, exposing, and etching. Copper metal can then be formed within the pattern by electroplating to create the second rewiring package layer.

[0065] Step 300: Connect the first super-wiring packaging layer and the second super-wiring packaging layer to achieve chip packaging.

[0066] In some embodiments, the exposed surfaces of the first wiring encapsulation layer and the second wiring encapsulation layer have one-to-one corresponding connection points. Therefore, when connecting the first wiring encapsulation layer and the second wiring encapsulation layer, the corresponding connection points are first aligned and then attached, and then the connection points are electrically connected, while the other areas are physically connected.

[0067] In the technical solution provided by this embodiment of the invention, a first rewiring encapsulation layer is fabricated on the chip on a first substrate, and a second rewiring encapsulation layer is fabricated on a second substrate. The final packaging structure connects the first and second rewiring encapsulation layers. This structure uses rewiring encapsulation layers entirely for chip rewiring, effectively reducing the number of substrate layers. Furthermore, since the properties of the first and second rewiring encapsulation layers are similar in this invention, warping deformation can be effectively avoided when connecting them, improving the chip packaging yield. In this embodiment, a first rewiring encapsulation layer is first fabricated on the chip for the first rewiring, and then a second rewiring encapsulation layer is fabricated on the second substrate. After connecting the second and first rewiring encapsulation layers, the second rewiring of the chip is completed.

[0068] As an optional implementation method, such as Figure 2 As shown, connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer includes:

[0069] Step 410: Remove the second carrier plate;

[0070] In some embodiments, since the second rewiring package layer on the second substrate is used to ultimately bring out the pins of the chip, pins need to be provided on the second rewiring package layer. The pins should be provided on the contact surface between the second substrate and the second rewiring package layer; therefore, the second substrate needs to be removed first to avoid the second substrate obstructing the pin preparation.

[0071] Step 420: Planarize the surface of the second rewiring encapsulation layer exposed after removing the second carrier board;

[0072] In some embodiments, in order to improve the quality of pin fabrication and the bonding effect in the subsequent packaging process, the surface of the second wiring packaging layer is first planarized in this embodiment.

[0073] Step 430: Fabricate pins on the surface of the second rewiring package layer.

[0074] In some embodiments, the pins fabricated on the surface of the second overlay package layer are typically implemented using a ball-mounting process, i.e., solder balls are placed on the surface of the second overlay package layer.

[0075] As an optional implementation method, such as Figure 3 As shown, the process before connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer includes:

[0076] Step 310: Remove the second carrier plate;

[0077] In some embodiments, besides connecting the second rewiring encapsulation layer of the second carrier board entirely to the first rewiring encapsulation layer, the second rewiring encapsulation layer can also be cut before being connected to the first rewiring encapsulation layer. Before cutting the second rewiring encapsulation layer, the second carrier board needs to be removed first to ensure its integrity and reusability.

[0078] Step 320: Based on the correspondence between the second overlay packaging layer and the chip, the second overlay packaging layer is cut to form multiple second overlay packaging layer single modules that correspond one-to-one with the chip.

[0079] In some embodiments, after the second wiring encapsulation layer is cut, multiple second wiring encapsulation layer individual modules are formed. The multiple second wiring encapsulation layer individual modules correspond to different regions of the first wiring encapsulation layer and can be connected to the corresponding regions of the first wiring encapsulation layer respectively.

[0080] As an optional implementation method, such as Figure 4 As shown, after connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer, the process further includes:

[0081] Step 440: Backfill and encapsulate the gaps between the individual modules of the second rewiring encapsulation layer to form an intermediate package;

[0082] In some embodiments, after the second rewiring encapsulation layer unit module is connected to the first rewiring encapsulation layer, there will be gaps between adjacent second encapsulation layer unit modules. In order for the smooth progress of subsequent encapsulation processes, the gaps need to be backfilled and flattened first to provide a flat surface.

[0083] Step 450: Planarize the intermediate package to expose the surface of the second rewiring package layer unit module;

[0084] In some embodiments, during the backfilling process, the film layer formed by the backfill material typically covers the surface of the second overlay packaging layer module. In order to form an electrical connection when the pins are subsequently fabricated, the surface of the second overlay packaging layer module needs to be exposed during the planarization process.

[0085] Step 460: Fabricate pins on the surface of each second rewiring package layer unit module.

[0086] In some embodiments, the pins fabricated on the surface of the second rewiring package module are the pins that ultimately connect the chip to the outside world, and the pins can typically be set using a ball-mounting process.

[0087] As an optional implementation, connecting the first redistribution layer and the second redistribution layer includes:

[0088] The first and second carrier boards are removed, and the first and second rewiring encapsulation layers are cut to form a package unit.

[0089] In some embodiments, the second carrier board may be removed before the first and second multi-layer wiring package (MLC) layers are connected; in this case, only the first carrier board needs to be removed. Alternatively, the second carrier board may remain after the first and second MLC layers are connected; in this case, both the first and second carrier boards need to be removed together. After cutting the first and second MLC layers, multiple package units are formed, and each package unit may include one or more chips.

[0090] As an optional implementation method, such as Figure 5 As shown, connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer includes:

[0091] Step 331: Apply a filler to the surface of the first or second wiring encapsulation layer;

[0092] In some embodiments, the underfill is a bonding material used to bond the first and second rewiring encapsulation layers together. The underfill can be applied to the surface of either the first or second rewiring encapsulation layer.

[0093] Step 332: Bond the first and second wiring encapsulation layers together.

[0094] In some embodiments, when the first and second wiring encapsulation layers are bonded together, it should be ensured that the connection points on the first and second wiring encapsulation layers are aligned so that an electrical connection can be successfully formed by subsequent soldering.

[0095] Step 333: Solder the connection points corresponding to the first and second wiring encapsulation layers.

[0096] In some embodiments, after the corresponding connection points are welded, an electrical connection can be successfully formed. The welding method can be thermocompression bonding (TCB) or thermocompression reflow soldering (TCR).

[0097] As an optional implementation method, such as Figure 6 As shown, connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer includes:

[0098] Step 341: In a vacuum environment, a solid film made of thermosetting composite material is pressed onto the surface of one of the first and second rewiring encapsulation layers.

[0099] In some embodiments, pressing a solid film onto the redistribution encapsulation layer in a vacuum environment facilitates the adhesion of the solid film to the redistribution encapsulation layer.

[0100] Step 342: Heat the solid film to wet the surface of the corresponding redistribution packaging layer.

[0101] In some embodiments, after the solid film is heated, the solid film will be completely immersed in the surface of the redistribution packaging layer, further improving the adhesion between the solid film and the surface of the redistribution packaging layer.

[0102] Step 343: Bond the first wiring encapsulation layer and the second wiring encapsulation layer together;

[0103] In some embodiments, when bonding the first wiring encapsulation layer and the second wiring encapsulation layer, it is necessary to first align the connection points of the first wiring encapsulation layer and the second wiring encapsulation layer so that electrical connections can be formed smoothly during subsequent soldering.

[0104] Step 344: Solder the connection points corresponding to the first and second rewiring encapsulation layers.

[0105] In some embodiments, connecting the first and second wiring encapsulation layers achieves an electrical connection between them. The soldering method can be, for example, reflow soldering.

[0106] As an optional implementation, depending on the position of the chip on the first carrier, before forming the second rewiring package layer on the second carrier, the method further includes: bonding at least one chip to the second carrier.

[0107] In some embodiments, chips are disposed on a second substrate and bonded using through-silicon via (TSV) technology, enabling 3D packaging of multiple chips.

[0108] As an optional implementation method, such as Figure 7 As shown, the number of the second rewiring encapsulation layers is one or more;

[0109] Connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer includes:

[0110] Step 351: Connect the current second wiring encapsulation layer to the first wiring encapsulation layer;

[0111] In some instances, the current redistribution layer is connected to the first redistribution layer in the same way as in the aforementioned embodiments.

[0112] Step 352: Expose the surface of the current second wiring encapsulation layer;

[0113] In some embodiments, when exposing the current second rewiring encapsulation layer, the second carrier board needs to be removed and planarized. Alternatively, if the second carrier board has already been removed and cut before the second rewiring encapsulation layer is connected, the gaps between the individual modules of the second rewiring encapsulation layer can be backfilled and planarized to expose the surface of the second rewiring encapsulation layer.

[0114] Step 353: Connect the next second routing layer to the current second routing layer.

[0115] In some embodiments, the next second wiring encapsulation layer has corresponding connection points with the current second wiring encapsulation layer. The connection points of the next second wiring encapsulation layer and the current second wiring encapsulation layer can be aligned before physical and electrical connections are made.

[0116] As an optional implementation, the first carrier board has multiple chip regions, each chip region corresponding to a chip combination, and each chip combination including at least one chip.

[0117] The following is an exemplary embodiment to illustrate the technical solution of the present invention:

[0118] Chips 120 are bonded to the first substrate 110, and the spaces between chips 120 are filled and planarized, for example, by mechanical physical polishing, to form a flat surface. The planarized surface is exposed and developed to form wiring patterns within the filled dielectric material. Copper metal lines are then formed within the patterns by electroplating, thus completing the first rewiring of chip 120. After the first rewiring is completed, its structure is as follows: Figure 8 As shown.

[0119] A dielectric film is fabricated on the second substrate 210. Photolithography, exposure, and etching are performed on the dielectric film to form wiring patterns within the dielectric material. Copper metal lines are then formed within the patterns through electroplating. The resulting structure is as follows. Figure 9 As shown.

[0120] The first rewiring encapsulation layer 130 and the second rewiring encapsulation layer 220 are connected to achieve the second rewiring of the chip 120. The structure after the first rewiring encapsulation layer 130 and the second rewiring encapsulation layer 220 are connected is as follows. Figure 10 As shown.

[0121] After the first wiring encapsulation layer 130 and the second wiring encapsulation layer 220 are connected, the second carrier board 210 is removed and planarized to accommodate the solder balls. The structure after removing the second carrier board 210 and completing planarization is as follows: Figure 11 As shown.

[0122] After removing the second carrier board 210, solder balls (not shown in the figure) are placed on the surface of the second rewiring encapsulation layer 220. After placing the solder balls, the first carrier board 110 is removed to allow for cutting of the first rewiring encapsulation layer 130 and the second rewiring encapsulation layer 220. After removing the first carrier board 110, the structure is as follows: Figure 12 As shown.

[0123] After removing the first carrier board 110, the first rewiring encapsulation layer 130 and the second rewiring encapsulation layer 220 are cut to form a package unit, the structure of which is as follows: Figure 13 As shown.

[0124] The following is an exemplary embodiment to illustrate the technical solution of the present invention:

[0125] Chips 120 are bonded to the first substrate 110, and the spaces between chips 120 are filled and planarized, for example, by mechanical physical polishing, to form a flat surface. The planarized surface is exposed and developed to form wiring patterns within the filled dielectric material. Copper metal lines are then formed within the patterns by electroplating, thus completing the first rewiring of chip 120. After the first rewiring is completed, its structure is as follows: Figure 14 As shown.

[0126] A dielectric film is fabricated on the second substrate 210. Photolithography, exposure, and etching are performed on the dielectric film to form wiring patterns within the dielectric material. Copper metal lines are then formed within the patterns through electroplating. The resulting structure is as follows. Figure 15 As shown.

[0127] After the second overlay encapsulation layer 220 is completed on the second carrier board 210, the second carrier board 210 is removed to allow for the cutting of the second overlay encapsulation layer 220. The structure after removing the second carrier board 210 is as follows. Figure 16 As shown.

[0128] After removing the second carrier board 210, the second rewiring encapsulation layer 220 is cut to form a second rewiring encapsulation unit module 221. The structure of the second rewiring encapsulation unit module 221 is as follows: Figure 17 As shown.

[0129] Multiple second-level wiring encapsulation unit modules 221 are sequentially connected to corresponding connection points on the first-level wiring encapsulation layer 130, resulting in the following structure: Figure 18 As shown.

[0130] To fabricate the pins, the gaps between the second wiring package modules 221 need to be filled and planarized. The structure after filling and planarization is as follows: Figure 19 As shown.

[0131] After the filling and planarization processes are completed, the first carrier board 110 needs to be removed to allow for the cutting of the first rewiring encapsulation layer 130 and the second rewiring encapsulation layer 220. After removing the first carrier board 110, its structure is as follows: Figure 20 As shown.

[0132] After removing the first carrier board 110, the first rewiring encapsulation layer 130 and the second rewiring encapsulation layer 220 are cut to form a package unit, the structure of which is as follows: Figure 21 As shown.

[0133] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip packaging method, characterized by, The method includes: At least one chip is bonded to the first carrier board, and a first rewiring encapsulation layer is formed on the chip; Based on the position of the chip on the first substrate, a second rewiring encapsulation layer is formed on the second substrate; The first multi-layer wiring package and the second multi-layer wiring package are connected to achieve chip packaging; the number of the second multi-layer wiring package is one or more. Connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer includes: Connect the current second wiring encapsulation layer to the first wiring encapsulation layer; Expose the surface of the current second wiring encapsulation layer; Connect the next second-level routing encapsulation layer to the current second-level routing encapsulation layer; After connecting the first redistribution layer and the second redistribution layer, the method further includes: Remove the second carrier plate; The surface of the second rewiring encapsulation layer exposed after the removal of the second carrier board is planarized; Pins are fabricated on the surface of the second rewiring package layer.

2. A chip packaging method, characterized by, The method includes: At least one chip is bonded to the first carrier board, and a first rewiring encapsulation layer is formed on the chip; Based on the position of the chip on the first substrate, a second rewiring encapsulation layer is formed on the second substrate; The first multi-layer wiring package and the second multi-layer wiring package are connected to achieve chip packaging; the number of the second multi-layer wiring package is one or more. Connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer includes: Connect the current second wiring encapsulation layer to the first wiring encapsulation layer; Expose the surface of the current second wiring encapsulation layer; Connect the next second-level routing encapsulation layer to the current second-level routing encapsulation layer; Before connecting the first redistribution layer and the second redistribution layer, the method further includes: Remove the second carrier plate; Based on the correspondence between the second wiring package layer and the chip, the second wiring package layer is cut to form multiple second wiring package layer individual modules that correspond one-to-one with the chip.

3. The method of claim 2, wherein, After connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer, the process further includes: The gaps between the individual modules of the second wiring encapsulation layer are backfilled and encapsulated to form an intermediate package. The intermediate package is planarized to expose the surface of the second rewiring package layer unit module; Pins are fabricated on the surface of each second rewiring package layer unit module.

4. The method according to claim 1 or 2, characterized in that, Connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer includes: Apply a filler to the surface of the first or second wiring encapsulation layer; The first and second wiring encapsulation layers are bonded together. Solder the connection points corresponding to the first and second wiring encapsulation layers.

5. The method according to claim 1 or 2, characterized in that, Connecting the first rewiring encapsulation layer and the second rewiring encapsulation layer includes: In a vacuum environment, a solid film made of thermosetting composite material is pressed onto the surface of one of the first and second rewiring encapsulation layers; The solid film is heated so that it wets the surface of the corresponding redistribution packaging layer; The first and second wiring encapsulation layers are bonded together; Solder the connection points corresponding to the first and second wiring encapsulation layers.

6. The method of claim 1 or 2, wherein, The first carrier board has multiple chip regions, each chip region corresponds to a chip combination, and each chip combination includes at least one chip.

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