Fabrication method of deep trench isolation structure with ultra-high aspect ratio

Abstract

This application provides a method for fabricating a deep trench isolation structure with an ultra-high aspect ratio, comprising: providing a substrate, on which a first dielectric layer, a first silicon nitride layer, a second dielectric layer, a second silicon nitride layer, and a third dielectric layer are sequentially formed, wherein a shallow trench isolation structure is formed in the first silicon nitride layer, the first dielectric layer, and the substrate; etching the third dielectric layer, the second silicon nitride layer, the second dielectric layer, the shallow trench isolation structure, and the substrate to form trenches of the deep trench isolation structure; forming an oxide liner on the inner wall of the trench; depositing a first high-density plasma film layer in the trench; depositing a high aspect ratio process film layer in the trench to form an air gap; and depositing a second high-density plasma film layer in the trench. According to this application, while ensuring a sufficiently large distance between the sidewalls of the air gap formed in the deep trench isolation structure and the sidewalls of the deep trench isolation structure, the height of the air gap is minimized as much as possible, thereby maximizing the isolation voltage of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for fabricating a deep trench isolation structure with an ultra-high aspect ratio. Background Technology

[0002] To achieve integration between high-density logic circuits and high-power custom circuits, appropriate isolation is required between high-voltage and low-voltage regions within a chip. Existing technologies achieve this isolation through multilayer epitaxial stacking and the introduction of deep trench isolation (DTI) technology. Since the deep trench isolation structure extends along the thickness direction of the substrate to improve isolation performance, its width can be further reduced, thereby saving chip area and increasing the voltage difference across the isolation terminals.

[0003] For deep trench isolation structures with an aspect ratio exceeding 10:1, existing technologies typically use monocrystalline silicon or polycrystalline silicon to fill the trenches. However, for large-size micron-level deep trench isolation structures, monocrystalline silicon or polycrystalline silicon fills the trenches slowly, which severely affects production capacity. At the same time, monocrystalline silicon or polycrystalline silicon is not as strong as oxide isolation.

[0004] If oxide is used to fill the trenches of a deep trench isolation structure with a depth-to-width ratio exceeding 10:1, the top sealing will cause air gaps to form in the filled oxide if the trenches are not completely filled. These air gaps need to meet specific conditions to avoid affecting the isolation performance of the deep trench isolation structure. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for fabricating a deep trench isolation structure with an ultra-high aspect ratio, in order to solve the problem that filling the trenches of the deep trench isolation structure with oxide, monocrystalline silicon or polycrystalline silicon in the prior art does not achieve the expected isolation effect or affects chip production capacity.

[0006] To achieve the above and other related objectives, this application provides a method for manufacturing a deep trench isolation structure with an ultra-high aspect ratio, comprising:

[0007] A substrate is provided, on which a first dielectric layer, a first silicon nitride layer, a second dielectric layer, a second silicon nitride layer and a third dielectric layer are sequentially formed, wherein a shallow trench isolation structure is formed in the first silicon nitride layer, the first dielectric layer and the substrate;

[0008] The third dielectric layer, the second silicon nitride layer, the second dielectric layer, the shallow trench isolation structure, and the substrate are etched to form the trench of the deep trench isolation structure;

[0009] An oxide lining is formed on the inner wall of the trench;

[0010] Deposit the first high-density plasma film layer in the trench;

[0011] High aspect ratio process films are deposited in the trenches to form air gaps;

[0012] A second high-density plasma film layer was deposited in the trench.

[0013] Preferably, a high-density plasma deposition process with a low deposition-etch ratio is used to deposit the first high-density plasma film in the trench.

[0014] Preferably, the high-density plasma deposition process with a low deposition-to-etch ratio uses oxygen / helium as the dominant gas.

[0015] Preferably, the deposition-etch ratio is 2.5-3.5.

[0016] Preferably, a high aspect ratio process film is deposited in the trench using a subatmospheric pressure chemical vapor deposition process.

[0017] Preferably, the reaction temperature of the subatmospheric chemical vapor deposition process is 500℃-600℃, and the reaction pressure is 500Torr-700Torr.

[0018] Preferably, the vertical distance between the top of the air gap and the bottom of the shallow groove isolation structure is greater than 0.9 micrometers.

[0019] Preferably, the vertical distance between the sidewall of the air gap and the sidewall of the deep groove isolation structure is greater than 0.5 micrometers.

[0020] Preferably, a second high-density plasma film layer is deposited in the trench using a high-density plasma deposition process.

[0021] Preferably, a high-temperature thermal annealing step is further included before depositing the second high-density plasma film layer in the trench.

[0022] Preferably, the high-temperature annealing temperature is 1000℃-1100℃, and the duration is 25min-35min.

[0023] Preferably, after depositing the second high-density plasma film layer in the trench, a planarization step is further performed to make the surface of the first silicon nitride layer flush with the surface of the deep trench isolation structure.

[0024] Preferably, the planarization is performed using a chemical mechanical polishing process.

[0025] As described above, the method for fabricating a deep trench isolation structure with an ultra-high aspect ratio provided in this application has the following beneficial effects: ensuring a sufficiently large distance between the sidewall of the air gap formed in the deep trench isolation structure and the sidewall of the deep trench isolation structure, while minimizing the height of the air gap, thereby maximizing the isolation voltage of the device. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 The flowchart shown is a method for manufacturing a deep trench isolation structure with an ultra-high aspect ratio provided in an embodiment of this application;

[0028] Figure 2 The diagram shown is a schematic cross-sectional view of the device formed after step S1 in the fabrication method of the deep trench isolation structure with ultra-high aspect ratio provided in the embodiments of this application.

[0029] Figure 3 The diagram shown is a cross-sectional view of the device formed after step S2 in the fabrication method of the deep trench isolation structure with ultra-high aspect ratio provided in the embodiments of this application.

[0030] Figure 4 The diagram shown is a cross-sectional view of the device formed after step S3 in the fabrication method of the deep trench isolation structure with ultra-high aspect ratio provided in the embodiments of this application.

[0031] Figure 5 The diagram shown is a cross-sectional view of the device formed after step S4 in the fabrication method of the deep trench isolation structure with ultra-high aspect ratio provided in the embodiments of this application.

[0032] Figure 6 The diagram shown is a schematic cross-sectional view of the device formed after step S5 in the method for fabricating a deep trench isolation structure with an ultra-high aspect ratio provided in the embodiments of this application.

[0033] Figure 7 The diagram shown is a schematic cross-sectional view of the device formed after step S6 in the method for fabricating a deep trench isolation structure with an ultra-high aspect ratio provided in the embodiments of this application.

[0034] Figure 8The diagram shows an air gap formed in a deep trench isolation structure manufactured using the method for manufacturing a deep trench isolation structure with an ultra-high aspect ratio provided in this application, in one embodiment. Detailed Implementation

[0035] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0036] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0038] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection between two components; and they can refer to wireless connections or wired connections. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0039] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0040] For deep trench isolation structures with an aspect ratio exceeding 10:1, existing technologies use monocrystalline silicon or polycrystalline silicon to fill the trenches. However, this results in slow filling speed, which severely impacts production capacity, and monocrystalline silicon or polycrystalline silicon does not have the same isolation capability as oxides.

[0041] If oxide is used to fill the trenches of a deep trench isolation structure with an aspect ratio exceeding 10:1, the top sealing when the trench is not completely filled will cause air gaps to form in the filled oxide. These air gaps need to meet specific conditions to avoid affecting the isolation performance of the deep trench isolation structure. For example, the vertical distance between the top of the air gap and the bottom of the shallow trench isolation structure must be greater than 0.9 micrometers, and the vertical distance between the sidewall of the air gap and the sidewall of the deep trench isolation structure must be greater than 0.5 micrometers. The air gaps formed in the oxide filled with existing technology do not meet these requirements.

[0042] Please see Figure 1 The diagram shows a flowchart of a method for manufacturing a deep trench isolation structure with an ultra-high aspect ratio, as provided in an embodiment of this application.

[0043] In step S1, a substrate is provided, on which a first dielectric layer, a first silicon nitride layer, a second dielectric layer, a second silicon nitride layer and a third dielectric layer are sequentially formed, wherein a shallow trench isolation structure is formed in the first silicon nitride layer, the first dielectric layer and the substrate.

[0044] like Figure 2 As shown, a substrate 100 is provided. Optionally, the substrate 100 is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate 100 may also include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the constituent material of the substrate 100 according to the type of device structure formed on the substrate 100, therefore the type of substrate 100 should not limit the scope of protection of this invention.

[0045] Next, a first dielectric layer 101 and a first silicon nitride layer 102 are sequentially formed on the substrate 100. Optionally, conventional CVD, PVD (with the first dielectric layer 101 being a thermal oxide material), or thermal oxidation processes are used to form the first dielectric layer 101 and the first silicon nitride layer 102. Since the lattice constant of the first silicon nitride layer 102 differs significantly from that of the substrate 100, directly depositing the first silicon nitride layer 102 on the substrate 100 will result in dislocations in the substrate 100, causing stress damage. Therefore, the first dielectric layer 101 serves as a buffer layer between the first silicon nitride layer 102 and the substrate 100 to buffer stress. Optionally, a gate oxide layer can be used as the first dielectric layer 101, eliminating the need to remove the first dielectric layer 101 before forming the gate oxide layer in subsequent processes, thereby improving the efficiency of gate oxide layer formation in semiconductor devices.

[0046] Next, a shallow trench isolation structure 107 is formed in the first silicon nitride layer 102, the first dielectric layer 101, and the substrate 100.

[0047] For example, after forming a first dielectric layer 101 and a first silicon nitride layer 102 sequentially on a substrate 100, the first silicon nitride layer 102, the first dielectric layer 101 and the substrate 100 are etched to form a bowl-shaped trench, and silicon oxide is deposited in the bowl-shaped trench to obtain a shallow trench isolation structure 107; then, a chemical mechanical polishing process is performed on the surface of the shallow trench isolation structure 107 to planarize the surface of the shallow trench isolation structure 107 and the surface of the first silicon nitride layer 102.

[0048] Then, a second dielectric layer 103, a second silicon nitride layer 105, and a third dielectric layer 106 are sequentially formed on the shallow trench isolation structure 107 and the first silicon nitride layer 102. Optionally, conventional CVD, PVD, or thermal oxidation processes are used to form the second dielectric layer 103, the second silicon nitride layer 105, and the third dielectric layer 106. The second dielectric layer 103, the second silicon nitride layer 105, and the third dielectric layer 106 act as a hard mask structure to avoid unnecessary damage to the shallow trench isolation structure 107 and the substrate 100 during the subsequent formation of the deep trench isolation structure.

[0049] The second dielectric layer 103 serves two purposes: firstly, to enhance the bonding force between the second silicon nitride layer 105 and the first silicon nitride layer 102; and secondly, to protect the first silicon nitride layer 102 during the subsequent formation of the deep trench isolation structure, preventing its thickness from being lost and causing differences in the thickness of the first silicon nitride layer 102 in different areas of the substrate 100, thus affecting its function as a polishing stop layer.

[0050] In step S2, the third dielectric layer, the second silicon nitride layer, the second dielectric layer, the shallow trench isolation structure, and the substrate are etched to form the trench of the deep trench isolation structure.

[0051] like Figure 3 As shown, photolithography and dry etching processes are used to expose, develop, and etch the third dielectric layer 106, the second silicon nitride layer 105, the second dielectric layer 103, the shallow trench isolation structure 107, and a substrate 100 of a certain thickness to form the trench 108 of the deep trench isolation structure. During the etching process, the third dielectric layer 106 of a certain thickness is etched.

[0052] For example, the embodiments of this application form the trench 108 by etching in two steps, that is, first etching to the bottom of the shallow trench isolation structure 107 and then etching a substrate 100 of a certain thickness. The reasons are: first, the shallow trench isolation structure 107 and the substrate 100 etched in the two steps are made of different materials; second, etching in two steps can make the morphology of the trench 108 better.

[0053] In step S3, an oxide lining is formed on the inner wall of the trench.

[0054] like Figure 4As shown, an oxide lining 109 is formed on the inner wall of the trench 108. Exemplarily, the oxide lining 109 is formed using a thermal oxidation process.

[0055] Since the substrate 100 exhibits post-etching stress and the edge surface of the trench 108 is damaged after etching to form the trench 108, the substrate 100 can be annealed to eliminate the corresponding post-etching stress and repair the damage. The oxide lining layer 109 can also be formed during the annealing process. It should be noted that the oxide lining layer 109 can also serve as a buffer when filling the trench 108 with insulating material, thus protecting the substrate 100.

[0056] In step S4, a first high-density plasma film is deposited in the trench.

[0057] like Figure 5 As shown, a first high-density plasma (HDP) film 110 is deposited in trench 108. In embodiments of this application, a high-density plasma deposition process with a low deposition-to-etch ratio is used to deposit the first high-density plasma film 110 in trench 108. This process uses oxygen / helium as the dominant gas and a deposition-to-etch ratio of 2.5-3.5, preferably 3.2.

[0058] The high-density plasma deposition process with a low deposition-etch ratio can reduce the position of the overhang portion of the first high-density plasma film 110 formed in the trench 108, which is the top position of the air gap formed subsequently. At the same time, it can also increase the thickness of the first high-density plasma film 110 at the bottom of the trench 108, thereby increasing the bottom isolation effect.

[0059] In step S5, a high aspect ratio process film is deposited in the trench to form an air gap.

[0060] like Figure 6 As shown, a high aspect ratio process (HARP) film 111 is deposited in trench 108. In the embodiments of this application, a subatmospheric pressure chemical vapor deposition (SACVD) process is used to deposit the HARP film 111 in trench 108. The SACVD process parameters are: reaction temperature 500℃-600℃, preferably 540℃; reaction pressure 500 Torr-700 Torr, preferably 600 Torr.

[0061] The SACVD process can make the deposited film layer have good shape retention and the film layer itself has good gap filling effect. Therefore, the HARP film layer 111 can start to grow at the position of the overhanging opening until it is sealed in the trench 108 to form an air gap 112.

[0062] SACVD process has strong step coverage capability, which can deposit the film layer on the surface of the first high-density plasma film layer 110 below the position of the overhanging opening, thereby making the distance between the sidewall of the formed air gap 112 and the sidewall of the trench 108 large enough to improve the isolation voltage of the deep trench isolation structure.

[0063] Optionally, after depositing the HARP film 111 in the trench 108, a high-temperature thermal annealing step is performed to release the stress in the first high-density plasma film 110 and the HARP film 111, thereby improving the quality of the HARP film 111. Exemplarily, the high-temperature thermal annealing temperature is 1000°C-1100°C, preferably 1050°C, and the duration is 25 min-35 min, preferably 30 min.

[0064] In step S6, a second high-density plasma film is deposited in the trench.

[0065] like Figure 7 As shown, a second high-density plasma film layer 113 is deposited in the trench 108. The second high-density plasma film layer 113, as a capping layer, can weaken the degree of top depression of the filler formed in the trench 108, reduce the surface step difference, and facilitate the implementation of subsequent chemical mechanical polishing processes.

[0066] In the embodiments of this application, a second high-density plasma film layer 113 is deposited in the trench 108 using a high-density plasma deposition process. The deposition-etch ratio of this process is 3.0-4.0, preferably 3.2.

[0067] The film layer formed in steps S4 to S6 constitutes the insulating material of the deep trench isolation structure 115.

[0068] Please see Figure 8 The illustration shows a schematic diagram of the air gap formed in a deep trench isolation structure manufactured using the method for manufacturing a deep trench isolation structure with an ultra-high aspect ratio provided in this application in one embodiment.

[0069] like Figure 8 As shown, the deep trench isolation structure fabricated in this embodiment has a depth of 19 micrometers, a top width feature dimension of 1.8 micrometers, a depth-to-width ratio greater than 10:1, a vertical distance between the top of the air gap and the bottom of the shallow trench isolation structure of 1312 nm, which is greater than 0.9 micrometers, and a vertical distance between the sidewall of the air gap and the sidewall of the deep trench isolation structure of 679 nm, which is greater than 0.5 micrometers.

[0070] In summary, the method for fabricating a deep trench isolation structure with an ultra-high aspect ratio provided in this application has the following beneficial effects: it ensures a sufficiently large distance between the sidewall of the air gap 112 formed in the deep trench isolation structure 115 and the sidewall of the deep trench isolation structure 115, while minimizing the height of the air gap 112, thereby maximizing the isolation voltage of the device. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0071] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0072] Next, the insulating material consisting of the film layers formed in steps S4 to S6 is planarized so that the surface of the first silicon nitride layer 102 is flush with the surface of the deep trench isolation structure 115. Exemplarily, this planarization can be performed using a chemical mechanical polishing process, with the first silicon nitride layer 102 serving as a polishing stop layer during the planarization process. Then, the first silicon nitride layer 102 is removed. Exemplarily, a wet process can be used, where a hot phosphoric acid solution reacts with the first silicon nitride layer 102 to remove it.

[0073] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for manufacturing a deep trench isolation structure with an ultra-high aspect ratio, characterized in that, The method includes: A substrate is provided, on which a first dielectric layer, a first silicon nitride layer, a second dielectric layer, a second silicon nitride layer and a third dielectric layer are sequentially formed, wherein a shallow trench isolation structure is formed in the first silicon nitride layer, the first dielectric layer and the substrate; The third dielectric layer, the second silicon nitride layer, the second dielectric layer, the shallow trench isolation structure, and the substrate are etched to form the trench of the deep trench isolation structure; An oxide lining layer is formed on the inner wall of the trench; A first high-density plasma film layer is deposited in the trench; A high aspect ratio process film is deposited in the trench to form an air gap; A second high-density plasma film layer is deposited in the trench.

2. The method according to claim 1, characterized in that, The first high-density plasma film layer is deposited in the trench using a high-density plasma deposition process with a low deposition-etch ratio.

3. The method according to claim 2, characterized in that, The high-density plasma deposition process with a low deposition-to-etch ratio uses oxygen / helium as the dominant gas.

4. The method according to claim 2 or 3, characterized in that, The deposition-etch ratio is 2.5-3.

5.

5. The method according to claim 1, characterized in that, The high aspect ratio process film is deposited in the trench using a subatmospheric pressure chemical vapor deposition process.

6. The method according to claim 5, characterized in that, The reaction temperature of the subatmospheric chemical vapor deposition process is 500℃-600℃, and the reaction pressure is 500 Torr-700 Torr.

7. The method according to claim 1, characterized in that, The vertical distance between the top of the air gap and the bottom of the shallow trench isolation structure is greater than 0.9 micrometers.

8. The method according to claim 1, characterized in that, The vertical distance between the sidewall of the air gap and the sidewall of the deep trench isolation structure is greater than 0.5 micrometers.

9. The method according to claim 1, characterized in that, The second high-density plasma film layer is deposited in the trench using a high-density plasma deposition process.

10. The method according to claim 1, characterized in that, Before depositing the second high-density plasma film in the trench, a high-temperature thermal annealing step is also included.

11. The method according to claim 10, characterized in that, The high-temperature annealing temperature is 1000℃-1100℃, and the duration is 25min-35min.

12. The method according to claim 1, characterized in that, After depositing the second high-density plasma film layer in the trench, a planarization step is further included to make the surface of the first silicon nitride layer flush with the surface of the deep trench isolation structure.

13. The method according to claim 12, characterized in that, The planarization is performed using a chemical mechanical polishing process.

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