System-in-package analog-to-digital conversion chip and test system and test method thereof

Abstract

The application provides a system-level package analog-digital conversion chip and a testing system and method thereof, the system-level package analog-digital conversion chip comprising a sample-hold sub-chip, a coupling capacitor and a time-interleaved analog-digital conversion sub-chip, compared with a traditional board-level integrated system, the overall device layout is more compact, the size specification is smaller, the interconnection line length between the sub-chips is shortened, the adverse effects such as delay, capacity resistance and parasitic effect can be reduced, and the data transmission speed can be improved; meanwhile, the sample input bandwidth is improved through the sample-hold sub-chip, the processing speed of analog-digital conversion is improved through the time-interleaved architecture of the time-interleaved analog-digital conversion sub-chip, and the mismatch error between each channel in the system-level package analog-digital conversion chip is corrected through the system-level package analog-digital conversion chip testing system and method, so that the analog-digital conversion precision and efficiency of the time-interleaved analog-digital conversion sub-chip are ensured, and a high-bandwidth super-high-speed analog-digital converter is simply and efficiently realized.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a system-in-package analog-to-digital converter chip and its testing system and testing method. Background Technology

[0002] In today's rapidly developing digital age, the frequencies of electrical signals being processed are increasingly higher in fields such as basic cutting-edge technologies and national defense, with rise times even reaching the picosecond level. To ensure distortion-free sampling of electrical signals, it is necessary to continuously improve the sampling rate and analog input bandwidth of the sampling system. The inherent characteristics of analog-to-digital converter (ADC) chips, such as sampling accuracy, sampling frequency, power consumption, and package size, will become key factors affecting the development of the digital age. However, currently, the sampling rate and analog input bandwidth of domestic ADC chips are still at a relatively low level, making it impossible to achieve distortion-free sampling of high-frequency signals through the chip itself.

[0003] To improve the sampling rate of ADC chips, there are currently two technical approaches: one is to start with existing chips and adopt the relatively mature time-alternating technology. However, its drawback is that it introduces system mismatch errors, and the analog input bandwidth of the system is still limited by the analog bandwidth of a single ADC chip. The other approach is to use an independent sample-and-hold chip (T / H chip) in conjunction with a high-speed ADC sub-chip to achieve high-frequency performance. The T / H+ADC structure is used to realize module-level RF sampling function, that is, to convert high-speed changing signals into slowly changing signals and send them to a low-bandwidth high-speed ADC for sampling. However, this is based on a fully packaged chip to build a T / H+multi-ADC structure acquisition system on the board level. The PCB design and wiring are complex, the reliability is low, the power consumption is high, and the length of the interconnecting cables between chips will cause delay, capacitance and other factors, which are detrimental to high-frequency signal transmission. The complete enclosure of the interconnecting cables between chips reduces the security of information transmission.

[0004] Therefore, there is an urgent need for a simple and efficient ultra-high-speed broadband analog-to-digital conversion technology solution. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an ultra-high-speed broadband analog-to-digital converter technology solution. This application utilizes existing sample-and-hold chips and analog-to-digital converter chips to design an ultra-high-speed analog-to-digital converter with higher analog input bandwidth, so as to make up for the defects of traditional design methods, and to optimize and improve its key indicators with a matching test and correction algorithm.

[0006] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0007] A system-in-package analog-to-digital converter chip, comprising:

[0008] A substrate, including a front side and a back side disposed opposite to each other;

[0009] A sample-and-hold sub-chip is disposed on the front side of the substrate and is used to sample and hold analog signals. Its input terminal is electrically led out from the back side of the substrate.

[0010] A coupling capacitor is disposed on the front side of the substrate, with one end connected to the output terminal of the sample-and-hold sub-chip;

[0011] A time-interleaved analog-to-digital converter sub-chip is disposed on the front side of the substrate. Its input terminal is connected to the other end of the coupling capacitor. It performs time-interleaved analog-to-digital conversion on the coupled and isolated analog signal to obtain and output a digital signal. The power supply terminal and the output terminal are electrically led out from the back side of the substrate.

[0012] A plastic encapsulation is disposed on the substrate and provides plastic protection for the sample-and-hold sub-chip, the coupling capacitor, and the time-interleaved analog-to-digital converter sub-chip.

[0013] Optionally, a redistribution layer is provided inside the substrate. The input terminal of the sample-and-hold sub-chip, the power supply terminal of the time-interleaved analog-to-digital converter (ADC) sub-chip, and the output terminal of the time-interleaved ADC sub-chip are electrically led out from the back side of the substrate through the redistribution layer and arranged in a ball-and-socket array on the back side of the substrate. The sample-and-hold sub-chip, the coupling capacitor, and the time-interleaved ADC sub-chip are respectively bonded and disposed on the front side of the substrate, and the redistribution layer realizes the electrical connection between the sample-and-hold sub-chip and the coupling capacitor, and the electrical connection between the coupling capacitor and the time-interleaved ADC sub-chip, respectively.

[0014] Optionally, the system-in-package analog-to-digital converter chip further includes:

[0015] A metal heat sink is disposed on the plastic encapsulation.

[0016] A system-in-package analog-to-digital converter chip testing system includes:

[0017] Host computer;

[0018] A digital logic processing board, including an FPGA chip, wherein the FPGA chip is connected to the host computer;

[0019] An analog signal source is connected to the host computer; and

[0020] An analog-to-digital converter test board, comprising a system-in-package analog-to-digital converter chip as described above, wherein the system-in-package analog-to-digital converter chip is connected to the FPGA chip and the analog signal source respectively;

[0021] The host computer controls the analog signal source to generate an analog signal; the FPGA chip controls the system-in-package analog-to-digital converter chip to collect the analog signal and perform analog-to-digital conversion on the analog signal to obtain a test digital signal; the FPGA chip receives the test digital signal and uploads it to the host computer; the host computer processes the test digital signal to obtain the mismatch error of the system-in-package analog-to-digital converter chip.

[0022] A system-in-package analog-to-digital converter chip testing method includes the following steps:

[0023] Provide a test system for the above-mentioned system-in-package analog-to-digital converter chip;

[0024] The host computer controls the analog signal source to generate analog signals.

[0025] The host computer and the FPGA chip control the system-in-package analog-to-digital converter chip to acquire the analog signal and perform analog-to-digital conversion on the analog signal to obtain the test digital signal;

[0026] The FPGA chip receives the test digital signal and uploads it to the host computer.

[0027] The host computer processes the test digital signal to obtain the mismatch error of the system-in-package analog-to-digital converter chip.

[0028] By controlling the mismatch error correction register inside the system-in-package analog-to-digital converter chip through the host computer, and combining the mismatch error, the system-in-package analog-to-digital converter chip is subjected to mismatch error correction.

[0029] The system-in-package analog-to-digital converter (ADC) chip, after mismatch error correction, performs analog-to-digital conversion to obtain a corrected digital signal, and then calculates the characteristic parameters of the ADC chip based on the corrected digital signal.

[0030] Optionally, the mismatch error includes at least the misalignment mismatch error, the gain mismatch error, and the time mismatch error.

[0031] Optionally, the system-in-package analog-to-digital converter chip includes m time-interleaved analog-to-digital conversion channels, where m is an integer greater than or equal to 2. The step of processing the test digital signal through the host computer to obtain the mismatch error of the system-in-package analog-to-digital converter chip includes:

[0032] For each of the analog-to-digital conversion channels, the mean value of the accumulated average of the test digital signals is calculated to obtain the mismatch error of the analog-to-digital conversion channel;

[0033] Choose any one of the analog-to-digital conversion channels as a reference channel, calculate the ratio of the average power of the test digital signal in the other analog-to-digital conversion channels to the average power of the reference channel, calculate the square root of the average power ratio, and obtain the gain mismatch error of the other analog-to-digital conversion channels relative to the reference channel.

[0034] Optionally, the step of processing the test digital signal through the host computer to obtain the mismatch error of the system-in-package analog-to-digital converter chip further includes:

[0035] For the m analog-to-digital conversion channels, the time value of each analog-to-digital conversion channel is calculated using a fast Fourier transform algorithm based on the test digital signal, and the relative time error between any two adjacent analog-to-digital conversion channels is calculated.

[0036] For the m analog-to-digital conversion channels, compare E i(i+1) With E (i+1)(i+2) Adjust the time error of the (i+2)th analog-to-digital conversion channel so that E i(i+1) With E (i+1)(i+2) Equal, E i(i+1) This represents the relative time error between the (i+1)th analog-to-digital conversion channel and the ith analog-to-digital conversion channel; compare E (m-1)m With E m1 Adjust the time error of the 2nd to mth analog-to-digital conversion channels respectively, so that E 12 =E 23 =E 34 =E (m-1)m =E m1 =E T The time mismatch error of the j-th analog-to-digital conversion channel relative to the first analog-to-digital conversion channel is calculated using the relative time error and the time error, where i is an integer from 1 to m-2 and j is an integer from 2 to m.

[0037] Optionally, the characteristic parameters include at least the signal-to-noise ratio, spurious-free dynamic range, and effective number of bits.

[0038] As described above, the system-in-package analog-to-digital converter chip and its testing system and method provided by the present invention have at least the following beneficial effects:

[0039] Based on existing sample-and-hold sub-chips, coupling capacitors, and time-interleaved analog-to-digital converter (ADC) sub-chips, a system-in-package (SoC) analog-to-digital converter (ADC) chip is designed. This chip-level integrated system, based on bare chips, offers a more compact overall device layout and smaller size compared to traditional board-level integrated systems. The shorter interconnect lengths between sub-chips mitigate adverse effects such as latency, capacitance, and parasitic effects, improving data transmission speed and enhancing information transmission security through complete enclosure. High performance and low power consumption overcome the complex layout and wiring challenges of PCB design, improving chip reliability. Furthermore, the sample-and-hold sub-chip increases sampling input bandwidth, and the time-interleaved architecture of the time-interleaved ADC sub-chip improves ADC processing speed. Combined with a SoC testing system and methods, mismatch errors between channels in the SoC are corrected, effectively improving the SoC's ADC accuracy and efficiency. The SoC has a wide range of applications. Attached Figure Description

[0040] Figure 1 The diagram shown is a structural schematic of the system-in-package analog-to-digital converter chip in this invention.

[0041] Figure 2 The diagram shown is a structural block diagram of the system-in-package analog-to-digital converter chip testing system of the present invention.

[0042] Figure 3 The diagram shows the steps of the system-in-package analog-to-digital converter chip testing method in this invention.

[0043] Figures 4-5 Displayed as Figure 3 Flowchart of the calculation process for correcting mismatch error. Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] Please see Figures 1 to 5It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0046] As mentioned in the background section, the inventors have discovered that there are generally two technical approaches to improve the sampling rate of ADC chips: one is to start with existing chips and use the relatively mature time-alternating technique, but its drawback is that it introduces system mismatch error, and the analog input bandwidth of the system is still limited by the analog bandwidth of a single ADC chip; the other is to use independent sample-and-hold chips in conjunction with high-speed ADC sub-chips to achieve high-frequency performance, and to use a T / H+ADC structure to realize module-level RF sampling function. However, this is a T / H+ multi-ADC structure acquisition system built on the board level based on already packaged chips. The PCB design and wiring are complex, the reliability is low, the power consumption is high, and the length of the interconnecting cables between chips will cause delay, capacitance and other factors, which are detrimental to high-frequency signal transmission. The complete enclosure of the interconnecting cables between chips reduces the security of information transmission.

[0047] Based on this, the present invention provides an ultra-high-speed broadband analog-to-digital converter (ADC) technology solution: adopting a system-in-package (SoC) architecture, an ultra-high-speed ADC chip with higher analog input bandwidth is designed through a sample-and-hold chip and an ADC chip to make up for the defects of traditional design methods, and a test and correction algorithm is provided to correct the mismatch error of each channel of the ADC chip in order to optimize and improve its key indicators.

[0048] like Figure 1 As shown, the present invention provides a system-in-package analog-to-digital converter chip, which includes:

[0049] Substrate 1 includes a front side and a back side disposed opposite to each other;

[0050] The sample-and-hold sub-chip 2 is disposed on the front side of the substrate 1 and is used to sample and hold analog signals. Its input terminal is electrically led out from the back side of the substrate 1.

[0051] Coupling capacitor 3 is disposed on the front side of substrate 1, with one end connected to the output terminal of sample-and-hold sub-chip 2 (not shown in the figure);

[0052] The time-interleaved analog-to-digital converter sub-chip 4 is disposed on the front side of the substrate 1. Its input terminal is connected to the other end of the coupling capacitor 3 (not shown in the figure). It performs time-interleaved analog-to-digital conversion on the coupled and isolated analog signal to obtain and output a digital signal. The power supply terminal and the output terminal are electrically led out from the back side of the substrate 1.

[0053] A plastic encapsulation 5 is disposed on the substrate 1 and provides plastic protection for the sample-and-hold sub-chip 2, the coupling capacitor 3, and the time-interleaved analog-to-digital converter sub-chip 4.

[0054] In detail, such as Figure 1 As shown, a redistribution layer (not shown) is provided inside the substrate 1. The input terminal of the sample-and-hold sub-chip 2, the power supply terminal of the time-interleaved analog-to-digital converter sub-chip 4, and the output terminal of the time-interleaved analog-to-digital converter sub-chip 4 are electrically led out from the back side of the substrate 1 through the redistribution layer and arranged in a ball grid array on the back side of the substrate 1. The sample-and-hold sub-chip 2, the coupling capacitor 3, and the time-interleaved analog-to-digital converter sub-chip 4 are respectively bonded and disposed on the front side of the substrate 1, and the electrical connection between the sample-and-hold sub-chip 2 and the coupling capacitor 3, and the electrical connection between the coupling capacitor 3 and the time-interleaved analog-to-digital converter sub-chip 4 are respectively realized through the redistribution layer.

[0055] More in detail, such as Figure 1 As shown, bare chips or components such as sample-and-hold sub-chip 2, coupling capacitor 3, and time-interleaved analog-to-digital converter sub-chip 4 are integrated in the plastic cavity formed by the plastic package 5 and the substrate 1 to form a system-in-package analog-to-digital converter chip. The package adopts the form of plastic BGA, based on a high thermal conductivity plastic package + copper-plated packaging scheme, with balls on the back and bare chips placed on the front and fixed by bonding wires.

[0056] In detail, such as Figure 1 As shown, the system-in-package analog-to-digital converter chip also includes:

[0057] A metal heat sink 7 is disposed on the plastic package 5 to improve the external heat dissipation capability of the system-in-package analog-to-digital converter chip.

[0058] In detail, such as Figure 1As shown, a system-in-a-package (SIP) analog-to-digital converter chip is designed based on the existing sample-and-hold sub-chip 2, coupling capacitor 3, and time-interleaved analog-to-digital converter sub-chip 4. It is a chip-level integrated system based on bare chips. Compared with traditional board-level integrated systems, its overall device layout is more compact, the size is smaller, and the interconnection length between sub-chips is shortened, which can reduce the adverse effects of delay, capacitance, and parasitic effects, improve data transmission speed and information transmission security brought by complete enclosure; it has high performance and low power consumption, which can overcome the complex layout and wiring in circuit board design and improve chip reliability.

[0059] More in detail, such as Figure 1 As shown, a broadband high-speed analog-to-digital converter is implemented at the system-in-package (SIP) level by combining bare chips or components such as sample-and-hold sub-chip 2, coupling capacitor 3, and time-interleaved analog-to-digital converter sub-chip 4. Sample-and-hold sub-chip 2 realizes the reception and conversion of broadband input signals, which is used to expand the analog input bandwidth of the subsequent time-interleaved analog-to-digital converter sub-chip 4. The time-interleaved analog-to-digital converter sub-chip 4 adopts a time-interleaved architecture to realize high-speed analog-to-digital conversion of input analog signals.

[0060] At the same time, such as Figure 2 As shown, the present invention also provides a system-in-package analog-to-digital converter chip testing system, which includes:

[0061] Host computer;

[0062] Digital logic processing board, including FPGA chip, which is connected to host computer;

[0063] Analog signal source, connected to host computer; and

[0064] The analog-to-digital converter test board includes a system-in-package (SIPP) analog-to-digital converter chip, which is connected to the FPGA chip and the analog signal source respectively.

[0065] Among them, the host computer controls the analog signal source to generate a pure, low-noise, low-harmonic analog signal V. A FPGA chip controls the system-level packaged analog-to-digital converter chip to acquire analog signal V A And for the analog signal V A Perform analog-to-digital conversion to obtain the test digital signal V. D The FPGA chip receives the test digital signal V. D And upload it to the host computer; the host computer tests the digital signal V. D The process is performed to obtain the mismatch error of the system-in-package analog-to-digital converter chip.

[0066] In detail, such as Figure 2As shown, the digital logic processing board and analog-to-digital converter test board used for data acquisition during testing are both circuit board-based board structures that support plug-and-play. The analog-to-digital converter test board is hardware-connected to the digital logic processing board. The system-in-package analog-to-digital converter chip test system also includes a DC power supply that provides the operating voltage and a clock signal source that provides the control clock. The FPGA chip is connected to the host computer via a USB cable, and each chip is connected to each signal source via a cable. For details, please refer to the prior art, which will not be repeated here.

[0067] It should be noted that in the analog-to-digital converter test board, the system-in-package (SoC) SoC chip under test is detachably mounted on the circuit board. It can be continuously removed and replaced to meet the testing needs of multiple different SoC chips under test, which will not be elaborated further here.

[0068] The system-in-package analog-to-digital converter chip testing system involved in this invention uses an FPGA-based digital logic processing board for multi-channel sampling data storage, eliminating the need to connect to instruments such as logic analyzers for data storage. The system is small in size and low in cost.

[0069] Furthermore, based on the aforementioned system-in-package analog-to-digital converter (SoC) and its testing system, this invention also provides a method for testing the SoC, such as... Figure 3 As shown, it includes the following steps:

[0070] S1. Provide a test system for the above-mentioned system-in-package analog-to-digital converter chip;

[0071] S2. The host computer controls the analog signal source to generate analog signals;

[0072] S3. Through the host computer and FPGA chip, the system-level packaged analog-to-digital converter chip is controlled to acquire analog signals and perform analog-to-digital conversion on the analog signals to obtain test digital signals.

[0073] S4. Receive test digital signals and upload them to the host computer via the FPGA chip;

[0074] S5. The test digital signal is processed by the host computer to obtain the mismatch error of the system-in-package analog-to-digital converter chip;

[0075] S6. By controlling the mismatch error correction register inside the system-in-package analog-to-digital converter chip through the host computer, and combining the mismatch error, the system-in-package analog-to-digital converter chip is mismatched and corrected.

[0076] S7. Perform analog-to-digital conversion using the system-in-package analog-to-digital converter chip after mismatch error correction to obtain the corrected digital signal, and calculate the characteristic parameters of the system-in-package analog-to-digital converter chip based on the corrected digital signal.

[0077] In detail, in the above-mentioned system-in-package (SiP) analog-to-digital converter (ADC) chip testing method, steps S1 to S4 mainly involve acquiring the SiP ADC test data and controlling the operating mode of the SiP ADC chip via a host computer. In step S5, the host computer uses a mismatch error correction algorithm to process the test digital signal and obtain the mismatch error of the SiP ADC chip. In step S6, the calculated mismatch error is saved to the internal mismatch error correction register of the SiP ADC chip. During subsequent analog-to-digital conversion, the mismatch error in the register is called and used in conjunction with the digital signal received by the host computer to correct the mismatch error of the digital signal output by the SiP ADC chip. In step S7, the SiP ADC chip with the corrected mismatch error is used for analog-to-digital conversion to obtain a corrected digital signal. The characteristic parameters of the SiP ADC chip are calculated based on the corrected digital signal, and the values ​​of the characteristic parameters are used to determine whether the SiP ADC chip with the corrected mismatch error meets the design requirements.

[0078] The mismatch error includes at least offset mismatch error, gain mismatch error, and timing mismatch error; the system-in-package analog-to-digital converter chip includes m time-interleaved analog-to-digital conversion channels, where m is an integer greater than or equal to 2, such as... Figure 4 The diagram shows m analog-to-digital conversion channels, ADC1, ..., ADC2. m .

[0079] In the aforementioned system-in-package (SiP) analog-to-digital converter (ADC) chip testing system, after configuring the operating mode of the SiP ADC chip using the host computer software, the host computer software triggers and acquires data from multiple channels of the SiP ADC chip, and then saves the acquired data in an Excel file on the host computer. In Matlab software, an error correction algorithm is used to process the data in the Excel file to calculate three types of mismatch errors. Based on the calculated three types of mismatch errors, a digital control word (DCW) is calculated, and the host computer transmits it to the error correction register inside the SiP ADC chip via the SPI interface for error correction.

[0080] In detail, step S5, which processes the test digital signal through a host computer to obtain the mismatch error of the system-in-package analog-to-digital converter chip, further includes:

[0081] S51, such as Figure 4As shown, for each analog-to-digital conversion channel, the mean value of the accumulated and averaged test digital signals is calculated to obtain the mismatch error P of the analog-to-digital conversion channel. i where i is a value from 1 to m;

[0082] S52, such as Figure 4 As shown, select any analog-to-digital conversion channel as the reference channel (such as ADC1), calculate the ratio of the average power of the test digital signal in the other analog-to-digital conversion channels to that in the reference channel, calculate the square root of the average power ratio (Sqrt), and obtain the gain mismatch error of the other analog-to-digital conversion channels relative to the reference channel.

[0083] More in detail, Figure 4 In the diagram, f(t) is the input analog signal, and ADC1 to ADC2 are... m For m parallel analog-to-digital conversion channels, f1[m]~f m [m] represents the digital signal obtained after analog-to-digital conversion; the mismatch error of the analog-to-digital conversion channel is calculated in step S51, and the gain mismatch error of the analog-to-digital conversion channel relative to the reference channel is calculated in step S52.

[0084] In detail, step S5, which processes the test digital signal through a host computer to obtain the mismatch error of the system-in-package analog-to-digital converter chip, also includes:

[0085] S53. For m analog-to-digital conversion channels, calculate the time value of each analog-to-digital conversion channel using the Fast Fourier Transform algorithm based on the test digital signal, and calculate the relative time error between any two adjacent analog-to-digital conversion channels.

[0086] S54. For m analog-to-digital conversion channels, compare E i(i+1) With E (i+1)(i+2) Adjust the time error of the (i+2)th analog-to-digital conversion channel so that E i(i+1) With E (i+1)(i+2) Equal, E i(i+1) This represents the relative time error between the (i+1)th analog-to-digital conversion channel and the ith analog-to-digital conversion channel; compare E (m-1)m With E m1 Adjust the time error of the 2nd to mth analog-to-digital conversion channels respectively, so that E 12 =E 23 =E 34 =E (m-1)m =E m1 =E T The time mismatch error of the j-th analog-to-digital conversion channel relative to the first analog-to-digital conversion channel is calculated by the relative time error and the time error, where i is an integer from 1 to m-2 and j is an integer from 2 to m.

[0087] More specifically, in an optional embodiment of the invention, such as Figure 5 As shown, the value of m is set to 4, meaning the system-in-package analog-to-digital converter chip includes 4 time-interleaved analog-to-digital conversion channels, as shown in the figure. Figure 5 For the analog-to-digital conversion channels 1, 2, 3, and 4 shown, the steps S53 to S54 for calculating the time mismatch error can be specified as follows:

[0088] Stp1: Calculate the time (phase) value of each analog-to-digital conversion channel using the Fast Fourier Transform (FFT) algorithm, and calculate the relative time error E between any two adjacent analog-to-digital conversion channels. 12 E 23 E 34 and E 41 ;

[0089] Stp2, Compare E 12 With E 23 Adjust the time error delta_3 of the third analog-to-digital conversion channel 3 so that E 12 With E 23 equal;

[0090] Stp3, Comparison E 23 With E 34 Adjust the time error delta_4 of the fourth analog-to-digital conversion channel 4 so that E 23 With E 34 equal;

[0091] Stp4, Comparison E 34 With E 41 Adjust the time error delta_2 of the second analog-to-digital conversion channel 2, and simultaneously adjust the time error delta_31 of the third analog-to-digital conversion channel 3 and the time error delta_41 of the fourth analog-to-digital conversion channel 4, until E 12 =E 23 =E 34 =E 41 =E T ;

[0092] Stp5. Calculate the time mismatch error of other analog-to-digital conversion channels relative to the first analog-to-digital conversion channel 1 using relative time error and time error. For example, the formula for calculating the time mismatch error of the second analog-to-digital conversion channel 2 relative to the first analog-to-digital conversion channel 1 is E. 12 +delta_2-E T And so on.

[0093] In an optional embodiment of the present invention, the performance of the system-in-package (SiP) analog-to-digital converter (ADC) chip is tested. The SiP chip is required to achieve a broadband signal input of 14.5 GHz, a sampling rate of 6 GHz in single-channel mode, and an effective bit depth of 7.5 bits. The chip is selected based on the clock jitter requirements of the sample-and-hold sub-chip 2. After the SiP chip is connected to the test system, a sinusoidal analog signal with a starting frequency of 100 MHz is input. The output sampled data is received and stored by the digital logic processing board and then transmitted to the host computer. The fundamental power P1 of the signal is calculated. The input frequency of the analog signal is gradually increased until the fundamental power P1 changes by -3 dB. The analog input bandwidth of the SiP chip can reach 14.5 GHz. The corresponding sampled data is directly calculated in the host computer's computing software, such as Matlab, which greatly shortens the test time and test development cycle.

[0094] This invention utilizes SiP (System-in-Package) packaging to extend the analog input bandwidth and double the sampling rate of a system-in-package (SiP) analog-to-digital converter (ADC). Combined with an efficient testing system and mismatch error correction algorithm, it achieves prototype verification and key performance testing of a high-speed broadband SiP ADC. Test results show that the advanced SiP packaging architecture, combined with the advanced mismatch error correction algorithm and the advanced testing system, yields advanced technical specifications.

[0095] In summary, the system-in-package (SiP) analog-to-digital converter (ADC) chip and its testing system and method provided by this invention, based on existing bare chips or components, achieves a more compact overall device layout and smaller size compared to traditional board-level integrated systems. The shorter interconnect length between sub-chips reduces adverse effects such as latency, capacitance, and parasitic effects, and improves data transmission speed. Simultaneously, the sample-and-hold sub-chip increases the sampling input bandwidth, and the time-interleaving architecture of the time-interleaving ADC sub-chip improves the sampling rate and processing speed of the ADC. Furthermore, the SiP testing system and method correct mismatch errors between channels in the SiP ADC chip, ensuring the ADC accuracy and efficiency of the time-interleaved ADC sub-chip. This simple and efficient implementation of a high-bandwidth, ultra-high-speed ADC achieves a superior solution.

[0096] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A system-in-package analog-to-digital converter chip testing system, characterized in that, include: Host computer; A digital logic processing board, including an FPGA chip, wherein the FPGA chip is connected to the host computer; An analog signal source is connected to the host computer. And an analog-to-digital converter test board, including a system-in-package analog-to-digital converter chip, wherein the system-in-package analog-to-digital converter chip is connected to the FPGA chip and the analog signal source respectively; The host computer controls the analog signal source to generate an analog signal; the FPGA chip controls the system-in-package analog-to-digital converter chip to collect the analog signal and perform analog-to-digital conversion on the analog signal to obtain a test digital signal; the FPGA chip receives the test digital signal and uploads it to the host computer; the host computer processes the test digital signal to obtain the mismatch error of the system-in-package analog-to-digital converter chip. The system-in-package analog-to-digital converter chip includes a sample-and-hold sub-chip, a coupling capacitor, and a time-interleaved analog-to-digital converter sub-chip. The sample-and-hold sub-chip is used to sample and hold analog signals. One end of the coupling capacitor is connected to the output terminal of the sample-and-hold sub-chip, and the other end of the coupling capacitor is connected to the input terminal of the time-interleaved analog-to-digital converter chip. The time-interleaved analog-to-digital converter chip performs time-interleaved analog-to-digital conversion on the coupled and isolated analog signal to obtain and output a digital signal. The mismatch error includes at least the misalignment error, gain mismatch error, and time mismatch error.

2. A method for testing a system-in-package analog-to-digital converter chip, characterized in that, Including the following steps: Provide a system-in-package analog-to-digital converter chip testing system as described in claim 1; The host computer controls the analog signal source to generate analog signals. The host computer and the FPGA chip control the system-in-package analog-to-digital converter chip to acquire the analog signal and perform analog-to-digital conversion on the analog signal to obtain the test digital signal; The FPGA chip receives the test digital signal and uploads it to the host computer. The host computer processes the test digital signal to obtain the mismatch error of the system-in-package analog-to-digital converter chip. By controlling the mismatch error correction register inside the system-in-package analog-to-digital converter chip through the host computer, and combining the mismatch error, the system-in-package analog-to-digital converter chip is subjected to mismatch error correction. The system-in-package analog-to-digital converter (ADC) chip, after mismatch error correction, performs analog-to-digital conversion to obtain a corrected digital signal, and then calculates the characteristic parameters of the ADC chip based on the corrected digital signal.

3. The system-in-package analog-to-digital converter chip testing method according to claim 2, characterized in that, The system-in-package analog-to-digital converter chip includes m time-interleaved analog-to-digital conversion channels, where m is an integer greater than or equal to 2. The step of processing the test digital signal through the host computer to obtain the mismatch error of the system-in-package analog-to-digital converter chip includes: For each of the analog-to-digital conversion channels, the mean value of the accumulated average of the test digital signals is calculated to obtain the mismatch error of the analog-to-digital conversion channel; Choose any one of the analog-to-digital conversion channels as a reference channel, calculate the ratio of the average power of the test digital signal in the other analog-to-digital conversion channels to the average power of the reference channel, calculate the square root of the average power ratio, and obtain the gain mismatch error of the other analog-to-digital conversion channels relative to the reference channel.

4. The system-in-package analog-to-digital converter chip testing method according to claim 3, characterized in that, The step of processing the test digital signal through the host computer to obtain the mismatch error of the system-in-package analog-to-digital converter chip further includes: For the m analog-to-digital conversion channels, the time value of each analog-to-digital conversion channel is calculated using a fast Fourier transform algorithm based on the test digital signal, and the relative time error between any two adjacent analog-to-digital conversion channels is calculated. For the m analog-to-digital conversion channels, compare E i(i+1) With E (i+1)(i+2) Adjust the time error of the (i+2)th analog-to-digital conversion channel so that E i(i+1) With E (i+1)(i+2) Equal, E i(i+1) This represents the relative time error between the (i+1)th analog-to-digital conversion channel and the ith analog-to-digital conversion channel; compare E (m-1)m With E m1 Adjust the time error of the 2nd to mth analog-to-digital conversion channels respectively, so that E 12 =E 23 =E 34 =E (m-1)m =E m1 =E T The time mismatch error of the j-th analog-to-digital conversion channel relative to the first analog-to-digital conversion channel is calculated using the relative time error and the time error, where i is an integer from 1 to m-2 and j is an integer from 2 to m.

5. The system-in-package analog-to-digital converter chip testing method according to claim 4, characterized in that, The characteristic parameters include at least the signal-to-noise ratio, spurious-free dynamic range, and effective number of bits.

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