Three-dimensional semiconductor structure and preparation method thereof

Abstract

The present application provides a three-dimensional semiconductor structure and a preparation method thereof, which relates to the field of semiconductor technology, in order to solve the technical problem that the characterization method of the uniformity of the thickness of the capacitor film is difficult. The three-dimensional semiconductor structure includes a substrate; a stacking structure, located on the substrate, the stacking structure includes a capacitor structure, the capacitor structure includes a first electrode, a dielectric layer and a plurality of second electrodes, the first electrode extends along a first direction, and the plurality of second electrodes are sequentially stacked and arranged at intervals along the first direction, and a support layer is arranged between two adjacent second electrodes; a test structure, located on the stacking structure, the test structure includes a first test pad and a plurality of second test pads, the first test pad is electrically connected to the first electrode, and the plurality of second test pads are arranged corresponding to the plurality of second electrodes, wherein one second test pad is electrically connected to at least one second electrode; the test structure is configured to test the voltage of the capacitor structure. The present application can reduce the difficulty of characterizing the uniformity of the thickness of the capacitor film.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a three-dimensional semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device, which includes many repeated memory cells. Each memory cell usually includes a transistor and a capacitor, and the gate of the transistor is connected to the word line (WL), the drain is connected to the bit line (BL), and the source is connected to the capacitor.

[0003] With the continuous development of semiconductor chips, their critical dimensions are constantly decreasing, and the thickness of the capacitor film material in the capacitor is getting thinner and thinner. The leakage of the capacitor is exponentially related to the thickness of the capacitor film. A small thickness difference of the capacitor film will lead to a large leakage difference. Therefore, the characterization of the thickness uniformity of the capacitor film is particularly important.

[0004] However, in the related art, there is a technical problem that the characterization method of the uniformity of the thickness of the capacitor film is difficult. Summary of the invention

[0005] In view of the above problems, the embodiments of the present application provide a three-dimensional semiconductor structure and a method for preparing the same, which can characterize the thickness of the capacitor film by testing the voltage, thereby reducing the difficulty of characterizing the uniformity of the thickness of the capacitor film.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] A first aspect of an embodiment of the present application provides a three-dimensional semiconductor structure, including:

[0008] substrate;

[0009] A stacking structure, the stacking structure is located on the substrate, the stacking structure includes a capacitor structure, the capacitor structure includes a first electrode, a dielectric layer and a plurality of second electrodes, the first electrode extends along a first direction, the plurality of second electrodes are sequentially stacked and spaced along the first direction, and a support layer is provided between any two adjacent second electrodes;

[0010] A test structure, wherein the test structure is located on the stacked structure, the test structure includes a first test pad and a plurality of second test pads, the first test pad is electrically connected to the first electrode, and the plurality of second test pads are arranged corresponding to the plurality of second electrodes, wherein at least one of the second test pads is electrically connected to one of the second electrodes; the test structure is configured to test the voltage of the capacitor structure.

[0011] The three-dimensional semiconductor structure provided by the embodiment of the present application is provided with a test structure on the stacked structure, and the first test pad in the test structure is electrically connected to the first electrode in the capacitor structure, and the multiple second test pads in the test structure are electrically connected to the multiple second electrodes in the capacitor structure. In this way, the test structure can test the leakage conditions at different positions of the capacitor structure, so that the uniformity of the film thickness in the capacitor can be characterized by the leakage size at different positions of the capacitor structure. The structure and the characterization method are simple and easy to implement.

[0012] In some optional embodiments, the stacking structure also includes a contact structure, which includes a first contact pad and a plurality of second contact pads, the first contact pad is connected between the first electrode and the first test pad; the second contact pad is connected between the second electrode and the second test pad, and an isolation structure is arranged between adjacent second contact pads.

[0013] By setting a contact structure in the stacked structure, the first contact pad in the contact structure realizes the electrical connection between the first electrode and the first test pad, and the second contact pad realizes the electrical connection between the second electrode and the second test pad. In this way, the leakage conditions of the capacitor structure at different height positions can be tested through the test structure subsequently, so as to obtain the characterization of the uniformity of the film thickness of the capacitor structure according to the leakage size of the capacitor structure, thereby reducing the difficulty of characterizing the uniformity of the film thickness in the capacitor structure.

[0014] In some optional embodiments, each of the second contact pads extends along the first direction, so that each of the second contact pads is vertically connected to its corresponding second electrode.

[0015] In this way, the stacked structure can achieve a smaller feature size, which is beneficial to reducing the overall size of the three-dimensional semiconductor structure.

[0016] In some optional embodiments, there are multiple capacitor structures, and the multiple capacitor structures are spaced apart along a second direction in the stacked structure, and an isolation layer is arranged between adjacent capacitor structures, wherein the second direction is perpendicular to the first direction.

[0017] In this way, the arrangement of the capacitor structure can be better and the volume can be smaller, which is conducive to increasing the number of arranged capacitor structures, thereby improving the storage density of the three-dimensional semiconductor structure.

[0018] In some optional implementations, a plurality of the capacitor structures are arranged in parallel.

[0019] In this way, the resolution of the three-dimensional semiconductor structure can be maximized.

[0020] In some optional embodiments, a first opening is provided on the stack structure and penetrates the stack structure along the first direction, the dielectric layer and the first electrode are located in the first opening, and the dielectric layer is located between the side wall of the first electrode and the inner wall of the first opening.

[0021] In this way, the arrangement between the first electrode and the dielectric layer can be more optimized and the volume can be smaller, which is beneficial to increase the number of arranged capacitor structures, thereby improving the storage density of the three-dimensional semiconductor structure.

[0022] In some optional embodiments, the plurality of second electrodes are arranged in sequence in a stepped manner from a direction close to the substrate to a direction away from the substrate.

[0023] In this way, the space occupied by the multiple second electrodes can be reduced, which is beneficial to reducing the characteristic size of the three-dimensional semiconductor structure while improving the storage density of the three-dimensional semiconductor structure.

[0024] A second aspect of an embodiment of the present application provides a method for preparing a three-dimensional semiconductor structure, comprising:

[0025] providing a substrate;

[0026] A stacking structure is formed on the substrate; the stacking structure includes a capacitor structure, the capacitor structure includes a first electrode, a dielectric layer and a plurality of second electrodes, the first electrode extends along a first direction, the plurality of second electrodes are sequentially stacked and spaced along the first direction, and a support layer is provided between any two adjacent second electrodes;

[0027] A test structure is formed on the stacked structure; the test structure includes a first test pad and a plurality of second test pads, the first test pad is electrically connected to the first electrode, and the plurality of second test pads are arranged corresponding to the plurality of second electrodes, wherein at least one of the second test pads is electrically connected to one of the second electrodes.

[0028] The method for preparing a three-dimensional semiconductor structure provided in an embodiment of the present application forms a test structure on a stacked structure, and electrically connects a first test pad in the test structure to a first electrode in a capacitor structure, and electrically connects a plurality of second test pads in the test structure to a plurality of second electrodes in the capacitor structure. In this way, the test structure can test the leakage conditions at different positions of the capacitor structure, so that the uniformity of the film thickness in the capacitor can be characterized by the leakage values ​​at different positions of the capacitor structure. The structure and the characterization method are simple and easy to implement.

[0029] In some optional embodiments, before the step of forming a stacked structure on the substrate and after the step of providing the substrate, the method further comprises:

[0030] forming a plurality of preset layers stacked on the substrate;

[0031] The plurality of preset layers include supporting layers and sacrificial layers which are alternately stacked in sequence.

[0032] In this way, it is convenient for subsequent processes to form a stacked structure on the preset layer.

[0033] In some optional embodiments, the step of forming a stacked structure on the substrate includes:

[0034] A plurality of first openings are formed in the preset layer and are spaced apart along the second direction; the first openings extend along the first direction and penetrate the preset layer;

[0035] A dielectric layer and a first electrode are sequentially formed in the first opening; wherein the dielectric layer is arranged around an outer side wall of the first electrode;

[0036] Removing the sacrificial layer in the preset layer and forming a first slit;

[0037] A second electrode is formed in the first slit.

[0038] In this way, on the one hand, the difficulty of preparing the second electrode in the three-dimensional semiconductor structure is reduced; on the other hand, multiple second electrodes in the capacitor structure can be arranged in sequence along the stacking direction of the stacking structure, thereby achieving a three-dimensional semiconductor structure with smaller characteristic dimensions and greater storage density.

[0039] In some optional implementations, before the step of removing the sacrificial layer in the preset layer and forming the first slit, the method further includes:

[0040] Part of the preset layer is removed to form a plurality of second slits spaced apart along a second direction, wherein the second slits penetrate the preset layer, and two adjacent first openings are located at opposite sides of the second slits.

[0041] In this way, it is convenient to remove the sacrificial layer in the preset layer through the second slit later, thereby reducing the difficulty of preparing the second electrode.

[0042] In some optional embodiments, the step of forming the second electrode in the first slit includes:

[0043] Filling a second electrode layer in the first slit;

[0044] forming an isolation layer in the second slit;

[0045] Parts of the support layer and the second electrode layer are removed along the second direction to expose the surface of each second electrode layer facing away from the substrate, and the remaining second electrode layer forms the second electrode.

[0046] In this way, the plurality of second electrodes can be arranged in a stepped manner, which can reduce the space occupied by the second electrodes, and is conducive to reducing the characteristic size of the three-dimensional semiconductor structure while improving the storage density of the three-dimensional semiconductor structure.

[0047] In some optional embodiments, the step after filling the second electrode layer in the first slit and before forming the isolation layer in the second slit includes:

[0048] The second electrode layer in the second slit is removed.

[0049] In this way, an isolation layer is formed in the second slit in a subsequent process, so that electrical isolation between adjacent capacitor structures can be achieved through the isolation layer.

[0050] In some optional embodiments, after removing a portion of the support layer and the second electrode layer along the second direction to expose the surface of each second electrode layer facing away from the substrate, and the retained second electrode layer forms the second electrode, the method further comprises:

[0051] forming an oxide layer on the remaining support layer and the second electrode;

[0052] forming a second opening and a plurality of third openings on the oxide layer, wherein the second opening exposes the first electrode, and the third opening exposes the second electrode; wherein at least one of the third openings corresponds to one of the second electrodes; and the oxide layer retained between adjacent third openings forms the isolation structure;

[0053] A first contact pad is formed in the second opening; a second contact pad is formed in the third opening; and the first contact pad and the second contact pad form a contact structure.

[0054] In this way, the capacitor structure is conveniently electrically connected to a test structure formed in a subsequent process through the first contact pad and the second contact pad.

[0055] In some optional embodiments, the step of forming a test structure on the stacked structure includes:

[0056] forming a metal layer on the stacked structure;

[0057] Part of the metal layer is removed, and the metal layers corresponding to the first contact pad and the second contact pad are retained respectively; wherein the metal layer corresponding to the first contact pad forms the first test pad, and the metal layer corresponding to the second contact pad forms the second test pad; the first test pad and the second test pad form the test structure.

[0058] In this way, by subsequently applying a test voltage to the first test pad and the second test pad, the leakage conditions at different positions of the capacitor structure can be obtained, thereby obtaining a characterization of the uniformity of the film thickness of the capacitor structure according to the leakage size of the capacitor structure, thereby reducing the difficulty of characterizing the uniformity of the film thickness in the capacitor structure.

[0059] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the three-dimensional semiconductor structure and the preparation method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0061] Figure 1 A schematic diagram of the structure of a three-dimensional semiconductor structure provided in an embodiment of the present application;

[0062] Figure 2 for Figure 1 Schematic diagram of the half-section structure at AA in the middle;

[0063] Figure 3 for Figure 2 A partial enlarged schematic diagram of point B in the middle;

[0064] Figure 4 A schematic diagram of a process for preparing a three-dimensional semiconductor structure provided in an embodiment of the present application;

[0065] Figure 5 for Figure 4 Schematic diagram of the process of step S103;

[0066] Figure 6 for Figure 4 Schematic diagram of the process of step S104;

[0067] Figures 7 to 17 A half-section structural schematic diagram of the formation process of a three-dimensional semiconductor structure provided in an embodiment of the present application.

[0068] Reference numerals:

[0069] 100-three-dimensional semiconductor structure; 10-substrate; 20-stacked structure; 21-capacitor structure;

[0070] 211 - first electrode; 212 - second electrode; 213 - dielectric layer; 22 - preset layer;

[0071] 221 - support layer; 222 - sacrificial layer; 223 - second slit; 224 - second electrode layer;

[0072] 23 - first opening; 24 - oxide layer; 241 - isolation layer; 25 - contact structure;

[0073] 251 - first contact pad; 252 - second contact pad; 30 - test structure; 301 - first test pad;

[0074] 302 - second test pad; 303 - metal layer; 40 - first mask layer; 41 - second mask layer;

[0075] 43 - mask block; 44 - fourth mask layer. DETAILED DESCRIPTION

[0076] As described in the background technology, in the related art, the uniformity of the film thickness at the top and bottom of the capacitor structure is usually analyzed by means of a transmission electron microscope, however, as the critical dimensions of semiconductor structures continue to decrease, the thickness of DRAM capacitor film materials is very thin, resulting in a problem that it is difficult to characterize the uniformity of the thickness of the films at the top and bottom of the capacitor structure by means of a transmission electron microscope.

[0077] In view of this, the present application provides a three-dimensional semiconductor structure and a preparation method thereof, by setting a test structure on a stacked structure, and electrically connecting a first test pad in the test structure to a first electrode in a capacitor structure, and electrically connecting multiple second test pads in the test structure to multiple second electrodes in the capacitor structure. In this way, the test structure can test the leakage conditions at different positions of the capacitor structure, so that the uniformity of the film thickness in the capacitor can be characterized by the leakage size at different positions of the capacitor structure, and the structure and characterization method are simple and easy to implement.

[0078] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of this application.

[0079] Embodiment 1

[0080] The embodiment of the present application provides a three-dimensional semiconductor structure, which can be a memory device or a non-memory device. The memory device may include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), or a magnetoresistive random access memory (MRAM). The non-memory device may be a logic device (such as a microprocessor, a digital signal processor, or a microcontroller) or a device similar thereto. The embodiment of the present application is described by taking a DRAM memory device as an example.

[0081] Figure 1 A schematic diagram of the structure of a three-dimensional semiconductor structure provided in an embodiment of the present application; Figure 2 for Figure 1 Schematic diagram of the half-section structure at AA in the middle; Figure 3 for Figure 2 The enlarged diagram of the part B in the figure. Please refer to Figures 1 to 3 As shown, the three-dimensional semiconductor structure 100 includes:

[0082] Substrate 10, it can be understood that the substrate 10 can provide a supporting basis for the structural layer on the substrate 10. The substrate 10 can be made of a crystalline semiconductor material, for example, a silicon (Si) substrate, and the substrate 10 can also be a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, etc., wherein the substrate 10 can be a single-layer structure or a multi-layer composite structure, and is adaptively designed according to actual needs, and is not specifically limited here. In the embodiment of the present application, the substrate 10 includes a silicon substrate as an example for introduction.

[0083] The stacked structure 20 is located on the substrate 10. The stacked structure 20 includes a capacitor structure 21. The capacitor structure 21 includes a first electrode 211, a dielectric layer 213, and a plurality of second electrodes 212. The first electrode 211 extends along a first direction. The plurality of second electrodes 212 are sequentially stacked and spaced along the first direction. A support layer 221 is provided between any two adjacent second electrodes 212. The support layer 221 can achieve electrical isolation between adjacent second electrodes 212 to avoid mutual interference between adjacent second electrodes 212.

[0084] It can be understood that a support layer 221 is arranged between any two adjacent second electrodes, and therefore, a plurality of spaced support layers 221 are formed in the stacking structure 20, wherein the thickness of each support layer 221 can be equal, for example, the thickness of all support layers 221 in the stacking structure 20 is equal; of course, in other embodiments, the thickness of each support layer 221 may also be unequal, and can be adaptively designed according to specific needs, and no specific limitation is made here.

[0085] In addition, the dielectric layer 213 can be understood as a thin film structure in the capacitor structure 21, wherein the thickness of the dielectric layer 213 in the stacked structure 20 can also be adaptively designed according to needs, and the density of the second electrode 212 can also be set according to the thickness of the dielectric layer 213. For example, where the dielectric layer 213 is thinner and easily broken down, the second electrode 212 can be set more densely, and where the dielectric layer 213 is thicker, the second electrode 212 can be set more sparsely.

[0086] The first direction may be understood as the stacking direction of the stacking structure 20. For example, when the stacking structure 20 is stacked along the vertical direction, the first direction is the vertical direction. Figure 1 and Figure 2 The Z direction in .

[0087] The capacitor structure 21 in the embodiment of the present application can be understood as a three-dimensional capacitor structure, that is, the capacitor structure 21 includes multiple sub-capacitor structures, the first electrode 211 is a common electrode in the multiple sub-capacitor structures, the first electrode 211, the dielectric layer 213 and a second electrode 212 can form a sub-capacitor structure, so that the multiple second electrodes 212 can respectively form multiple sub-capacitor structures with the dielectric layer 213 and the first electrode 211, and the multiple sub-capacitor structures are stacked in sequence along the first direction. In this way, the storage density of the three-dimensional semiconductor structure 100 can be improved while the characteristic size of the three-dimensional semiconductor structure 100 can be reduced.

[0088] A test structure 30, the test structure 30 is located on the stacked structure 20, the test structure 30 includes a first test pad 301 and multiple second test pads 302, the first test pad 301 is electrically connected to the first electrode 211, and the multiple second test pads 302 are correspondingly arranged to the multiple second electrodes 212, wherein at least one second test pad 302 is electrically connected to a second electrode 212; the test structure 30 is configured to test the voltage of the capacitor structure 21.

[0089] For example, in Figure 1 and Figure 2 In the embodiment, each second test pad 302 has another second test pad 302 with the first test pad as a symmetrical reference, so that the two second test pads 302 arranged opposite to each other are electrically connected to the same second electrode 212 to test the voltage at different positions of the second electrode 212 through different second test pads 302.

[0090] In the above scheme, the test structure 30 is arranged on the stacked structure 20, and the first test pad 301 in the test structure 30 is electrically connected to the first electrode 211 in the capacitor structure 21, and the plurality of second test pads 302 in the test structure 30 are respectively electrically connected to the plurality of second electrodes 212 in the capacitor structure 21. In this way, the test structure 30 can test the leakage magnitude at different positions of the capacitor structure 21, so that the uniformity of the film thickness in the capacitor structure 21 can be characterized through the leakage magnitude at different positions of the capacitor structure 21, and the structure and the characterization method are simple and easy to implement.

[0091] In a specific implementation, a ground voltage can be applied to the first test pad 301 electrically connected to the first electrode 211, and a test voltage can be applied to each second test pad 302 electrically connected to each second electrode 212, so that each capacitor structure 21 is charged; then the actual voltage value between the first electrode 211 and each second electrode 212 is obtained through the first test pad 301 and each second test pad 302, and the actual voltage value obtained is compared with the preset voltage value previously preset. If there is a voltage difference between the detected actual voltage value and the preset voltage value, it means that the capacitor structure 21 has a leakage condition, and the magnitude of the voltage difference can characterize the magnitude of the leakage at different height positions of the capacitor structure 21. Since the magnitude of the leakage of the capacitor structure 21 is exponentially related to the film thickness of the capacitor structure 21, the thickness uniformity of the capacitor structure 21 at different height positions can be characterized by the magnitude of the leakage at different height positions of the capacitor structure 21. The structure is simple and easy to implement, thereby reducing the difficulty of characterizing the uniformity of the film thickness of the capacitor structure 21.

[0092] In some embodiments, please refer to Figure 2As shown, the stacked structure 20 also includes a contact structure 25, and the contact structure 25 includes a first contact pad 251 and a plurality of second contact pads 252, wherein the first contact pad 251 is connected between the first electrode 211 and the first test pad 301, that is, the first electrode 211 and the first test pad 301 are electrically connected through the first contact pad 251; the second contact pad 252 is connected between the second electrode 212 and the second test pad 302, that is, the second electrode 212 and the second test pad 302 are electrically connected through the second contact pad 252; and an isolation structure is provided between any two adjacent second contact pads 252 to achieve electrical isolation between two adjacent second contact pads 252 through the isolation structure.

[0093] In this way, the leakage conditions at different height positions of the capacitor structure 21 can be tested subsequently through the test structure 30, so as to characterize the uniformity of the film thickness of the capacitor structure 21 according to the leakage size of the capacitor structure 21, thereby reducing the difficulty of characterizing the uniformity of the film thickness in the capacitor structure 21.

[0094] In some embodiments, each second contact pad 252 extends along the first direction (eg Figure 1 and Figure 2 In the embodiment of the present invention, the first contact pad 251 is provided on the first electrode 211 and extends along the first direction. In this way, by respectively extending the first contact pad 251 and the second contact pad 252 along the first direction, the space occupied by the contact structure 25 in the stacked structure can be reduced, so that the arrangement of the capacitor structure 21 is better and the volume is smaller, which is conducive to increasing the number of capacitor structures 21, thereby improving the storage density of the three-dimensional semiconductor structure 100.

[0095] In some embodiments, Figure 3 As shown, there may be multiple capacitor structures 21, and the multiple capacitor structures 21 are arranged at intervals along the second direction in the stacked structure 20, and an isolation layer is provided between adjacent capacitor structures 21, and the adjacent capacitor structures 21 are electrically isolated by the isolation layer.

[0096] In other embodiments, an isolation layer may not be set between adjacent capacitor structures 21, and adjacent capacitor structures 21 are set at intervals. In this way, for example, an air gap is formed between adjacent capacitor structures 21, so that electrical isolation between adjacent capacitor structures 21 is achieved through the air gap between adjacent capacitor structures 21. The specific adaptive design can be carried out according to needs. The following embodiment is introduced by taking the example of setting an isolation layer between adjacent capacitor structures 21.

[0097] The second direction is perpendicular to the first direction. For example, in a three-dimensional coordinate system, the first direction may be the Z direction, and the second direction may be the X direction or the Y direction. Figure 2 In the embodiment, a plurality of capacitor structures 21 are arranged at intervals along the Y direction. Of course, the second direction may be a direction having an inclined angle with the X direction or the Y direction, and the adaptive design is performed according to actual needs.

[0098] It can be understood that multiple capacitor structures 21 are arranged at intervals along the second direction in the stacked structure 20. This arrangement can make the arrangement of the capacitor structures 21 more compact, so that the arrangement form of the multiple capacitor structures 21 in the stacked structure 20 is better, and the volume they occupy is smaller, which is conducive to increasing the number of arranged capacitor structures 21, thereby improving the storage density of the three-dimensional semiconductor structure 100.

[0099] In some embodiments, Figure 2 As shown, multiple capacitor structures 21 are arranged in parallel along the Y direction. It can be understood that since the leakage difference between the two ends of a single capacitor structure 21 in the first direction is small, if the signal collected by a single capacitor structure 21 is represented by i, by arranging multiple capacitor structures 21 in parallel, for example, N capacitor structures 21 are arranged in parallel, then the total collected signal (represented by I) is: I=N*i, thereby maximizing the resolution.

[0100] In some embodiments, please refer to Figure 2 and Figure 3 As shown, the stack structure 20 is provided with a first opening 23 that penetrates the stack structure 20 along a first direction (see Figure 8 As shown in FIG. 2 , the dielectric layer 213 and the first electrode 211 are located in the first opening 23 , and the dielectric layer 213 is located between the side wall of the first electrode 211 and the inner wall of the first opening 23 .

[0101] It can be understood that the dielectric layer 213 is a thin film structure formed on the inner wall of the first opening 23, and then the first electrode 211 fills the first opening 23 with the dielectric layer 213, so that the dielectric layer 213 wraps around the outer wall of the first electrode 211, as shown in FIG. Figure 3 As shown in , in this way, the arrangement between the first electrode 211 and the dielectric layer 213 can be better, the volume of the capacitor structure 21 can be smaller, which is conducive to increasing the number of arrangements of the capacitor structure 21, thereby improving the storage density of the three-dimensional semiconductor structure 100.

[0102] In some embodiments, please refer to Figure 2 As shown, the plurality of second electrodes 212 are arranged in a step-by-step manner from a direction close to the substrate 10 to a direction away from the substrate 10 .

[0103] For example, Figure 2As shown, the distances between the connection points of the second electrodes 212 and their corresponding second contact pads 252 and the first electrodes 211 decrease from bottom to top along the first direction, so that the second electrodes 212 are stepped from bottom to top.

[0104] It can be understood that by arranging the multiple second electrode layers 224 in a stepped manner, on the one hand, each second electrode 212 can be exposed, so that the second contact pad 252 electrically connected to each second electrode 212 can be prevented from being connected in series with other second electrodes 212 while being electrically connected to the corresponding second electrode 212, thereby improving the connection reliability of the electrical connection between the second contact pad 252 and the corresponding second electrode 212; on the other hand, the space occupied by the multiple second electrodes 212 can be reduced, which is beneficial to reducing the characteristic size of the three-dimensional semiconductor structure 100 while improving the storage density of the three-dimensional semiconductor structure 100.

[0105] Embodiment 2

[0106] An embodiment of the present application provides a method for preparing a three-dimensional semiconductor structure. The method for preparing a three-dimensional semiconductor structure can be used to prepare the three-dimensional semiconductor structure 100 in the above embodiment.

[0107] Figure 4 This is a schematic diagram of a process for preparing a three-dimensional semiconductor structure provided in an embodiment of the present application. Figure 4 As shown, the method for preparing the three-dimensional semiconductor structure includes:

[0108] Step S101: providing a substrate.

[0109] In the embodiment of the present application, the substrate 10 includes a silicon substrate and an oxide layer formed on the silicon substrate, and the silicon substrate is insulated and protected by the oxide layer. Figure 7 as shown in .

[0110] Step S102: forming a plurality of preset layers stacked on a substrate.

[0111] Among them, Figure 7 As shown, the plurality of preset layers 22 include support layers 221 and sacrificial layers 222 alternately stacked in sequence, and the preset layers 22 close to the silicon substrate are sacrificial layers 222. In this way, it is convenient to form a stacked structure 20 on the preset layers 22 in subsequent processes.

[0112] In some embodiments, the material of the sacrificial layer 222 can be silicon nitride (SIN) and the material of the supporting layer 221 can be made of insulating materials such as oxide, so as to achieve electrical isolation between adjacent second electrodes 212 in the stacked structure 20 formed by subsequent processes through the supporting layer 221 to avoid mutual interference between adjacent second electrodes 212.

[0113] The plurality of preset layers 22 may be formed sequentially by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process.

[0114] Step S103: forming a stacking structure on the substrate.

[0115] The stacked structure 20 includes a capacitor structure 21, which includes a first electrode 211, a dielectric layer 213 and multiple second electrodes 212. The first electrode 211 extends along a first direction, and the multiple second electrodes 212 are stacked in sequence along the first direction, and a support layer 221 is arranged between any two adjacent second electrodes 212.

[0116] It can be understood that the first electrode 211 is equivalent to a plurality of first sub-electrodes stacked in sequence along the first direction, so that the plurality of first sub-electrodes form an integrated structure, and the dielectric layer 213 is also equivalent to a plurality of sub-dielectric layers stacked in sequence along the first direction, and the plurality of sub-dielectric layers form an integrated structure, that is, forming the dielectric layer 213. The plurality of second electrodes 212 are stacked in sequence along the first direction, and two adjacent second electrodes 212 are insulated from each other. The first electrode 211 and the dielectric layer 213 respectively form a plurality of sub-capacitor structures with the plurality of second electrodes 212, and the plurality of sub-capacitor structures are stacked in sequence along the first direction, thereby forming a capacitor structure 21 stacked in the Z direction, such as in the Z direction. In this way, the arrangement of the plurality of sub-capacitor structures can be optimized, so that the three-dimensional semiconductor structure 100 can achieve a smaller feature size while improving the storage density of the three-dimensional semiconductor structure 100.

[0117] Figure 5 for Figure 4 Please refer to the flowchart of step S103 in Figure 5 As shown, the step of forming a stacked structure on a substrate specifically includes:

[0118] Step S1031: forming a plurality of first openings spaced apart along a second direction in a preset layer; the first openings extend along the first direction and penetrate the preset layer.

[0119] Specifically, Figure 8 As shown, a first mask layer 40 is first formed on the preset layer 22, and the first mask layer 40 is patterned by exposure, development, etc., and the patterned first mask layer 40 is used as a mask to etch a portion of the preset layer 22, and a first opening 23 penetrating the preset layer 22 is formed on the preset layer 22, so that the first opening 23 exposes the substrate 10 (for example, exposes the oxide layer on the silicon substrate).

[0120] The cross-sectional shape of the first opening 23 may be circular, elliptical, rectangular or square, etc. It should be noted that the cross-sectional shape of the first opening 23 refers to the cross-sectional shape along the plane parallel to the substrate.

[0121] After the first opening 23 is formed, the first mask layer 40 is removed to expose the surface of the top predetermined layer 22 .

[0122] Step S1032: forming a dielectric layer and a first electrode in sequence in the first opening; wherein the dielectric layer is disposed around an outer wall of the first electrode.

[0123] After removing the first mask layer 40 on the surface of the preset layer 22, a thin film structure can be formed on the preset layer 22 by a chemical deposition process or a physical deposition process, and the thin film structure covers the inner wall of the first opening 23, such as Fig. 9 shown.

[0124] After the thin film structure is formed on the inner wall of the first opening 23, the thin film structure on the surface of the preset layer 22 can be removed by chemical mechanical polishing (CMP) or etching, and the surface of the preset layer 22 is exposed, and the thin film structure covering the inner wall of the first opening 23 is retained to form the dielectric layer 213 of the capacitor structure 21.

[0125] The material of the dielectric layer 213 may be a high-K gate dielectric material, and the high-K gate dielectric material may include nitride, metal oxide, etc., for example, SI3N4, SION, etc. By setting the dielectric layer 213 to be made of a high-K gate dielectric material, the electron tunneling effect can be effectively suppressed, thereby reducing the leakage phenomenon of the capacitor structure 21. It can be understood that K is a dielectric constant.

[0126] A first electrode layer is formed on the preset layer 22 by a chemical deposition process or a physical deposition process, and the first electrode layer fills the first opening 23 on the inner wall of which the dielectric layer 213 is attached. The first electrode layer can be formed of a material such as a metal with conductive properties. For example, the material of the first electrode layer can be a material with low resistance such as W, TiN, TaN, Al, Ru or Cu.

[0127] After the first electrode layer fills the first opening 23, the first electrode layer on the surface of the preset layer 22 can be removed by chemical mechanical polishing (CMP) or etching, and the surface of the preset layer 22 is exposed, and the first electrode layer in the first opening 23 is retained. The first electrode layer retained in the first opening 23 is formed into the first electrode 211 of the capacitor structure 21, such as Fig.10As shown in , the dielectric layer 213 is wrapped around the outer side wall of the first electrode 211 , so that the dielectric layer 213 is located between the outer wall of the first electrode 211 and the inner wall of the first opening 23 .

[0128] It can be seen that the multiple first sub-electrodes stacked along the first direction in the capacitor structure 21 are an integral part formed by an integrated molding process, thereby simplifying the preparation process of the capacitor structure 21 and reducing the preparation cost. In this way, the multiple second electrodes 212 formed subsequently share one first electrode 211 to form multiple sub-capacitor structures stacked in sequence along the first direction, so that the multiple sub-capacitor structures are stacked in sequence along the first direction to form the capacitor structure 21.

[0129] Step S1033: removing part of the preset layer to form a plurality of second slits spaced apart along the second direction, wherein the second slits penetrate the preset layer, and two adjacent first openings are located at opposite sides of the second slits.

[0130] Specifically, Fig.11 As shown in the figure, before removing part of the preset layer 22, a second mask layer 41 is formed on the preset layer 22, and the second mask layer 41 is patterned by exposure, development, etc., and the patterned second mask layer 41 is used as a mask to remove part of the preset layer 22 by an etching process, and the area where the preset layer 22 is removed forms a second slit 223, wherein the second slit 223 exposes the substrate 10, and the second slit 223 is located between two adjacent first openings 23.

[0131] There are multiple second slits 223, and the multiple second slits 223 are arranged at intervals along the second direction. Fig.11 In the embodiment, the first electrode 211 is located between two adjacent second slits 223 , so that in a subsequent process, an isolation layer 241 is formed in the second slit 223 , so that electrical isolation between multiple capacitor structures 21 formed in the subsequent process is achieved through the isolation layer 241 .

[0132] Step S1034: removing the sacrificial layer in the preset layer and forming a first slit.

[0133] Specifically, after forming the second slits 223 on the preset layer 22 , each sacrificial layer 222 in the preset layer 22 can be removed through the second slits 223 by wet etching or other processes, and the support layers 221 in the preset layer 22 are retained, so that first slits are formed between adjacent support layers 221 .

[0134] Step S1035: forming a second electrode in the first slit.

[0135] After the first slits are formed, conductive material can be filled into each first slit through the second slits 223 by a chemical deposition process or a physical deposition process, and then the conductive material filled in the second slits 223 is removed to expose the conductive material filled in the first slits, so that the conductive material filled in the first slits forms a second electrode layer 224, and there are multiple second electrode layers 224, and the multiple second electrode layers 224 are spaced apart along the first direction; Fig.12 As shown in , the material of the second electrode layer 224 can be a material with low resistance such as W, TiN, TaN, Al, Ru or Cu.

[0136] Since the material filled in the first slit is filled into the first slit through the second slit 223, that is, when the second electrode layer 224 is formed in the first slit, the second electrode layer 224 must also be formed in the second slit 223. Therefore, after the second electrode layer 224 is formed in the first slit, the second electrode layer 224 in the second slit 223 is first removed by etching and other processes, and the second electrode layer 224 in the first slit is retained. Then, the isolation material is filled in the second slit 223 to form an isolation layer 241, and the top of the isolation layer 241 can be flush with the upper surface of the stacked structure 20.

[0137] The material of the isolation layer 241 may be a material with relatively high resistance, such as silicon nitride (SiN) and aluminum oxide (Al 2 O 3 ).

[0138] After forming the isolation layer 241 in each second slit 223, a mask block 43 is formed on the isolation layer 241. Fig.13 and Fig.14 As shown in the figure, using the mask block 43 as a mask, part of the support layer 221 and the second electrode layer 224 is removed to expose the surface of each second electrode layer 224 facing away from the substrate 10, and the retained second electrode layers 224 are formed into each second electrode 212 in the capacitor structure 21.

[0139] Among them, the retained second electrode layer 224 forms a stepped structure from the edge to the center of the stacked structure 20, and the length dimension of the second electrode layer 224 from the edge to the center of the stacked structure 20 is reduced successively. In this way, each second electrode 212 can be exposed from the top to the bottom of the stacked structure 20, avoiding that when each second electrode 212 is subsequently electrically connected to the second test pad 302 through the second contact pad 252, the second electrodes 212 are electrically connected in series with each other, thereby affecting the test effect.

[0140] In other embodiments, the preset layer 22 may not be provided, and the second electrode layer 224 and the support layer 221 may be directly formed on the substrate 10 and alternately stacked in sequence along the thickness direction of the substrate 10. The appropriate process may be adaptively selected according to actual needs.

[0141] Step S1036: forming an oxide layer on the remaining support layer and the second electrode.

[0142] like Fig.15 As shown, an oxide layer is filled on the remaining support layer 221 and the second electrode 212, so that the oxide layer 24 is flush with the surface of the stacked structure 20. The oxide layer can be insulating such as silicon oxide or aluminum oxide.

[0143] Step S1037: forming a second opening and a plurality of third openings on the oxide layer, wherein the second opening exposes the first electrode and the third opening exposes the second electrode; wherein at least one third opening corresponds to one second electrode, and the oxide layer retained between adjacent third openings forms an isolation structure.

[0144] After the oxide layer 24 is formed on the retained support layer 221 and the second electrode 212, a third mask layer (not shown in the figure) is formed on the oxide layer 24, the third mask layer is patterned, and the patterned third mask layer is used as a mask to remove a portion of the oxide layer 24 to form a second opening exposing the first electrode 211 and a third opening exposing the second electrode 212, wherein the second opening and the third opening both extend along the first direction. In this way, the space occupied by the second opening and the third opening can be reduced, which is beneficial to reducing the characteristic size of the three-dimensional semiconductor structure 100 while improving the storage density of the three-dimensional semiconductor structure 100.

[0145] It can be understood that at least one second opening corresponds to a second electrode 212. For example, with the second opening as a symmetrical reference, two relatively arranged third openings correspond to a second electrode 212, that is, the two third openings expose the same second electrode 212. In this way, a second contact pad is formed in each third opening in the subsequent process to be electrically connected to the corresponding second test pad formed in the subsequent process through the second contact pad, that is, the two second contact pads correspond to two test pads, and the two test pads are arranged relatively to each other, so that the two relatively arranged second test pads are electrically connected to the same second electrode 212, so that the voltages at different positions of the second electrode 212 can be tested through the two second test pads, thereby improving the test accuracy.

[0146] The oxide layer 24 retained between two adjacent third openings forms an isolation structure, and the isolation structure can be used to electrically isolate two adjacent second contact pads 252 formed in a subsequent process.

[0147] The cross-sectional shape of the second opening may be any shape such as a circle, an ellipse, a rectangle, a square, etc. The cross-sectional shape of the third opening may also be any shape such as a circle, an ellipse, a rectangle, a square, etc. It should be noted that the cross-sectional shapes of the second opening and the third opening refer to the cross-sectional shapes along the plane parallel to the substrate.

[0148] Step S1038: forming a first contact pad in the second opening; forming a second contact pad in the third opening; the first contact pad and the second contact pad form a contact structure.

[0149] like Fig.16 As shown, the conductive material can be filled in the second opening through a deposition process, so that the conductive material filled in the second opening is formed into a first contact pad 251 electrically connected to the first electrode 211; it can be understood that the first electrode 211 can be electrically connected to the first test pad 301 formed in the subsequent process through the first contact pad 251; while forming the first contact pad 251, the conductive material can be filled in each third opening through a deposition process, so that the conductive material filled in the third opening is formed into a second contact pad 252 electrically connected to the second electrode 212, so that the second electrode 212 corresponding to it is electrically connected to the second test pad 302 formed in the subsequent process through the second contact pad 252.

[0150] It can be understood that the first contact pad 251 and the second contact pad 252 can be formed simultaneously in the same process or in different processes. In the embodiment of the present application, the first contact pad 251 and the second contact pad 252 are formed integrally through the same process. In this way, the preparation process can be reduced, thereby reducing the preparation cost.

[0151] The materials of the first contact pad 251 and the second contact pad 252 may be materials with low resistance such as W, TiN, TaN, Al, Ru or Cu. The materials of the first contact pad 251 and the second contact pad 252 may be the same or different. In the embodiment of the present application, the materials of the first contact pad 251 and the second contact pad 252 may be the same and may be prepared by the same process, so that the preparation process can be reduced, the preparation difficulty can be reduced, and the cost can be reduced.

[0152] Step S104: forming a test structure on the stacked structure. The test structure includes a first test pad and a plurality of second test pads, the first test pad is electrically connected to the first electrode, the plurality of second test pads are arranged corresponding to the plurality of second electrodes, and at least one second test pad is electrically connected to one second electrode.

[0153] It can be understood that by forming a test structure 30 on the stacked structure 20, and making the first test pad 301 electrically connected to the first electrode 211, and the second test pad 302 electrically connected to the second electrode 212, in this way, the leakage conditions at different positions of the capacitor structure 21 can be tested through the test structure 30, and the thickness uniformity of the dielectric layer 213 in the capacitor structure 21 can be characterized through the leakage conditions of the capacitor structure 21. The structure and characterization method are simple and easy to implement, thereby reducing the problem of difficulty in characterizing the thickness uniformity of the dielectric layer 213 in the capacitor structure 21.

[0154] Figure 6 for Figure 4 Please refer to the flowchart of step S104 in Figure 6 As shown, in some embodiments, the step of forming a test structure on the stacked structure specifically includes:

[0155] Step S1041: forming a metal layer on the stacked structure.

[0156] like Fig.16 As shown, a metal layer 303 covering the upper surface of the stacked structure 20 is formed on the top of the stacked structure 20 , wherein the material of the metal layer 303 can be a conductive material such as W, TiN, TaN, Al, Ru or Cu.

[0157] In some embodiments, the material of the metal layer 303 can be the same as that of the first contact pad 251 and the second contact pad 252, and the metal layer 303, the first contact pad 251 and the second contact pad 252 are formed in a one-time molding process, which can reduce the process and reduce the cost.

[0158] Step S1042: remove part of the metal layer and retain the metal layers corresponding to the first contact pad and the second contact pad respectively; wherein the metal layer corresponding to the first contact pad forms a first test pad, and the metal layer corresponding to the second contact pad forms a second test pad; the first test pad and the second test pad together form a test structure.

[0159] Specifically, after forming the metal layer 303 on the stacked structure 20, a fourth mask layer 44 is formed on the metal layer 303, such as Fig.17 As shown, the fourth mask layer 44 is patterned, and part of the metal layer 303 is removed using the patterned fourth mask layer 44 as a mask, retaining the metal layers 303 corresponding to the first contact pad 251 and the second contact pad 252 respectively, that is, retaining the metal layer 303 on the top of the first contact pad 251 and the second contact pad 252.

[0160] In some embodiments, the metal layer 303 above the first contact pad 251 in each capacitor structure 21 is formed as an integrated structure to form a first test pad 301; and the metal layer 303 above the second contact pad 252 corresponding to the same height position in each capacitor structure 21 is formed as an integrated structure to form a second test pad 302. Since there are multiple second electrodes 212 of the capacitor structure 21, there are also multiple second test pads 302 formed. In this way, the first test pad 301 and each second test pad 302 will extend along the arrangement direction of the multiple capacitors, such as Figure 1 and Figure 2 as shown in .

[0161] When characterizing the uniformity of the film thickness in each capacitor structure 21, first, apply a ground voltage to the first test pad 301, and apply a test voltage to each second test pad 302 to charge each capacitor structure 21; then obtain the actual voltage value between the first electrode 211 and each second electrode 212 through the first test pad 301 and each second test pad 302, and compare the obtained actual voltage value with the preset voltage value. If there is a voltage difference between the actual voltage value and the preset voltage value, it means that the capacitor structure 21 has leakage, and the magnitude of the voltage difference can characterize the magnitude of leakage at different heights of the capacitor structure 21. Since the magnitude of the leakage of the capacitor structure 21 is exponentially related to the thickness of the film of the capacitor structure 21, the uniformity of the thickness of the film of the capacitor structure 21 at different heights can be characterized by the magnitude of the leakage at different heights of the capacitor structure 21. The structure is simple and easy to implement, thereby reducing the difficulty of characterizing the uniformity of the film thickness of the capacitor structure 21.

[0162] The three-dimensional semiconductor structure provided by the embodiment of the present application includes: a substrate; a stacking structure, the stacking structure is located on the substrate, the stacking structure includes a capacitor structure, the capacitor structure includes a first electrode, a dielectric layer and a plurality of second electrodes, the first electrode extends along the first direction, the plurality of second electrodes are sequentially stacked and arranged at intervals along the first direction, and a support layer is arranged between any two adjacent second electrodes; a test structure, the test structure is located on the stacking structure, the test structure includes a first test pad and a plurality of second test pads, the first test pad is electrically connected to the first electrode, and the plurality of second test pads are arranged correspondingly to the plurality of second electrodes, wherein at least one second test pad is electrically connected to a second electrode; the test structure is configured to test the voltage of the capacitor structure. By arranging the test structure on the stacking structure, and electrically connecting the first test pad in the test structure to the first electrode in the capacitor structure, the plurality of second test pads in the test structure are electrically connected to the plurality of second electrodes in the capacitor structure respectively. In this way, the test structure can test the leakage of different positions of the capacitor structure, so that the uniformity of the film thickness in the capacitor can be characterized by the leakage size of different positions of the capacitor structure, and the structure and characterization method are simple and easy to implement.

[0163] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0164] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A three-dimensional semiconductor structure, characterized in that: include: substrate; A stacking structure, the stacking structure is located on the substrate, the stacking structure includes a capacitor structure, the capacitor structure includes a first electrode, a dielectric layer and a plurality of second electrodes, the first electrode extends along a first direction, the plurality of second electrodes are sequentially stacked and spaced along the first direction, and a supporting layer is provided between any two adjacent second electrodes, wherein the first direction is a direction perpendicular to the substrate; A test structure, wherein the test structure is located on the stacked structure, the test structure includes a first test pad and a plurality of second test pads, the first test pad is electrically connected to the first electrode, and the plurality of second test pads are arranged corresponding to the plurality of second electrodes, wherein at least one of the second test pads is electrically connected to one of the second electrodes; the test structure is configured to test the voltage of the capacitor structure.

2. The three-dimensional semiconductor structure according to claim 1, characterized in that: The stacking structure also includes a contact structure, which includes a first contact pad and multiple second contact pads, the first contact pad is connected between the first electrode and the first test pad; the second contact pad is connected between the second electrode and the second test pad, and an isolation structure is arranged between adjacent second contact pads.

3. The three-dimensional semiconductor structure according to claim 2, characterized in that: Each of the second contact pads extends along the first direction, so that each of the second contact pads is vertically connected to its corresponding second electrode.

4. The three-dimensional semiconductor structure according to any one of claims 1 to 3, characterized in that: There are a plurality of capacitor structures, and the plurality of capacitor structures are arranged at intervals along a second direction in the stacked structure, and an isolation layer is arranged between adjacent capacitor structures, wherein the second direction is perpendicular to the first direction.

5. The three-dimensional semiconductor structure according to claim 4, characterized in that: A plurality of the capacitor structures are arranged in parallel.

6. The three-dimensional semiconductor structure according to any one of claims 1 to 3, characterized in that: The stack structure is provided with a first opening penetrating the stack structure along the first direction. The dielectric layer and the first electrode are located in the first opening, and the dielectric layer is located between the side wall of the first electrode and the inner wall of the first opening.

7. The three-dimensional semiconductor structure according to any one of claims 1 to 3, characterized in that: The plurality of second electrodes are arranged in sequence in a step-like manner from a direction close to the substrate to a direction far away from the substrate.

8. A method for preparing a three-dimensional semiconductor structure, characterized in that: include: providing a substrate; A stacking structure is formed on the substrate; the stacking structure includes a capacitor structure, the capacitor structure includes a first electrode, a dielectric layer and a plurality of second electrodes, the first electrode extends along a first direction, the plurality of second electrodes are sequentially stacked and spaced along the first direction, and a supporting layer is provided between any two adjacent second electrodes, wherein the first direction is a direction perpendicular to the substrate; A test structure is formed on the stacked structure; the test structure includes a first test pad and a plurality of second test pads, the first test pad is electrically connected to the first electrode, and the plurality of second test pads are arranged corresponding to the plurality of second electrodes, wherein at least one of the second test pads is electrically connected to one of the second electrodes.

9. The method for preparing a three-dimensional semiconductor structure according to claim 8, characterized in that: Before the step of forming a stacked structure on the substrate and after the step of providing the substrate, the method comprises: forming a plurality of preset layers stacked on the substrate; The plurality of preset layers include supporting layers and sacrificial layers which are alternately stacked in sequence.

10. The method for preparing a three-dimensional semiconductor structure according to claim 9, characterized in that: The step of forming a stacked structure on the substrate includes: A plurality of first openings are formed in the preset layer and are spaced apart along the second direction; the first openings extend along the first direction and penetrate the preset layer; A dielectric layer and a first electrode are sequentially formed in the first opening; wherein the dielectric layer is arranged around an outer side wall of the first electrode; Removing the sacrificial layer in the preset layer and forming a first slit; A second electrode is formed in the first slit.

11. The method for preparing a three-dimensional semiconductor structure according to claim 10, characterized in that: Before the step of removing the sacrificial layer in the preset layer and forming the first slit, the method further includes: Part of the preset layer is removed to form a plurality of second slits spaced apart along a second direction, wherein the second slits penetrate the preset layer, and two adjacent first openings are located at opposite sides of the second slits.

12. The method for preparing a three-dimensional semiconductor structure according to claim 11, characterized in that: The step of forming the second electrode in the first slit includes: Filling a second electrode layer in the first slit; removing the second electrode layer in the second slit; forming an isolation layer in the second slit; Parts of the support layer and the second electrode layer are removed along the second direction to expose the surface of each second electrode layer facing away from the substrate, and the remaining second electrode layer forms the second electrode.

13. The method for preparing a three-dimensional semiconductor structure according to claim 12, characterized in that: The method further comprises: removing a portion of the support layer and the second electrode layer along the second direction to expose the surface of each second electrode layer facing away from the substrate, and forming the second electrode with the retained second electrode layer, comprising: forming an oxide layer on the remaining support layer and the second electrode; forming a second opening and a plurality of third openings on the oxide layer, wherein the second opening exposes the first electrode, and the third opening exposes the second electrode; wherein at least one of the third openings corresponds to one of the second electrodes; and the oxide layer retained between adjacent third openings forms an isolation structure; A first contact pad is formed in the second opening; a second contact pad is formed in the third opening; and the first contact pad and the second contact pad form a contact structure.

14. The method for preparing a three-dimensional semiconductor structure according to claim 13, characterized in that: The step of forming a test structure on the stack structure includes: forming a metal layer on the stacked structure; Part of the metal layer is removed, and the metal layers corresponding to the first contact pad and the second contact pad are retained respectively; wherein the metal layer corresponding to the first contact pad forms the first test pad, and the metal layer corresponding to the second contact pad forms the second test pad; the first test pad and the second test pad form the test structure.

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