High space utilization FCBGA package structure and its packaging method

Abstract

The application provides a high-space-usage FCBGA packaging structure and a packaging method thereof, which comprises a substrate and a heat sink, the substrate and the heat sink are oppositely arranged, one side of the substrate is provided with at least two first pretreatment welding interfaces, the mounting surface of the heat sink is provided with a regional insulation layer, the regional insulation layer is provided with circuit lines, the circuit lines are paved with a solder resist layer, the solder resist layer is provided with at least two second pretreatment welding interfaces, the first pretreatment welding interfaces are connected with one end of conductive copper columns, the second pretreatment welding interfaces are connected with the other end of the conductive copper columns to realize the expansion of the mounting space, and the mounting space is provided with a chip; thus, the mounting space is expanded, the utilization space of the chip is improved, the packaging space is saved, and the mounting space is effectively expanded without affecting heat dissipation.

Description

Technical Field

[0001] This invention relates to the field of FCBGA packaging technology, and specifically to an FCBGA packaging structure and packaging method with high space utilization. Background Technology

[0002] The existing FCBGA (Flip Chip Ball Grid Array) packaging structure offers excellent electrical performance, reduces interconnect losses and inductance, lowers electromagnetic interference, and allows for higher frequencies, making overclocking possible. Due to its unique flip-chip packaging, the back of the chip is exposed to air for direct heat dissipation, improving stability during high-frequency operation. However, despite these advantages, the existing FCBGA packaging structure still has the following technical challenges:

[0003] 1) Currently, passive components are generally mounted on the front or back of the substrate in the industry. As chips become more concentrated, the space layout of the substrate becomes more demanding. The load-bearing capacity of the substrate is approaching its limit. Design breakthroughs and industrial process capabilities need to be effectively improved.

[0004] 2) The mounting space for passive components cannot be expanded, the chip space utilization is low, and there will be a problem of wasted packaging space;

[0005] 3) Moreover, expanding the mounting space for passive components may lead to heat dissipation risks that affect the FCBGA package structure. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides an FCBGA packaging structure and packaging method with high space utilization, which expands the mounting space, not only improving the utilization space of the chip but also saving packaging space, effectively expanding the mounting space without affecting heat dissipation.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows:

[0008] This invention provides a space-efficient FCBGA packaging structure, comprising: a substrate and a heat sink, wherein the substrate and the heat sink are disposed opposite to each other; at least two first pre-processing solder joints are provided on one side of the substrate; a regionalized insulating layer is provided on the mounting surface of the heat sink; circuit lines are provided on the regionalized insulating layer; a solder resist layer is laid on the circuit lines; at least two second pre-processing solder joints are provided on the solder resist layer; the first pre-processing solder joints are connected to one end of a conductive copper pillar; and the second pre-processing solder joints are connected to the other end of the conductive copper pillar to enable expansion to form a mounting space, wherein a chip is disposed within the mounting space.

[0009] The present invention provides an FCBGA packaging structure and packaging method with high space utilization, which expands the mounting space, not only improving the utilization space of the chip, but also saving packaging space, and effectively expanding the mounting space without affecting heat dissipation.

[0010] As a preferred technical solution, the chip is disposed in the middle area of ​​the mounting space. The mounting space is further provided with a thermal adhesive layer and a chip bottom filler layer. One side of the thermal adhesive layer is connected to the mounting surface of the heat sink, the other side of the thermal adhesive layer is connected to one side of the chip, the other side of the chip is connected to one side of the chip bottom filler layer, and the other side of the chip bottom filler layer is connected to one side of the substrate.

[0011] As a preferred technical solution, multiple component mounting windows are also provided on the solder resist layer, and the component mounting windows are connected to the components.

[0012] As a preferred technical solution, multiple components are connected to one side of the substrate, and multiple components and solder balls are connected to the other side of the substrate.

[0013] As a preferred technical solution, the height of the component is less than the height of the chip plus the bump.

[0014] As a preferred technical solution, the height of the conductive copper pillar = chip thickness + bump height + thermal adhesive layer thickness - tinning thickness × 2, wherein the thickness of the thermal adhesive layer is 50-60um.

[0015] As a preferred technical solution, the end of the conductive copper pillar is connected to a tin-coated portion, and the tin-coated portion is covered with an NI layer.

[0016] As a preferred technical solution, a plastic encapsulation layer is applied between the substrate and the heat sink.

[0017] This invention provides a space-efficient FCBGA packaging method, comprising the following steps:

[0018] S1 avoids the heat dissipation adhesive layer connection area, plates a regionalized insulating layer on the heat sink, electroplats circuit lines on the regionalized insulating layer, lays a solder resist layer on the circuit lines, and opens at least two second pre-treatment solder joints on the solder resist layer.

[0019] S2 has at least two first pre-processing solder joints on one side of the substrate, one end of a conductive copper pillar is attached to the first pre-processing solder joint, a chip is attached to the middle area of ​​one side of the substrate, and a chip bottom filler layer is made.

[0020] S3 uses a coating process to apply tin or place tin balls at the ends of the conductive copper pillars to tin-encapsulate them. After tin-encapsulation, a Ni layer is plated on the surface of the tin-encapsulated part. Adhesive thermal adhesive is then applied to the chip to form a thermal adhesive layer.

[0021] S4 attaches the thermal adhesive to the heat sink, attaches the other end of the conductive copper pillar to the second pre-treated solder joint, and after the attachment is completed, it is heated and passed through the oven.

[0022] The S5 uses a molding process to encapsulate the substrate and heat sink, while multiple components and substrate balls are mounted on the other side of the substrate to form solder balls.

[0023] As a preferred technical solution, step S1 also includes the following steps: opening a component mounting window on the solder mask layer, and mounting components in the component mounting window;

[0024] Step S2 also includes the following steps: avoiding the connection area of ​​the bottom filler layer of the chip, multiple components are mounted on one side of the substrate.

[0025] The present invention provides an FCBGA packaging structure and packaging method with high space utilization, which has the following beneficial effects:

[0026] 1) The present invention provides an FCBGA packaging structure and packaging method with high space utilization, which expands the mounting space, not only increases the usable space of the chip, but also saves packaging space, and effectively expands the mounting space without affecting heat dissipation.

[0027] 2) The present invention provides a high space utilization FCBGA packaging structure and packaging method. During substrate fabrication, a first pre-treatment solder joint is provided. Conductive copper pillars are packaged and mounted at the first pre-treatment solder joint. The number of conductive copper pillars increases as the number of components on the heat sink mounting surface increases. After the heat sink is fabricated, a regional insulation treatment is performed on the heat sink mounting surface, followed by electroplating to form circuit lines. Components are mounted on the circuit lines. A second pre-treatment solder joint is provided on the circuit lines to conduct electricity with the conductive copper pillars connected to the substrate. The middle area of ​​the heat sink is positioned opposite to the chip, effectively expanding the mounting space of passive components without affecting heat dissipation.

[0028] 3) The present invention provides a high space utilization FCBGA packaging structure and packaging method. The component integration packaging achieved by the present invention does not damage the heat dissipation structure, and multiple components are integrated below the heat sink without the need for complex mounting processes. Using this packaging structure can save packaging space, increase the utilization space of the chip, and the heat sink is supported and fixed by the conductive copper pillars and the molding layer, which can protect the product chip while satisfying heat dissipation. Attached Figure Description

[0029] Figure 1 A schematic diagram of the FCBGA packaging structure with high space utilization provided by the present invention;

[0030] Figure 2 The present invention provides a schematic diagram of avoiding the heat dissipation adhesive layer connection area, depositing a regionalized insulating layer on the heat sink, electroplating circuit lines on the regionalized insulating layer, laying a solder resist layer on the circuit lines, opening at least two second pre-treatment solder joints on the solder resist layer, opening component mounting windows on the solder resist layer, and mounting components in the component mounting windows.

[0031] Figure 3 The present invention provides a schematic diagram of a substrate having at least two first pre-treatment solder joints on one side, one end of a conductive copper pillar attached to the first pre-treatment solder joints, a chip attached to the middle area of ​​one side of the substrate, and a chip bottom filler layer, avoiding the chip bottom filler layer connection area, and multiple components attached to one side of the substrate.

[0032] Figure 4 This is a schematic diagram of the present invention, which shows the process of applying tin to the end of a conductive copper pillar using a coating process or a tin-plating part, depositing a Ni layer on the surface of the tin-plated part after the tin-plating process, and then coating the chip with an adhesive thermal paste.

[0033] Figure 5 This is a schematic diagram of the process of attaching thermal adhesive to a heat sink, attaching the other end of a conductive copper pillar to a second pre-treated solder joint, completing the attachment, and then heating the furnace.

[0034] Figure 6 This is a schematic diagram of the substrate and heat sink being encapsulated using a molding process, with multiple components mounted on the other side of the substrate and substrate ball-mounting provided by the present invention.

[0035] 1-Substrate; 2-Heat sink; 4-First pre-treatment solder joint; 5-Regulated insulating layer; 6-Second pre-treatment solder joint; 7-Conductive copper pillar; 8-Mounting space; 9-Chip; 10-Chip bottom filler layer; 11-Thermoplastic layer; 12-Component mounting window; 13-Component; 14-Solder ball; 15-Molding layer; 16-Tinized section. Detailed Implementation

[0036] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0037] It is understood that the present invention achieves its objectives through certain embodiments, such as... Figure 1 As shown, the present invention provides a high space utilization FCBGA package structure, including: a substrate 1 and a heat sink 2, wherein the substrate 1 and the heat sink 2 are disposed opposite to each other, and at least two first pre-processing solder joints 4 are provided on one side of the substrate 1, and a regionalized insulating layer 5 is provided on the mounting surface of the heat sink 2, the regionalized insulating layer 5 being disposed away from the middle area of ​​the mounting surface of the heat sink 2, circuit lines (not shown) are provided on the regionalized insulating layer 5, a solder resist layer (not shown) is laid on the circuit lines (not shown), and at least two second pre-processing solder joints 6 are provided on the solder resist layer (not shown). A pre-processed solder joint 4 is connected to one end of a conductive copper pillar 7, and a second pre-processed solder joint 6 is connected to the other end of a conductive copper pillar 7 to expand and form a mounting space 8. A chip 9 is disposed within the mounting space 8. The chip 9 is located in the middle area of ​​the mounting space 8. The mounting space 8 also includes a thermal adhesive layer 11 and a chip bottom filler layer 10. The chip 9 is disposed between the thermal adhesive layer 11 and the chip bottom filler layer 10. One side of the thermal adhesive layer 11 is connected to the mounting surface of the heat sink 2, and the other side of the thermal adhesive layer 11 is connected to one side of the chip 9. The other side of the chip 9 is connected to... One side of the bottom filler layer 10 of the chip is connected to the substrate 1, and the other side of the bottom filler layer 10 is connected to the substrate 1. Multiple component mounting windows 12 are also provided on the solder resist layer (not shown), and the component mounting windows 12 are connected to components 13. Multiple components 13 are also connected to one side of the substrate 1, and multiple components 13 and solder balls 14 are connected to the other side of the substrate 1. The height of the component 13 is less than the height of the chip 9 plus the bump height. The height of the conductive copper pillar 7 = the thickness of the chip 9 + the bump height + the thickness of the thermal adhesive layer 11 - the thickness of the tinned portion 16 × 2, wherein the thermal adhesive layer 11... The thickness is 50-60um. The increase in the number of conductive copper pillars 7 imposes requirements on the minimum size of SMT soldering. The minimum size of SMT soldering is ≥1.8X18mm. When the size of SMT soldering is <1.8X18mm, there is a risk of soldering misalignment and misalignment of the conductive copper pillars 7. The end of the conductive copper pillar 7 is connected to a tinning part 16, and the tinning part 16 is covered with a NI layer. A molding compound 15 is wrapped between the substrate 1 and the heat sink 2. This packaging structure expands the mounting space, improves the utilization space of the chip, saves packaging space, and effectively expands the mounting space without affecting heat dissipation.

[0038] This invention provides a space-efficient FCBGA packaging method, comprising the following steps:

[0039] S1 avoids the connection area of ​​the heat dissipation adhesive layer 11, plates a regionalized insulating layer 5 on the heat sink 2, electroplats circuit lines (not shown) on the regionalized insulating layer 5, lays a solder resist layer (not shown) on the circuit lines (not shown), opens at least two second pre-treatment solder joints 6 on the solder resist layer (not shown), opens a component mounting window 12 on the solder resist layer (not shown), and mounts components 13 in the component mounting window 12.

[0040] S2 has at least two first pre-treatment solder joints 4 on one side of the substrate 1, one end of a conductive copper pillar 7 is attached to the first pre-treatment solder joint 4, a chip 9 is attached to the middle area of ​​one side of the substrate 1, and a chip bottom filler layer 10 is made, avoiding the connection area of ​​the chip bottom filler layer 10, and multiple components 13 are attached to one side of the substrate 1.

[0041] S3 uses a coating process to apply tin or place tin balls at the end of the conductive copper pillar 7 to perform tinning treatment. After tinning treatment, a layer of Ni layer (not shown) is plated on the surface of the tinned part 7. Adhesive thermal adhesive is coated on the chip 9 to form thermal adhesive layer 11.

[0042] S4 attaches the heat dissipation adhesive layer 11 to the heat sink 2, attaches the other end of the conductive copper pillar 7 to the second pre-processed solder joint 6, and after the attachment is completed, heats it through the oven.

[0043] S5 uses a molding process to encapsulate the substrate 1 and the heat sink 2. On the other side of the substrate 1, multiple components 13 and substrate balls are mounted to form solder balls 14.

[0044] In step S3, the ends of the conductive copper pillar 7 are tinned using a coating process or by placing solder balls. Specifically, this includes the following steps: tinning is performed on the ends of the conductive copper pillar 7 using a coating process to form a tinned portion 16. When the thickness of the conductive copper pillar 7 is small, solder balls are placed on the ends of the conductive copper pillar to form the tinned portion 16. Because the conductive copper pillar 7 cannot be exposed to air, oxygen isolation treatment is applied to its sides. Tinning is performed on both ends of the conductive copper pillar 7. Since copper and tin are difficult to solder, a Ni layer is plated on the surface of the tinned portion 16. This not only prevents tin from oxidizing in the air, but also facilitates the soldering of the first pre-treatment solder joint 4 and the second pre-treatment solder joint 6 to the conductive copper pillar 7. This method not only improves the utilization space of the chip 9, but also saves packaging space, effectively expanding the mounting space without affecting heat dissipation.

[0045] The present invention provides an FCBGA packaging structure and packaging method with high space utilization, which has the following beneficial effects:

[0046] 1) The present invention provides an FCBGA packaging structure and packaging method with high space utilization, which expands the mounting space 8, not only increasing the usable space of the chip 9, but also saving packaging space, and effectively expanding the mounting space without affecting heat dissipation.

[0047] 2) The present invention provides a high space utilization FCBGA packaging structure and packaging method. During the fabrication of the substrate 1, a first pre-treatment soldering port 4 is provided. Conductive copper pillars 7 are packaged and mounted in the first pre-treatment soldering port 4. The number of conductive copper pillars 7 is increased as the number of components on the mounting surface of the heat sink 2 increases. After the heat sink 2 is fabricated, a regional insulation treatment is performed on the mounting surface of the heat sink 2, followed by electroplating to form circuit lines. Components 13 are mounted on the circuit lines. A second pre-treatment soldering port 6 is provided on the circuit lines to conduct electricity with the conductive copper pillars 7 connected to the substrate 1. The middle area of ​​the heat sink 2 is arranged opposite to the chip 9, which effectively expands the mounting space of passive components without affecting heat dissipation.

[0048] 3) The present invention provides a high space utilization FCBGA packaging structure and packaging method. The component 13 integrated packaging achieved by the present invention does not damage the heat dissipation structure. Moreover, multiple components 13 are integrated below the heat sink, eliminating the need for complex mounting processes. Using this packaging structure can save packaging space, making the utilization space of the chip 9 higher. Furthermore, the heat sink 2 is supported and fixed by the conductive copper pillars 7 and the molding layer 15, which can protect the product chip 9 while satisfying heat dissipation.

[0049] It is understood that this invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are protected by this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of this invention.

Claims

1. A space-efficient FCBGA packaging structure, characterized in that, include: A substrate and a heat sink are arranged opposite to each other. At least two first pre-processing solder joints are provided on one side of the substrate. A regional insulating layer is provided on the mounting surface of the heat sink. Circuit lines are provided on the regional insulating layer. A solder resist layer is laid on the circuit lines. At least two second pre-processing solder joints are provided on the solder resist layer. The first pre-processing solder joints are connected to one end of a conductive copper pillar, and the second pre-processing solder joints are connected to the other end of the conductive copper pillar to enable expansion to form a mounting space. A chip is provided in the mounting space. The chip is disposed in the middle area of ​​the mounting space, and the bump is located between the chip and the substrate; the mounting space is also provided with a thermal adhesive layer and a chip bottom filler layer, one side of the thermal adhesive layer is connected to the mounting surface of the heat sink, the other side of the thermal adhesive layer is connected to one side of the chip, the other side of the chip is connected to one side of the chip bottom filler layer, and the other side of the chip bottom filler layer is connected to one side of the substrate. Multiple component mounting windows are also provided on the solder mask layer, and the component mounting windows are connected to the components. The end of the conductive copper pillar is connected to a tin-plated portion, and the tin-plated portion is covered with a Ni layer. The height of the conductive copper pillar = chip thickness + bump height + thermal adhesive layer thickness - tinning layer thickness × 2, wherein the thickness of the thermal adhesive layer is 50-60μm.

2. The high space utilization FCBGA packaging structure according to claim 1, characterized in that, Multiple components are connected to one side of the substrate, and multiple components and solder balls are connected to the other side of the substrate.

3. The high space utilization FCBGA packaging structure according to claim 1 or 2, characterized in that, The height of the component is less than the sum of the chip height and the bump height.

4. The FCBGA packaging structure with high space utilization according to claim 1, characterized in that, A plastic encapsulation layer is applied between the substrate and the heat sink.

5. A packaging method for a high space utilization FCBGA packaging structure as described in any one of claims 1-4, characterized in that, Includes the following steps: S1 avoids the heat dissipation adhesive layer connection area, plates a regionalized insulating layer on the heat sink, electroplats circuit lines on the regionalized insulating layer, lays a solder resist layer on the circuit lines, and opens at least two second pre-treatment solder joints on the solder resist layer. S2 has at least two first pre-processing solder joints on one side of the substrate, one end of a conductive copper pillar is attached to the first pre-processing solder joint, a chip is attached to the middle area of ​​one side of the substrate, and a chip bottom filler layer is made. S3 uses a coating process to apply tin to the ends of the conductive copper pillars or to apply tin to the tin-coated portion. After the tin-coated portion is formed, a Ni layer is plated on the surface of the tin-coated portion. Adhesive thermal adhesive is then applied to the chip to form a thermal adhesive layer. S4 attaches the thermal adhesive to the heat sink, attaches the other end of the conductive copper pillar to the second pre-treated solder joint, and after the attachment is completed, it is heated and passed through the oven. S5 uses a molding process to encapsulate the substrate and heat sink, and multiple components and substrate balls are mounted on the other side of the substrate to form solder balls. The height of the conductive copper pillar = chip thickness + bump height + thermal adhesive layer thickness - tinning layer thickness × 2, wherein the thickness of the thermal adhesive layer is 50-60μm.

6. The FCBGA packaging method with high space utilization according to claim 5, characterized in that, Step S1 also includes the following steps: a component mounting window is opened on the solder mask layer, and components are mounted in the component mounting window; Step S2 also includes the following steps: avoiding the connection area of ​​the bottom filler layer of the chip, multiple components are mounted on one side of the substrate.

Images