阵列基板和显示模组
By increasing the parasitic capacitance Cgs of the first sub-pixel on the array substrate, the problem of uneven monochrome display caused by the Dual Gate design was solved, and the uniformity of the display image was achieved.
CN115799267BActive Publication Date: 2026-07-17HEFEI BOE DISPLAY TECH CO LTD +1
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HEFEI BOE DISPLAY TECH CO LTD
- Filing Date
- 2022-11-30
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
The existing display products suffer from uneven monochrome images due to the Dual Gate design, especially in green images where a grid pattern with a period of four sub-pixels appears.
Method used
By designing the second end area of the first sub-pixel in each pixel group on the array substrate to be larger than the second end area of other sub-pixels, the parasitic capacitance Cgs is increased, and the brightness of the first sub-pixel is reduced by using capacitive coupling, so that the brightness of sub-pixels in the same pixel group tends to be consistent.
Benefits of technology
It achieves uniform display of monochrome images, eliminates grid phenomena, and improves the consistency of display effects.
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Smart Images
Figure CN115799267B_ABST
Abstract
本发明涉及一种阵列基板，包括：衬底基板，以及设置于衬底基板上的栅线，数据线和多个子像素，多个子像素划分为多组像素组；子像素包括像素电极和控制写入晶体管，控制写入晶体管的栅极与对应的栅线耦接，控制写入晶体管的第一极与对应的数据线耦接，控制写入晶体管的第二极与像素电极耦接；第二极包括沿与栅线的延伸方向相对设置的第一端部和第二端部，第一端部靠近第一极设置，且第一端部和第一极间隔设置，第二端部在衬底基板上的正投影位于栅线在衬底基板上的正投影的内部；每个像素组中第一子像素包括的第二端部的面积，大于该像素组中与第一子像素相同颜色的其他子像素包括的第二端部的面积。
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