Trench-type insulated gate bipolar transistor and method for manufacturing the same

Abstract

The present invention provides a trench-type insulated gate bipolar transistor and a method for manufacturing the same. The trench-type insulated gate bipolar transistor comprises an N-type silicon substrate, a first shield gate, a second shield gate, a control gate, an emitter, a front P-type well region, an N-type carrier storage layer, and a highly doped carrier storage layer. A trench is formed in the N-type silicon substrate, with the front P-type well region, the N-type carrier storage layer, and the emitter located on either side of the trench, the highly doped carrier storage layer on the left, and the emitter located above the front P-type well region, which is located above the N-type carrier storage layer. The first shield gate, the second shield gate, and the control gate are disposed within the trench, with the first shield gate and the control gate arranged side by side, and the second shield gate located below the first shield gate and the control gate. The first and second shield gates have the same potential as the emitter. The present invention eliminates the influence of the collector on the trench gate, reduces gate charge, and improves dynamic characteristics.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a trench-type insulated gate bipolar transistor and a preparation method thereof. Background Art

[0002] Insulated-gate bipolar transistors (IGBTs) are widely used as a primary switching device in power electronics systems. They combine the high-frequency characteristics of power MOSFETs with the low on-state voltage drop of BJTs, offering high input impedance and low switching losses. In recent years, trench IGBTs have proven to be one of the most competitive IGBT devices due to their advantages in manufacturing, reliability, and current handling capability. Compared to planar IGBTs, trench IGBTs can significantly reduce Von. The deep trench also eliminates the JFET effect, increases channel density, enhances carrier concentration near the interface, and reduces on-resistance in the channel region.

[0003] Various trench IGBT structures and technologies have been proposed and studied to improve their performance. However, the introduction of the trench also presents challenges. First, the presence of the trench bottom increases the coupling between the gate and drain compared to planar devices, resulting in larger gate capacitance. As chip feature sizes continue to shrink, parasitic capacitance increases, and dynamic losses continue to rise, limiting the application of IGBTs in medium and high frequency applications. Furthermore, the trench generates a strong electric field at the bottom, leading to premature breakdown and thus compromising device stability. The presence of a carrier storage layer at the trench bottom exacerbates this problem. Summary of the Invention

[0004] The object of the present invention is to provide a trench-type insulated gate bipolar transistor and a method for preparing the same, which eliminates the influence of the collector on the trench gate, reduces the gate charge and improves the dynamic characteristics.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a trench-type insulated gate bipolar transistor, comprising an N-type silicon substrate, a first shield gate, a second shield gate, a control gate, an emitter, a front P-type well region, an N-type carrier storage layer, and a highly doped carrier storage layer;

[0006] A trench is formed on the N-type silicon substrate, and the front P-type well region, the N-type carrier storage layer, the highly doped carrier storage layer and the emitter are formed on the front side of the N-type silicon substrate, the front P-type well region, the N-type carrier storage layer and the emitter are respectively located on both sides of the trench, the highly doped carrier storage layer is on the left side of the trench, and the emitter is located above the front P-type well region, and the front P-type well region is located above the N-type carrier storage layer;

[0007] The first shielding gate, the second shielding gate and the control gate are arranged in the groove, and the first shielding gate and the control gate are arranged side by side and spaced apart, and the second shielding gate is located at the bottom of the first shielding gate and the control gate; wherein the first shielding gate and the second shielding gate have the same potential as the emitter.

[0008] In some embodiments, the highly doped storage layer is disposed on one side of the trench and close to the emitter, and the highly doped storage layer separates the front P-type well region on one side of the trench into two upper and lower parts.

[0009] In some embodiments, the trench further includes a gate dielectric layer, and the gate dielectric layer separates the first shielding gate, the second shielding gate, and the control gate.

[0010] In some embodiments, a contact region is formed between the front P-type well region and the emitter, and the contact region includes a P+ contact region and an N+ contact region.

[0011] The trench-type insulated gate bipolar transistor provided by the present invention has the following beneficial effects: the first and second shield gates on the left and bottom sides are set to the same potential as the emitter, thereby eliminating the influence of the collector on the trench gate, reducing gate charge, and improving dynamic characteristics. Furthermore, a highly doped storage layer on the left side near the emitter is formed by ion implantation. This highly doped storage layer enhances the hole carrier storage effect near the emitter, reducing the voltage drop Von without affecting the breakdown characteristics of the device. Compared with existing devices at the same Von, the present invention significantly improves Qg and short-circuit duration, and reduces the off time (Toff) and saturation current.

[0012] In a second aspect, an embodiment of the present invention provides a method for preparing a trench-type insulated gate bipolar transistor, for preparing the above-mentioned trench-type insulated gate bipolar transistor, the preparation method comprising:

[0013] Implanting ions into an N-type silicon substrate to form an N-type carrier storage layer;

[0014] Implanting ions above the N-type carrier storage layer to form a front P-type well region;

[0015] Etching to form a first trench, and depositing a first oxide layer in the first trench;

[0016] depositing a first polysilicon layer on the first oxide layer to form a second shield gate;

[0017] Etching the first polysilicon layer to form a second trench, and depositing a second oxide layer in the second trench;

[0018] forming a left-right symmetrical first shield gate and a control gate in the second oxide layer;

[0019] Using high-energy ion implantation to form a highly doped storage layer;

[0020] Doping is performed on the front surface of the N-type silicon substrate and above the P-type well region to form a contact region, and an emitter is formed on the contact region;

[0021] A back N-well region is formed on the back side of the N-type silicon substrate by N-type ion implantation, and then a back P-well region is formed by P-type ion implantation, wherein the back P-well region is located at the bottom and the back N-well region is located above the back P-well region.

[0022] In some embodiments, forming the highly doped storage layer using high-energy ion implantation includes:

[0023] Phosphorus is implanted into the P-type well region to form a highly doped storage layer, and the highly doped storage layer separates the front P-type well region located on one side of the trench into two upper and lower parts.

[0024] In some embodiments, forming a bilaterally symmetrical first shield gate and a control gate in the second oxide layer includes:

[0025] Etching a bilaterally symmetrical third trench on the second oxide layer;

[0026] A second polysilicon layer is filled in the third trench to form a first shield gate and a control gate; wherein the trench includes the first trench, the second trench and the third trench.

[0027] The beneficial effects of the method for preparing a trench-type insulated gate bipolar transistor provided by the present invention are as follows: by setting the first and second shielding gates on the left and bottom sides to the same potential as the emitter, the collector's influence on the trench gate is eliminated, the gate charge is reduced, and the dynamic characteristics are improved. Furthermore, on the left side, another highly doped storage layer near the emitter is formed by ion implantation. This highly doped storage layer enhances the hole carrier storage effect near the emitter, reducing the voltage drop Von without affecting the breakdown characteristics of the device. Compared with existing devices at the same Von, the present invention significantly improves Qg and short-circuit duration, and reduces the off time (Toff) and saturation current. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic structural diagram of a trench-type insulated gate bipolar transistor according to an embodiment of the present invention;

[0029] Figure 2 This is a flow chart of a method for preparing a trench-type insulated gate bipolar transistor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the usual meanings understood by people with ordinary skills in the field to which the present invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Unless otherwise specified, the "connection" described in this article can be a direct connection or an indirect connection, that is, a connection through an intermediate.

[0031] In view of the problems existing in the prior art, an embodiment of the present invention provides a trench-type insulated gate bipolar transistor, referring to Figure 1 As shown, the device comprises an N-type silicon substrate, a first shield gate 5, a second shield gate 7, a control gate 6, an emitter 1, a front P-type well region 3, a contact region 2, an N-type carrier storage layer 8, and a highly doped carrier storage layer 4. A trench is formed in the N-type silicon substrate, the bottom of which extends to an N-type drift region 9 on the N-type silicon substrate. The contact region 2, the front P-type well region 3, the N-type carrier storage layer 8, the highly doped carrier storage layer 4, and the emitter 1 are formed on the front surface of the N-type silicon substrate. The contact region 2, the front P-type well region 3, the N-type carrier storage layer 8, and the emitter 1 are located on either side of the trench, with the highly doped carrier storage layer 4 on the left side of the trench. The contact region 2 and the emitter 1 are located above the front P-type well region 3, which is located above the N-type carrier storage layer 8. The first shield gate 5, the second shield gate 7, and the control gate 6 are disposed within the trench, which is filled with a gate dielectric layer. The gate dielectric layer separates the first shield gate 5, the second shield gate 7, and the control gate 6. The gate dielectric layer is an oxide formed within the trench. The first shield gate 5 and the control gate 6 are spaced side by side, and the second shield gate 7 is located at the bottom of the first shield gate 5 and the control gate 6. It should be noted that the first shield gate 5 and the second shield gate 7 have the same potential as the emitter 1.

[0032] In this embodiment, the first shield gate 5 and the second shield gate 7 on the left and bottom sides are set to the same potential as the emitter 1 to eliminate the influence of the collector (the back P-well region 10 and the back N-well region 11 formed on the back side of the N-type silicon substrate) on the trench gate, thereby reducing the gate charge and improving the dynamic characteristics. The doping concentration of the N-type drift region 9 is 5.9×10 13 cm -3 The doping concentration of the highly doped storage layer 4 on the left is 4×10 17 cm -3 , the doping concentration of the N-type carrier storage region 8 is 1×10 17 cm -3 The doping concentration of the front P-type well region 3 is 3×10 16 cm -3 .

[0033] Optionally, the trench-type insulated gate bipolar transistor also includes a highly doped storage layer 4 formed by injecting phosphorus (P) ions, wherein the highly doped storage layer 4 is formed on one side of the trench and close to the emitter 1, and the highly doped storage layer 4 separates the front P-type well 3 located on one side of the trench into two upper and lower parts.

[0034] In this embodiment, the additional highly doped storage layer 4 is formed by implanting phosphorus during the formation of the emitter 1. The highly doped storage layer 4 is formed on the left side, close to the emitter 1. This highly doped storage layer 4 enhances the hole carrier storage effect near the emitter 1, reducing the voltage drop Von without affecting the breakdown characteristics of the device. Compared with existing devices, at the same Von, the device Qg and short-circuit duration of the embodiment of the present invention are significantly improved, and the off time (Toff) and saturation current are reduced. In addition, by providing the highly doped storage layer 4 to form another barrier layer, the accumulation of hole carriers is more effectively suppressed, which can improve the carrier storage effect and reduce conduction loss.

[0035] In another embodiment disclosed in the present invention, a method for preparing a trench-type insulated gate bipolar transistor is provided, referring to Figure 2 As shown, the method includes:

[0036] S201: Implanting ions into an N-type silicon substrate to form an N-type carrier storage layer.

[0037] In this step, an N-type silicon substrate is formed by epitaxial growth technology, and then N-type ions, such as phosphorus (P) ions, are implanted deep into the N-type silicon substrate to form N-type carrier storage layers on the left and right sides. The doping concentration of the N-type carrier storage region is 1×10 17 cm -3 .

[0038] S202: Implanting ions above the N-type carrier storage layer to form a front P-type well region.

[0039] In this step, P-type ions, such as boron (B) ions, are implanted on the N-type silicon substrate to form a front P-type well region above the N-type carrier storage layer. The doping concentration of the P-type well region is 3×10 16 cm -3 .

[0040] S203: etching to form a first trench, and depositing a first oxide layer in the first trench.

[0041] In this step, the first oxide layer covers the surface of the first trench but does not completely fill the first trench.

[0042] S204: depositing a first polysilicon layer on the first oxide layer to form a second shield gate.

[0043] In this step, the first polysilicon layer is deposited on the first oxide layer, the first polysilicon layer completely fills the first trench, and then the first polysilicon layer is etched back to form the second shielding gate.

[0044] S205: Etching the first polysilicon layer to form a second trench, and depositing a second oxide layer in the second trench.

[0045] In this step, a second trench is formed in the first polysilicon layer during etching back, and then a second oxide layer is deposited in the second trench, so that the second oxide layer completely fills the second trench.

[0046] S206: forming a left-right symmetrical first shield gate and a control gate in the second oxide layer.

[0047] Specifically, in this step, a bilaterally symmetrical third trench is etched in the second oxide layer. After the third trench is filled with a second polysilicon layer, the second polysilicon layer is photolithographically processed to form a first shield gate and a control gate. It should be noted that the trenches in the above embodiment include the first trench, the second trench, and the third trench.

[0048] S207: Using high-energy ion implantation to form a highly doped storage layer.

[0049] In this step, phosphorus (P) is implanted into the P-type well region to form the highly doped storage layer. The highly doped storage layer separates the front P-type well region located on one side of the trench into two parts, the upper and lower parts. The doping concentration of the highly doped storage layer is 4×10 17 cm -3 .

[0050] S208: performing doping on the front surface of the N-type silicon substrate and above the P-type well region to form a contact region, and forming an emitter on the contact region.

[0051] S209: Forming a back N-well region on the back side of the N-type silicon substrate by N-type ion implantation, and then forming a back P-well region by P-type ion implantation, wherein the back P-well region is located at the bottom, and the back N-well region is located above the back P-well region.

[0052] In this embodiment, the first and second shield gates on the left and bottom sides are set to the same potential as the emitter to eliminate the collector's influence on the trench gate, reduce gate charge, and improve dynamic characteristics. Furthermore, on the left side, another highly doped storage layer near the emitter is formed by ion implantation. This highly doped storage layer enhances the hole carrier storage effect near the emitter, reducing the voltage drop Von without affecting the device's breakdown characteristics. Compared to existing devices at the same Von, the present invention significantly improves Qg and short-circuit duration, while reducing the turn-off time (Toff) and saturation current.

[0053] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A trench-type insulated gate bipolar transistor, characterized in that: It includes an N-type silicon substrate, a first shielding gate, a second shielding gate, a control gate, an emitter, a front P-type well region, an N-type carrier storage layer and a highly doped carrier storage layer; A trench is formed on the N-type silicon substrate, and the front P-type well region, the N-type carrier storage layer, the highly doped carrier storage layer and the emitter are formed on the front side of the N-type silicon substrate, the front P-type well region, the N-type carrier storage layer and the emitter are respectively located on both sides of the trench, the highly doped carrier storage layer is on the left side of the trench, and the emitter is located above the front P-type well region, and the front P-type well region is located above the N-type carrier storage layer; The first shielding gate, the second shielding gate and the control gate are arranged in the groove, and the first shielding gate and the control gate are arranged side by side and spaced apart, and the second shielding gate is located at the bottom of the first shielding gate and the control gate; wherein the first shielding gate and the second shielding gate have the same potential as the emitter.

2. The trench-type insulated gate bipolar transistor according to claim 1, wherein: The highly doped storage layer is arranged on one side of the trench and close to the emitter, and the highly doped storage layer divides the front P-type well region located on one side of the trench into two upper and lower parts.

3. The trench-type insulated gate bipolar transistor according to claim 1, wherein: A gate dielectric layer is further provided in the trench, and the gate dielectric layer separates the first shielding gate, the second shielding gate and the control gate.

4. The trench-type insulated gate bipolar transistor according to claim 1, wherein: A contact region is formed between the front P-type well region and the emitter, and the contact region includes a P+ contact region and an N+ contact region.

5. A method for preparing a trench-type insulated gate bipolar transistor, characterized in that: For preparing a trench-type insulated gate bipolar transistor according to any one of claims 1 to 4, the preparation method comprising: Implanting ions into an N-type silicon substrate to form an N-type carrier storage layer; Implanting ions above the N-type carrier storage layer to form a front P-type well region; Etching to form a first trench, and depositing a first oxide layer in the first trench; depositing a first polysilicon layer on the first oxide layer to form a second shield gate; Etching the first polysilicon layer to form a second trench, and depositing a second oxide layer in the second trench; forming a left-right symmetrical first shield gate and a control gate in the second oxide layer; Using high-energy ion implantation to form a highly doped storage layer; Doping is performed on the front surface of the N-type silicon substrate and above the P-type well region to form a contact region, and an emitter is formed on the contact region; A back N-well region is formed on the back side of the N-type silicon substrate by N-type ion implantation, and then a back P-well region is formed by P-type ion implantation, wherein the back P-well region is located at the bottom and the back N-well region is located above the back P-well region.

6. The preparation method according to claim 5, characterized in that The method of forming a highly doped storage layer by high-energy ion implantation includes: Phosphorus is implanted into the P-type well region to form a highly doped storage layer, and the highly doped storage layer separates the front P-type well region located on one side of the trench into two upper and lower parts.

7. The preparation method according to claim 5, characterized in that The forming of a bilaterally symmetrical first shield gate and a control gate in the second oxide layer includes: Etching a bilaterally symmetrical third trench on the second oxide layer; A second polysilicon layer is filled in the third trench to form a first shield gate and a control gate; wherein the trench includes the first trench, the second trench and the third trench.

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