Spiking signal processing circuit

Abstract

The application provides a processing circuit of a spike signal, which comprises a signal input end, a signal output end, a signal path detection module, a comparison module and a filtering module. The signal path detection module comprises a first branch and a second branch. The first branch comprises a first voltage dividing resistor and a second voltage dividing resistor. The comparison module comprises a positive phase input end, a negative phase input end and an enable output end. The positive phase input end is electrically connected between the first voltage dividing resistor and the second voltage dividing resistor, and the negative phase input end is electrically connected to the second branch. The filtering module is electrically connected to the enable output end. When the signal input end inputs a spike signal, the first branch and the second branch are turned on, the comparison module outputs a first enable signal through the enable output end, the filtering module is controlled to be turned on, and thus the filtering module filters out the spike signal. Therefore, compared with a technical solution adopting a D flip-flop, the application does not need a digital circuit, can reduce the area of the circuit, further reduces the complexity of the circuit, and effectively improves the reaction speed of the circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically, to a processing circuit for spike signals. Background Technology

[0002] Due to the influence of the external environment, signals will generate various spike signals during propagation. For example, when a magnetic sensor is affected by an external high-frequency magnetic field signal, it will sense the external high-frequency magnetic field spike signal, causing the output to change due to the disturbance of the input magnetic field. Power supplies often generate some spike signals when providing power voltage signals to electronic devices.

[0003] With the advancement of technology, smart cards are becoming increasingly common, and their security has become a major concern. Smart cards, used in the security field for user identification and critical data storage, are widely applied in the financial sector, making them a prime target for attackers. High-security areas such as identity authentication and finance place higher demands on the anti-attack capabilities of the smart cards used.

[0004] Attackers can exploit faults, such as power glitch attacks, to cause chips to operate abnormally, leading to erroneous behavior. In this case, attackers can use Deterministic Finite Automaton (DFA) analysis techniques to compromise keys and obtain critical data.

[0005] A Power Glitch Detector (PGD) is used to detect glitches in the power supply voltage. When the PGD module detects a large glitch that poses a potential attack risk, it generates an alarm signal, thereby increasing the robustness and security of the chip system.

[0006] Spike signal detection circuits require a resistor-capacitor (RC) sampling structure and a comparator structure. The RC sampling structure samples the voltage on the signal path to be detected, and the comparator structure sets a threshold value through a resistor divider. It then compares the sampled voltage with the threshold value to determine whether to trigger an alarm signal. Furthermore, existing power supply glitches detection circuits often require D flip-flops for spike signal acquisition and output, increasing circuit complexity. Existing glitches detection circuits suffer from drawbacks such as low response speed, low sensitivity, and low portability. Summary of the Invention

[0007] In view of the deficiencies in the prior art, the purpose of this invention is to provide a processing circuit and device for spike signals.

[0008] A spike signal processing circuit according to the present invention includes:

[0009] Signal input terminal and signal output terminal;

[0010] The signal path detection module includes a first branch and a second branch connected in parallel; both the first branch and the second branch are electrically connected to the signal input terminal, wherein the first branch includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series.

[0011] The comparator module includes a positive input terminal and a negative input terminal, wherein the positive input terminal is electrically connected between the first voltage divider resistor R1 and the second voltage divider resistor R2, and the negative input terminal is electrically connected to the second branch; the comparator module also includes an enable output terminal.

[0012] The filtering module is electrically connected between the signal input terminal Vin and the signal output terminal Vout, and is also electrically connected to the enable output terminal.

[0013] When a spike signal is input to the signal input terminal, the first branch and the second branch are turned on, causing the comparison module to output a first enable signal through the enable output terminal to control the filtering module to turn on.

[0014] Preferably, the processing circuit includes a current mirror module, which is electrically connected to the first branch of the signal path detection module and is used to supply power to the first branch;

[0015] When a low-frequency signal is input to the signal input terminal, the first branch is turned on and the second branch is turned off, causing the comparison module to output a second enable signal through the enable output terminal to control the filter module to turn off.

[0016] Preferably, the filtering module includes a filtering submodule and a gating switch assembly, wherein the filtering submodule includes a filtering resistor R. F and filter capacitor C F The gating switch assembly includes a first gating switch ~EN and a second gating switch EN.

[0017] The filter resistor R F One end of the filter resistor R is electrically connected to the signal input terminal; F The other end is connected to the filter capacitor C via the first selection switch ~EN. F Electrically connected, and electrically connected to the signal output terminal via the second gating switch EN; the first gating switch EN is shorted to the second gating switch EN.

[0018] Preferably, the first gating switch ~EN and the second gating switch EN are mutually selected.

[0019] Preferably, the signal path detection module includes a sampling resistor R. L The first branch includes a first sampling capacitor C2; the second branch includes a second sampling capacitor C1; one end of the first sampling capacitor C2 is connected to the sampling resistor R. L One end of the capacitor is electrically connected to the signal input terminal, and the other end is electrically connected to the non-inverting input terminal through the first voltage divider resistor R1; one end of the second sampling capacitor C1 is connected to the sampling resistor R L One end is electrically connected to the signal input terminal, and the other end is electrically connected to the negative phase input terminal.

[0020] Preferably, the processing circuit further includes a power supply terminal VDD; the current mirror module includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3;

[0021] The source of the first PMOS transistor PM1, the source of the second PMOS transistor PM2, and the source of the third PMOS transistor PM3 are electrically connected to the power supply terminal VDD; the gate of the first PMOS transistor PM1 is electrically connected to the gate of the second PMOS transistor PM2 and the gate of the third PMOS transistor PM3, and the gate of the first PMOS transistor PM1 is shorted to the drain of the first PMOS transistor PM1; the drain of the second PMOS transistor PM2 is electrically connected to the non-inverting input terminal through the first voltage divider resistor R1.

[0022] The processing circuit further includes a reference current terminal Ibias; the drain of the first NMOS transistor NM1 is electrically connected to the reference current terminal Ibias, the gate of the first NMOS transistor NM1 is electrically connected to the gate of the second NMOS transistor NM2 and the gate of the third NMOS transistor NM3, and the drain of the first NMOS transistor NM1 is shorted to the gate of the first NMOS transistor NM1; the source of the first NMOS transistor NM1, the source of the second NMOS transistor NM2 and the source of the third NMOS transistor NM3 are all grounded; the drain of the second NMOS transistor NM2 is electrically connected to the drain of the first PMOS transistor PM1.

[0023] Preferably, the first branch further includes a fourth NMOS transistor NM4 and a fifth NMOS transistor NM5. The drain of the fourth NMOS transistor NM4 is electrically connected to the second voltage divider resistor R2; the gate of the fourth NMOS transistor NM4 is electrically connected to the gate of the fifth NMOS transistor NM5; the source of the fourth NMOS transistor NM4 is electrically connected to the drain of the fifth NMOS transistor NM5, and the gate of the fourth NMOS transistor NM4 is short-circuited to the drain of the fifth NMOS transistor NM5; the source of the fifth NMOS transistor is grounded.

[0024] Preferably, the processing circuit further includes a fourth PMOS transistor PM4; the second branch further includes a fifth PMOS transistor PM5; the source of the fourth PMOS transistor PM4 is electrically connected to the drain of the second PMOS transistor PM2, the drain of the fourth PMOS transistor PM4 is electrically connected to the drain of the third NMOS transistor NM3, the gate of the fourth PMOS transistor PM4 is electrically connected to the gate of the fifth PMOS transistor PM5, and the gate of the fourth PMOS transistor PM4 is shorted to the drain of the fourth PMOS transistor PM4; the source of the fifth PMOS transistor PM5 is electrically connected to the negative input terminal, and the drain of the fifth PMOS transistor PM5 is grounded;

[0025] When a spike signal is input to the signal input terminal, the gate of the PMOS transistor PM4 provides a bias voltage to the fifth PMOS transistor PM5, causing the fifth PMOS transistor PM5 to conduct.

[0026] Preferably, the first branch further includes a fourth NMOS transistor NM4; the current mirror module further includes a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and an eighth NMOS transistor NM8;

[0027] The drain of the sixth NMOS transistor NM6 is electrically connected to the drain of the third PMOS transistor PM3, the source of the sixth NMOS transistor NM6 is grounded, and the gate of the sixth NMOS transistor NM6 is shorted to its drain. The drain of the seventh NMOS transistor NM7 is electrically connected to the negative output terminal, and the gate of the seventh NMOS transistor NM7 is electrically connected to the gate of the sixth NMOS transistor NM6. The gate of the eighth NMOS transistor NM8 is electrically connected to the gate of the sixth NMOS transistor NM6, and the drain of the eighth NMOS transistor NM8 is electrically connected to the source of the seventh NMOS transistor NM7. The source of the eighth NMOS transistor NM8 is electrically connected to the source of the sixth NMOS transistor NM6 and is also electrically connected to the drain of the fourth NMOS transistor NM4.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. The spike signal processing circuit provided by the present invention can detect the amplitude and frequency of the signal input at the signal input terminal in real time. When a spike signal exists at the signal input terminal, the comparison module controls the filter module to turn on, thereby filtering out the spike signal.

[0030] 2. This invention uses an analog method, eliminating the need for D flip-flops and thus eliminating the need for digital circuitry. This reduces the area of ​​the spike signal processing circuit, thereby lowering the circuit complexity and effectively improving the circuit's response speed. Furthermore, the technical solution of this invention is highly portable and has a wide range of applications. Attached Figure Description

[0031] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0032] Figure 1 This is a block diagram of the spike signal processing circuit of the present invention;

[0033] Figure 2 This is a circuit diagram of the spike signal processing circuit of the present invention.

[0034] Explanation of reference numerals in the attached figures:

[0035] 1. Current mirror module 31, enable output terminal

[0036] 2. Signal path detection module; 4. Filtering module

[0037] 21. First branch 41. Filtering submodule

[0038] 22. Second branch 42. Selector switch assembly

[0039] 3. Comparison Module Detailed Implementation

[0040] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0041] This invention discloses a processing circuit for spike signals, with reference to... Figure 1 As shown, it includes: a signal input terminal Vin, a signal output terminal Vout, a current mirror module 1, a signal path detection module 2, a comparison module 3, a filtering module 4, and a signal output terminal Vout; the signal path detection module 2 is electrically connected to the signal input terminal Vin, the current mirror module 1 is electrically connected to the signal path detection module 2 and is used to supply power to the signal path detection module, the signal path detection module 2 is connected to the comparison module 3 and outputs an enable signal to the filtering module 4 through the comparison module 3, one end of the filtering module 4 is connected to the signal input terminal Vin, and the other end is connected to the signal output terminal Vout.

[0042] Specifically, refer to Figure 2 As shown:

[0043] In some embodiments, the signal path detection module 2 includes a first branch 21 and a second branch 22 connected in parallel; both the first branch 21 and the second branch 22 are electrically connected to the signal input terminal Vin, wherein the first branch 21 includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series.

[0044] Comparison module 3 includes a positive input terminal and a negative input terminal, wherein the positive input terminal is electrically connected between the first voltage divider resistor R1 and the second voltage divider resistor R2, and the negative input terminal is electrically connected to the second branch 22; comparison module 3 also includes an enable output terminal 31. In this embodiment, comparison module 3 includes, but is not limited to, a comparator.

[0045] The filter module 4 is electrically connected between the signal input terminal Vin and the signal output terminal Vout, and is also electrically connected to the enable output terminal 31.

[0046] The current mirror module 1 is electrically connected to the first branch 21 of the signal path detection module 2 and is used to supply power to the first branch 21.

[0047] When a spike signal is input to the signal input terminal Vin, the first branch 21 and the second branch 22 are turned on, so that the comparison module 3 outputs a first enable signal through the enable output terminal 31 to control the filter module 4 to turn on.

[0048] When a low-frequency signal is input to the signal input terminal Vin, the first branch 21 is turned on and the second branch 22 is turned off, causing the comparison module 3 to output a second enable signal through the enable output terminal 31, thereby controlling the filter module 4 to turn off. Thus, compared to the technical solution using D flip-flops, this technical solution does not require the participation of digital circuits, thereby reducing the area of ​​the spike signal processing circuit, reducing circuit complexity, effectively improving circuit response speed, and the technical solution of this invention has strong portability and wide applicability.

[0049] The circuit structure of each module will be further explained below.

[0050] In some embodiments, the filtering module 4 includes a filtering submodule 41 and a gating switch assembly 42, wherein the filtering submodule 41 includes a filtering resistor R. F and filter capacitor C F The gating switch assembly 42 includes a first gating switch EN and a second gating switch EN. The processing circuit also includes a signal output terminal Vout.

[0051] The filter resistor R F One end of the filter resistor R is electrically connected to the signal input terminal Vin; FThe other end is connected to the filter capacitor C via the first selection switch ~EN. F The circuit is electrically connected, and also electrically connected to the signal output terminal Vout via the second selector switch EN; the first selector switch ~EN and the second selector switch EN are short-circuited. The first selector switch ~EN and the second selector switch EN are mutually selectable, that is, when the first selector switch ~EN is closed, the second selector switch EN is open; when the first selector switch ~EN is open, the second selector switch EN is closed, thus controlling the filter resistor R. F With filter capacitor C F It has a good switching effect.

[0052] The working principle of filter module 4 is as follows: When the enable output terminal 31 outputs the first enable signal, it indicates that the voltage at the negative input terminal - of comparator module 3 is greater than that at the positive input terminal +. The enable output terminal 31 of comparator module 3 outputs a low level, thereby opening the second gating switch EN and closing the first gating switch ~EN, thus causing the filter resistor R to... F and filter capacitor C F Connected in series between the signal input terminal Vin and ground, the spike signal input at the signal input terminal Vin can then pass through the filter resistor R. F and filter capacitor C F Filtering. When the enable output terminal 31 outputs the second enable signal, it indicates that the voltage at the negative input terminal - of the comparator module 3 is less than that at the positive input terminal +. The enable output terminal 31 of the comparator module 3 outputs a high level, thereby closing the second gating switch EN and opening the first gating switch ~EN, which in turn causes the filter resistor R to... F With filter capacitor C F When disconnected, the low-frequency signal input at the signal input terminal Vin passes through the filter resistor R. F Transmitted to the signal output terminal Vout.

[0053] In some embodiments, the signal path detection module 2 includes a sampling resistor R. L The first branch 21 includes a first sampling capacitor C2; the second branch 22 includes a second sampling capacitor C1; one end of the first sampling capacitor C2 is connected to the sampling resistor R. L One end of the capacitor is electrically connected to the signal input terminal Vin, and the other end is electrically connected to the non-inverting input terminal through the first voltage divider resistor R1; one end of the second sampling capacitor C1 is connected to the sampling resistor R L One end is electrically connected to the signal input terminal Vin, and the other end is electrically connected to the negative phase input terminal. In this embodiment, the first branch 21 and the second branch 22 share a single sampling resistor R. L The sampling resistor R LThe first sampling capacitor C2 in the first branch 21 forms an RC sampling structure, and the second sampling capacitor C1 in the second branch 22 forms another RC sampling structure. These two RC sampling structures are used to sample the voltage signal input from the signal input terminal Vin. In this way, the sampling effect is good and the circuit is simple.

[0054] In some embodiments, the first branch 21 further includes a fourth NMOS transistor NM4 and a fifth NMOS transistor NM5. The drain of the fourth NMOS transistor NM4 is electrically connected to the second voltage divider resistor R2; the gate of the fourth NMOS transistor NM4 is electrically connected to the gate of the fifth NMOS transistor NM5; the source of the fourth NMOS transistor NM4 is electrically connected to the drain of the fifth NMOS transistor NM5, and the gate of the fourth NMOS transistor NM4 is short-circuited to the drain of the fifth NMOS transistor NM5; the source of the fifth NMOS transistor is grounded; and the gate of the fourth NMOS transistor NM4 is electrically connected to the negative input terminal - of the comparator module 3. When a low-frequency signal is input to the signal input terminal Vin, the drain current of the second PMOS transistor PM2 passes sequentially through the first voltage divider resistor R1, the second voltage divider resistor R2, the fourth NMOS transistor NM4, and the fifth NMOS transistor NM5 before being grounded. The gate of the fourth NMOS transistor NM4 inputs a voltage signal to the negative input terminal - of the comparator module 3, which serves as the minimum operating voltage of the comparator module 3. When a spike signal is input to the signal input terminal Vin, the spike current signal in the first branch 21 passes through the first voltage divider resistor R1, the second voltage divider resistor R2, the fourth NMOS transistor NM4, and the fifth NMOS transistor NM5 in sequence before being grounded.

[0055] In some embodiments, the current mirror module 1 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3; the processing circuit also includes a power supply terminal VDD.

[0056] The source of the first PMOS transistor PM1, the source of the second PMOS transistor PM2, and the source of the third PMOS transistor PM3 are electrically connected to the power supply terminal VDD; the gate of the first PMOS transistor PM1 is electrically connected to the gate of the second PMOS transistor PM2 and the gate of the third PMOS transistor PM3, and the gate of the first PMOS transistor PM1 is shorted to the drain of the first PMOS transistor PM1; the drain of the second PMOS transistor PM2 is electrically connected to the non-inverting input terminal through the first voltage divider resistor R1.

[0057] In some embodiments, the processing circuit further includes a reference current terminal Ibias; the drain of the first NMOS transistor NM1 is electrically connected to the reference current terminal Ibias, the gate of the first NMOS transistor NM1 is electrically connected to the gate of the second NMOS transistor NM2 and the gate of the third NMOS transistor NM3, and the drain of the first NMOS transistor NM1 is shorted to the gate of the first NMOS transistor NM1; the source of the first NMOS transistor NM1, the source of the second NMOS transistor NM2 and the source of the third NMOS transistor NM3 are all grounded; the drain of the second NMOS transistor NM2 is electrically connected to the drain of the first PMOS transistor PM1.

[0058] The working principle of the current mirror module 1: The first NMOS transistor NM1 is connected to the reference current terminal Ibias and copies the current Ibias to the second NMOS transistor NM2 and the third NMOS transistor NM3. The second NMOS transistor NM2 is connected to the first PMOS transistor PM1 and the currents of the two are the same. At this time, the first PMOS transistor PM1 copies the current to the second PMOS transistor PM2 and the third PMOS transistor PM3. The second PMOS transistor PM2 supplies power to the first branch 21.

[0059] In some embodiments, the current mirror module 1 further includes a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and an eighth NMOS transistor NM8. The drain of the sixth NMOS transistor NM6 is electrically connected to the drain of the third PMOS transistor PM3, the source of the sixth NMOS transistor NM6 is grounded, and the gate of the sixth NMOS transistor NM6 is shorted to its drain. The drain of the seventh NMOS transistor NM7 is electrically connected to the negative phase output terminal, and the gate of the seventh NMOS transistor NM7 is electrically connected to the gate of the sixth NMOS transistor NM6. The gate of the eighth NMOS transistor NM8 is electrically connected to the gate of the sixth NMOS transistor NM6, and the drain of the eighth NMOS transistor NM8 is electrically connected to the source of the seventh NMOS transistor NM7. The source of the eighth NMOS transistor NM8 is electrically connected to the source of the sixth NMOS transistor NM6 and is also electrically connected to the drain of the fourth NMOS transistor NM4.

[0060] When a low-frequency signal is input to the signal input terminal 5, the third PMOS transistor PM3 and the sixth NMOS transistor NM6 are connected, and there is bias current in the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5. At this time, the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 act as a transmission gate to transmit the gate voltage of the fifth NMOS transistor NM5 to the negative input terminal of the comparator module 3, which serves as the minimum operating voltage of the negative input terminal of the comparator module 3.

[0061] In some embodiments, the processing circuit further includes a fourth PMOS transistor PM4; the second branch 22 further includes a fifth PMOS transistor PM5; the source of the fourth PMOS transistor PM4 is electrically connected to the drain of the second PMOS transistor PM2, the drain of the fourth PMOS transistor PM4 is electrically connected to the drain of the third NMOS transistor NM3, the gate of the fourth PMOS transistor PM4 is electrically connected to the gate of the fifth PMOS transistor PM5, and the gate of the fourth PMOS transistor PM4 is shorted to the drain of the fourth PMOS transistor PM4; the source of the fifth PMOS transistor PM5 is electrically connected to the negative input terminal, and the drain of the fifth PMOS transistor PM5 is grounded;

[0062] When a spike signal is input to the signal input terminal Vin, the gate of the PMOS transistor PM4 provides a bias voltage to the fifth PMOS transistor PM5, causing PM5 to conduct. The spike current in the second branch 22 is divided into two paths: one flows to the negative input terminal of the comparator module 3, and the other flows to ground through the fifth PMOS transistor PM5. A large amount of the spike current flows out through the fifth PMOS transistor PM5, and a small amount flows to the negative input terminal. At this time, the current in the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 is equal to the current in the third PMOS transistor PM3 and the sixth NMOS transistor NM6.

[0063] Spike signal processing principle:

[0064] When a spike signal is input to the signal input terminal Vin, the first capacitor C1 and the second capacitor C2 are turned on, and the first branch 21 and the second branch 22 are turned on. Since the spike voltage is large, the spike voltage has the main impact on the input terminal of the comparison module 3. Therefore, the voltage at the negative input terminal of the comparison module 3 is the coupled spike voltage, and the voltage at the positive input terminal of the comparison module 3 is the voltage after the spike voltage is divided by the first voltage divider resistor R1 and the second voltage divider resistor R2. The voltage at the negative input terminal is greater than the voltage at the positive input terminal. The comparison module 3 outputs a first enable signal through the enable output terminal 31 to control the filter module 4 to turn on.

[0065] When a low-frequency signal is input to the signal input terminal Vin, the first capacitor C1 and the second capacitor C2 are not conducting. The drain of the second PMOS transistor supplies power to the first branch 21, and the first branch 21 is conducting. At this time, the second branch 22 is disconnected. The voltage at the positive input terminal of the comparison module 3 consists of two parts: the voltage after the drain voltage of the second PMOS transistor is divided by the first voltage divider resistor R1 and the second voltage divider resistor R2, and the gate voltage of the fifth NMOS transistor NM5. The voltage at the negative input terminal of the comparison module 3 is the gate voltage of the fifth NMOS transistor NM5. At this time, the voltage at the positive input terminal is greater than the voltage at the negative input terminal, so that the comparison module 3 outputs a second enable signal through the enable output terminal 31 to control the filter module 4 to disconnect.

[0066] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A processing circuit for spike signals, characterized in that, include: Signal input terminal Vin and signal output terminal Vout; The signal path detection module (2) includes a first branch (21) and a second branch (22) connected in parallel; the first branch (21) and the second branch (22) are both electrically connected to the signal input terminal Vin, wherein the first branch (21) includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series; The comparison module (3) includes a positive input terminal and a negative input terminal, wherein the positive input terminal is electrically connected between the first voltage divider resistor R1 and the second voltage divider resistor R2, and the negative input terminal is electrically connected to the second branch (22); the comparison module (3) also includes an enable output terminal (31). The filter module (4) is electrically connected between the signal input terminal Vin and the signal output terminal Vout, and is also electrically connected to the enable output terminal (31). When the signal input terminal Vin receives a spike signal, the first branch (21) and the second branch (22) are turned on, so that the comparison module (3) outputs a first enable signal through the enable output terminal (31) to control the filter module (4) to turn on; The filtering module (4) includes a gating switch component (42); The gating switch assembly (42) includes a first gating switch. Second selector switch EN; When the first selection switch When closed, the second selector switch EN is open; when the first selector switch... When disconnected, the second selector switch EN is closed; The filtering module (4) includes a filtering submodule (41), and the filtering submodule (41) includes a filtering resistor. and filter capacitor ; The filter resistor One end of the filter resistor is electrically connected to the signal input terminal Vin; The other end is connected to the first selector switch. With the filter capacitor Electrically connected, and electrically connected to the signal output terminal Vout via the second gating switch EN; the first gating switch It is short-circuited with the second selector switch EN.

2. The spike signal processing circuit according to claim 1, characterized in that, The processing circuit includes a current mirror module (1), which is electrically connected to the first branch (21) of the signal path detection module (2) and is used to supply power to the first branch (21); When a low-frequency signal is input to the signal input terminal Vin, the first branch (21) is turned on and the second branch (22) is turned off, so that the comparison module (3) outputs a second enable signal through the enable output terminal (31) to control the filter module (4) to turn off.

3. The spike signal processing circuit according to claim 1, characterized in that, First selection switch It is mutually selected with the second selection switch EN.

4. The spike signal processing circuit according to claim 1, characterized in that, The signal path detection module (2) includes a sampling resistor. The first branch (21) includes a first sampling capacitor C2; the second branch (22) includes a second sampling capacitor C1; one end of the first sampling capacitor C2 is connected to the sampling resistor. One end of the capacitor is electrically connected to the signal input terminal Vin, and the other end is electrically connected to the non-inverting input terminal through the first voltage divider resistor R1; one end of the second sampling capacitor C1 is connected to the sampling resistor. One end is electrically connected to the signal input terminal Vin, and the other end is electrically connected to the negative phase input terminal.

5. The spike signal processing circuit according to claim 2, characterized in that, The processing circuit also includes a power supply terminal VDD; the current mirror module (1) includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3; The source of the first PMOS transistor PM1, the source of the second PMOS transistor PM2, and the source of the third PMOS transistor PM3 are electrically connected to the power supply terminal VDD; the gate of the first PMOS transistor PM1 is electrically connected to the gate of the second PMOS transistor PM2 and the gate of the third PMOS transistor PM3, and the gate of the first PMOS transistor PM1 is shorted to the drain of the first PMOS transistor PM1; the drain of the second PMOS transistor PM2 is electrically connected to the non-inverting input terminal through the first voltage divider resistor R1. The processing circuit further includes a reference current terminal Ibias; the drain of the first NMOS transistor NM1 is electrically connected to the reference current terminal Ibias, the gate of the first NMOS transistor NM1 is electrically connected to the gate of the second NMOS transistor NM2 and the gate of the third NMOS transistor NM3, and the drain of the first NMOS transistor NM1 is shorted to the gate of the first NMOS transistor NM1; the source of the first NMOS transistor NM1, the source of the second NMOS transistor NM2 and the source of the third NMOS transistor NM3 are all grounded; the drain of the second NMOS transistor NM2 is electrically connected to the drain of the first PMOS transistor PM1.

6. The spike signal processing circuit according to claim 1, characterized in that, The first branch (21) further includes a fourth NMOS transistor NM4 and a fifth NMOS transistor NM5. The drain of the fourth NMOS transistor NM4 is electrically connected to the second voltage divider resistor R2. The gate of the fourth NMOS transistor NM4 is electrically connected to the gate of the fifth NMOS transistor NM5. The source of the fourth NMOS transistor NM4 is electrically connected to the drain of the fifth NMOS transistor NM5, and the gate of the fourth NMOS transistor NM4 is short-circuited to the drain of the fifth NMOS transistor NM5. The source of the fifth NMOS transistor is grounded.

7. The spike signal processing circuit according to claim 5, characterized in that, The processing circuit further includes a fourth PMOS transistor PM4; the second branch (22) further includes a fifth PMOS transistor PM5; the source of the fourth PMOS transistor PM4 is electrically connected to the drain of the second PMOS transistor PM2, the drain of the fourth PMOS transistor PM4 is electrically connected to the drain of the third NMOS transistor NM3, the gate of the fourth PMOS transistor PM4 is electrically connected to the gate of the fifth PMOS transistor PM5, and the gate of the fourth PMOS transistor PM4 is short-circuited with the drain of the fourth PMOS transistor PM4; the source of the fifth PMOS transistor PM5 is electrically connected to the negative input terminal, and the drain of the fifth PMOS transistor PM5 is grounded; When a spike signal is input to the signal input terminal Vin, the gate of the PMOS transistor PM4 provides a bias voltage to the fifth PMOS transistor PM5, causing the fifth PMOS transistor PM5 to conduct.

8. The spike signal processing circuit according to claim 5, characterized in that, The first branch (21) also includes a fourth NMOS transistor NM4; the current mirror module (1) also includes a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and an eighth NMOS transistor NM8; The drain of the sixth NMOS transistor NM6 is electrically connected to the drain of the third PMOS transistor PM3, the source of the sixth NMOS transistor NM6 is grounded, and the gate of the sixth NMOS transistor NM6 is shorted to its drain. The drain of the seventh NMOS transistor NM7 is electrically connected to the negative input terminal, and the gate of the seventh NMOS transistor NM7 is electrically connected to the gate of the sixth NMOS transistor NM6. The gate of the eighth NMOS transistor NM8 is electrically connected to the gate of the sixth NMOS transistor NM6, and the drain of the eighth NMOS transistor NM8 is electrically connected to the source of the seventh NMOS transistor NM7. The source of the eighth NMOS transistor NM8 is electrically connected to the source of the sixth NMOS transistor NM6 and is also electrically connected to the drain of the fourth NMOS transistor NM4.

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