Control circuit, control method and primary side feedback flyback converter applying the same

Abstract

The application discloses a control circuit, a control method and a primary side feedback flyback converter applying the same. The primary side feedback flyback converter is controlled according to a feedback of a current sampling signal to work in a constant conduction time control mode when an input voltage is relatively large, and to switch between a current peak value mode and a first working mode at a fixed time when the input voltage is near a valley, so that the primary side current peak value will not be too low due to a low input voltage, and will not be too high due to working in the current peak value mode all the time when the input voltage is near the valley, thereby avoiding errors in sampling after a blanking time caused by a too large demagnetization time, and avoiding distortion of the input current valley, thereby avoiding worsening of the PF value and THD.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a control circuit, a control method, and a primary-side feedback flyback converter using the same. Background Technology

[0002] For switching converters, a constant on-time control method is typically used to achieve a higher power factor. This is because the ratio of the input current to the input voltage is directly proportional to the square of the on-time and the ratio of the switching period. Therefore, by fixing the on-time, and given that the switching period does not vary significantly throughout the power frequency cycle, the input current can largely follow the input voltage, thus achieving a higher power factor (PFC). Consequently, converters controlled by constant on-time are frequently used in power factor correction circuits.

[0003] However, due to periodic or non-periodic fluctuations in the input voltage, if the constant on-time control is still applied when the input voltage is near its lowest point, the peak current flowing through the primary power switch near this voltage trough will become very low. This leads to a decrease in the peak secondary current, which in turn shortens the secondary demagnetizing time. The shortened demagnetizing time results in incorrect voltage information being sampled after the blanking time, leading to a significant deviation in the output voltage.

[0004] To solve the above-mentioned technical problems, in one existing technical solution, reference is made to... Figure 1 The working waveform shown is based on the feedback V of the current sampling signal. ISEN The primary-side feedback flyback converter is controlled to operate in constant on-time control mode when the input voltage is high, and in peak current mode when the input voltage is near its lowest point, so that the peak primary-side current is equal to V. ISEN_MIN This method avoids excessively low input voltage, thus preventing sampling errors after the blanking time due to large variations in demagnetization time. However, a drawback of this control method is that when the input voltage is near its lowest point, the current sampling signal is large, causing the Pai filter to oscillate. This distorts the input AC current at its lowest point, worsening the power factor (PF) and total electrical discharge temperature (THD). Summary of the Invention

[0005] In view of this, the present invention provides a control circuit, a control method, and a primary-side feedback flyback converter using the same, to solve the problem that when the input voltage is near its valley value, the large input current causes distortion at the valley of the input AC current, thereby worsening the power factor (PF) and total voltage distortion (THD).

[0006] In a first aspect, a control circuit is provided for controlling the power stage circuit of a primary-side feedback flyback converter, the control circuit comprising:

[0007] The current sampling circuit is used to sample the primary current to obtain the current sampling signal;

[0008] The voltage sampling circuit is used to sample the voltage of the auxiliary winding to obtain a voltage sampling signal;

[0009] A control signal generation circuit is used to generate a switch control signal based on the voltage sampling signal, the current sampling signal, and a timing signal. The control signal generation circuit generates the switch control signal in a first operating mode when the current sampling signal is greater than a current threshold at a predetermined time; generates the switch control signal in a current peak mode when the timing signal is valid at a predetermined time and generates the switch control signal in the first operating mode when the timing signal is invalid.

[0010] The predetermined time is the time when the effective state of the switch control signal ends in the first working mode.

[0011] Preferably, the control signal generation circuit includes:

[0012] A set signal generation circuit is used to output a set signal based on the voltage sampling signal when the secondary current crosses zero or the voltage sampling signal is at its lowest point.

[0013] A zero-set signal generation circuit is used to output a zero-set signal when the predetermined time arrives when the timing signal is in an invalid state; and to output a zero-set signal when the current sampling signal is greater than the current threshold and the predetermined time arrives when the timing signal is in an valid state.

[0014] A logic circuit is used to enable the switch control signal according to the set signal and disable the switch control signal according to the reset signal.

[0015] Preferably, the zero-set signal generation circuit includes:

[0016] A timing circuit is used to generate the timing signal;

[0017] A comparator is used to compare the current sampling signal and the current threshold and output a comparison result;

[0018] A conduction time control circuit is used to generate a first reset signal, which is used to characterize the time when the effective state of the switch control signal ends;

[0019] The zero-set logic circuit generates the zero-set signal based on the timing signal, the comparison result, and the first reset signal.

[0020] Preferably, the timing circuit outputs a valid timing signal when the timing reaches a timing threshold, and outputs an invalid timing signal when the timing signal is valid and the current sampling signal reaches the current threshold.

[0021] Preferably, the timing circuit outputs a valid timing signal when the timing reaches a timing threshold, and outputs an invalid timing signal when the timing signal is valid, the current sampling signal reaches the current threshold, and the switch control signal jumps to an invalid state.

[0022] Preferably, when the timing signal is in an invalid state, the zero-set logic circuit sets the zero-set signal to an active state when the first reset signal is active; when the timing signal is active, the zero-set signal is set to an active state when both the first reset signal and the comparison result are active.

[0023] Preferably, the conduction time control circuit is a constant conduction time control circuit, which generates a first reset signal for the valid state when the duration of the switch control signal being in the valid state reaches a predetermined constant conduction time.

[0024] Preferably, the conduction time control circuit is a peak current control circuit, which generates a first reset signal of the effective state when the current sampling signal reaches the compensation signal, wherein the compensation signal is used to characterize the error between the output current and the current reference signal.

[0025] Preferably, the current threshold value is constant.

[0026] Preferably, the current threshold value is related to the output load of the circuit. When the load is heavy, the current threshold value is small; when the load is light, the current threshold value is large.

[0027] Preferably, the frequency of the timing signal is fixed, or the duration of the timing signal being in an invalid state is fixed.

[0028] Preferably, the voltage sampling circuit samples the auxiliary winding voltage after the blanking time to obtain the voltage sampling signal, wherein the blanking time varies according to the peak value of the current sampling signal.

[0029] Secondly, a primary-side feedback flyback converter is provided, comprising:

[0030] Power stage circuits; and

[0031] The control circuit described above.

[0032] Thirdly, a control method is provided for controlling a primary-side feedback flyback converter, including:

[0033] Sample the primary current to obtain the current sampling signal, and sample the auxiliary winding voltage to obtain the voltage sampling signal;

[0034] The power switch of the primary-side feedback flyback converter is controlled according to the voltage sampling signal, the current sampling signal, and a timing signal. When the current sampling signal is greater than the current threshold at a predetermined time, the power switch is controlled in a first operating mode. When the current sampling signal is less than the current threshold at a predetermined time, the power switch is controlled by switching the current peak mode and the first operating mode according to the timing signal.

[0035] The predetermined time is the time when the effective state of the switch control signal ends in the first working mode.

[0036] Preferably, controlling the power switch of the primary-side feedback flyback converter according to the voltage sampling signal, the current sampling signal, and a certain timing signal includes:

[0037] The power switch is controlled to turn on when the secondary current crosses zero or the voltage sampling signal is at its lowest point, based on the voltage sampling signal; and

[0038] When the timing signal is invalid, the power switch is controlled to turn off when the predetermined time is reached; when the timing signal is valid, the power switch is controlled to turn off when the current sampling signal is greater than the current threshold and the predetermined time is reached.

[0039] This invention aims to provide a control circuit, a control method, and a primary-side feedback flyback converter using the same. By controlling the primary-side feedback flyback converter based on the feedback of the current sampling signal, it operates in a constant on-time control mode when the input voltage is high, and switches periodically between a current peak mode and a first operating mode when the input voltage is near its valley. This ensures that the primary-side current peak is not too low due to a low input voltage, nor too high due to continuous operation in current peak mode when the input voltage is near its valley. This not only avoids sampling errors after the blanking time due to excessive changes in demagnetization time, but also avoids distortion due to the input current valley, which would worsen the power factor (PF) and total electrical discharge (THD). Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0041] Figure 1 The waveform diagram shows the working waveform of a flyback converter in the prior art.

[0042] Figure 2 This is a circuit diagram of a primary-side feedback flyback converter according to an embodiment of the present invention;

[0043] Figure 3 This is a waveform diagram of the control circuit under light load in an embodiment of the present invention;

[0044] Figure 4 This is a waveform diagram of the control circuit under heavy load in an embodiment of the present invention;

[0045] Figure 5 This is a circuit diagram of the control signal generation circuit according to an embodiment of the present invention. Detailed Implementation

[0046] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0047] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0048] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0049] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0050] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0051] Figure 2 This is a circuit diagram of a primary-side feedback flyback converter according to an embodiment of the present invention. Figure 2 As shown, the primary-side feedback flyback converter includes a power stage circuit 1 and a control circuit 2. The power stage circuit 1 is a flyback topology, including a primary winding L1 and a power switch S connected in series between the voltage input terminal Vin and the ground terminal, a secondary winding L2 coupled to the primary winding L1, and a secondary rectifier circuit 11 connected to the secondary winding L2. The power stage circuit 1 also includes an auxiliary winding L3 and voltage divider resistors R1 and R2 that divide the voltage across the auxiliary winding. The auxiliary winding L3 is coupled to the primary winding L1. The output voltage information of the power stage circuit 1, the zero-crossing time of the current in the secondary winding L2, and the current valley time information can be obtained through the voltage across the auxiliary winding L3. Therefore, by sampling the voltage across the auxiliary winding L3 after voltage division, the above information can be obtained, and the power switch S can be controlled based on the above information.

[0052] After the power switch S is turned off, the voltage across the auxiliary winding L3 will oscillate. This oscillation causes voltage fluctuations, leading to missampling. The missampled voltage is not correlated with the output voltage of power stage circuit 1, resulting in errors in the control of the power switch S. To avoid missampling, a blanking time needs to be set to prevent voltage sampling during the oscillation period of the auxiliary winding L3.

[0053] Existing control circuits, based on feedback from the current sampling signal, control the primary-side feedback flyback converter to operate in constant on-time control mode when the input voltage is high, and in peak current mode when the input voltage is near its valley. This prevents the primary-side current peak from becoming excessively low due to a low input voltage, thus avoiding sampling errors after the blanking time due to excessive changes in demagnetization time. However, when the input voltage is near its valley, the large input current causes distortion at the valley of the input AC current, thus worsening the power factor (PF) and total electrical discharge temperature (THD). Therefore, the control circuit 2 of this embodiment of the invention is needed to solve the above problems.

[0054] The control circuit 2 includes a current sampling circuit 21, a voltage sampling circuit 22, and a control signal generation circuit 23.

[0055] Among them, the current sampling circuit 21 is used to sample the primary current I. P Acquire current sampling signal VISEN Current sampling signal V ISEN The primary current IP is used to characterize the current, which is a voltage signal. It should be understood that a current signal can also be used as the current sampling signal.

[0056] Voltage sampling circuit 22 is used to sample the auxiliary winding voltage V after the blanking time. SEN Acquire voltage sampling signal V DEC Voltage sampling signal V DEC It is used to characterize the change in auxiliary winding voltage after the blanking time.

[0057] The control signal generation circuit 23 is used to generate signals based on the voltage sampling signal V. DEC Current sampling signal V ISEN And a switching control signal Q is generated from a certain time signal V3. The switching control signal Q is used to control the power switch S to turn on or off. The control signal generation circuit 23 generates the switching control signal Q based on the current sampling signal V3. ISEN The current is greater than the predetermined threshold V at the predetermined time. ISEN_MIN At that time, a switch control signal Q is generated in the first operating mode; when the current sampling signal V... ISEN The current is less than the predetermined threshold V at the predetermined time. ISEN_MIN When the timing signal V3 is active, the switch control signal Q is generated in peak current mode; when the timing signal V3 is inactive, the switch control signal Q is generated in the first operating mode. The predetermined time is the time when the active state of the switch control signal Q ends in the first operating mode.

[0058] It should be noted that the first operating mode may be, but is not limited to, a constant on-time control mode, where the constant on-time control mode uses a constant on-time T. ON The on-time when generating the switch control signal Q. When the first operating mode is the constant on-time control mode, the above-mentioned predetermined time is the duration during which the switch control signal Q remains effective until the constant on-time T is reached. ON The time or current sampling signal V ISEN From the lowest point, the conduction time T remains constant and increases continuously. ON At that moment. The first operating mode can also be peak control mode, where the peak control mode is activated by the current sampling signal V. ISEN To achieve the compensation signal V COMP When the switch control signal Q is set to an invalid state, the compensation signal V... COMP This is used to characterize the error between the output current and the current reference signal. When the first operating mode is peak control mode, the aforementioned predetermined time is the current sampling signal V. ISEN It rises from its lowest point to reach the compensation signal V. COMPAt that moment. It should be noted that the peak control mode here specifically refers to the time when the current sampling signal V... ISEN To achieve the compensation signal V COMP This control mode sets the switch control signal Q to an invalid state, which differs from the current peak mode mentioned above. The current peak mode refers to the mode where the current sampling signal V is set to an invalid state. ISEN The rise reaches the current threshold V ISEN_MIN The mode that sets the switch control signal Q to an invalid state.

[0059] Figure 3 This is a waveform diagram of the control circuit under light load according to an embodiment of the present invention. Here, the first operating mode is a constant on-time control mode, as an example. Figure 3 As shown, the input voltage Vin decreases periodically or non-periodically, causing the slope of the primary current IP (i.e., the input current) to decrease, and its peak value also decreases accordingly. During the time interval t0-t1, the primary current IP undergoes a constant on-time T. ON After the rise, its value at the end of the constant conduction time of the power switch S is less than the current threshold V. ISEN_MIN At this time, the timing signal V3 is low, i.e., in an invalid state. A switch control signal Q is generated in the first operating mode, i.e., constant on-time control mode. The switch control signal Q is set to an invalid state at the end of the constant on-time, the power switch S is turned off, and the primary current IP becomes 0, until the power switch S is turned on again. During the time interval t1-t2, the primary current IP passes through a constant on-time T. ON After rising, its value is less than the current threshold V at the end of the constant conduction time. ISEN_MIN This indicates that the current input voltage is still too low. The low peak value of the primary current IP will result in a very short demagnetization time, leading to missampling. At this time, the timing signal V3 is high, i.e., in an active state, and generates the switch control signal Q in peak current mode. Therefore, the power switch S is not turned off, and the system waits for the primary current IP to continue rising to the current threshold V. ISEN_MIN Then turn off the power switch S. And so on, during the time interval t2-t3, the primary current IP rises for a constant on-time T. ON After the power switch S is turned off, during the time interval t3-t4, the primary current IP rises to the current threshold V. ISEN_MIN Turn off the power switch S again.

[0060] Therefore, it can be ensured that when the input voltage is low, the peak value of the primary current IP can periodically rise to the current threshold V according to the timing signal. ISEN_MINThis ensures that the demagnetization time of the secondary current IS does not fall below a minimum value. Since the minimum demagnetization time can be increased, the blanking time can be set so that voltage sampling at the minimum demagnetization time will not lead to missampling. Therefore, it avoids errors in sampling after the blanking time due to excessive changes in the demagnetization time. Furthermore, when the input voltage is low, the peak value of the primary current IP only rises to the current threshold V when the timing signal is valid. ISEN_MIN When the timing signal is invalid, the primary current IP only rises for a constant on-time T. ON This ensures that the input current is not too large, thereby avoiding distortion due to the input current trough, which could worsen the power factor (PF) and total shock (THD).

[0061] Figure 4 This is a waveform diagram of the control circuit under heavy load according to an embodiment of the present invention. Figure 4 As shown, during the time interval t0-t1, the primary current IP undergoes a constant conduction time T. ON After the rise, its value at the end of the constant conduction time is greater than the current threshold V. ISEN_MIN At this time, regardless of the state of the timing signal V3, the switching control signal Q is generated in peak current mode. The switching control signal Q rises to the current threshold V when the primary current IP reaches the current threshold V. ISEN_MIN When time t1 is set to invalid, power switch S is turned off, and the primary current IP becomes 0 until the next time power switch S is turned on. During time t1-t2, the primary current IP undergoes a constant on-time T. ON After rising, its value is less than the current threshold V at the end of the constant conduction time. ISEN_MIN This indicates that the current input voltage is low. At this time, the timing signal V3 is low, and the switch control signal Q is generated in the first operating mode, i.e., the constant on-time control mode. The switch control signal Q is set to an invalid state at the end of the constant on-time. During the period t2-t3, the primary current IP passes through the constant on-time T. ON After rising, its value is less than the current threshold V at the end of the constant conduction time. ISEN_MIN At this time, the timing signal V3 is high, generating the switch control signal Q in peak current mode. Therefore, the power switch S is not turned off, and the system waits for the primary current IP to continue rising to the current threshold V. ISEN_MIN Then turn off the power switch S. During the time interval t3-t4, the primary current IP has a constant on-time T. ON After rising, its value is less than the current threshold V at the end of the constant conduction time. ISEN_MIN At this time, the timing signal V3 is low, and the switch control signal Q is generated in the first working mode, namely the constant conduction time control mode. The switch control signal Q is set to an invalid state at the end of the constant conduction time.

[0062] Figure 5 This is a circuit diagram of the control signal generation circuit according to an embodiment of the present invention. Figure 5 As shown, the control signal generation circuit 23 includes a set signal generation circuit 31, a zero signal generation circuit 32, and a logic circuit 33.

[0063] The set signal generation circuit 31 is used to generate a set signal based on the voltage sampling signal V. DEC The detection time is when the secondary current crosses zero or when the auxiliary winding voltage reaches its lowest point. This occurs when the secondary current Is crosses zero or when the voltage sampling signal V... DEC When the voltage is at its lowest point, a set signal Vs is output. The set signal Vs can be a voltage pulse, a rising edge, or a falling edge.

[0064] It should be noted that the voltage sampling signal V DEC It has two functions: first, to detect the output voltage signal, used for constant voltage output control or overvoltage detection of the flyback converter; second, to detect the valley signal, used to generate the set signal Vs. In this invention, since it is not necessary to sample the current signal Vs in each switching cycle... ISEN All reached the current threshold V ISEN_MIN Therefore, to avoid the primary current IP being too low and the demagnetization time being too short, which would lead to a short voltage sampling signal V... DEC If the sampled output voltage signal is incorrect, preferably, it should only be detected in the current sampling signal V. ISEN Able to reach the current threshold V ISEN_MIN During the switching cycle, the voltage sampling signal V DEC Only the sampled output voltage signal is valid. When the current sampling signal V... ISEN The current threshold V is not reached ISEN_MIN At this time, the demagnetization time is very short, and the voltage sampling signal V obtained in the current switching cycle is... DEC It is prone to errors, therefore the voltage sampling signal V obtained in the current switching cycle is not used. DEC Instead of using the output voltage signal, the most recent current sampling signal V is used. ISEN Able to reach the current threshold V ISEN_MIN The voltage sampling signal V obtained and held during the switching cycle DEC To characterize the output voltage signal.

[0065] The zero-set signal generation circuit 32 is used to output a zero-set signal V when the predetermined time arrives, while the timing signal V3 is in an invalid state. R When timing signal V3 is active, current sampling signal V ISEN Greater than the current threshold V ISEN_MIN And when the predetermined time arrives, the output is set to zero signal V. R .

[0066] The zero-set signal generation circuit 32 is used to control the switching between constant on-time control mode and current peak mode. Its required operation is to keep the power switch S on for a constant on-time T. ON or current sampling signal V ISEN To achieve the compensation signal V COMP At that time, the current sampling signal V is detected. ISEN Is it greater than the current threshold V? ISEN_MIN If it is greater than, then immediately output a zero-set signal V. R Turn off power switch S (first operating mode); if less than, and if timing signal V3 is valid, wait for current sampling signal V. ISEN It continues to rise until its peak value reaches the current threshold V. ISEN_MIN Then output a zero-set signal V R When power switch S is turned off (current peak control mode), if timing signal V3 is invalid, the power switch S will remain on for a constant on time T. ON or current sampling signal V ISEN To achieve the compensation signal V COMP Output zero signal V R Turn off power switch S (current peak control mode). Specifically, this can be achieved using methods such as... Figure 5 The circuit shown is used to implement this, but it is easy to understand that those skilled in the art can implement the specific circuit in other ways based on the above settings.

[0067] like Figure 5 As shown, the zero-set signal generation circuit 32 includes a timing circuit 321, a comparator 322, an on-time control circuit 323, and a zero-set logic circuit 324.

[0068] Timing circuit 321 is used to generate timing signal V3. When the timing reaches a timing threshold (which represents the duration for which timing signal V3 is in an invalid state), timing circuit 321 outputs a valid timing signal V3 (e.g., a high level), and when timing signal V3 is in a valid state and current sampling signal V... ISEN Reaching the current threshold V ISEN_MIN The timing signal V3 is in an invalid state (e.g., low level) or the timing signal V3 is in an valid state and the current sampling signal V ISEN Reaching the current threshold VISEN_MINFurthermore, when the switch control signal Q transitions to an invalid state, an invalid timing signal V3 (e.g., a low level) is output. In this embodiment, the duration of the invalid state of the timing signal V3 is fixed, while the duration of its valid state is not fixed; therefore, the frequency of the timing signal V3 is not fixed. However, it is understood that in other embodiments, the frequency of the timing signal V3 can also be fixed, and the frequency of the timing signal V3 can be set according to the lowest input current.

[0069] Comparator 322 is used to compare the current sampling signal V. ISEN and current threshold V ISEN_MIN Output the comparison result V2.

[0070] The on-time control circuit 323 is used to generate a first reset signal V1. The timing signal V1 is used to characterize the time when the effective state of the switch control signal Q ends (that is, when the constant on-time of the current cycle ends or the current sampling signal V). ISEN To achieve the compensation signal V COMP When the on-time control circuit 323 is a constant on-time control circuit, a first reset signal V1 for the active state is generated when the duration of the active state of the switch control signal Q reaches the predetermined constant on-time. When the on-time control circuit 323 is a peak current control circuit, a first reset signal V1 for the active state is generated when the current sampling signal V... ISEN To achieve the compensation signal V COMP The first reset signal V1 is generated at each effective state.

[0071] Therefore, the timing signal V1 and the comparison result V2 output by the conduction time control circuit 323 and comparator 322 can respectively characterize the conduction time T reached by the switch control signal Q remaining in an active state. ON Whether it meets the requirements, and the current sampling signal V ISEN Rise to the current threshold V ISEN_MIN Does it meet the requirements?

[0072] The zero-set logic circuit 324 generates the zero-set signal V based on the timing signal V3, the comparison result V2, and the first reset signal V1. R Specifically, when the timing signal V3 of the reset logic circuit 324 is in an invalid state, and the first reset signal V1 is in an valid state, the reset signal V... R The timer signal V3 is set to an active state; when the timer signal V3 is active, and both the first reset signal V1 and the comparison result V2 are active, the zero signal V is set to an active state. R It has been set to a valid state.

[0073] In this embodiment, the timing signal V3 is high to indicate its active state, and the first reset signal V1 is high to indicate that the switch control signal Q remains active for the conduction time T.ON The comparison result V2 also represents the current sampling signal V with a high level. ISEN Rise to the current threshold V ISEN_MIN Therefore, the zero-set logic circuit 324 can be constructed using NOT gate N, AND gate AND1, OR gate OR, and AND gate AND2. Specifically, AND gate AND1 takes timing signal V3 and comparison result V2 as inputs, and outputs a valid state fifth signal V5 when both are high. OR gate OR takes fifth signal V5 and fourth signal V4 (the result of inverting timing signal V3 via NOT gate N) as inputs, and outputs a valid state sixth signal V6 when either one is high. AND gate AND1 takes sixth signal V6 and first reset signal V1 as inputs, and outputs a zero-set signal V that transitions at that moment when both are high. R This causes the control signal generation circuit 23 to set the switch control signal Q to invalid.

[0074] Logic circuit 33 is used to set the switch control signal Q to active based on the set signal Vs, and to set the switch control signal Q to active based on the reset signal Vs. R The switch control signal Q is set to invalid. In this embodiment, setting the switch control signal to valid means setting it to a level that enables the power switch to turn on, and setting it to invalid means setting it to a level that enables the power switch to turn off. In this embodiment, logic circuit 33 is implemented using an RS flip-flop.

[0075] By controlling the primary-side feedback flyback converter based on the feedback of the current sampling signal, it operates in a constant on-time control mode when the input voltage is high, and switches between the current peak mode and the first operating mode at regular intervals when the input voltage is near the valley. This ensures that the primary-side current peak is not too low due to the low input voltage, nor too high due to continuous operation in the current peak mode when the input voltage is near the valley. This not only avoids sampling errors after the blanking time due to excessive changes in demagnetization time, but also avoids distortion due to the input current valley, which would worsen the power factor (PF) and total electrical discharge (THD).

[0076] Furthermore, the current sampling signal V can be set to... ISEN The blanking time is varied to better prevent sampling errors caused by a predetermined blanking time. According to circuit principles, the current sampling signal V... ISEN A higher value indicates greater leakage inductance energy, and also suggests a longer demagnetizing time, meaning more severe oscillations of the leakage inductance and its parasitic capacitance after the power switch is turned off. Therefore, it is preferable to use a blanking time that follows the current sampling signal V. ISEN The way of working changes with the changes.

[0077] Furthermore, the current threshold V in peak current modeISEN_MIN The value of V can be constant or related to the output load of the circuit. When the load is heavy, the current threshold V... ISEN_MIN A smaller value for V allows for further reduction of input current distortion when the input voltage is near its lowest point; when the load is light, the current threshold V... ISEN_MIN A larger value is used to increase the demagnetization time and further improve the voltage sampling signal V. DEC The accuracy.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A control circuit for controlling the power stage circuit of a primary-side feedback flyback converter, the control circuit comprising: The current sampling circuit is used to sample the primary current to obtain the current sampling signal; The voltage sampling circuit is used to sample the voltage of the auxiliary winding to obtain a voltage sampling signal; A control signal generation circuit is used to generate a switch control signal based on the voltage sampling signal, the current sampling signal, and a timing signal. The control signal generation circuit generates the switch control signal in a first operating mode when the current sampling signal is greater than a current threshold at a predetermined time; generates the switch control signal in a current peak mode when the timing signal is valid at a predetermined time and generates the switch control signal in the first operating mode when the timing signal is invalid. The predetermined time is the time when the effective state of the switch control signal ends in the first working mode.

2. The control circuit according to claim 1, characterized in that, The control signal generation circuit includes: A set signal generation circuit is used to output a set signal based on the voltage sampling signal when the secondary current crosses zero or the voltage sampling signal is at its lowest point. A zero-set signal generation circuit is used to output a zero-set signal when the predetermined time arrives when the timing signal is in an invalid state; and to output a zero-set signal when the current sampling signal is greater than the current threshold and the predetermined time arrives when the timing signal is in an valid state. A logic circuit is used to enable the switch control signal according to the set signal and disable the switch control signal according to the reset signal.

3. The control circuit according to claim 2, characterized in that, The zero-set signal generation circuit includes: A timing circuit is used to generate the timing signal; A comparator is used to compare the current sampling signal and the current threshold and output a comparison result; A conduction time control circuit is used to generate a first reset signal, which is used to characterize the time when the effective state of the switch control signal ends. The zero-set logic circuit generates the zero-set signal based on the timing signal, the comparison result, and the first reset signal.

4. The control circuit according to claim 3, characterized in that, The timing circuit outputs a valid timing signal when the timing reaches a timing threshold, and outputs an invalid timing signal when the timing signal is valid and the current sampling signal reaches the current threshold.

5. The control circuit according to claim 3, characterized in that, The timing circuit outputs a valid timing signal when the timing reaches a timing threshold, and outputs an invalid timing signal when the timing signal is valid, the current sampling signal reaches the current threshold, and the switch control signal switches to an invalid state.

6. The control circuit according to claim 3, characterized in that, When the timing signal is invalid, the zero-set logic circuit sets the zero-set signal to an active state when the first reset signal is active; when the timing signal is active, the zero-set signal is set to an active state when both the first reset signal and the comparison result are active.

7. The control circuit according to claim 3, characterized in that, The conduction time control circuit is a constant conduction time control circuit, which generates a first reset signal for the valid state when the duration of the switch control signal being in the valid state reaches a predetermined constant conduction time.

8. The control circuit according to claim 3, characterized in that, The conduction time control circuit is a peak current control circuit, which generates a first reset signal for an effective state when the current sampling signal reaches the compensation signal. The compensation signal is used to characterize the error between the output current and the current reference signal.

9. The control circuit according to claim 1, characterized in that, The current threshold value is constant.

10. The control circuit according to claim 1, characterized in that, The current threshold value is related to the output load of the circuit. When the load is heavy, the current threshold value is small; when the load is light, the current threshold value is large.

11. The control circuit according to claim 3, characterized in that, The frequency of the timing signal is fixed, or the duration during which the timing signal is in an invalid state is fixed.

12. The control circuit according to claim 1, characterized in that, The voltage sampling circuit samples the auxiliary winding voltage after the blanking time to obtain the voltage sampling signal, wherein the blanking time varies according to the peak value of the current sampling signal.

13. A primary-side feedback flyback converter, comprising: Power stage circuit; and The control circuit according to any one of claims 1-12.

14. A control method for controlling a primary-side feedback flyback converter, comprising: Sample the primary current to obtain the current sampling signal, and sample the auxiliary winding voltage to obtain the voltage sampling signal; A switching control signal for controlling the power switch of the primary-side feedback flyback converter is generated based on the voltage sampling signal, the current sampling signal, and a certain timing signal. Specifically, when the current sampling signal is greater than a current threshold at a predetermined time, the switching control signal is generated in a first operating mode; when the current sampling signal is less than the current threshold at a predetermined time, the switching control signal is generated in a current peak mode when the timing signal is valid, and in the first operating mode when the timing signal is invalid. The predetermined time is the time when the effective state of the switch control signal ends in the first working mode.

15. The control method according to claim 14, characterized in that, Controlling the power switch of the primary-side feedback flyback converter based on the voltage sampling signal, the current sampling signal, and a certain timing signal includes: The power switch is controlled to turn on when the secondary current crosses zero or the voltage sampling signal is at its lowest point, based on the voltage sampling signal; and When the timing signal is invalid, the power switch is controlled to turn off when the predetermined time is reached; when the timing signal is valid, the power switch is controlled to turn off when the current sampling signal is greater than the current threshold and the predetermined time is reached.

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