amplifier

Abstract

The present application provides a high-efficiency amplifier, which includes an input stage, a control stage, a power stage and a degeneration stage. The input stage is used to receive an input signal to generate an amplified signal. The control stage is used to generate a first driving signal and a second driving signal according to the amplified signal. The power stage includes a first input terminal and a second input terminal, wherein the power stage is coupled to a power voltage and a ground voltage, and is used to receive the first driving signal and the second driving signal from the first input terminal and the second input terminal respectively to generate an output signal. The degeneration stage is coupled to the power stage, and is used to generate a first control signal to the first input terminal according to the second driving signal.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to amplification techniques, and more specifically, to a high-efficiency amplifier. Background Technology

[0002] Traditional Class AB amplifiers typically consist of an amplification stage and a power stage. The amplification stage is configured to generate two drive signals to control the P-type metal-oxide-semiconductor (PMOS) and N-type metal-oxide-semiconductor (NMOS) connected in series in the power stage. Ideally, the NMOS and PMOS in the power stage should not be enabled simultaneously. However, in practical applications, when the NMOS is enabled to draw current, the PMOS will also be enabled due to the unavoidable capacitive coupling effect between the drive signals, resulting in leakage current in the PMOS. Furthermore, this phenomenon is more pronounced when the amplifier operates at high frequencies; for example, a Class AB amplifier may operate like a Class A amplifier with lower efficiency. Summary of the Invention

[0003] Therefore, the object of the present invention is to provide a high-efficiency amplifier to solve the above-mentioned problems.

[0004] In a first aspect, the present invention provides an amplifier comprising an input stage, a control stage, a power stage, and a gain-reduction stage. The input stage receives an input signal to generate an amplified signal; the control stage is coupled to the input stage and generates a first drive signal and a second drive signal based on the amplified signal; the power stage includes a first input terminal and a second input terminal, wherein the power stage is coupled to a power supply voltage and a ground voltage, and receives the first drive signal and the second drive signal from the first input terminal and the second input terminal, respectively, and generates an output signal; and the gain-reduction stage is coupled to the power stage and generates a first control signal to the first input terminal based on the second drive signal.

[0005] In some embodiments, the control level is Class AB.

[0006] In some embodiments, the degaussing stage includes: a first low-pass filter for filtering the second drive signal to generate a filtered second drive signal; and a first control circuit coupled to the first low-pass filter for generating the first control signal to a first input terminal of the power stage to limit the swing of the first drive signal according to the filtered second drive signal.

[0007] In some embodiments, in response to the filtered second drive signal being greater than the first threshold level, the first control circuit couples the first input terminal of the power stage to the power supply voltage or the output signal via a capacitor.

[0008] In some embodiments, in response to the filtered second drive signal not being greater than the first threshold level, the first control circuit does not couple the first input terminal of the power stage to the power supply voltage or the output signal through the capacitor.

[0009] In some embodiments, in response to the filtered second drive signal being greater than a first threshold level, the first control circuit uses a transconductance amplifier to provide current to the first input of the power stage.

[0010] In some embodiments, in response to the filtered second drive signal not being greater than the first threshold level, the first control circuit does not provide current to the first input terminal of the power stage.

[0011] In some embodiments, the first control circuit includes a damping circuit coupled between a first input terminal of the power stage and an internal terminal or input terminal of the transconductance amplifier.

[0012] In some embodiments, the power stage further includes a P-type transistor and an N-type transistor, the P-type transistor being coupled between the power supply voltage and the output terminal, the N-type transistor being coupled between the output terminal and the ground voltage, the P-type transistor receiving the first drive signal from the first input terminal, and the N-type transistor receiving the second drive signal from the second input terminal to generate the output signal.

[0013] In some embodiments, the degaussing stage further includes: a second low-pass filter for filtering the first drive signal to generate a filtered first drive signal; and a second control circuit coupled to the second low-pass filter for generating a second control signal to a second input terminal of the power stage based on the filtered first drive signal, so as to limit the swing of the second drive signal based on the filtered first drive signal.

[0014] In some embodiments, in response to the filtered first drive signal being less than the second threshold level, the second control circuit couples the second input terminal of the power stage to the ground voltage or the output signal via a capacitor.

[0015] In some embodiments, in response to the filtered first drive signal being not less than the second threshold level, the second control circuit does not couple the second input terminal of the power stage to the ground voltage or the output signal via a capacitor.

[0016] In some embodiments, in response to the filtered first drive signal being less than a second threshold level, the second control circuit draws current from the second input terminal of the power stage using a transconductance amplifier.

[0017] In some embodiments, in response to the filtered first drive signal being not less than the second threshold level, the second control circuit does not draw current from the second input terminal of the power stage.

[0018] In a second aspect, the present invention provides a power modulator, wherein the power modulator includes any of the amplifiers described above.

[0019] These and other objects of the invention will be readily understood by those skilled in the art upon reading the following detailed description of the preferred embodiments illustrated in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the accompanying drawings. Attached Figure Description

[0020] The accompanying drawings (in which the same numerals denote the same components) illustrate embodiments of the present invention. The included drawings are used to provide a further understanding of embodiments of the present disclosure, and are incorporated in and constitute a part of the present disclosure. The drawings illustrate implementations of embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure. It is understood that the drawings are not necessarily drawn to scale, as some components may be shown out of proportion to actual dimensions in order to clearly illustrate the concepts of the embodiments of the present disclosure.

[0021] Figure 1 This is a schematic diagram of an amplifier according to an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram illustrating a gain-removal stage according to an embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram illustrating a gain-removal stage according to an embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of an amplifier according to an embodiment of the present invention.

[0025] Figure 5 This is illustrated in another embodiment of the present invention. Figure 4 The diagram shows a low-pass filter and a second control circuit.

[0026] Figure 6 This is a schematic diagram of a control circuit according to an embodiment of the present invention.

[0027] Figure 7 This is a schematic diagram of a power modulator and a power amplifier according to an embodiment of the present invention.

[0028] In the following detailed description, numerous specific details are set forth for illustrative purposes so that those skilled in the art can more thoroughly understand the embodiments of the invention. However, it will be apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments illustrated in the accompanying drawings. Detailed Implementation

[0029] The following description illustrates preferred embodiments of the present invention and is intended only to exemplify the technical features of the invention, not to limit the scope of the invention. Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names for the same element. Therefore, this specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "element," "system," and "device" used in this invention can refer to computer-related entities, where the computer can be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" as used in the following description and claims are open-ended terms and should be interpreted as "comprising, but not limited to...". Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0030] Unless otherwise indicated, the corresponding numbers and symbols in the various figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0031] The terms "basically" or "roughly" as used in this document mean that, within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the desired technical effect. For example, "roughly equal to" means a method that a person skilled in the art can accept with a certain margin of error from "exactly equal to" without affecting the correctness of the result.

[0032] Figure 1 This is a schematic diagram of an amplifier 100 according to an embodiment of the present invention. Figure 1 In the example, amplifier 100 is a class-AB amplifier, but this invention does not limit it. For ease of explanation, this invention uses a class-AB amplifier as an example for illustration. Figure 1As shown, amplifier 100 includes an input stage 110, a control stage (in this embodiment, a Class AB stage 120 is used as an example control stage), a power stage 130, and a de-gain stage (or alternatively, a "reduced gain stage") 140. Input stage 110 includes multiple PMOS transistors MP1 to MP5 and multiple NMOS transistors MN1 to MN4, coupled between a supply voltage VDD and a ground voltage. Input stage 110 is configured to receive input signals Vip and Vin (Vip and Vin constitute a differential input signal) to generate an amplified signal to the Class AB stage (or alternatively, a "Class AB control stage") 120. It should be noted that... Figure 1 The input stage 110 shown is merely an example and not a limitation of the invention. For example, input stage 110 can be configured to receive a single-ended input signal but produce an amplified differential output signal. Class AB stage 120 includes a PMOS MP6, a floating voltage source 122, and an NMOS MN5 coupled between the supply voltage VDD and ground. The PMOS MP6 and NMOS MN5 are configured to receive the amplified signal provided by input stage 110 (it should be noted that although...). Figure 1 The amplified signal is shown as a differential signal, but the invention is not limited thereto; for example, the amplified signal can also be a single-ended signal to generate drive signals Vgp and Vgn. Power stage 130 includes a first input terminal N1, a second input terminal N2, capacitors C1 and C2, resistors R1 and R2, two voltage buffers 132 and 134, a PMOS MP7, and an NMOS MN6. Capacitor C1 and resistor R1 are connected in series between the power supply voltage VDD and the first input terminal N1; capacitor C2 and resistor R2 are connected in series between the second input terminal N2 and the ground voltage; and the PMOS MP7 and NMOS MN6 are connected in series between the power supply voltage VDD and the ground voltage. The PMOS MP7 and NMOS MN6 are used to receive drive signals Vgp and Vgn through voltage buffers 132 and 134 and generate an output signal Vout. The degaussing stage 140 includes a low-pass filter (LPF) 142 and a control circuit 144, wherein the degaussing stage 140 is configured to receive a drive signal Vgn from the second input terminal N2 to generate a control signal Vc to the first input terminal N1.

[0033] In one embodiment, the low-pass filter 142 may be a configurable low-pass filter, meaning that the -3dB bandwidth of the low-pass filter 142 is configurable. Understandably, the -3dB bandwidth of a low-pass filter (LPF) is defined as follows: in direct current (DC), if the gain of the LPF is 0dB, the gain of the LPF decreases as the frequency increases. At a certain frequency, when the gain of the LPF is -3dB, this frequency is called the -3dB bandwidth of the LPF.

[0034] The circuit design of power stage 130 is for illustrative purposes only and is not intended to limit the invention. In other embodiments, voltage buffers 132 and 134 may be removed from power stage 130 (i.e., power stage 130 may not include voltage buffers 132 and 134), or one or more transistors may be located between the supply voltage VDD and PMOS MP7, or one or more transistors may be located between PMOS MP7 and the output of power stage 130, or one or more transistors may be located between NMOS MN6 and ground, or one or more transistors may be located between NMOS MP6 and the output of power stage 130. Specifically, the invention is not limited thereto.

[0035] Since the operation of input stage 110 and Class AB stage 120 is well known to those skilled in the art, the following description will focus primarily on power stage 130 and degaussing stage 140.

[0036] In the operation of power stage 130, ideally, NMOS MN6 and PMOS MP7 will not be enabled simultaneously. That is, when PMOS MP7 is enabled to source current from the supply voltage VDD to the output, NMOS MN6 is disabled; and when NMOS MN6 is enabled to draw current from the output to ground, PMOS MP7 is disabled. Specifically, Class AB amplifier 120 can generate drive signals Vgp and Vgn to enable PMOS MP7 and disable NMOS MN6, thereby providing current from the supply voltage VDD to the output terminal and increasing the voltage level of the output signal Vout (this current can be referred to as "sucking current"). Conversely, Class AB amplifier 120 can also generate drive signals Vgp and Vgn to disable PMOS MP7 and enable NMOS MN6, thereby drawing current from the output terminal and decreasing the voltage level of the output signal Vout (this current can be referred to as "sinking current"). However, due to the unavoidable capacitive coupling effect between drive signals Vgp and Vgn, both PMOS MP7 and NMOS MN6 will be enabled simultaneously for a certain time interval, which reduces the efficiency of amplifier 100. For example, when Class AB 120 switches the voltage level of the drive signal Vgn from high (or alternatively, "high voltage level") to low (or alternatively, "low voltage level"), that is, the sinking current of NMOS MN6 gradually decreases until NMOS MN6 is completely disabled, the voltage level of the drive signal Vgp will decrease due to the capacitive coupling effect between the drive signals Vgp and Vgn. As a result, PMOS MP7 may draw current from the supply voltage VDD during the "sinking current reduction" period.

[0037] To address the aforementioned issues, amplifier 100 is designed with a degaussing stage 140 to provide different path gain control for the P-side path (i.e., the path from the input to MP7) and the N-side path (i.e., the path from the input to MN6) to stabilize the drive signal Vgp as the voltage level of the drive signal Vgn switches from high to low. Specifically, low-pass filter 142 filters the drive signal Vgn to generate a filtered drive signal Vgn', and control circuit 144 receives the filtered drive signal Vgn' and generates a control signal Vc to the first input N1 to limit the swing of the drive signal Vgp. In other words, by providing the control signal Vc to the first input N1, the voltage level of the drive signal Vgp will not drop too much with the drive signal Vgn due to capacitive coupling effects, thus making the voltage level of the drive signal Vgp more stable.

[0038] Figure 2 This is a schematic diagram of a degaussing stage 140 according to an embodiment of the present invention. Figure 2As shown, the control circuit 144 includes transistors M1 to M5, a current source 202, and a capacitor C3. Transistors M1 and M2 are NMOS transistors, transistors M3 to M5 are PMOS transistors, and capacitor C3 has a large capacitance, for example, 10pF. Transistors M1 to M4 act as current comparators to detect the presence of a large current sinking event (i.e., detecting whether the drive signal Vgn has a high voltage level, for example, detecting whether the filtered drive signal Vgn' is greater than a first threshold level; understandably, if the filtered drive signal Vgn' is detected to be greater than the first threshold level, a large current sinking event is considered to have been detected) and generate a first signal V1. The first signal V1 is used to enable or disable transistor M5. Specifically, when the drive signal Vgn has a high voltage level (e.g., the drive signal Vgn is greater than a preset first threshold level), the filtered drive signal Vgn' will also have a high voltage level, thereby enabling transistors M1 and M2, causing the first signal V1 to have a lower voltage level. At this point, transistor M5 is enabled, causing the first input terminal N1 to be coupled (connected to) the power supply voltage VDD or the output voltage Vout via capacitor C3. Therefore, since the path gain is reduced by coupling the first input terminal N1 to the power supply voltage VDD or the output voltage Vout via capacitor C3, the drive signal Vgp at the first input terminal N1 will not drop too much due to the unavoidable capacitive coupling effect when the voltage level of the drive signal Vgn changes from high to low. Furthermore, when the drive signal Vgn has a low voltage level (i.e., the filtered drive signal Vgn' will also have a low voltage level), transistors M1 and M2 are disabled, causing the first signal V1 to have a high voltage level to disable transistor M5. At this time, the first input terminal N1 is not coupled to the power supply voltage VDD or the output voltage Vout via capacitor C3, thus the path gain returns to the original design, and the path gain of the gain stage 140 is not affected at this point.

[0039] It is worth noting that, Figure 2 The circuit design shown is for illustrative purposes only and is not intended to limit the invention. In other embodiments, as long as the control circuit 144 can couple the first input terminal N1 to the power supply voltage VDD or the output voltage Vout through the capacitor C3 when a large current sinking event occurs in the power stage 130, then Figure 2 The control circuit 144 shown can have different circuit designs.

[0040] Figure 3 This is a schematic diagram of a degaussing stage 140 according to another embodiment of the present invention. Figure 3As shown, the control circuit 144 includes transistors M6 to M9, where transistors M6 and M7 are NMOS transistors, and transistors M8 and M9 are PMOS transistors. In this embodiment, transistors M6 to M9 are used as transconductance amplifiers to detect the presence of a large current sinking event (i.e., to detect whether the drive signal Vgn has a high voltage level, for example, to detect whether the filtered drive signal Vgn' is greater than a first threshold level) and determine whether to provide current to the first input terminal N1. Specifically, when the drive signal Vgn has a high voltage level, the filtered drive signal Vgn' will also have a high voltage level, thereby enabling all transistors M6 to M9, allowing a large current to flow from the power supply voltage VDD to the first input terminal N1. Therefore, since a large current flows from the power supply voltage VDD to the first input terminal N1, the voltage level of the drive signal Vgp at the first input terminal N1 will be close to or substantially equal to the power supply voltage VDD. Furthermore, the drive signal Vgp at the first input terminal N1 will not drop to the level required to enable the PMOS MP7 due to unavoidable capacitive coupling when the voltage level of the drive signal Vgn changes from high to low. Additionally, when the drive signal Vgn has a low voltage level (i.e., the filtered drive signal Vgn' will also have a low voltage level), transistors M6 to M9 are disabled. Therefore, no current flows from the power supply voltage VDD to the first input terminal N1 via transistor M9. At this time, the first input terminal N1 is not connected to the power supply voltage VDD through transistor M9, thus the path gain returns to the original design.

[0041] It is worth noting that, Figure 3 The circuit design shown is for illustrative purposes only and is not intended to limit the invention. In other embodiments, as long as the control circuit 144 is able to provide current to the first input terminal N1 to increase the voltage level of the drive signal Vgp when a large sinking current event occurs in the power stage 130, then Figure 3 The control circuit 144 shown can have different circuit designs.

[0042] Figure 4 This is a schematic diagram of an amplifier 400 according to an embodiment of the present invention. Figure 4 In the example, amplifier 400 is a Class AB amplifier. Figure 4As shown, amplifier 400 includes an input stage 410, a control stage (in this embodiment, a Class AB stage 420 is used as an example control stage), a power stage 430, and a degaussing stage 440. Input stage 410 includes a plurality of PMOS transistors MP1 to MP5 and a plurality of NMOS transistors MN1 to MN4, coupled between a power supply voltage VDD and a ground voltage. Input stage 410 is configured to receive input signals Vip and Vin (Vip and Vin constitute a differential input signal) to generate an amplified signal to Class AB stage 420. Class AB stage 420 includes a PMOS transistor MP6, a floating voltage source 422, and an NMOS transistor MN5 coupled between the power supply voltage VDD and a ground voltage. PMOS transistor MP6 and NMOS transistor MN5 are configured to receive the amplified signal provided by input stage 410 to generate drive signals Vgp and Vgn. The power stage 430 includes a first input terminal N1, a second input terminal N2, capacitors C1 and C2, resistors R1 and R2, two voltage buffers 432 and 434, a PMOS MP7 and an NMOS MN6. Capacitor C1 and resistor R1 are connected in series between the power supply voltage VDD and the first input terminal N1. Capacitor C2 and resistor R2 are connected in series between the second input terminal N2 and the ground voltage. The PMOS MP7 and NMOS MN6 are connected in series between the power supply voltage VDD and the ground voltage. The PMOS MP7 and NMOS MN6 are used to receive drive signals Vgp and Vgn through voltage buffers 432 and 434 to generate an output signal Vout. The degaussing stage 440 includes a low-pass filter 442, a first control circuit 444, a low-pass filter 446, and a second control circuit 448. The degaussing stage 440 is configured to receive a drive signal Vgn from the second input terminal N2 to generate a first control signal Vc1 to the first input terminal N1, and to receive a drive signal Vgp from the first input terminal N1 to generate a second control signal Vc2 to the second input terminal N2.

[0043] In one embodiment, low-pass filters 442 and 446 may be configurable low-pass filters, i.e., the -3dB bandwidth of each of low-pass filters 442 and 446 is configurable.

[0044] The circuit design of power stage 430 is for illustrative purposes only and is not intended to limit the invention. In other embodiments, voltage buffers 432 and 434 may be removed from power stage 430, or one or more transistors may be located between the supply voltage VDD and PMOS MP7, or one or more transistors may be located between PMOS MP7 and the output of power stage 430, or one or more transistors may be located between NMOS MN6 and ground, or one or more transistors may be located between NMOS MP6 and the output of power stage 430.

[0045] Since the operation of input stage 410 and Class AB stage 420 is well known to those skilled in the art, the following description will focus primarily on power stage 430 and degaussing stage 440.

[0046] In the operation of power stage 430, ideally, NMOS MN6 and PMOS MP7 should not be enabled simultaneously. That is, when PMOS MP7 is enabled to provide current from the supply voltage VDD to the output, NMOS MN6 is disabled; and when NMOS MN6 is enabled to draw current from the output to ground, PMOS MP7 is disabled. Specifically, class AB stage 420 can generate drive signals Vgp and Vgn to enable PMOS MP7 and disable NMOS MN6 to provide current from the supply voltage VDD to the output, thereby increasing the voltage level of the output signal Vout; and class AB stage 420 can generate drive signals Vgp and Vgn to disable PMOS MP7 and enable NMOS MN6 to draw current from the output, thereby decreasing the voltage level of the output signal Vout. However, due to the unavoidable capacitive coupling effect between drive signals Vgp and Vgn, both PMOS MP7 and NMOS MN6 will be enabled simultaneously for a certain time interval, thereby reducing the efficiency of amplifier 400. For example, when Class AB stage 420 switches the voltage level of the drive signal Vgn from high to low, i.e., the sink current of NMOS MN6 gradually decreases until NMOS MN6 is completely disabled, the voltage level of the drive signal Vgp will be affected by the drive signal Vgn and decrease due to capacitive coupling. Therefore, PMOS MP7 will draw current from the supply voltage VDD during the "sink current reduction" period. Similarly, when Class AB stage 420 switches the voltage level of the drive signal Vgp from low to high, i.e., the sourcing current of PMOS MP7 gradually decreases until PMOS MP7 is completely disabled, the voltage level of the drive signal Vgn will increase with the drive signal Vgp due to capacitive coupling, causing NMOS MN6 to draw current from the output of power stage 430 during the "sourcing current reduction" period.

[0047] To address the aforementioned issues, amplifier 400 is designed with a degaussing stage 440 to provide different path gain control for the P-side path (i.e., the path from the input to MP7) and the N-side path (i.e., the path from the input to MN6). This stabilizes the drive signal Vgp when the voltage level of the drive signal Vgn switches from high to low, and stabilizes the drive signal Vgn when the voltage level of the drive signal Vgp switches from low to high. Specifically, low-pass filter 442 filters the drive signal Vgn to generate a filtered drive signal Vgn'. The first control circuit 444 receives the filtered drive signal Vgn' to generate a first control signal Vc1 to the first input N1 to limit the swing of the drive signal Vgp. In other words, by providing the first control signal Vc1 to the first input N1, the voltage level of the drive signal Vgp will not drop too much with the drive signal Vgn due to the capacitive coupling effect between Vgp and Vgn. Similarly, low-pass filter 446 filters the drive signal Vgp to generate a filtered drive signal Vgp'. The second control circuit 448 receives the filtered drive signal Vgp' and generates a second control signal Vc2 to the second input terminal N2 to limit the swing of the drive signal Vgn. That is, by providing the second control signal Vc2 to the second input terminal N2, the voltage level of the drive signal Vgn will not drop too much with the drive signal Vgp due to the capacitive coupling effect between Vgp and Vgn.

[0048] The operation of the low-pass filter 442 and the first control circuit 444 is similar to Figure 1 The operation of the low-pass filter 142 and control circuit 144 shown, and the fact that the first control circuit 444 can be controlled by... Figure 2 and Figure 3 The embodiment shown is used to implement this. Specifically, when the power stage 430 experiences a large current sinking event (e.g., the filtered drive signal Vgn' is greater than a first threshold level), the first control circuit 444 can couple the first input terminal N1 to the power supply voltage VDD or the output voltage Vout through the capacitor C3; and when the power stage 430 does not experience a large current sinking event, the first input terminal N1 is not connected to the power supply voltage VDD or the output voltage Vout through the capacitor C3. Alternatively, when the power stage 430 experiences a large current sinking event, the first control circuit 444 provides current to the first input terminal N1 to increase / raise the voltage level of the drive signal Vgp, while when the power stage 430 does not experience a large current sinking event, the first control circuit 444 does not provide current to the first input terminal N1.

[0049] Similar to the operation of the first control circuit 444, the second control circuit 448 can couple (connect to) the second input terminal N2 to the ground voltage or the output signal Vout via a capacitor when a large current-pull event occurs in the power stage 430 (i.e., the drive signal Vgp and the filtered drive signal Vgp' have low voltage levels, for example, the filtered drive signal Vgp' is below a second threshold level, wherein the second threshold level and the first threshold level may be the same or different). Furthermore, when there is no large current-pull event in the power stage 430, the second input terminal N2 is not connected to the ground voltage or the output voltage Vout via a capacitor. Alternatively, the second control circuit 448 can draw current from the second input terminal N2 to reduce the voltage level of the drive signal Vgn when a large current-pull event occurs in the power stage 430, and the second control circuit 448 does not draw current from the second input terminal N2 when there is no large current-pull event in the power stage 430.

[0050] Figure 5 This is a schematic diagram of a low-pass filter 446 and a second control circuit 448 according to another embodiment of the present invention. Figure 5 As shown, the second control circuit 448 includes transistors M10 to M12, where transistor M10 is a PNMOS and transistors M11 and M12 are NMOS. In this embodiment, transistors M10 to M12 act as transconductance amplifiers to detect large current-pull events (i.e., detect whether the drive signal Vgp has a low voltage level) and determine whether to supply current to the second input terminal N2. Specifically, when the drive signal Vgp has a low voltage level (e.g., less than a preset second threshold level), the filtered drive signal Vgp' will also have a low voltage level, and transistors M10 to M12 are all enabled, thereby drawing a large current from the second input terminal N2 to the ground voltage. Therefore, since a large current is drawn from the second input terminal N2 to the ground voltage, the voltage level of the drive signal Vgn at the second input terminal N2 will be close to the ground voltage, and the drive signal Vgn at the second input terminal N2 will not rise to the level that enables NMOS MN6 due to the unavoidable capacitive coupling effect when the voltage level of the drive signal Vgp changes from low to high. Furthermore, when the drive signal Vgp has a high voltage level (i.e., the filtered drive signal Vgp' will also have a high voltage level), transistors M10 to M12 are disabled, so that no current flows from the second input terminal N2 through transistor M12 to the ground voltage. At this time, the second input terminal N2 is not connected to the ground voltage through transistor M12, thus the path gain returns to the original design.

[0051] It is worth noting that, Figure 5The circuit designs shown are for illustrative purposes only and are not intended to limit the invention. In other embodiments, the second control circuit 448 may have different circuit designs, provided that it can provide current to the second input terminal N2 to reduce the voltage level of the drive signal Vgn when a large current-pull event occurs in the power stage 430.

[0052] exist Figure 3 and Figure 5 In the illustrated embodiment, by utilizing a transconductance amplifier to provide a large current at the appropriate time, the drive signals Vgp and Vgn can be stabilized. However, injecting a large current can cause a direct current (DC) offset problem. To address this issue, Figure 3 and Figure 5 The illustrated embodiment can be modified to add a damping circuit to make the current supplied by the transconductance amplifier smoother. Figure 6 This is a schematic diagram of a control circuit 144 or a first control circuit 444 according to another embodiment of the present invention. Figure 6 As shown, the control circuit 144 includes transistors M13 to M20, and the damping circuit includes transistors M17 to M20, resistor RD, and capacitor CD. Transistors M13 and M14 are NMOS transistors, and transistors M15 to M20 are PMOS transistors. In this embodiment, transistors M13 to M20 act as transconductance amplifiers to detect large sink current events and determine whether to supply current to the first input terminal N1. The damping circuit is coupled between the first input terminal N1 and the internal terminals or input terminal of the transconductance amplifier. Specifically, when the drive signal Vgn has a high voltage level, the filtered drive signal Vgn' will also have a high voltage level, and all transistors M13 to M20 are enabled, causing a large current to flow from the power supply voltage VDD to the first input terminal N1. Simultaneously, due to the damping circuit, the transconductance amplifier can generate a large and stable output impedance at the output terminal, thus preventing DC offset problems (i.e., the DC level shifting from one value to another) from occurring at the first input terminal N1.

[0053] In one embodiment, amplifier 100 / 400 may be used as an amplifier within a supply modulator or envelope tracking modulator, such as a linear amplifier. Figure 7 This is a schematic diagram of a power modulator and power amplifier 730 according to an embodiment of the present invention, wherein the power modulator includes a linear amplifier 710 and a switching converter 720. Figure 7As shown, power amplifier 730 receives RF input signal RFin to generate RF output signal RFout, and the power supply voltage of power amplifier 730 is generated by linear amplifier 710 and switching converter 720. Specifically, switching converter 720 is used to provide a high-efficiency low-frequency current I. SW The linear amplifier 710 is used to provide moderately efficient high-frequency current I. L And, current I SW and current I L The sum of these currents forms the output current Iout, which flows into the power amplifier 730.

[0054] In short, in the amplifier of the present invention, by designing a degaussing stage in the amplifier to limit the swing / oscillation of the drive signal Vgp when a large current sinking event occurs in the power stage, and / or to limit the swing / oscillation of the drive signal Vgn when a large current sourcing event occurs in the power stage, the problem of the PMOS and NMOS in the power stage being enabled simultaneously for certain time periods due to capacitive coupling effects can be avoided, thereby improving the efficiency of the amplifier.

[0055] The use of ordinal terms such as “first,” “second,” and “third” in the claims to modify claim elements does not in itself indicate any priority, precedence, or order of one claim element relative to another claim element, or the chronological order of the execution of method actions. Rather, it is merely used as a marker to distinguish one claim element with the same name from another element with the same name.

[0056] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various variations and similar structures (as will be apparent to those skilled in the art), such as combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such variations and similar structures.

Claims

1. An amplifier, characterized in that, The amplifier includes: The input stage is used to receive input signals and generate amplified signals. A control stage, coupled to the input stage, is used to generate a first drive signal and a second drive signal based on the amplified signal. A power stage, including a first input terminal and a second input terminal, wherein the power stage is coupled to a power supply voltage and a ground voltage, and is used to receive a first drive signal and a second drive signal from the first input terminal and the second input terminal respectively, and generate an output signal; and The gain stage is decoupled from the power stage and used to generate a first control signal to the first input terminal based on the second drive signal. The gain reduction stage includes: A first low-pass filter is used to filter the second driving signal to generate a filtered second driving signal; and A first control circuit, coupled to the first low-pass filter, is used to generate the first control signal to the first input terminal of the power stage, so as to limit the swing of the first drive signal according to the filtered second drive signal.

2. The amplifier as claimed in claim 1, characterized in that, The control level is Class AB.

3. The amplifier as claimed in claim 1, characterized in that, In response to the filtered second drive signal being greater than the first threshold level, the first control circuit couples the first input terminal of the power stage to the power supply voltage or the output signal via a capacitor.

4. The amplifier as described in claim 3, characterized in that, In response to the filtered second drive signal not being greater than the first threshold level, the first control circuit does not couple the first input terminal of the power stage to the power supply voltage or the output signal through the capacitor.

5. The amplifier as claimed in claim 1, characterized in that, In response to the filtered second drive signal being greater than the first threshold level, the first control circuit uses a transconductance amplifier to supply current to the first input terminal of the power stage.

6. The amplifier as claimed in claim 5, characterized in that, In response to the filtered second drive signal not being greater than the first threshold level, the first control circuit does not supply current to the first input terminal of the power stage.

7. The amplifier as claimed in claim 5, characterized in that, The first control circuit includes a damping circuit coupled between the first input terminal of the power stage and the internal terminal or input terminal of the transconductance amplifier.

8. The amplifier as claimed in claim 1, characterized in that, The power stage also includes a P-type transistor and an N-type transistor. The P-type transistor is coupled between the power supply voltage and the output terminal, and the N-type transistor is coupled between the output terminal and the ground voltage. The P-type transistor receives the first drive signal from the first input terminal, and the N-type transistor receives the second drive signal from the second input terminal to generate the output signal.

9. The amplifier as claimed in claim 8, characterized in that, The gain stage also includes: A second low-pass filter is used to filter the first driving signal to generate a filtered first driving signal; and The second control circuit, coupled to the second low-pass filter, is used to generate a second control signal to the second input terminal of the power stage based on the filtered first drive signal, so as to limit the swing of the second drive signal based on the filtered first drive signal.

10. The amplifier as claimed in claim 9, characterized in that, In response to the filtered first drive signal being less than the second threshold level, the second control circuit couples the second input terminal of the power stage to the ground voltage or the output signal via a capacitor.

11. The amplifier as claimed in claim 10, characterized in that, In response to the filtered first drive signal being no less than the second threshold level, the second control circuit does not couple the second input terminal of the power stage to the ground voltage or the output signal via a capacitor.

12. The amplifier as claimed in claim 9, characterized in that, In response to the filtered first drive signal being less than the second threshold level, the second control circuit draws current from the second input terminal of the power stage using a transconductance amplifier.

13. The amplifier as claimed in claim 12, characterized in that, In response to the filtered first drive signal being no less than the second threshold level, the second control circuit does not draw current from the second input terminal of the power stage.

14. A power modulator, characterized in that, The power modulator includes the amplifier as described in any one of claims 1 to 13.

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