A radio frequency switch tube driving circuit

Abstract

The application relates to a radio frequency switch tube driving circuit, which comprises an input level conversion unit, a D latch, an LDO, a logic gate, a level conversion unit and a driving output stage; wherein the input level conversion unit converts an input positive voltage domain signal into a negative voltage domain control signal with a hysteresis function; the D latch realizes the latch control function of two-way input control signals; the LDO provides various power supplies for a main circuit; the logic gate realizes the non-overlapping control of two-way differential signals; the level conversion unit converts the control signals with high level VSS and low level VSS_5V into control signals with high level VEE_5V and low level VEE; and the driving output stage provides a large output current capacity. The application realizes the control of a GaN switch tube in a large negative voltage range, and simultaneously has the latch function; the built-in non-overlapping control logic can effectively inhibit the direct through of the high side and the low side of the internal driving, and avoids the burning of the chip by large current.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design and manufacturing technology, and in particular to a radio frequency switch driving circuit. Background Technology

[0002] With the continuous development of integrated circuit technology and design techniques, high-voltage drive technology is increasingly being used in automotive electronics, motor drives, and high-power transmitter control, characterized by high integration, simple circuit structure, and ease of implementation. Due to the advantages of GaN switches—high operating voltage, low on-resistance, and good frequency characteristics—GaN-based voltage modulation is gradually being adopted in transmitter control and other fields. However, existing GaAs switch modulation suffers from disadvantages compared to GaN switch modulation, including lower operating voltage and lower efficiency, and lacks signal latching functionality. Therefore, developing GaN-based drive and level-shifting control technologies is crucial. Summary of the Invention

[0003] To address the existing technical problems, this invention provides a radio frequency switch driving circuit.

[0004] The specific content of this invention is as follows: A radio frequency switch driving circuit includes an input level conversion unit, a D latch, an LDO, logic gates, a level conversion unit, and a driver output stage; wherein the input level conversion unit converts the input positive voltage domain signal into a negative voltage domain control signal with hysteresis function; the D latch implements the latching control function of two input control signals; the LDO provides multiple power supplies to the main circuit; the logic gate implements non-overlap control of two differential signals; the level conversion unit converts the high-level VSS and low-level VSS_5V signals into high-level VEE_5V and low-level VEE control signals; the driver output stage provides a large output current capability.

[0005] Furthermore, the input level conversion unit includes: resistors R1, R2, R3, and R4; Schmitt triggers S1 and S2; wherein the TTL input terminal is connected to one end of R1, the other end of R1 is connected to one end of R2, and is also connected to the input terminal of Schmitt trigger S1; the other end of R2 is connected to the LDO output terminal VSS_5V; one power input terminal of Schmitt trigger S1 is connected to VSS, the other power input terminal is connected to VSS_5V, and the output is connected to one input terminal of the D latch; the enable EN input terminal is connected to one end of R3, the other end of R3 is connected to one end of R4, and is also connected to the input terminal of Schmitt trigger S2; the other end of R4 is connected to the LDO output terminal VSS_5V; one power input terminal of Schmitt trigger S2 is connected to VSS, the other power input terminal is connected to VSS_5V, and the output is connected to the other input terminal of the D latch.

[0006] Furthermore, the D latch includes logic gates, wherein one power input terminal of the D latch is connected to VSS, the other power input terminal is connected to VSS_5V, the output terminal of the D latch is connected to the input terminal of inverter U1, and is also connected to one input terminal of two-input NAND gate U2.

[0007] Furthermore, the logic gates include inverter U1, two-input NAND gates U2 and U3, and inverters U4 and U5; wherein the output of inverter U1 is connected to one input of two-input NAND gate U3; the other input of two-input NAND gate U3 is connected to the output of two-input NAND gate U2; the output of two-input NAND gate U3 is connected to the other input of two-input NAND gate U2, and is also connected to the input of inverter U5 and the input of buffer U7; the output of two-input NAND gate U2 is connected to the input of inverter U4 and the input of buffer U6; the output of inverter U4 is connected to one input of a level conversion unit; and the output of inverter U5 is connected to the other input of a level conversion unit.

[0008] Furthermore, the level conversion unit includes a switching transistor and a voltage divider resistor, wherein one power input terminal of the level conversion unit is connected to VSS, the other power input terminal is connected to VEE, one output terminal of the level conversion unit is connected to the input terminal of buffer U8, and the other output terminal is connected to the input terminal of buffer U9.

[0009] Furthermore, the drive output stage includes buffers U6, U7, U8, and U9, and MOSFETs M1, M2, M3, and M4. The output of buffer U6 is connected to the gate of MOSFET M1; the output of buffer U7 is connected to the gate of MOSFET M4; one power input of buffer U8 is connected to VEE_5V, and the other power input is connected to VEE; the output of buffer U8 is connected to the gate of MOSFET M2; one power input of buffer U9 is connected to VEE_5V, and the other power input is connected to VEE; the output of buffer U9 is connected to the gate of MOSFET M3; the source of MOSFET M1 is connected to power supply VSS, and its drain is connected to the drain of MOSFET M2, serving as the non-inverting output stage OUTP of the drive circuit; the source of MOSFET M2 is connected to power supply VEE; the source of MOSFET M4 is connected to power supply VSS, and its drain is connected to the drain of MOSFET M3, serving as the inverting output stage OUTN of the drive circuit; the source of MOSFET M3 is connected to power supply VEE.

[0010] Furthermore, the LDO includes a voltage reference source, an amplifier-based follower, and an on-chip voltage regulator capacitor. One power input terminal of the LDO is connected to VSS, and the other power input terminal is connected to VEE. The two voltage outputs are VSS_5V and VEE_5V, respectively.

[0011] The beneficial effects of this invention are as follows: This invention achieves control of GaN switching transistors within a wide negative voltage range, while also possessing a latching function. The built-in non-overlapping control logic effectively suppresses direct conduction between the high and low sides of the internal drive, preventing high current from burning out the chip. Compared to the operation mode of GaAs switching modulation for the same size, this invention, based on the driving and level conversion control technology of GaN switching transistors, significantly improves operating efficiency and has a wider operating voltage range. Attached Figure Description

[0012] The specific embodiments of the present invention will be further explained below with reference to the accompanying drawings.

[0013] Figure 1 This is a schematic diagram of the radio frequency switch driving circuit of the present invention. Detailed Implementation

[0014] Combination Figure 1 The radio frequency switch driving circuit of the present invention includes an input level conversion unit, a D latch, an LDO, logic gates, a level conversion unit, and a driver output stage. The input level conversion unit converts the input positive voltage domain signal into a negative voltage domain control signal with hysteresis. The D latch implements the latching control function of two input control signals. The LDO provides multiple power supplies to the main circuit. The logic gates implement non-overlapping control of two differential signals. The level conversion unit converts the high-level VSS and low-level VSS_5V signals into high-level VEE_5V and low-level VEE control signals. The driver output stage is used to provide a large output current capability.

[0015] The input level conversion unit includes: resistors R1, R2, R3, and R4; Schmitt triggers S1 and S2; the TTL input is connected to one end of R1, the other end of R1 is connected to one end of R2, and also to the input of Schmitt trigger S1; the other end of R2 is connected to the LDO output VSS_5V; one power input of Schmitt trigger S1 is connected to VSS, the other power input is connected to VSS_5V, and its output is connected to one input of a D latch; the enable (EN) input is connected to one end of R3, the other end of R3 is connected to one end of R4, and also to the input of Schmitt trigger S2; the other end of R4 is connected to the LDO output VSS_5V; one power input of Schmitt trigger S2 is connected to VSS, the other power input is connected to VSS_5V, and its output is connected to the other input of a D latch.

[0016] The D latch is composed of common logic gates. One power input terminal of the D latch is connected to VSS, and the other power input terminal is connected to VSS_5V. The output terminal of the D latch is connected to the input terminal of inverter U1 and also to one input terminal of two-input NAND gate U2.

[0017] The logic gate consists of inverter U1, two-input NAND gates U2 and U3, and inverters U4 and U5. The output of inverter U1 is connected to one input of two-input NAND gate U3; the other input of two-input NAND gate U3 is connected to the output of two-input NAND gate U2; the output of two-input NAND gate U3 is connected to the other input of two-input NAND gate U2, and also to the input of inverter U5 and the input of buffer U7; the output of two-input NAND gate U2 is connected to the input of inverter U4 and the input of buffer U6; the output of inverter U4 is connected to one input of a level conversion unit; and the output of inverter U5 is connected to the other input of a level conversion unit.

[0018] The level conversion unit consists of common switching transistors and voltage divider resistors. One power input terminal of the level conversion unit is connected to VSS, and the other power input terminal is connected to VEE. One output terminal of the level conversion unit is connected to the input terminal of buffer U8, and the other output terminal is connected to the input terminal of buffer U9.

[0019] The drive output stage consists of buffers U6, U7, U8, and U9, and MOSFETs M1, M2, M3, and M4. The output of buffer U6 is connected to the gate of MOSFET M1; the output of buffer U7 is connected to the gate of MOSFET M4; one power input of buffer U8 is connected to VEE_5V, and the other power input is connected to VEE; the output of buffer U8 is connected to the gate of MOSFET M2; one power input of buffer U9 is connected to VEE_5V, and the other power input is connected to VEE; the output of buffer U9 is connected to the gate of MOSFET M3; the source of MOSFET M1 is connected to power supply VSS, and its drain is connected to the drain of MOSFET M2, serving as the non-inverting output stage OUTP of the drive circuit; the source of MOSFET M2 is connected to power supply VEE; the source of MOSFET M4 is connected to power supply VSS, and its drain is connected to the drain of MOSFET M3, serving as the inverting output stage OUTN of the drive circuit; the source of MOSFET M3 is connected to power supply VEE.

[0020] An LDO consists of a common voltage reference source, an amplifier-based follower, and an on-chip voltage regulator. One power input terminal of the LDO is connected to VSS, and the other power input terminal is connected to VEE. The two voltage outputs are VSS_5V and VEE_5V, respectively.

[0021] When the EN enable signal is high (e.g., 5V), Schmitt trigger S2 outputs a high level VSS, the D latch output retains its current value, and the differential output signals OUTP and OUTN maintain their current values. When the EN enable signal is low (e.g., 0V), Schmitt trigger S2 outputs a low level VSS_5V, and the D latch output changes according to the output of Schmitt trigger S1. When the TTL input is high (e.g., 5V), Schmitt trigger S1 outputs a high level VSS, the D latch outputs a high level, and after passing through the logic and level conversion unit, the output OUTP is high (VSS) and OUTN is low (VEE). When the TTL input is low (e.g., 0V), Schmitt trigger S1 outputs a low level VSS_5V, the D latch outputs a low level, and after passing through the logic and level conversion unit, the output OUTP is low (VEE) and OUTN is high (VSS). The specific correspondences are shown in Table 1 below.

[0022] Table 1 Truth Table

[0023]

[0024] The resistor divider in the input level conversion unit converts the control signal from the positive voltage domain to the negative voltage domain. Taking the TTL input signal conversion as an example, R1=2R2. By reasonably designing the size of the Schmitt trigger S1, the high-level toggle level of the TTL input is designed to be 3V, and the low-level toggle level is designed to be 0.8V, realizing the hysteresis conversion function. Similarly, the level conversion of the EN enable signal has the same working principle, except that in order to reduce input current and power consumption, the values ​​of resistors R3 and R4 can be increased. The TTL input signal and the EN enable signal are logically judged and controlled by the level conversion and the D latch. The logic circuit composed of inverter U1, two-input NAND gates U2 and U3 converts the output of the D latch into two non-overlapping signals. In order to avoid the overlap caused by process deviation and transmission delay, which would cause the PMOS and NMOS transistors in the output stage to conduct simultaneously, one of the non-overlapping signals is buffered and then controls the gate of the PMOS transistor in the driver stage. The other control signal is level shifted and then controls the gate of the NMOS transistor in the bleeder of the driver stage. When the gate of PMOS transistor M1 goes high, M1 is turned off, the gate of M2 goes high, and M2 turns on, thus pulling the OUTP signal low. When the gate of NMOS transistor M2 goes low, M2 is turned off, the gate of M1 goes low, and M1 turns on, thus pulling the OUTP signal high.

[0025] The LDO's negative voltage supply VEE can cover a wide range of -20 to -40V, with the reference level VSS at ground (0V). Internally, it includes a voltage reference source that generates a -5V voltage, which remains constant regardless of changes in the VEE supply. Simultaneously, it generates an output voltage 5V higher than the VEE supply, the absolute value of which varies with the VEE supply. These two reference voltages are buffered by a follower to generate two voltages, VSS_5V and VEE_5V, which power the input level conversion unit, D latches, logic gates, and buffers U6 and U7. VEE_5V and VEE power buffers U8 and U9. The LDO integrates on-chip capacitors for voltage regulation and freewheeling, ensuring the stability of VSS_5V and VEE_5V during signal conversion.

[0026] The resistor divider in the input level conversion unit converts the control signal from the positive voltage domain to the negative voltage domain. A Schmitt trigger performs a hysteresis transition. The two converted input signals and the enable signal are then logically judged and controlled by a D latch. To avoid overlap caused by process variations and transmission delays that could lead to simultaneous conduction of the PMOS and NMOS transistors in the output stage, one of the non-overlapping signals is buffered and then controls the gate of the PMOS transistor in the driver stage. The other control signal is level-shifted and then controls the gate of the NMOS transistor at the bleeder terminal of the driver stage. When the input TTL signal is high (e.g., 5V), the driver stage outputs a high level (VSS); when the input TTL signal is low (e.g., 0V), the driver stage outputs a low level (VEE), achieving dynamic level conversion control.

[0027] The LDO's negative voltage supply VEE can cover a wide range of -20 to -40V. The reference level VSS is ground (0V), and its output voltage VSS_5V is a fixed -5V, independent of VEE. Its other output voltage, VEE_5V, is 5V higher than the negative voltage supply VEE, and its absolute value varies with VEE. The reference voltages VSS and VSS_5V power the input level conversion unit, the D latch, logic gates, and buffers U6 and U7. VEE_5V and VEE power buffers U8 and U9.

[0028] The level conversion unit converts the high-level VSS and low-level VSS_5V control signals into high-level VEE_5V and low-level VEE control signals, realizing level conversion over a wide voltage range.

[0029] This invention enables control of GaN switching transistors over a wide voltage range and also provides latching functionality; the built-in non-overlapping control logic effectively suppresses direct conduction between the high and low sides, preventing high current from burning out the chip.

[0030] Many specific details have been set forth in the foregoing description to provide a thorough understanding of the present invention. However, the above description is merely a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A radio frequency switch driving circuit, characterized in that: It includes an input level conversion unit, a D latch, an LDO, logic gates, a level conversion unit, and a driver output stage. The input level conversion unit converts the positive voltage domain signal into a negative voltage domain control signal with hysteresis. The D latch implements the latching control function for two input control signals. The LDO provides multiple power supplies to the main circuit. The logic gates implement non-overlapping control of two differential signals. The level conversion unit converts the high-level VSS and low-level VSS_5V signals into high-level VEE_5V and low-level VEE control signals. The driver output stage provides a large output current capability. The input level conversion unit includes: resistors R1, R2, R3, and R4; Schmitt triggers S1 and S2; wherein the TTL input terminal is connected to one end of R1, the other end of R1 is connected to one end of R2, and is also connected to the input terminal of Schmitt trigger S1; the other end of R2 is connected to the LDO output terminal VSS_5V; one power input terminal of Schmitt trigger S1 is connected to VSS, the other power input terminal is connected to VSS_5V, and the output is connected to one input terminal of a D latch; the enable EN input terminal is connected to one end of R3, the other end of R3 is connected to one end of R4, and is also connected to the input terminal of Schmitt trigger S2; the other end of R4 is connected to the LDO output terminal VSS_5V; one power input terminal of Schmitt trigger S2 is connected to VSS, the other power input terminal is connected to VSS_5V, and the output is connected to the other input terminal of a D latch; The drive output stage includes buffers U6, U7, U8, and U9, and MOSFETs M1, M2, M3, and M4. The output of buffer U6 is connected to the gate of MOSFET M1; the output of buffer U7 is connected to the gate of MOSFET M4; one power input of buffer U8 is connected to VEE_5V, and the other power input is connected to VEE; the output of buffer U8 is connected to the gate of MOSFET M2; one power input of buffer U9 is connected to VEE_5V, and the other power input is connected to VEE; the output of buffer U9 is connected to the gate of MOSFET M3; the source of MOSFET M1 is connected to power supply VSS, and its drain is connected to the drain of MOSFET M2, serving as the non-inverting output stage OUTP of the drive circuit; the source of MOSFET M2 is connected to power supply VEE; the source of MOSFET M4 is connected to power supply VSS, and its drain is connected to the drain of MOSFET M3, serving as the inverting output stage OUTN of the drive circuit; the source of MOSFET M3 is connected to power supply VEE. The LDO's negative voltage power supply VEE covers a range of -20 to -40V, with the reference level VSS being ground. Its output voltage VSS_5V is a fixed -5V voltage that does not change with the power supply VEE. Its other output voltage, VEE_5V, is 5V higher than the negative voltage power supply VEE, and its absolute voltage value changes with the power supply VEE. The reference voltages VSS and VSS_5V serve as the power supply for the input level conversion unit, the D latch, logic gates, and buffers U6 and U7. VEE_5V and VEE serve as the power supply for buffers U8 and U9.

2. The RF switch driver circuit according to claim 1, characterized in that: The D latch includes logic gates, wherein one power input terminal of the D latch is connected to VSS, the other power input terminal is connected to VSS_5V, the output terminal of the D latch is connected to the input terminal of inverter U1, and is also connected to one input terminal of two-input NAND gate U2.

3. The RF switch driver circuit according to claim 1, characterized in that: The logic gates include inverter U1, two-input NAND gates U2 and U3, and inverters U4 and U5; The output of inverter U1 is connected to one input of two-input NAND gate U3; the other input of two-input NAND gate U3 is connected to the output of two-input NAND gate U2; the output of two-input NAND gate U3 is connected to the other input of two-input NAND gate U2, and is also connected to the input of inverter U5 and the input of buffer U7; the output of two-input NAND gate U2 is connected to the input of inverter U4 and the input of buffer U6; the output of inverter U4 is connected to one input of the level conversion unit; and the output of inverter U5 is connected to the other input of the level conversion unit.

4. The RF switch driver circuit according to claim 1, characterized in that: The level conversion unit includes a switching transistor and a voltage divider resistor. One power input terminal of the level conversion unit is connected to VSS, and the other power input terminal is connected to VEE. One output terminal of the level conversion unit is connected to the input terminal of buffer U8, and the other output terminal is connected to the input terminal of buffer U9.

5. The RF switch driver circuit according to claim 1, characterized in that: The LDO includes a voltage reference source, an amplifier-based follower, and an on-chip voltage regulator capacitor. One power input terminal of the LDO is connected to VSS, and the other power input terminal is connected to VEE. The two voltage outputs are VSS_5V and VEE_5V, respectively.

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