A level conversion control circuit for a switching power supply

Abstract

The application provides a level conversion control circuit for a switching power supply, which is applied to the technical field of switching power supply control circuits and comprises a switching power supply control module, an adjusting module and an output module which are sequentially electrically connected. The switching power supply control module comprises a switching power supply control unit for outputting a pulse signal, and the pulse signal is a PWM signal. The adjusting module comprises a waveform separation unit for separating the pulse signal output by the switching power supply control unit into a wave form a and a wave form b, a level conversion unit for respectively converting the wave form a and the wave form b into a wave form c and a wave form d, and a waveform merging unit for merging the wave form c and the wave form d to generate a wave form e and transmitting the wave form e to an upper tube driving unit. The output module comprises the upper tube driving unit and a lower tube driving unit. The input signal is processed through the waveform separation unit and the waveform merging unit, so that the on time of the switching power supply is shortened.

Description

Technical Field

[0001] This invention belongs to the field of switching power supply control circuit technology, specifically relating to a level conversion control circuit for a switching power supply. Background Technology

[0002] A switching power supply is a type of power supply that uses modern power electronics technology to control the on-time ratio of switching transistors to maintain a stable output voltage. Switching power supplies are widely used in various electronic devices to provide high-quality, high-efficiency power. In many applications, it is desirable to minimize the on-time of the drive pulse of the switching power supply, because a shorter on-time allows for a larger duty cycle, a wider input voltage range, and a wider range of applications.

[0003] Currently known popular switching power supply products have a conduction time in the range of 100 nanoseconds. A shorter conduction time results in higher power consumption or requires more specialized manufacturing processes, leading to higher costs.

[0004] Therefore, there is a need to propose a switching power supply with extremely short conduction time, low cost, and low power consumption. Summary of the Invention

[0005] In view of the above-mentioned problems in the prior art, the purpose of the present invention is to provide a level conversion control circuit for a switching power supply, which processes the input signal through a waveform separation unit and a waveform merging unit to shorten the conduction time of the switching power supply.

[0006] A level conversion control circuit for a switching power supply includes a switching power supply control module, an adjustment module, and an output module connected in sequence; the switching power supply control module includes a switching power supply control unit for outputting pulse signals;

[0007] The adjustment module includes:

[0008] The waveform separation unit is electrically connected to the switching power supply control unit and is used to separate the pulse signal output by the switching power supply control unit into waveform a and waveform b.

[0009] At least one level conversion unit is electrically connected to the waveform separation unit and is used to convert waveform a and waveform b into waveform c and waveform d respectively.

[0010] The waveform merging unit, electrically connected to the level conversion unit, is used to merge the C and D waveforms to generate the E waveform and transmit it to the upper transistor drive unit.

[0011] The output module includes an upper MOSFET drive unit and a lower MOSFET drive unit. The upper MOSFET drive unit is electrically connected to the adjustment module, and the lower MOSFET drive unit is electrically connected to the switching power supply control unit.

[0012] The upper drive unit is electrically connected to the gate of MOSFET M1A. The source of MOSFET M1A is electrically connected to inductor L1 and the drain of MOSFET M2A. The other end of inductor L1 is connected to capacitor C1A and resistor R1A. The other end of capacitor C1A is grounded. The other end of resistor R1A is connected to resistor R2A and the FB pin of the switching power supply control unit. The other end of resistor R2A is grounded. The source of MOSFET M2A is grounded. The gate of MOSFET M2A is connected to the lower drive unit.

[0013] In order to separate the waveform a, the pulse signal passes through a rising edge extension circuit consisting of MOSFET M1, MOSFET M2, resistor R1, and capacitor C1, and then passes through MOSFET M3 and MOSFET M4 for inversion and shaping to produce the waveform a. The waveform a controls the on / off state of MOSFET Ma.

[0014] To separate the b waveform, the pulse signal passes through a falling edge extension circuit consisting of MOSFETs M5, M6, M7, M8, R2, and C2, and then is shaped into the b waveform by MOSFETs M9 and M10. The b waveform controls the on / off state of MOSFET Mb.

[0015] Two level conversion units are provided, namely low-speed level conversion unit one and low-speed level conversion unit two. The drain of MOSFET Ma is electrically connected to low-speed level conversion unit one, which outputs a c-waveform. Low-speed level conversion unit one includes resistor R3, MOSFET M11, MOSFET M12, and diode D1. The drain of MOSFET Mb is electrically connected to low-speed level conversion unit two, which outputs a d-waveform. Low-speed level conversion unit two includes resistor R4, MOSFET M13, MOSFET M14, and diode D2.

[0016] The pulse signal is input to the gates of MOSFETs M1, M2, M5, and M6. The gates of MOSFETs M1 and M2 are interconnected, and the gates of MOSFETs M5 and M6 are interconnected. The sources of MOSFETs M1, M3, M5, M7, and M9 are connected to a voltage source. The sources of MOSFETs M2, M4, Ma, M6, M8, M10, and Mb are connected to ground.

[0017] The drain of MOSFET M1 is connected to the drain of MOSFET M2 through resistor R1. The drain of MOSFET M2, the gate of MOSFET M4, and the gate of MOSFET M3 are all connected to one end of capacitor C1. The other end of capacitor C1 is grounded. The drain of MOSFET M3 and the drain of MOSFET M4 are both connected to the gate of MOSFET Ma.

[0018] The drains of MOSFET M5, M6, M7, and M8 are interconnected. The drain of MOSFET M7 is connected to the drain of MOSFET M8 via resistor R2. The drains of MOSFET M8, M9, and M10 are all connected to one end of capacitor C2, and the other end of capacitor C2 is grounded. The drains of MOSFET M9 and M10 are both connected to the gate of MOSFET Mb.

[0019] To output waveform c, the drain of MOSFET Ma is electrically connected to the cathode of diode D1, resistor R3, the gate of MOSFET M11, and the gate of MOSFET M12. The other end of resistor R3 is connected to the source of MOSFET M11, the anode of diode D1 is connected to the source of MOSFET M12, and the drains of MOSFET M11 and MOSFET M12 are interconnected and connected to the waveform merging unit.

[0020] To output the d waveform, the drain of the MOS transistor Mb is electrically connected to the cathode of diode D2, resistor R4, the gate of MOS transistor M13, and the gate of MOS transistor M14. The other end of resistor R4 is connected to the source of MOS transistor M13, the anode of diode D2 is connected to the source of MOS transistor M14, and the drains of MOS transistor M13 and MOS transistor M14 are interconnected and connected to the waveform merging unit.

[0021] To output the e-waveform, the waveform merging unit includes:

[0022] Digital inverter X1 is used to output a digital signal that is inverted from the input. The input terminal of digital inverter X1 is connected to the drain of MOSFET 13 M13 and MOSFET 14 M14, and the output terminal is connected to the first input terminal of AND gate X2.

[0023] AND gate X2 is used to combine the c waveform and d waveform through logical operation to output the e waveform. The second output terminal of AND gate X2 is connected to the drain of MOSFET 11 M11 and the drain of MOSFET 12 M12, and the output terminal is connected to the input terminal of buffer X3.

[0024] Buffer X3 is used to amplify the driving capability of the input signal.

[0025] The pulse signal is a PWM signal.

[0026] The beneficial effects of this invention are as follows: The level conversion control circuit for the switching power supply separates the pulse signal output by the switching power supply control unit into waveform a and waveform b through a waveform separation unit, and adjusts waveform a and waveform b into waveform c and waveform d through a level conversion unit. Then, the waveform c and waveform d are combined into waveform e and output through a waveform merging unit. Through waveform separation, level conversion, and waveform merging operations, the circuit can input PWM signals with a minimum width of 10ns. Compared with existing circuits that can input PWM signals with a minimum width of 100ns, this circuit can shorten the conduction time of the switching power supply, have a larger duty cycle, and a wider range of input voltages, thus having a wider range of applications. At the same time, the circuit has a simple structure, low cost, and low power consumption, which is conducive to its widespread use. Attached Figure Description

[0027] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0028] Figure 1 This is a circuit diagram of an existing switching power supply;

[0029] Figure 2 This is a circuit diagram of the level conversion unit in an existing switching power supply;

[0030] Figure 3 This is the circuit diagram of the present invention;

[0031] Figure 4 This is a circuit diagram of the adjustment module of the present invention;

[0032] Figure 5 This is a waveform diagram of the present invention. Detailed Implementation

[0033] like Figure 1As shown, an existing switching power supply circuit includes a switching power supply control unit, a level conversion unit, an upper transistor driving unit, and a lower transistor driving unit. The output terminal of the switching power supply control unit is connected to the level conversion unit and the lower transistor driving unit. The level conversion unit is connected to the upper transistor driving unit. The upper transistor driving unit is electrically connected to the gate of MOSFET M1A. The source of MOSFET M1A is electrically connected to inductor L1 and the drain of MOSFET M2A. The other end of inductor L1 is connected to capacitor C1A and resistor R1A. The other end of capacitor C1A is grounded. The other end of resistor R1A is connected to resistor R2A and the FB pin of the switching power supply control unit. The other end of resistor R2A is grounded. The source of MOSFET M2A is grounded. The gate of MOSFET M2A is connected to the lower transistor driving unit.

[0034] like Figure 2 As shown, the level shifting unit in an existing switching power supply circuit includes a diode DX, a MOSFET MX, and a buffer X0, used to achieve level shifting. Existing switching power supply circuits have a minimum input signal width of 100ns, a relatively long conduction time, a small input voltage range, and a large duty cycle.

[0035] Example 1

[0036] like Figure 3 As shown, a level conversion control circuit for a switching power supply includes a switching power supply control module, an adjustment module, and an output module that are electrically connected in sequence.

[0037] The switching power supply control module includes a switching power supply control unit for outputting pulse signals, which are PWM signals.

[0038] The adjustment module includes a waveform separation unit for separating the pulse signal output by the switching power supply control unit into waveform a and waveform b, a level conversion unit for converting waveform a and waveform b into waveform c and waveform d respectively, and a waveform merging unit for merging waveform c and waveform d to generate waveform e and transmit it to the upper transistor drive unit.

[0039] The output module includes an upper MOSFET driver unit and a lower MOSFET driver unit.

[0040] like Figure 3As shown, specifically, the output terminal of the switching power supply control unit is connected to the waveform separation unit and the lower transistor drive unit, respectively. The waveform separation unit is connected to two level conversion units, and the other end of each of the two level conversion units is connected to the waveform merging unit. The waveform merging unit is connected to the upper transistor drive unit, and the upper transistor drive unit is electrically connected to the gate of MOSFET M1A. The source of MOSFET M1A is electrically connected to the inductor L1 and the drain of MOSFET M2A, respectively. The other end of inductor L1 is connected to capacitor C1A and resistor R1A, respectively. The other end of capacitor C1A is grounded. The other end of resistor R1A is connected to resistor R2A and the FB pin of the switching power supply control unit, respectively. The other end of resistor R2A is grounded. The source of MOSFET M2A is grounded, and the gate of MOSFET M2A is connected to the lower transistor drive unit.

[0041] like Figure 4 , Figure 5 As shown, the waveform separation unit includes a rising edge extension circuit and a falling edge extension circuit; wherein, the process of generating waveform a by pulse signal includes: the pulse signal passes through the rising edge extension circuit composed of MOSFET M1M1, MOSFET M2, resistor R1, and capacitor C1, and then passes through MOSFET M3 and MOSFET M4 for inversion and shaping to produce waveform a, and waveform a controls the on and off of MOSFET Ma.

[0042] The process of generating the b waveform by the pulse signal includes: the pulse signal passes through the falling edge extension circuit composed of MOSFETs M5, M6, M7, M8, R2, and C2, and then passes through MOSFETs M9 and M10, and is shaped into the b waveform by the inverter. The b waveform controls the on and off of MOSFET Mb.

[0043] like Figure 5 As shown, the rising edge of the PWM signal generates the rising edge of waveform a, and the falling edge of the PWM signal generates the rising edge of waveform b. The minimum width of waveforms a and b is 100ns.

[0044] Specifically, such as Figure 4 As shown, a pulse signal is input to the gates of MOSFETs M1, M2, M5, and M6. The gates of MOSFETs M1 and M2 are interconnected, as are the gates of MOSFETs M5 and M6. The sources of MOSFETs M1, M3, M5, M7, and M9 are connected to a voltage source. The sources of MOSFETs M2, M4, Ma, M6, M8, M10, and Mb are connected to ground.

[0045] The drain of MOSFET M1 is connected to the drain of MOSFET M2 through resistor R1. The drain of MOSFET M2, the gate of MOSFET M4, and the gate of MOSFET M3 are all connected to one end of capacitor C1. The other end of capacitor C1 is grounded. The drain of MOSFET M3 and the drain of MOSFET M4 are both connected to the gate of MOSFET Ma.

[0046] The drains of MOSFET M5, M6, M7, and M8 are interconnected. The drain of MOSFET M7 is connected to the drain of MOSFET M8 via resistor R2. The drains of MOSFET M8, M9, and M10 are all connected to one end of capacitor C2, and the other end of capacitor C2 is grounded. The drains of MOSFET M9 and M10 are both connected to the gate of MOSFET Mb.

[0047] like Figure 4 , Figure 5 As shown, there are two level conversion units: a low-speed level conversion unit 1 and a low-speed level conversion unit 2. The rising edge extension circuit is connected to the low-speed level conversion unit 1, and the falling edge extension circuit is connected to the low-speed level conversion unit 2. The drain of MOSFET Ma is electrically connected to the low-speed level conversion unit 1. The low-speed level conversion unit 1 outputs a c-waveform and includes a resistor R3, MOSFETs M11 and M12, and a diode D1. The drain of MOSFET Mb is electrically connected to the low-speed level conversion unit 2. The low-speed level conversion unit 2 outputs a d-waveform and includes a resistor R4, MOSFETs M13 and M14, and a diode D2.

[0048] like Figure 5 As shown, the widths of waveforms c and d are the same as those of waveforms a and b, respectively. The lowest point voltages of waveforms c and d, after being processed by the level conversion unit, are higher than the lowest point voltages of waveforms a and b. For example... Figure 5 As shown, the lowest point of waveforms a and b is 0V, while waveforms c and d are signals converted by the level conversion unit, with their lowest points above 0V.

[0049] like Figure 4 As shown, specifically, the drain of MOSFET Ma is electrically connected to the negative terminal of diode D1, resistor R3, the gate of MOSFET M11, and the gate of MOSFET M12, respectively. The other end of resistor R3 is connected to the source of MOSFET M11, the positive terminal of diode D1 is connected to the source of MOSFET M12, and the drains of MOSFET M11 and MOSFET M12 are interconnected and connected to the waveform merging unit.

[0050] The drain of MOSFET Mb is electrically connected to the cathode of diode D2, resistor R4, the gate of MOSFET M13, and the gate of MOSFET M14. The other end of resistor R4 is connected to the source of MOSFET M13. The anode of diode D2 is connected to the source of MOSFET M14. The drains of MOSFET M13 and MOSFET M14 are interconnected and connected to the waveform merging unit.

[0051] like Figure 4 As shown, the waveform merging unit includes a digital inverter X1, an AND gate X2, and a buffer X3; wherein, the digital inverter X1 is used to output a digital signal that is inverted from the input; the AND gate X2 is used to merge the c waveform and the d waveform through logical operations to output the e waveform; the buffer X3 is used to amplify the driving capability of the input signal, so as to drive the subsequent circuit.

[0052] Specifically, the input terminal of the digital inverter X1 is connected to the drain of MOSFET M13 and MOSFET M14, the output terminal is connected to the first input terminal of AND gate X2, the second output terminal of AND gate X2 is connected to the drain of MOSFET M11 and MOSFET M12, and the output terminal is connected to the input terminal of buffer X3.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A level conversion control circuit for a switching power supply, characterized in that, It includes a switching power supply control module, an adjustment module, and an output module that are electrically connected in sequence; the switching power supply control module includes a switching power supply control unit for outputting pulse signals; The adjustment module includes: The waveform separation unit is electrically connected to the switching power supply control unit and is used to separate the pulse signal output by the switching power supply control unit into waveform a and waveform b. The pulse signal passes through a rising edge extension circuit consisting of MOSFET M1, MOSFET M2, resistor R1, and capacitor C1, and then passes through MOSFET M3 and MOSFET M4 to invert and shape waveform a. The waveform a controls the on / off state of MOSFET Ma. The pulse signal passes through a falling edge extension circuit consisting of MOSFETs M5, M6, M7, M8, R2, and C2, and is then inverted and shaped by MOSFETs M9 and M10 to produce waveform b. The waveform b controls the on / off state of MOSFET Mb. Two level conversion units are provided: a low-speed level conversion unit one and a low-speed level conversion unit two, which are electrically connected to the waveform separation unit. They are used to convert waveforms a and b into waveforms c and d, respectively. The level conversion units ensure that the output c waveform matches the input a waveform, and the output d waveform matches the input b waveform, with varying level heights. The drain of MOSFET Ma is electrically connected to low-speed level conversion unit one, which outputs the c waveform. Low-speed level conversion unit one includes resistor R3, MOSFETs M11 and M12, and diode D1. The drain of MOSFET Mb is electrically connected to low-speed level conversion unit two, which outputs the d waveform. Low-speed level conversion unit two includes resistor R4, MOSFETs M13 and M14, and diode D2. A waveform merging unit, electrically connected to a level conversion unit, is used to merge the c-waveform and d-waveform to generate the e-waveform and transmit it to the upper transistor drive unit; the waveform merging unit includes: Digital inverter X1 is used to output a digital signal that is inverted from the input. The input terminal of digital inverter X1 is connected to the drain of MOSFET 13 M13 and MOSFET 14 M14, and the output terminal is connected to the first input terminal of AND gate X2. AND gate X2 is used to combine the c waveform and d waveform through logical operation to output the e waveform. The second output terminal of AND gate X2 is connected to the drain of MOSFET 11 M11 and the drain of MOSFET 12 M12, and the output terminal is connected to the input terminal of buffer X3. Buffer X3 is used to amplify the driving capability of the input signal; The output module includes an upper MOSFET drive unit and a lower MOSFET drive unit. The upper MOSFET drive unit is electrically connected to the adjustment module, and the lower MOSFET drive unit is electrically connected to the switching power supply control unit.

2. The level conversion control circuit for a switching power supply according to claim 1, characterized in that, The upper drive unit is electrically connected to the gate of MOSFET M1A. The source of MOSFET M1A is electrically connected to inductor L1 and the drain of MOSFET M2A. The other end of inductor L1 is connected to capacitor C1A and resistor R1A. The other end of capacitor C1A is grounded. The other end of resistor R1A is connected to resistor R2A and the FB pin of the switching power supply control unit. The other end of resistor R2A is grounded. The source of MOSFET M2A is grounded. The gate of MOSFET M2A is connected to the lower drive unit.

3. The level conversion control circuit for a switching power supply according to claim 1, characterized in that, The pulse signal is input to the gates of MOSFETs M1, M2, M5, and M6. The gates of MOSFETs M1 and M2 are interconnected, and the gates of MOSFETs M5 and M6 are interconnected. The sources of MOSFETs M1, M3, M5, M7, and M9 are connected to a voltage source. The sources of MOSFETs M2, M4, Ma, M6, M8, M10, and Mb are connected to ground. The drain of MOSFET M1 is connected to the drain of MOSFET M2 through resistor R1. The drain of MOSFET M2, the gate of MOSFET M4, and the gate of MOSFET M3 are all connected to one end of capacitor C1. The other end of capacitor C1 is grounded. The drain of MOSFET M3 and the drain of MOSFET M4 are both connected to the gate of MOSFET Ma. The drains of MOSFET M5, M6, M7, and M8 are interconnected. The drain of MOSFET M7 is connected to the drain of MOSFET M8 via resistor R2. The drains of MOSFET M8, M9, and M10 are all connected to one end of capacitor C2, and the other end of capacitor C2 is grounded. The drains of MOSFET M9 and M10 are both connected to the gate of MOSFET Mb.

4. The level conversion control circuit for a switching power supply according to claim 1, characterized in that, The drain of MOSFET Ma is electrically connected to the cathode of diode D1, resistor R3, the gate of MOSFET M11, and the gate of MOSFET M12. The other end of resistor R3 is connected to the source of MOSFET M11, the anode of diode D1 is connected to the source of MOSFET M12, and the drains of MOSFET M11 and MOSFET M12 are interconnected and connected to the waveform merging unit.

5. The level conversion control circuit for a switching power supply according to claim 1, characterized in that, The drain of the MOS transistor Mb is electrically connected to the negative terminal of diode D2, resistor R4, the gate of MOS transistor M13, and the gate of MOS transistor M14. The other end of resistor R4 is connected to the source of MOS transistor M13. The positive terminal of diode D2 is connected to the source of MOS transistor M14. The drains of MOS transistor M13 and MOS transistor M14 are interconnected and connected to the waveform merging unit.

6. The level conversion control circuit for a switching power supply according to claim 1, characterized in that, The pulse signal is a PWM signal.

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