A charge pump phase-locked loop

Abstract

This invention discloses a charge pump phase-locked loop (PLL), comprising: a frequency and phase detector output terminal connected to both a first charge pump and a second charge pump; a low-pass filter output terminal generating a feedback clock signal via a voltage-controlled oscillator and a loop divider, the feedback clock signal being input to the second input terminal of the frequency and phase detector, while an external reference clock is input to the first input terminal of the frequency and phase detector; a lock detector output signal connected to the enable terminal of a voltage comparator, the lock detector being used to detect the lock state of the charge pump PLL output when the chip is powered on, the voltage comparator being enabled under the control of the lock detector output signal, being used to compare the magnitude between the control voltage and the fixed voltage, and outputting an enable signal; a first charge pump providing a control voltage to the low-pass filter when a first switch is enabled; and a second charge pump providing a control voltage to the low-pass filter when a second switch is enabled.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a charge pump phase-locked loop. Background Technology

[0002] Currently, charge pump phase-locked loops (PLLs) are a commonly used clock PLL circuit structure, characterized by low noise and a wide capture range. This technology has a wide range of applications, from system clock generation and clock recovery circuits to wireless communication frequency synthesizers. A PLL is a negative feedback control system. The output clock is fed back along a certain ratio and compared with the input clock frequency and phase. The output is adjusted based on the comparison result, ultimately resulting in a clock whose frequency is proportional to the input clock and whose phase is aligned.

[0003] The charge pump phase-locked loop (PLL) consists of several main modules, including a frequency and phase discriminator, a charge pump, a low-pass filter, a voltage-controlled oscillator (VCO), and a loop divider. The comparison result of the frequency and phase discriminator is a digital pulse signal, including pull-up and pull-down signals. These two signals control the charge pump current to be pulled up or down, thereby charging or discharging the charge pump capacitor, which in turn generates the control voltage for the VCO.

[0004] The glitches in the output clock of a charge pump phase-locked loop (PLL) are primarily caused by the periodic ripple in the control voltage output by the charge pump. During the locking phase, the feedback clock and the reference clock are in phase and frequency, and theoretically, the charge pump output voltage should not change. However, in design, to avoid a "dead zone" in the comparison of the frequency and phase detector, a minimum pulse is often set in the pull-up and pull-down signals. This means that even if the input signals are completely in phase and frequency, a high-level pulse will appear in the output pull-up and pull-down signals within each comparison cycle. This causes the pull-up and pull-down currents output by the charge pump to be simultaneously active for a period of time each cycle. During this "dead zone," if the pull-up and pull-down currents are different, it will cause the output voltage to change, thus contributing jitter to the voltage-controlled oscillator (VCO) output and exhibiting "glitch" in the output clock spectrum.

[0005] Therefore, the present invention provides a new charge pump phase-locked loop design to improve the above-mentioned problems. Summary of the Invention

[0006] This invention provides a charge pump phase-locked loop to improve the "glitches" problem in the output clock spectrum.

[0007] This invention provides a charge pump phase-locked loop (PLL), comprising: a frequency-phase detector output terminal simultaneously connected to a first charge pump and a second charge pump; the first charge pump connected to a low-pass filter via a first switch; the second charge pump connected to the input terminal of the low-pass filter via a second switch; the output terminal of the low-pass filter generates a feedback clock signal via a voltage-controlled oscillator (VCO) and a loop divider; the feedback clock signal is input to the second input terminal of the frequency-phase detector; simultaneously, an external reference clock is input to the first input terminal of the frequency-phase detector; concurrently, the external reference clock and the feedback clock signal are input to a lockout detector; the output signal of the lockout detector is connected to the enable terminal of a voltage comparator; the first input terminal of the voltage comparator receives a fixed voltage Vref; and the second input terminal of the voltage comparator receives a control voltage Vctrl. The control voltage Vctrl is the output voltage of the first charge pump and the second charge pump. When the chip is powered on, the lockout detector is used to detect the lockout state of the output of the charge pump phase-locked loop. The voltage comparator is enabled under the control of the output signal of the lockout detector and is used to compare the magnitude between the control voltage Vctrl and the fixed voltage Vref, and output the first enable signal of the first switch and the second enable signal of the second switch. The polarity of the second enable signal is opposite to that of the first enable signal. The first charge pump is used to provide the control voltage Vctrl to the low-pass filter after the first switch is enabled under the control of the first enable signal. The second charge pump is used to provide the control voltage Vctrl to the low-pass filter after the second switch is enabled under the control of the second enable signal.

[0008] The beneficial effects of the charge pump phase-locked loop provided by the present invention are as follows: Since both the first charge pump and the second charge pump use a negative feedback circuit to keep the current of the pull-up path and the pull-down path consistent, the output voltage Vctrl of the first charge pump and the second charge pump are compared with the fixed voltage Vref to control the pull-up current or pull-down current, thereby reducing the mismatch current and thus improving the problem of output clock spectrum glitches.

[0009] In one possible implementation, the first charge pump and the second charge pump are complementary charge pumps.

[0010] In another possible implementation, the first charge pump includes a P-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and an N-type comparator amplifier; the second charge pump is a complementary charge pump including an N-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and a P-type comparator amplifier.

[0011] In another possible implementation, the first charge pump includes an N-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and a P-type comparator amplifier; the second charge pump is a complementary charge pump including a P-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and an N-type comparator amplifier.

[0012] In one possible implementation, both the first switch and the second switch are CMOS transmission gates.

[0013] In one possible implementation, the first switch is a P-type transmission transistor and the second switch is an N-type transmission transistor; or, the first switch is an N-type transmission transistor and the second switch is a P-type transmission transistor; the gate of the N-type transmission transistor is connected to the first enable signal, and the gate of the P-type transmission transistor is connected to the second enable signal.

[0014] In one possible implementation, both the first charge pump and the second charge pump include a bias generation branch, a pull-up current branch, a pull-down current branch, a replication circuit, and an amplification comparator. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of a charge pump phase-locked loop circuit structure provided in an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of the basic circuit structure of the first charge pump;

[0018] Figure 3 A schematic diagram of the basic circuit structure of the second charge pump;

[0019] Figure 4 This is a schematic diagram illustrating the change in mismatch current of a charge pump.

[0020] Figure 5 This diagram illustrates the voltage fluctuations caused by charge pump switching. Detailed Implementation

[0021] The glitches in a charge pump phase-locked loop (PLL) mainly occur during the "deadband" period. This deadband (Tdeadband) is characterized by the simultaneous high output of both the pull-up and pull-down signals from the phase detector, meaning both the charge pump's pull-up and pull-down current paths are open simultaneously. This simultaneous opening of the charge pump's current paths generates a mismatch current, Icpmis. Assuming the charge pump's charging capacitor is C0, the voltage fluctuation ΔVctrl generated on the charge pump per cycle is:

[0022]

[0023] It can be seen that the larger the charge pump mismatch current Icpmis is, the larger ΔVctrl is. Since the output frequency of the voltage-controlled oscillator is proportional to the output voltage of the charge pump, the larger the charge pump mismatch current is, the larger the voltage fluctuation ΔVctrl will be, and the greater the power of the "glitch" appearing on the output clock spectrum of the voltage-controlled oscillator.

[0024] To improve the "glitches" problem in the output clock spectrum, this invention provides a novel charge pump phase-locked loop that can reduce the output clock "glitches" problem while ensuring the output frequency range. Figure 1 This is a schematic diagram of a charge pump phase-locked loop circuit structure provided in an embodiment of the present invention. The charge pump phase-locked loop includes: a frequency and phase detector, a first charge pump, a second charge pump, a first switch, a second switch, a low-pass filter, a voltage-controlled oscillator, a loop divider, a lockout detector, and a voltage comparator (CMP).

[0025] The output of the frequency and phase detector is connected to both the first and second charge pumps. The first charge pump is connected to a low-pass filter via a first switch, and the second charge pump is connected to the input of the low-pass filter via a second switch. An external reference clock and a feedback clock signal are input to the lock-in detector. The output signal of the lock-in detector is connected to the enable terminal of a voltage comparator. A fixed voltage Vref is input to the first input terminal of the voltage comparator, and a control voltage Vctrl is input to the second input terminal of the voltage comparator. The control voltage Vctrl is the output voltage of the first and second charge pumps.

[0026] In addition, the output of the low-pass filter generates a feedback clock signal Fdiv via a voltage-controlled oscillator and a loop divider. The feedback clock signal Fdiv is input to the second input of the frequency and phase detector, while the first input of the frequency and phase detector is input to an external reference clock Fref.

[0027] As shown in the diagram, the inputs to the frequency and phase detector are a reference clock Fref and a feedback clock signal Fdiv. The phase difference between the two clocks is compared to obtain a control signal, which includes pull-up and pull-down signals. When the phase of the reference clock Fref is ahead of the feedback clock signal Fdiv, the pull-up signal is high and the pull-down signal is low. When the reference clock Fref is later than the feedback clock signal Fdiv, the pull-down signal is high and the pull-up signal is low. The pull-up and pull-down signals are connected to the first and second charge pumps, respectively. When the pull-up signal is high and the pull-down signal is low, the pull-up branch outputs operating current, charging the charge pump capacitor in the low-pass filter, increasing the control voltage Vctrl, and causing the voltage-controlled oscillator (VCO) output frequency to become high. When the pull-down signal is high and the pull-up signal is low, the charge pump capacitor in the low-pass filter discharges, decreasing the control voltage Vctrl, and causing the VCO output frequency to become low. When both the pull-up and pull-down signals are low, the charge pump pull-up and pull-down branches are disconnected from the charge pump capacitor, the stored charge in the charge pump capacitor remains unchanged, and the control voltage Vctrl remains constant. When both the pull-up and pull-down signals are high, the charge pump pull-up and pull-down paths are simultaneously connected to the charge pump capacitor. If the charging current of the capacitor from the pull-up branch is not equal to the discharging current of the capacitor from the pull-down branch (i.e., there is a mismatch current Icpmis), the control voltage Vctrl across the capacitor will change, causing the output clock of the phase-locked loop to still deviate from the locked frequency even after locking.

[0028] In this embodiment, when the external reference clock Fref and the feedback clock signal Fdiv are phase-aligned, the lock detector outputs a high level; when the phase difference between the external reference clock Fref and the feedback clock signal Fdiv still changes, the lock detector outputs a low level. When the lock detector output signal is high, the voltage comparator is enabled and begins to work. That is, when the chip is powered on, the lock detector is used to detect the lock state of the charge pump phase-locked loop output. The voltage comparator is enabled under the control of the lock detector output signal and begins to compare the magnitude between the control voltage Vctrl and the fixed voltage Vref, outputting a first enable signal En1 for the first switch and a second enable signal En2 for the second switch. The polarity of the second enable signal En2 is opposite to that of the first enable signal En1. In other words, when the first charge pump is working, the second charge pump is not working; or when the first charge pump is not working, the second charge pump is working.

[0029] In this embodiment, when the first switch is enabled under the control of the first enable signal, the first charge pump provides the control voltage Vctrl to the low-pass filter, i.e., outputs a control pull-down current; when the second switch is enabled under the control of the second enable signal, the second charge pump provides the control voltage Vctrl to the low-pass filter, i.e., outputs a control pull-up current. In this way, the two charge pumps can switch their operating states. The charging current of the pull-up branch to the capacitor is equal to the discharging current of the pull-down branch to the capacitor, ensuring that the charge pumps maintain a low mismatch current level within a voltage range close to the power supply voltage, reducing "glitch" output. During the charge pump switching process, since the charge is all stored on the large capacitor of the charge pump, the switching process does not cause a jump in the Vctrl voltage, and the ripple caused on Vctrl during the switching process does not accumulate, allowing the second charge pump to still achieve phase-locked loop (PLL) locking.

[0030] In one possible embodiment, both the first switch and the second switch are CMOS transmission gates. For example, the first switch is a P-type transmission gate and the second switch is an N-type transmission gate; or, the first switch is an N-type transmission gate and the second switch is a P-type transmission gate. The gate of the N-type transmission gate is connected to the first enable signal En1, and the gate of the P-type transmission gate is connected to the second enable signal En2.

[0031] exist Figure 1 In the illustrated embodiment, the VOUT output terminals of the first and second charge pumps are respectively connected to a first switch and a second switch. The output terminals of the first and second switches are short-circuited. The output voltages of both switches are the control voltage Vctrl. The first and second switches are CMOS transmission gate circuits, which can transmit any voltage signal from 0 to VDD. The control voltage VCTRL is the input signal of the low-pass filter and also one input signal of the voltage comparator. The other input signal is a fixed voltage Vref. The voltage comparator compares the input control voltage VCTRL with the fixed voltage Vref. When the control voltage Vctrl is higher than the fixed voltage Vref, the first enable signal En1 is high and the second enable signal En2 is low. When the control voltage Vctrl is lower than the fixed voltage Vref, the first enable signal En1 is low-high and the second enable signal En2 is high. The first enable signal En1 is the enable signal of the first switch, and the second enable signal En2 is the enable signal of the second switch.

[0032] In one possible embodiment, the first charge pump and the second charge pump are complementary charge pumps. In one possible example, the first charge pump includes a P-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and an N-type comparator amplifier; the second charge pump, being a complementary charge pump, includes an N-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and a P-type comparator amplifier. In another possible example, the first charge pump includes an N-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and a P-type comparator amplifier; the second charge pump, being a complementary charge pump, includes a P-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and an N-type comparator amplifier.

[0033] In one embodiment, Figure 2 The schematic diagram illustrates the basic circuit structure of the first charge pump. Figure 3 The schematic diagram of the basic circuit structure of the second charge pump is shown.

[0034] like Figure 2 As shown, the first charge pump includes a bias generation branch, a pull-up current branch, a pull-down current branch, a replication circuit, and an amplification comparator. The bias generation branch includes a current source I0 and a self-biased transistor PM0. One end of the current source I0 is grounded, and the other end is connected to the drain and gate of the self-biased transistor PM0. The source of the self-biased transistor PM0 is connected to the power supply VDD.

[0035] The pull-up current branch includes a current source transistor PM2 and a switching transistor SWP2. The source and substrate of current source transistor PM2 are connected to the power supply VDD. The gate of current source transistor PM2 is connected to the gate of self-biased transistor PM0, and the drain is connected to the source of switching transistor SWP2. The gate of switching transistor SWP2 is connected to the control signal UPN, which is the inverted signal of the pull-up signal. The drain is connected to the output node P1, and the voltage of node P1 is the output voltage VOUT of the pull-up current branch. When the pull-up signal is high, UPN is low, and the channel of switching transistor SWP2 is open, forming a current path between current source transistor PM2 and node P1. When the pull-up signal is low, UPN is high, and the channel of switching transistor SWP2 is closed, breaking the current path between current source transistor PM2 and node P1.

[0036] The pull-down current branch includes a current source transistor NM2 and a switching transistor SWN2. The source and substrate of the current source transistor NM2 are grounded to VSS, its gate is connected to the output of the amplifier comparator, and its drain is connected to the source of the switching transistor SWN2. The gate of the switching transistor SWN2 is connected to the control pull-down signal, and its drain is connected to the output node P1. When the pull-down signal is high, the channel of the switching transistor SWN2 is open, forming a current path between the current source transistor NM2 and node P1. When the pull-down signal is low, the switching transistor SWN2 is closed, and the current path between the current source transistor NM2 and node P1 is broken.

[0037] The replication circuit includes an N-type current source transistor NM1 and an N-type switching transistor SWN1, a P-type current source transistor PM1 and a P-type switching transistor SWP1. The source of P-type current source transistor PM1 is connected to VDD, its gate is connected to the gate of the self-biased transistor PM0, and its drain is connected to the switching transistor SWP1. The gate of switching transistor SWP1 is connected to a low potential, keeping its channel normally open, and its drain is connected to the drain of switching transistor SWN1, i.e., node P2. The output voltage of node P2 is VREF_OUT. The gate of switching transistor SWN1 is connected to a high potential, keeping its channel normally open, and its source is connected to the drain of N-type current source transistor NM1. The gates of both N-type current source transistor NM1 and current source transistor NM2 are connected to the output of the amplifier comparator, and the source of N-type current source transistor NM1 is grounded. The dimensions of N-type current source transistor NM1 and N-type switching transistor SWN1 in this branch are the same as or maintain a fixed proportional relationship with the current source transistor NM2 and switching transistor SWN2 in the pull-down circuit branch. The dimensions of the P-type current source transistor PM1 and the switching transistor SWP1 in this branch are the same as or maintain a fixed proportional relationship with PM2 and SWP2 in the pull-up current branch. It is important to note that the two fixed proportional relationships must remain consistent. The comparator amplifier has a positive input VREF_OUT and a negative input VOUT.

[0038] The first charge pump operates on the principle that the replication circuit is always on. When the gate bias voltages of PM1 and NM1 remain constant, a stable DC operating point exists at node P2. However, during the phase-locked loop (PLL) locking process, the pull-up and pull-down branches on the right are individually opened to charge or discharge the charge pump capacitor to adjust the control voltage Vctrl. The control voltage Vctrl differs at different set frequencies. Therefore, although the gate and source voltages of PM2 are the same as those of PM1, if the drain voltages are different, due to the AC length modulation effect, its channel current will also be different from that of PM1. Similarly, if the VOUT voltage is different from the VREF_OUT voltage, the current of NM2 will also be different from that of NM1. It is known that with the replication circuit always on, the channel current of PM1 flows entirely through NM1; therefore, the channel currents of PM1 and NM1 are the same. Therefore, when the VREF_OUT voltage is different from the control voltage Vctrl, the currents of PM2 and NM2 will be different, that is, the pull-up current and pull-down current of the charge pump will be mismatched. At this time, the mismatched current will charge and discharge the charge pump capacitor when the pull-up signal / pull-down signal (UP / DN) of each frequency and phase detector output is high at the same time.

[0039] Figure 2In the first charge pump embodiment, when the control voltage Vctrl is higher than REF_OUT, the amplifier output becomes lower, causing the gate voltages of NM1 / NM2 to decrease. At this time, in the loop-locked state, SWN2 is off most of the time, and the control voltage Vctrl remains unchanged. The lower gate voltage of NM1 causes the drain voltage to increase. SWN1 is constantly on, thus raising REF_OUT until the REF_OUT voltage is the same as the control voltage Vctrl. At this point, the gate voltages of NM1 and NM2 ensure that under the new control voltage Vctrl, the pull-up current and pull-down current are the same, minimizing mismatch. Conversely, when the control voltage Vctrl is lower than REF_OUT, the amplifier output becomes higher, the gate voltages of NM1 / NM2 become higher, and since NM1 is connected to node P2 via SWN1, the drain voltage of NM1 becomes lower, pulling REF_OUT lower, ultimately causing REF_OUT to match Vctrl.

[0040] Figure 3 This is a schematic diagram of the basic circuit structure of the second charge pump. The structure is similar to that of the first charge pump, and it also includes a bias generation branch, a pull-up current branch, a pull-down current branch, a replication circuit, and an amplifier comparator.

[0041] The bias generation circuit includes a current source I0 and a self-biasing transistor NM0. One end of I0 is grounded, and the other end is connected to the drain and gate of NM0. The source of NM0 is grounded to VSS.

[0042] The pull-down current branch includes a current source transistor NM2 and a switching transistor SWN2. The source and substrate of NM2 are grounded to VSS, its gate is connected to the gate of NM0, and its drain is connected to the source of SWN2. The gate of SWN2 is connected to the control signal DN, and its drain is connected to the output node P1. When the pull-down signal is high, the channel of SWN2 is open, forming a current path between NM2 and node P1. When the pull-down signal is low, the communication of SWN2 is closed, and the current path between NM2 and node P1 is broken.

[0043] The pull-up current branch includes a current source transistor PM2 and a switching transistor SWP2. The source and substrate of PM2 are connected to the power supply VDD, the gate is connected to the output of the amplifier comparator, and the drain is connected to the source of SWP2. The gate of SWP2 is connected to the control signal UP, and the drain is connected to the output node P1. When the pull-up signal is high, UPN is low, and the SWP2 channel is open, forming a current path between PM2 and node P1. When the pull-up signal is low, UPN is high, and the SWP2 channel is closed, breaking the current path between PM2 and node P1.

[0044] The replication circuit includes an N-type current source transistor NM1 and an N-type switch transistor SWN1, a P-type current source transistor PM1 and a P-type switch transistor SWP1. PM1's source is connected to VDD, its gate is the same as PM2's, and it is connected to the output of the amplifier comparator. Its drain is connected to switch SWP1, whose gate is connected to a low potential, keeping the channel normally open. SWP1's drain is connected to the drain of switch SWN1, i.e., node P2, where the output voltage is VREF_OUT. SWN1's gate is connected to a high potential, keeping the channel normally open, and its source is connected to the drain of NM1. NM1's gate is the same as NM2's, connected to the gate of NM0, and NM1's source is grounded. The dimensions of NM1 and SWN1 in this branch are the same as or maintain a fixed proportional relationship with NM2 and SWN2 in the pull-down circuit branch. The dimensions of PM1 and SWP1 in this branch are the same as or maintain a fixed proportional relationship with PM2 and SWP2 in the pull-up current branch. It is important to note that the two fixed proportional relationships must be consistent. The comparator amplifier is connected similarly to the first charge pump, with inputs REF_OUT and VOUT, and outputs controlling PM2 and PM1.

[0045] Figure 3 In the current loop, when Vctrl is higher than REF_OUT, the amplifier output goes lower, causing the gate voltages of PM1 / PM2 to decrease. During this time, in the loop-locked state, SWP2 is off most of the time, and Vctrl remains unchanged. The lower gate voltage of PM1 causes the drain voltage to rise. SWP1 remains on, thus pulling REF_OUT high until REF_OUT equals Vctrl. At this point, the gate voltages of PM1 and PM2 ensure that under the new Vctrl, the pull-up and pull-down currents are equal, minimizing mismatch. Conversely, when Vctrl is lower than REF_OUT, the amplifier output goes higher, the gate voltages of PM1 / PM2 go higher, and the drain voltage of PM1 goes lower. This causes REF_OUT to go lower via SWP1, eventually bringing REF_OUT to match Vctrl.

[0046] To further explain the working principle of the invention described above, Figure 4 and Figure 5 The mismatch current and Vctrl ripple changes before and after charge pump switching of the complementary charge pump are given respectively in the output range of 0 to VDD.

[0047] from Figure 4 As can be seen, the mismatch current of the first charge pump (Icpmis_CP1) is less than 1uA when it is between 200mV and VDD. However, when the output voltage is lower, the mismatch current increases significantly, reaching 200uA. The mismatch current of the second charge pump (Icpmis_CP2) is very small between 0 and (VDD-200mV). It is worth noting that 200mV is equal to 0.3 times the transistor threshold voltage Vth.

[0048] At higher output voltages, the mismatch current increases significantly. The two charge pumps can achieve good complementarity.

[0049] Figure 5 By analyzing the waveforms before and after the switching, we can more intuitively see the control of the charge pump switching on the Vctrl ripple. Before the switching, the Vctrl ripple was larger, and after the switching, the Vctrl ripple was smaller.

[0050] The above description is merely a preferred embodiment of the present invention. The embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made based on the description and drawings of the present invention should also be included within the scope of protection of the present invention.

[0051] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.

[0052] Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A charge pump phase-locked loop, characterized in that, include: The output of the frequency and phase detector is connected to both the first charge pump and the second charge pump. The first charge pump is connected to the low-pass filter via the first switch, and the second charge pump is connected to the input of the low-pass filter via the second switch. The output of the low-pass filter generates a feedback clock signal via a voltage-controlled oscillator and a loop divider. The feedback clock signal is input to the second input of the frequency and phase detector, while an external reference clock is input to the first input of the frequency and phase detector. Simultaneously, an external reference clock and a feedback clock signal are input to the lock detector. The output signal of the lock detector is connected to the enable terminal of a voltage comparator. A fixed voltage Vref is input to the first input terminal of the voltage comparator, and a control voltage Vctrl is input to the second input terminal of the voltage comparator. The control voltage Vctrl is the output voltage of the first charge pump and the second charge pump. When the chip is powered on, the lock detector is used to detect the lock status of the output of the charge pump phase-locked loop. The voltage comparator is enabled under the control of the output signal of the lock detector and is used to compare the magnitude between the control voltage Vctrl and the fixed voltage Vref. It outputs a first enable signal of the first switch and a second enable signal of the second switch. The polarity of the second enable signal is opposite to that of the first enable signal. The first charge pump is used to provide the control voltage Vctrl to the low-pass filter when the first switch is enabled under the control of the first enable signal; the second charge pump is used to provide the control voltage Vctrl to the low-pass filter when the second switch is enabled under the control of the second enable signal. The first charge pump and the second charge pump are complementary charge pumps; wherein, the first charge pump includes a P-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and an N-type comparator amplifier, and the second charge pump, being a complementary charge pump, includes an N-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and a P-type comparator amplifier; or, the first charge pump includes an N-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and a P-type comparator amplifier, and the second charge pump, being a complementary charge pump, includes a P-type bias generation circuit, a pull-up branch, a pull-down branch, a proportional replication circuit, and an N-type comparator amplifier.

2. The charge pump phase-locked loop according to claim 1, characterized in that, Both the first switch and the second switch are CMOS transmission gates.

3. The charge pump phase-locked loop according to claim 2, characterized in that, The first switch is a P-type transmission tube, and the second switch is an N-type transmission tube; or, the first switch is an N-type transmission tube, and the second switch is a P-type transmission tube. The gate of the N-type transmission transistor is connected to the first enable signal, and the gate of the P-type transmission transistor is connected to the second enable signal.

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