High-speed switched-capacitor dynamic biasing circuit and pipelined analog-to-digital converter

Abstract

The application provides a high-speed switched capacitor dynamic bias circuit and a pipeline type analog-digital converter, which combines a "capacitor module + first switch module + second switch module" design dynamic bias circuit, adopts a switched capacitor structure to realize dynamic switching of a bias voltage, and can quickly switch the output dynamic bias voltage between a first threshold value and a second threshold value. When the high-speed switched capacitor dynamic bias circuit is applied to the pipeline type analog-digital converter, the MOS current source can be biased to a sub-threshold working area in a sampling clock phase half cycle through switching control of the dynamic bias voltage, so that the current of the MOS current source tends to be zero, and the MOS current source can be biased to a saturation working area in an amplification clock phase half cycle, so that the average current of the amplifier circuit is reduced by half in a complete clock cycle, and the average power consumption of the amplifier circuit is reduced. Meanwhile, the switching speed of the dynamic bias voltage is fast, and the high-speed switched capacitor dynamic bias circuit is suitable for the pipeline type analog-digital converter working at a high speed.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-speed switched capacitor dynamic bias circuit and a pipelined analog-to-digital converter. Background Technology

[0002] Next-generation wireless communication systems place further demands on the accuracy, speed, and power consumption of analog-to-digital converters (ADCs), requiring low power consumption while maintaining high speed and accuracy. Traditional pipelined ADCs used in communication systems generally consume high power even with high speed and accuracy specifications. To meet the overall system power consumption requirements, low-power design techniques are needed for technological upgrades. In pipelined ADCs, the most power-consuming module is usually the operational amplifier, whose specifications directly determine the system's speed and linearity. It typically accounts for more than half of the ADC's power consumption. Therefore, to achieve both low power consumption and high speed, it is necessary to reduce the amplifier's power consumption while maintaining its speed. For devices operating continuously, reducing average power consumption is usually more meaningful than reducing instantaneous power consumption. Therefore, reducing the average current over a cycle can reduce the amplifier's average power consumption, and dynamically switching the amplifier's bias current becomes an important way to reduce the average current.

[0003] However, existing methods for dynamically biasing amplifier current sources using switches cannot meet the requirements of high-speed operation. This is because the current source itself has a large device size, resulting in a large time constant for the switching network. This prevents the amplifier from operating in a stable state within a specified period, and its slew rate is generally below 50 MSPS. Therefore, new dynamic biasing techniques are needed to achieve higher slew rates. A typical implementation of a dynamic biasing circuit involves controlling the bias voltage of some MOSFETs in the operational amplifier's current source using switches. These MOSFETs are turned off during the sampling phase clock cycle and biased to their normal operating voltage during the amplification phase clock cycle, thereby reducing the amplifier's average current. However, traditional dynamic biasing circuits have a slow high-low level switching speed for the output bias voltage and a complex structure.

[0004] Therefore, there is an urgent need for a dynamic biasing technology solution that is simple in structure and has a fast switching speed. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-speed switched capacitor dynamic biasing technology solution to solve the technical problem of slow bias voltage switching speed in pipelined analog-to-digital converters operating in high-speed mode.

[0006] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0007] A high-speed switched capacitor dynamic bias circuit includes:

[0008] The capacitor module is connected to a reference voltage and a static bias voltage. It samples and redistributes the reference voltage and the static bias voltage to obtain and output a dynamic bias voltage.

[0009] The first switching module is connected in the reference voltage sampling circuit and the static bias voltage sampling circuit of the capacitor module. Under the control of the first clock control signal, it samples the reference voltage and the static bias voltage through the capacitor module and pulls the dynamic bias voltage up to the first threshold.

[0010] The second switching module is connected in the charge redistribution circuit of the capacitor module. Under the control of the second clock control signal, it redistributes the charge of the reference voltage and the static bias voltage through the capacitor module and pulls the dynamic bias voltage down to the second threshold.

[0011] Optionally, the capacitor module includes a first capacitor, a second capacitor, a third capacitor, and a parasitic capacitor; the first switch module includes a first switch, a second switch, a third switch, and a fourth switch; the second switch module includes a fifth switch, a sixth switch, and a seventh switch; one end of the first capacitor is connected to the operating voltage; the other end of the first capacitor is connected to the output terminal of the second switch and the input terminal of the seventh switch; the input terminal of the second switch is connected to the static bias voltage; the output terminal of the seventh switch is connected to one end of the parasitic capacitor; the other end of the parasitic capacitor is connected to the operating voltage; one end of the second capacitor is connected to the output terminal of the first switch and the output terminal of the fifth switch; the other end of the second capacitor is connected to the input terminal of the third switch and the input terminal of the sixth switch; the input terminal of the first switch is connected to the reference voltage; the input terminal of the fifth switch is connected to the operating voltage; the output terminal of the third switch is connected to the operating voltage; the output terminal of the sixth switch is connected to one end of the third capacitor; the other end of the third capacitor is connected to the output terminal of the seventh switch; the input terminal of the fourth switch is connected to the operating voltage; and the output terminal of the fourth switch is connected to the output terminal of the sixth switch; wherein the parasitic capacitor connected to one end of the seventh switch outputs the dynamic bias voltage.

[0012] Optionally, the control terminals of the first switch, the second switch, the third switch, and the fourth switch are respectively connected to the first clock control signal, and the control terminals of the fifth switch, the sixth switch, and the seventh switch are respectively connected to the second clock control signal.

[0013] Optionally, the phase of the first clock control signal is opposite to the phase of the second clock control signal.

[0014] Optionally, the high-speed switched capacitor dynamic bias circuit also includes:

[0015] The reference voltage generation module generates and outputs the reference voltage.

[0016] Optionally, the reference voltage generation module includes an operational amplifier, an NMOS transistor, a first resistor, and a second resistor. The non-inverting input of the operational amplifier is connected to a reference voltage, the output of the operational amplifier is connected to the gate of the NMOS transistor, the drain of the NMOS transistor is connected to the operating voltage, the source of the NMOS transistor is grounded after passing through the first resistor and the second resistor connected in series, the inverting input of the operational amplifier is connected to the common terminal of the first resistor and the second resistor, and the source of the NMOS transistor outputs the reference voltage.

[0017] A pipelined analog-to-digital converter includes at least an amplifier circuit and a high-speed switched-capacitor dynamic bias circuit as described in any of the preceding claims. The amplifier circuit includes a MOS current source. The dynamic bias voltage output by the high-speed switched-capacitor dynamic bias circuit is connected to the gate of the MOS transistor in the MOS current source. By controlling the dynamic bias voltage, the MOS current source is biased to the subthreshold operating region during half a cycle of the sampling clock phase and to the saturation operating region during half a cycle of the amplification clock phase.

[0018] As described above, the high-speed switched-capacitor dynamic bias circuit and pipelined analog-to-digital converter provided by the present invention have at least the following beneficial effects:

[0019] A high-speed switched-capacitor dynamic bias circuit is designed by combining a capacitor module, a first switch module, and a second switch module. The switched-capacitor structure enables dynamic switching of the bias voltage, allowing the output dynamic bias voltage to quickly switch between a first and a second threshold. When applied to a pipelined analog-to-digital converter (ADC), this high-speed switched-capacitor dynamic bias circuit, through the switching control of the dynamic bias voltage, can bias the MOS current source to the subthreshold operating region during half a sampling clock cycle, bringing its current close to zero, and to the saturation operating region during the other half of the amplification clock cycle. This reduces the average current of the amplifier circuit by half over a complete clock cycle, significantly lowering the average power consumption of the amplifier circuit. Simultaneously, the fast switching speed of the dynamic bias voltage allows the amplifier circuit to quickly enter a stable operating state. This high-speed switched-capacitor dynamic bias circuit is suitable for high-speed pipelined ADCs. Attached Figure Description

[0020] Figure 1 The diagram shown is a circuit diagram of a high-speed switched capacitor dynamic bias circuit in an optional embodiment of the present invention.

[0021] Figure 2 Displayed as Figure 1 Timing diagram of the first clock control signal Ф1 and the second clock control signal Ф2.

[0022] Figure 3 The diagram shown is a circuit diagram of the reference voltage generation module in a high-speed switched capacitor dynamic bias circuit according to an optional embodiment of the present invention.

[0023] Figure 4 The diagram shows the dynamic bias voltage output waveforms of a conventional dynamic bias circuit and the high-speed switched capacitor dynamic bias circuit of the present invention in an optional embodiment of the present invention. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] Please see Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0026] As described in the background section, the inventors discovered that in order to achieve low-power and high-speed pipelined analog-to-digital converters (ADCs), the bias current of the amplifier in the pipelined ADC can be dynamically switched to reduce the average current. However, the technical solution of dynamically biasing the amplifier current source by switching cannot meet the requirements of high-speed operation because the current source itself has a large device size, resulting in a large time constant of the switching network, which cannot allow the amplifier to operate in a stable state within a specified period. In addition, other dynamic bias circuit technologies have slow high and low level switching speeds for the output bias voltage and corresponding complex structures.

[0027] Based on this, the present invention provides a dynamic biasing technology solution, which uses a switched capacitor to realize the dynamic switching of the bias voltage, and the corresponding circuit structure is simple and the switching speed is fast.

[0028] like Figure 1 As shown, the present invention provides a high-speed switched capacitor dynamic bias circuit, which includes:

[0029] The capacitor module is connected to the reference voltage V. R And the static bias voltage PBIAS, relative to the reference voltage V R The static bias voltage PBIAS is sampled and redistributed to obtain and output the dynamic bias voltage PBIAS_D;

[0030] The first switching module is connected to the reference voltage sampling circuit and the static bias voltage sampling circuit of the capacitor module. Under the control of the first clock control signal Ф1, it controls the reference voltage V through the capacitor module. R The static bias voltage PBIAS is sampled, and the dynamic bias voltage PBIAS_D is pulled up to the first threshold.

[0031] The second switching module is connected in the charge redistribution circuit of the capacitor module. Under the control of the second clock control signal Ф2, it controls the reference voltage V through the capacitor module. R Charge redistribution is performed with the static bias voltage PBIAS, and the dynamic bias voltage PBIAS_D is pulled down to the second threshold.

[0032] In detail, such as Figure 1 As shown, the capacitor module includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a parasitic capacitor C. P The first switch module includes a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4. The second switch module includes a fifth switch SW5, a sixth switch SW6, and a seventh switch SW7. One end of the first capacitor C1 is connected to the operating voltage V. DD The other end of the first capacitor C1 is connected to the output terminal of the second switch SW2 and the input terminal of the seventh switch SW7. The input terminal of the second switch SW2 is connected to the static bias voltage PBIAS, and the output terminal of the seventh switch SW7 is connected to the parasitic capacitance C. P At one end, the parasitic capacitance C P The other end is connected to the working voltage V. DD One end of the second capacitor C2 is connected to the output terminals of the first switch SW1 and the fifth switch SW5, respectively. The other end of the second capacitor C2 is connected to the input terminals of the third switch SW3 and the sixth switch SW6, respectively. The input terminal of the first switch SW1 is connected to the reference voltage V. R The input terminal of the fifth switch SW5 is connected to the operating voltage V. DDThe output terminal of the third switch SW3 is connected to the operating voltage V. DD The output terminal of the sixth switch SW6 is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is connected to the output terminal of the seventh switch SW7. The input terminal of the fourth switch SW4 is connected to the operating voltage V. DD The output terminal of the fourth switch SW4 is connected to the output terminal of the sixth switch SW6, wherein the parasitic capacitance C P Connect one end of the seventh switch SW7 to output the dynamic bias voltage PBIAS_D.

[0033] In detail, such as Figure 1 As shown, the control terminals of the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 are respectively connected to the first clock control signal Ф1, and the control terminals of the fifth switch SW5, the sixth switch SW6, and the seventh switch SW7 are respectively connected to the second clock control signal Ф2.

[0034] The timing states of the first clock control signal Ф1 and the second clock control signal Ф2 are as follows: Figure 2 As shown; Figure 2 As shown, the phase of the first clock control signal Ф1 is opposite to the phase of the second clock control signal Ф2. The high level of the first clock control signal Ф1 corresponds to the sampling clock phase S, and the high level of the second clock control signal Ф2 corresponds to the amplification clock phase H.

[0035] More specifically, in combination with, for example Figure 2 The timing signals shown are as follows: Figure 1 The specific working principle of the high-speed switched capacitor dynamic bias circuit shown is as follows:

[0036] 1) When the first clock control signal Ф1 is high and the second clock control signal Ф2 is low, the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 in the first switch module are turned on, while the fifth switch SW5, the sixth switch SW6, and the seventh switch SW7 in the second switch module are turned off. The high-speed switched capacitor dynamic bias circuit outputs the dynamic bias voltage PBIAS_D at the sampling clock phase. At this time, the reference voltage V is sampled through the second capacitor C2. R The static bias voltage PBIAS is sampled through the first capacitor C1, and the operating voltage V is connected across the third capacitor C3. DD And output node A, at this time the third capacitor C3 and parasitic capacitor C P The series connection causes the dynamic bias voltage PBIAS_D of the output node A to rise in phase with the amplification clock. When the gate of the PMOS transistor connected to the amplifier's PMOS current source is engaged, it drives the amplifier's PMOS current source into the subthreshold region, making the output current close to zero.

[0037] 2) When the first clock control signal Ф1 is low and the second clock control signal Ф2 is high, the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 in the first switch module are turned off, and the fifth switch SW5, the sixth switch SW6 and the seventh switch SW7 in the second switch module are turned on. The high-speed switched capacitor dynamic bias circuit outputs the dynamic bias voltage PBIAS_D when amplifying the clock phase. At this time, the switched capacitor circuit composed of the second switch SW2, the seventh switch SW7 and the first capacitor C1 is equivalent to a frequency-dependent resistor, which pulls the dynamic bias voltage PBIAS_D down to the second threshold (i.e., the static bias voltage PBIAS), so that the output dynamic bias voltage PBIAS_D is equal to the static bias voltage PBIAS. Since the voltage difference across the first capacitor C1 cannot jump, the dynamic bias voltage PBIAS_D is established very quickly, which allows the amplifier to quickly switch from the subthreshold operating state to the normal operating state and generate a stable output signal.

[0038] 3) When the first clock control signal Ф1 is low and the second clock control signal Ф2 is high, the switched capacitor circuit composed of the second switch SW2, the seventh switch SW7, and the first capacitor C1 is equivalent to a frequency-dependent resistor, pulling the dynamic bias voltage PBIAS_D low and maintaining it at the second threshold, so that the output dynamic bias voltage PBIAS_D is equal to the static bias voltage PBIAS. When the first clock control signal Ф1 is high and the second clock control signal Ф2 is low, the seventh switch SW7 is turned off, and the dynamic bias voltage PBIAS_D is no longer equal to the static bias voltage PBIAS. At this time, the sampling clock phase begins, and because the upper plate of the third capacitor C3 is pulled up to V... DD Then, the dynamic bias voltage PBIAS_D of the lower plate of the third capacitor C3 is pulled up to the first threshold, rising relative to the second threshold during the amplification clock phase. This drives the PMOS current source of the amplifier into the subthreshold region, making the output current close to zero. This cycle repeats, and the dynamic bias voltage PBIAS_D quickly switches back and forth between the first and second thresholds, forming a square wave shape.

[0039] The calculation process for the first threshold is as follows: Assume PBIAS = V P PBIAS_D is V when the first clock control signal Ф1 is high. A (That is, the first threshold), the upper plate of the third capacitor C3 is V when the second clock control signal Ф2 is high. B Furthermore, when the second clock control signal Ф2 is high, the final value of PBIAS_D eventually tends to V. P Then, at nodes A and B, by the principle of charge conservation, we obtain the following formula:

[0040]

[0041]

[0042]

[0043] Substituting equation (3) into equation (1), we get:

[0044]

[0045] In other words, the first threshold of the dynamic bias voltage PBIAS_D, or the dynamic bias voltage PBIAS_D when the first clock control signal Ф1 is high, is:

[0046]

[0047] As can be seen from equation (4), by adjusting the capacitance values ​​of the second capacitor C2 and the third capacitor C3, the first threshold of the output dynamic bias voltage PBIAS_D can be changed, so that the output voltage value is within the subthreshold bias voltage range, making the PMOS transistor of the corresponding PMOS current source close to turn off, and the output current close to zero.

[0048] In detail, such as Figure 3 As shown, the high-speed switched capacitor dynamic bias circuit also includes:

[0049] The reference voltage generation module generates and outputs a reference voltage. R .

[0050] More in detail, such as Figure 3 As shown, the reference voltage generation module includes operational amplifier A1, NMOS transistor M1, first resistor R1, and second resistor R2. The non-inverting input of operational amplifier A1 is connected to the reference voltage V. REF The output of operational amplifier A1 is connected to the gate of NMOS transistor M1, and the drain of NMOS transistor M1 is connected to the operating voltage V. DD The source of NMOS transistor M1 is grounded to GND via a first resistor R1 and a second resistor R2 connected in series. The inverting input of operational amplifier A1 is connected to the common terminal of the first resistor R1 and the second resistor R2. The source output of NMOS transistor M1 is a reference voltage V. R .

[0051] More in detail, such as Figure 3 As shown, based on the virtual short of operational amplifier A1, the reference voltage V REF The voltage is copied to the common terminal of the first resistor R1 and the second resistor R2, where the first resistor R1 and the second resistor R2 act as a voltage divider to obtain the reference voltage V. RNMOS transistor M1 is used to drive the reference voltage V of the output node. R The reference voltage V is adjusted by adjusting the ratio of the first resistor R1 to the second resistor R2. R The output voltage value.

[0052] To further verify the aforementioned advantages of the high-speed switched-capacitor dynamic bias circuit of the present invention, in an optional embodiment of the present invention, a conventional dynamic bias circuit and the high-speed switched-capacitor dynamic bias circuit of the present invention were constructed and a simulation comparison experiment was conducted to obtain the dynamic bias voltage output waveforms of the two circuits as shown below. Figure 4 As shown. Figure 4 As shown, compared with the traditional dynamic bias circuit, the high-speed switched capacitor dynamic bias circuit of the present invention has the advantage of fast bias voltage establishment speed. Among them, the PBIAS voltage (i.e. the second threshold) is the bias voltage when the amplifier is working normally, and the PBIAS_S voltage (i.e. the first threshold) is the bias voltage when the amplifier is working in the subthreshold region. This structure enables the high-speed amplifier to achieve a slew rate of more than 100MSPS while meeting the requirements of low power consumption.

[0053] Furthermore, based on the aforementioned high-speed switched-capacitor dynamic bias circuit, this invention also provides a pipelined analog-to-digital converter, which includes at least an amplifier circuit and the aforementioned high-speed switched-capacitor dynamic bias circuit. The amplifier circuit includes a MOS current source, and the dynamic bias voltage output by the high-speed switched-capacitor dynamic bias circuit is connected to the gate of the MOS transistor in the MOS current source. By controlling the dynamic bias voltage, the MOS current source is biased to the subthreshold operating region during half a cycle of the sampling clock phase and to the saturation operating region during half a cycle of the amplification clock phase. At the same time, the dynamic bias voltage has a fast switching speed, which can quickly bring the amplifier circuit into a stable operating state, thus facilitating the improvement of the operating speed of the pipelined analog-to-digital converter.

[0054] In summary, the high-speed switched-capacitor dynamic bias circuit and pipelined analog-to-digital converter provided by this invention combine a "capacitor module + first switch module + second switch module" design for the high-speed switched-capacitor dynamic bias circuit. A switched-capacitor structure is used to achieve rapid dynamic switching of the bias voltage. The output dynamic bias voltage can quickly switch back and forth between a first threshold and a second threshold. When this high-speed switched-capacitor dynamic bias circuit is applied to a pipelined analog-to-digital converter, the switching control of the dynamic bias voltage enables the MOS current source to be biased to the subthreshold operating region during half a cycle of the sampling clock phase, causing its current to approach zero. During the other half cycle of the amplification clock phase, it is biased to the saturation operating region, thereby reducing the average current of the amplifier circuit by half within a complete clock cycle, significantly reducing the average power consumption of the amplifier circuit. Simultaneously, the fast switching speed of the dynamic bias voltage allows the amplifier circuit to quickly enter a stable operating state. This high-speed switched-capacitor dynamic bias circuit is suitable for high-speed pipelined analog-to-digital converters.

[0055] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-speed switched capacitor dynamic bias circuit, characterized in that, include: The capacitor module is connected to a reference voltage and a static bias voltage. It samples and redistributes the reference voltage and the static bias voltage to obtain and output a dynamic bias voltage. The first switching module is connected in the reference voltage sampling circuit and the static bias voltage sampling circuit of the capacitor module. Under the control of the first clock control signal, it samples the reference voltage and the static bias voltage through the capacitor module and pulls the dynamic bias voltage up to the first threshold. The second switching module is connected in the charge redistribution circuit of the capacitor module. Under the control of the second clock control signal, it redistributes the charge of the reference voltage and the static bias voltage through the capacitor module and pulls the dynamic bias voltage down to the second threshold. The capacitor module includes a first capacitor, a second capacitor, a third capacitor, and a parasitic capacitor. The first switch module includes a first switch, a second switch, a third switch, and a fourth switch. The second switch module includes a fifth switch, a sixth switch, and a seventh switch. One end of the first capacitor is connected to the operating voltage, and the other end of the first capacitor is connected to the output terminal of the second switch and the input terminal of the seventh switch. The input terminal of the second switch is connected to the static bias voltage. The output terminal of the seventh switch is connected to one end of the parasitic capacitor, and the other end of the parasitic capacitor is connected to the operating voltage. One end of the second capacitor is connected to the output terminal of the first switch and the output terminal of the fifth switch. The other end of the second capacitor is connected to the input terminals of the third switch and the sixth switch, respectively. The input terminal of the first switch is connected to the reference voltage, the input terminal of the fifth switch is connected to the operating voltage, the output terminal of the third switch is connected to the operating voltage, the output terminal of the sixth switch is connected to one end of the third capacitor, the other end of the third capacitor is connected to the output terminal of the seventh switch, the input terminal of the fourth switch is connected to the operating voltage, and the output terminal of the fourth switch is connected to the output terminal of the sixth switch. The parasitic capacitor is connected to one end of the seventh switch to output the dynamic bias voltage. The phase of the first clock control signal is opposite to the phase of the second clock control signal.

2. The high-speed switched capacitor dynamic bias circuit according to claim 1, characterized in that, The control terminals of the first switch, the second switch, the third switch, and the fourth switch are respectively connected to the first clock control signal, and the control terminals of the fifth switch, the sixth switch, and the seventh switch are respectively connected to the second clock control signal.

3. The high-speed switched capacitor dynamic bias circuit according to claim 1, characterized in that, The high-speed switched capacitor dynamic bias circuit also includes: The reference voltage generation module generates and outputs the reference voltage.

4. The high-speed switched capacitor dynamic bias circuit according to claim 3, characterized in that, The reference voltage generation module includes an operational amplifier, an NMOS transistor, a first resistor, and a second resistor. The non-inverting input of the operational amplifier is connected to a reference voltage, the output of the operational amplifier is connected to the gate of the NMOS transistor, the drain of the NMOS transistor is connected to the operating voltage, the source of the NMOS transistor is grounded after passing through the first resistor and the second resistor connected in series, the inverting input of the operational amplifier is connected to the common terminal of the first resistor and the second resistor, and the source of the NMOS transistor outputs the reference voltage.

5. A pipelined analog-to-digital converter, characterized in that, It includes at least an amplifier circuit and a high-speed switched capacitor dynamic bias circuit as described in any one of claims 1-4. The amplifier circuit includes a MOS current source. The dynamic bias voltage output by the high-speed switched capacitor dynamic bias circuit is connected to the gate of the MOS transistor in the MOS current source. By controlling the dynamic bias voltage, the MOS current source is biased to the subthreshold operating region during half a cycle of the sampling clock phase and to the saturation operating region during half a cycle of the amplification clock phase.

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