Semiconductor memory device and method of manufacturing the same

Abstract

Embodiments of the present application provide a semiconductor storage device capable of suppressing an increase in chip area and an increase in channel resistance of a NAND string, and a manufacturing method thereof. The semiconductor storage device (2) of the embodiments is provided with a plurality of wiring layers (632) laminated on a semiconductor substrate (71), a memory pillar (634) penetrating the plurality of wiring layers (632) in a D3 direction, and a semiconductor pillar (638) provided inside the memory pillar (634) and extending in the D3 direction. In addition, the semiconductor storage device (2) of the embodiments is also provided with a wiring layer (631) extending in a D2 direction, provided more upward than the plurality of wiring layers (632), and penetrating the semiconductor pillar (638).

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-146467 (filed on September 8, 2021). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] This embodiment relates to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0004] NAND (Not AND) flash memory is known as a semiconductor storage device. Summary of the Invention

[0005] This embodiment provides a semiconductor memory device and its manufacturing method that can suppress the increase in chip area and the increase in channel resistance of NAND strings.

[0006] The semiconductor memory device of this embodiment includes: a plurality of first wirings disposed above a first direction orthogonal to a semiconductor substrate; a memory pillar extending through the plurality of first wirings in the first direction; and a semiconductor layer disposed inside the memory pillar and extending in the first direction. Furthermore, the semiconductor memory device of this embodiment also includes a second wiring extending in a second direction orthogonal to the first direction, disposed above the plurality of first wirings in the first direction, and extending through the semiconductor layer. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example configuration of a storage system using a semiconductor storage device according to an implementation method.

[0008] Figure 2 This is a block diagram illustrating an example of the configuration of a non-volatile memory in an implementation.

[0009] Figure 3 This is a diagram illustrating an example of the block structure of a three-dimensional memory cell array.

[0010] Figure 4A This is a schematic diagram of a portion of a three-dimensional storage cell array.

[0011] Figure 4B This is another schematic diagram of a storage cell array.

[0012] Figure 4C This is another schematic diagram of a storage cell array.

[0013] Figure 4D This is another schematic diagram of a storage cell array.

[0014] Figure 5A It is a cross-sectional view of a portion of a three-dimensional storage cell array.

[0015] Figure 5B This is another cross-sectional view of a portion of a three-dimensional storage cell array.

[0016] Figures 6-10 These are top views and cross-sectional views of a memory cell array, illustrating an example of the manufacturing steps of a memory cell array according to an embodiment.

[0017] Figures 11A to 11D This is a cross-sectional view illustrating an example of the machining shape of a slotted SLS.

[0018] Figures 12A-12D This is a cross-sectional view illustrating an example of the fabricated shape of wiring layer 631.

[0019] Figure 13 This is a simplified cross-sectional view illustrating the structure of a semiconductor memory device formed by bonding array chips and circuit chips.

[0020] Figure 14 It is a cross-sectional view of a portion of a NAND string memory cell array containing two layers of structure. Detailed Implementation

[0021] Hereinafter, the embodiments will be described with reference to the accompanying drawings.

[0022] (1. Composition)

[0023] (1-1. Composition of a storage system)

[0024] Figure 1 This is a block diagram illustrating an example configuration of a storage system using a semiconductor storage device according to an embodiment. The storage system of this embodiment includes a memory controller 1 and a non-volatile memory 2, which is a semiconductor storage device. The storage system can be connected to a host computer. The host computer is, for example, an electronic device such as a personal computer or a mobile terminal.

[0025] Non-volatile memory 2 is a memory that stores data non-volatilely, such as NAND flash memory. Non-volatile memory 2 is, for example, a NAND memory with each storage cell capable of storing 3 bits of data, i.e., a 3-bit / Cell (TLC: Triple Level Cell) NAND memory. Furthermore, non-volatile memory 2 can also be a NAND memory capable of storing multiple bits of data, such as 1 bit / Cell, 2 bits / Cell, or 4 bits / Cell or more. Additionally, non-volatile memory 2 typically comprises multiple memory chips.

[0026] Memory controller 1 controls the writing of data to non-volatile memory 2 based on write requests from the host. Additionally, memory controller 1 controls the reading of data from non-volatile memory 2 based on read requests from the host. Between memory controller 1 and non-volatile memory 2, the following signals are used: transceiver enable signal / CE, standby / busy signal / RB, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, write protect signal / WP, data signals DQ<7:0>, data strobe signal DQS, and / DQS. Furthermore, the " / " in the signal names indicates that it is active low.

[0027] For example, the non-volatile memory 2 and the memory controller 1 are respectively formed as semiconductor chips (hereinafter also simply referred to as "chips").

[0028] The chip enable signal / CE is used to select a specific memory chip in the non-volatile memory 2 and enable that memory chip. The standby / busy signal / RB indicates whether the non-volatile memory 2 is in a standby state (able to accept commands from external sources) or a busy state (unable to accept commands from external sources). The memory controller 1 can understand the status of the non-volatile memory 2 by receiving the R / B signal. The command latch enable signal CLE indicates that the signal DQ<7:0> represents a command. The command latch enable signal CLE latches the command sent as signal DQ into the command register of the selected memory chip in the non-volatile memory 2. The address latch enable signal ALE indicates that the signal DQ<7:0> represents an address. The address latch enable signal ALE latches the address sent as signal DQ into the address register of the selected memory chip in the non-volatile memory 2. The write enable signal / WE is used to capture the received signal into the non-volatile memory 2, and is asserted each time a command, address, and data are received from the memory controller 1. When the signal / WE is at the "L" level, it indicates that the non-volatile memory 2 should capture the signal DQ<7:0>.

[0029] The read enable signals RE and / RE are used to enable memory controller 1 to read data from non-volatile memory 2. For example, when outputting signal DQ<7:0>, it controls the timing of operation of non-volatile memory 2. The write protect signal / WP is used to instruct non-volatile memory 2 to prohibit data writing and erasure. Signal DQ<7:0> represents the data transmitted and received between non-volatile memory 2 and memory controller 1, including commands, addresses, and data. The data strobe signals DQS and / DQS are used to control the timing of input and output of signal DQ<7:0>.

[0030] The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correct) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0031] The host interface 13 outputs requests received from the host, user data (write data), etc., to the internal bus 16. Additionally, the host interface 13 sends user data read from the non-volatile memory 2, responses from the processor 12, etc., to the host.

[0032] The memory interface 15 controls, based on instructions from the processor 12, processes such as writing user data to the non-volatile memory 2 and reading user data from the non-volatile memory 2.

[0033] Processor 12 provides overall control over memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). Upon receiving a request from the host via host interface 13, processor 12 performs control according to the request. For example, processor 12 may instruct memory interface 15 to write user data and parity data to non-volatile memory 2 based on a request from the host. Additionally, processor 12 may instruct memory interface 15 to read user data and parity data from non-volatile memory 2 based on a request from the host.

[0034] The processor 12 determines the storage area (storage region) on the non-volatile memory 2 for the user data stored in RAM 11. The user data is stored in RAM 11 via the internal bus 16. The processor 12 determines the storage region for data in page units (page data) written as units. In this specification, the user data stored in one page of the non-volatile memory 2 is defined as cell data. Generally, cell data is encoded by the ECC circuit 14 and stored as codewords in the non-volatile memory 2. In this embodiment, encoding is not necessary. The memory controller 1 may also store cell data in the non-volatile memory 2 without encoding. Figure 1 The example shown is an encoding configuration. When the memory controller 1 does not perform encoding, the page data is identical to the cell data. Alternatively, a codeword can be generated based on a single cell data unit, or it can be generated based on segmented data obtained by dividing the cell data. Furthermore, multiple cell data units can be used to generate a single codeword.

[0035] Processor 12 determines the storage region of the non-volatile memory 2 to be written to based on each unit of data. Physical addresses are allocated to the storage regions of the non-volatile memory 2. Processor 12 uses physical addresses to manage the storage regions of the target units for writing data. Processor 12 specifies the determined storage region (physical address) and instructs memory interface 15 to write user data into non-volatile memory 2. Processor 12 manages the mapping between the logical address (the logical address managed by the host) of user data and the physical address. Upon receiving a read request containing a logical address from the host, processor 12 specifies the physical address corresponding to the logical address, assigns the physical address, and instructs memory interface 15 to read the user data.

[0036] ECC circuit 14 encodes the user data stored in RAM 11 to generate codewords. Additionally, ECC circuit 14 decodes the codewords read from non-volatile memory 2.

[0037] RAM 11 temporarily stores user data received from the host before transferring it to non-volatile memory 2, or temporarily stores data read from non-volatile memory 2 before sending it to the host. RAM 11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0038] Figure 1The diagram shows an example configuration where the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can also be integrated into the non-volatile memory 2.

[0039] When a write request is received from the host, the storage system operates as described below. Processor 12 temporarily stores the data to be written in RAM 11. Processor 12 reads the data stored in RAM 11 and inputs the data to ECC circuit 14. ECC circuit 14 encodes the input data and inputs the codeword to memory interface 15. Memory interface 15 writes the input codeword to non-volatile memory 2.

[0040] When a read request is received from the host, the storage system operates as described below. The memory interface 15 inputs the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and saves the decoded data to the RAM 11. The processor 12 sends the data saved in the RAM 11 to the host via the host interface 13.

[0041] (1-2. The structure of non-volatile memory)

[0042] Figure 2 This is a block diagram illustrating an example of the configuration of the non-volatile memory in this embodiment. The non-volatile memory 2 includes: a logic control circuit 21, an input / output circuit 22, a memory cell array 23, a sense amplifier 24, a line decoder 25, a register 26, a sequencer 27, a voltage generation circuit 28, an input / output pad group 32, a logic control pad group 34, and a power input terminal group 35.

[0043] The memory cell array 23 comprises multiple blocks. Each block BLK comprises multiple memory cell transistors (memory cells). The memory cell array 23 is equipped with multiple bit lines, multiple word lines, and source lines to control the voltage applied to the memory cell transistors. The specific structure of the block BLK will be explained later.

[0044] The input / output pad group 32 has multiple terminals (pads) corresponding to the signals DQ<7:0> and the data strobe signals DQS and / DQS in order to transmit and receive various signals including data with the memory controller 1.

[0045] The logic control pad group 34 has multiple terminals (pads) corresponding to the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protect signal / WP in order to transmit and receive various signals with the memory controller 1.

[0046] The power input terminal group 35 has multiple terminals for inputting power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss to supply various operating power supplies to the non-volatile memory 2 from the outside. The power supply voltage Vcc is the circuit power supply voltage generally supplied externally as the operating power supply, for example, an input voltage of approximately 3.3V. The power supply voltage VccQ is, for example, an input voltage of 1.2V. The power supply voltage VccQ is used when transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2.

[0047] The power supply voltage Vpp is a higher voltage than the power supply voltage Vcc, for example, an input voltage of 12V. When writing or erasing data to the memory cell array 23, a high voltage of approximately 20V is required. In this case, boosting the approximately 12V power supply voltage Vpp can generate the required voltage more quickly and with lower power consumption than boosting the approximately 3.3V power supply voltage Vcc using the boost circuit of the voltage generation circuit 28. The power supply voltage Vcc is the power supplied to the non-volatile memory 2 standard, while the power supply voltage Vpp is a power supply that may be added or arbitrarily supplied, depending on the usage environment.

[0048] The logic control circuit 21 and the input / output circuit 22 are connected to the memory controller 1 via a NAND bus. The input / output circuit 22 transmits and receives signals DQ (e.g., DQ0 to DQ7) with the memory controller 1 via the NAND bus.

[0049] The logic control circuit 21 receives external control signals (e.g., chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protect signal / WP) from the memory controller 1 via the NAND bus. Additionally, the logic control circuit 21 sends a standby / busy signal / RB to the memory controller 1 via the NAND bus.

[0050] Input / output circuit 22 transmits and receives signals DQ<7:0> and data strobe signals DQS and / DQS with memory controller 1. Input / output circuit 22 transmits the command and address in signal DQ<7:0> to register 26. In addition, input / output circuit 22 transmits and receives write data and read data with sense amplifier 24.

[0051] Register 26 includes a command register, an address register, and a status register. The command register temporarily stores commands. The address register temporarily stores addresses. The status register temporarily stores data required for the operation of the non-volatile memory 2. Register 26 may contain, for example, SRAM.

[0052] The sequencer 27, acting as the control unit, receives commands from the register 26 and controls the non-volatile memory 2 according to the sequence of commands.

[0053] The voltage generation circuit 28 receives a power supply voltage from the external source of the non-volatile memory 2 and uses this power supply voltage to generate multiple voltages required for write, read, and erase operations. The voltage generation circuit 28 supplies the generated voltages to the memory cell array 23, the sense amplifier 24, and the line decoder 25, etc.

[0054] The row decoder 25 receives the row address from register 26 and decodes it. Based on the decoded row address, the row decoder 25 performs word line selection. Then, the row decoder 25 transmits multiple voltages required for write, read, and erase operations to the selected block.

[0055] The sense amplifier 24 receives the column address from register 26 and decodes it. The sense amplifier 24 has a sense amplifier unit group 24A and a data register 24B. The sense amplifier unit group 24A is connected to each bit line and selects any bit line based on the decoded column address. Additionally, when reading data, the sense amplifier unit group 24A detects and amplifies the data read from the memory cell transistor to the bit line. Furthermore, when writing data, the sense amplifier unit group 24A transmits the written data to the bit line.

[0056] When reading data, data register 24B temporarily stores the data detected by the sense amplifier unit group 24A and serially transmits the data to the input / output circuit 22. Conversely, when writing data, data register 24B temporarily stores the data serially transmitted from the input / output circuit 22 and transmits the data to the sense amplifier unit group 24A. Data register 24B includes SRAM, etc.

[0057] (1-3. Block structure of a storage cell array)

[0058] Figure 3 This is a diagram illustrating an example of the block structure of a three-dimensional memory cell array. Figure 3 The image shows one block BLK, one of the multiple blocks constituting the storage cell array 23. The other blocks in the storage cell array also have the same characteristics. Figure 3 Same composition.

[0059] As shown in the figure, block BLK contains, for example, four string cells (SU0 to SU3). Each string cell SU contains multiple NAND strings NS. Here, each NAND string NS contains eight memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. The memory cell transistors MT have a gate and a charge accumulation layer to non-volatilely store data. Furthermore, for convenience, the number of memory cell transistors MT contained in each NAND string NS is set to eight, but it can also be more.

[0060] Although the select-gate transistors ST1 and ST2 are represented as a single transistor in the circuit, their structure can be identical to that of the memory cell transistor. Alternatively, multiple select-gate transistors can be used, each acting as a separate select-gate transistor ST1 and ST2. Furthermore, a dummy cell transistor can be placed between the memory cell transistor MT and the select-gate transistors ST1 and ST2.

[0061] The memory cell transistor MT is configured to be connected in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one side is connected to the select gate transistor ST1, and the memory cell transistor MT0 on the other side is connected to the select gate transistor ST2.

[0062] The gates of the select gate transistors ST1 for each of the serial cells SU0 to SU3 are respectively connected to select gate lines SGD0 to SGD3 (hereinafter, without distinguishing between these select gate lines, they are referred to as select gate lines SGD). On the other hand, the gates of the select gate transistors ST2 are commonly connected to the same select gate line SGS among multiple serial cells SU located in the same block BLK. In addition, the gates of the memory cell transistors MT0 to MT7 located in the same block BLK are commonly connected to word lines WL0 to WL7. That is, word lines WL0 to WL7 and select gate lines SGS are commonly connected among multiple serial cells SU0 to SU4 in the same block BLK. In contrast, the select gate lines SGD are independent for each serial cell SU0 to SU3, even within the same block BLK.

[0063] The gates of the memory cell transistors MT0 to MT7 that constitute the NAND string NS are connected to word lines WL0 to WL7, respectively. The gates of the memory cell transistors MTi located in the same row within block BLK are connected to the same word line WLi. Furthermore, in the following description, the NAND string NS will sometimes be referred to simply as "string".

[0064] Each NAND string NS is connected to a corresponding bit line. Therefore, each memory cell transistor MT is connected to the bit line via the select gate transistor ST or other memory cell transistor MT contained in the NAND string NS. As described above, the data of the memory cell transistor MT located within the same block BLK is erased all at once. On the other hand, data reading and writing are performed on a unit basis (or on a page basis) of memory cell group MG. In this specification, a group of memory cell transistors MT connected to one word line WLi and belonging to one string cell SU is defined as a memory cell group MG. During read and write operations, one word line WLi and one select gate line SGD are selected based on the physical address, thereby selecting the memory cell group MG.

[0065] (1-4. Planar structure of non-volatile memory)

[0066] Figure 4A This is a schematic diagram of a portion of a three-dimensional storage cell array. Figure 4A The diagram shows a schematic of a single block BLK. In the following description, the extension direction of the bit line BL in a plane parallel to the semiconductor substrate surface is defined as D1. Furthermore, the direction parallel to the semiconductor substrate surface and orthogonal to D1 is defined as D2. Additionally, the direction orthogonal to the semiconductor substrate surface is defined as D3.

[0067] The memory cell array 23 has a cell region CR and a stepped region SR. The cell region CR is the region where NAND strings NS are formed. The stepped region SR is the region where contacts CT are formed, which connect the select gate line SGS and word lines WL0 to WL7, and a wiring layer (not shown) located above in the D3 direction. In this embodiment, the select gate line SGS and word lines WL0 to WL7 are sequentially deposited on top of the semiconductor substrate. When viewed from above in the D3 direction, the contacts CT connected to the word lines WL0 to WL7 and the select gate line SGS are arranged in a non-overlapping manner, thus making the area of ​​the wiring on the lower layer larger than the area of ​​the wiring on the upper layer. That is, a region (step) where the word line WL0 is not deposited is formed on the upper surface of the select gate line SGS. Similarly, a region (step) where the word line WL(i+1) is not deposited is formed on the upper surface of the word lines WLi (i = 0 to 6). Contacts CT are formed on these steps. Figure 4A An example of a stepped region SR with a three-step structure is shown. That is, the select gate line SGS and word lines WL0 to WL7 are processed such that the step difference between adjacent steps in the D2 direction is 3 layers, and the step difference between adjacent steps in the D1 direction is 1 layer.

[0068] Figure 4AThe image shows a portion of the cell region CR and a portion of the stepped region SR formed in the memory cell array 23. For example... Figure 4A As shown, on the two sides of the character line WL extending in the D2 direction toward the D1 direction, there are slits SL1 to SL3 extending in the D2 direction.

[0069] Four string cells SU0 to SU3 constituting one block BLK are arranged side-by-side in the D1 direction. A slit SL1 is provided between string cell SU0 and string cells SU of other blocks BLK (not shown). Additionally, a slit SL2 is provided between string cells SU1 and SU2. Furthermore, a slit SL3 is provided between string cell SU3 and string cells SU of other blocks BLK (not shown). In other words, four string cells SU0 to SU3 are arranged between slits SL1 and SL3. Slits SL1 to SL3 are provided to separate the select gate line SGS and the word line WL. Furthermore, slits SL1 and SL3 are formed to extend from the cell region CR to the stepped region SR, and to separate the select gate line SGS and word lines WL0 to WL7 between adjacent blocks BLK. On the other hand, slit SL2 is only formed in the cell region CR, and although it is designed to separate the select gate line SGS and word lines WL0 to WL7, it does not reach the stepped region SR. In other words, in the stepped region SR located to the right of the D2 direction of the slit SL2, the gate line SGS and word lines WL0 to WL7 are electrically connected.

[0070] The string cell SU contains multiple memory pillars MP. The memory pillars MP correspond to the memory cell transistors MT0-MT7 and the select gate transistors ST1 and ST2 within the NAND string NS. The memory pillars MP, extending in the D3 direction, pass through the select gate line SGS and the word lines WL0-WL7. Details regarding the structure of the memory pillars MP will be explained later.

[0071] The memory columns MP in the cell region CR are arranged in an eight-link zigzag pattern. That is, there are 8 columns of memory columns MPL between adjacent slits SL. These columns of memory columns MPL contain multiple memory columns MP that are in the same position in the D1 direction and are equally spaced in the D2 direction. Figure 4A In one example shown, since two string units SU are arranged between the slits SL, one string unit SU contains four memory columns MPL.

[0072] More specifically, for example, in serial cell SU0, memory cylinders MP1 and MP2 are arranged adjacent to each other in the D1 direction, and memory cylinders MP3 and MP4 are arranged adjacent to each other in the D1 direction. Additionally, memory cylinders MP5 and MP6 are arranged adjacent to each other in the D1 direction, and memory cylinders MP7 and MP8 are arranged adjacent to each other in the D1 direction. Further, memory cylinders MP3 and MP7 are arranged adjacent to each other in the D2 direction, and memory cylinders MP1 and MP5 are arranged adjacent to each other in the D2 direction. Additionally, memory cylinders MP4 and MP8 are arranged adjacent to each other in the D2 direction, and memory cylinders MP2 and MP6 are arranged adjacent to each other in the D2 direction.

[0073] Furthermore, memory cylinder MP1 is positioned between memory cylinders MP3 and MP4 in the D1 direction, and in a different position from memory cylinders MP3 and MP4 in the D2 direction. Memory cylinder MP4 is positioned between memory cylinders MP1 and MP2 in the D1 direction, and in a different position from memory cylinders MP1 and MP2 in the D2 direction. Additionally, memory cylinder MP5 is positioned between memory cylinders MP7 and MP8 in the D1 direction, and in a different position from memory cylinders MP7 and MP8 in the D2 direction. Memory cylinder MP8 is positioned between memory cylinders MP5 and MP6 in the D1 direction, and in a different position from memory cylinders MP5 and MP6 in the D2 direction.

[0074] The select gate line (SGD) extends in the D2 direction. Each of the string cells SU0 to 3 has four select gate lines (SGD). That is, there is a one-to-one correspondence between the memory column MPL and the select gate line (SGD). In the following description, a symbol with a subscript is used to represent a specific select gate line. For example, the select gate line k-th from the D1 direction for string cell SUj (j = 0, 1, 2, ...) is represented as select gate line SGDj_k. Any select gate line is represented as select gate line SGD.

[0075] The serial cell SU0 is equipped with four select gate lines SGD0_1, SGD0_2, SGD0_3, and SGD0_4. Each select gate line SGD0_1, SGD0_2, SGD0_3, and SGD0_4 is positioned at a different location in the D1 direction. The width (length in the D1 direction) of the select gate line SGD0_1 is smaller than the diameter of the memory cylinder MP. Select gate line SGD0_1 is formed to pass through multiple memory cylinders MP3 and MP7 arranged side-by-side in the same location in the D1 direction and along the D2 direction. Similarly, select gate line SGD0_2 is formed to pass through multiple memory cylinders MP1 and MP5 arranged side-by-side in the same location in the D1 direction and along the D2 direction. Furthermore, select gate line SGD0_3 is formed to pass through multiple memory cylinders MP4 and MP8 arranged side-by-side in the same location in the D1 direction and along the D2 direction. Furthermore, the select gate line SGD0_4 is formed to pass through multiple memory pillars MP2 and MP6 arranged side-by-side in the same position along the D1 direction and along the D2 direction. That is, the select gate line SGD is configured to pass through one memory pillar MP, with any one of the multiple select gate lines SGD passing through it. A select gate transistor ST1 is formed at the intersection of the select gate line SGD and the memory pillar MP.

[0076] The four select gate lines SGD0_1, SGD0_2, SGD0_3, and SGD0_4 configured in the serial unit SU0 are electrically connected to the wiring VL0 via via VA within the stepped region SR. That is, the same voltage is applied to the select gate lines SGD0_1, SGD0_2, SGD0_3, and SGD0_4 from wiring VL0. Similarly, select gate lines SGD1_0 to SGD1_3 are electrically connected to wiring VL1, select gate lines SGD2_0 to SGD2_3 are electrically connected to wiring VL2, and select gate lines SGD3_0 to SGD3_3 are electrically connected to wiring VL3 within the stepped region SR via via VA. In other words, the configuration allows voltage to be applied to select gate lines SGD configured in the same serial unit SU from the same wiring VL, and voltage to select gate lines configured in different serial units SU from different wiring VL, thus enabling the application of independent voltages to different select gate lines SGD within the respective serial unit SU. Furthermore, although the cross-sectional shape of the through hole VA is represented as an ellipse, it can also be a circular shape, etc.

[0077] A contact plug CP2 is formed on the memory cylinder MP. Furthermore, the contact plug CP2 is connected to any one of the multiple bit lines BL extending in the D1 direction. That is, multiple memory cylinders MP within the string cell SU are connected to different bit lines BL via the contact plug CP2. More specifically, for example, memory cylinders MP1 to MP8 are each connected to different bit lines BL. One memory cylinder MP of each string cell SU is commonly connected to one bit line BL. Figure 4A As shown, when multiple memory cylinders MP are arranged in a four-column sawtooth configuration within each string cell SU, the width of each bit line BL becomes the width of two bit lines BL that can be configured above one memory cylinder MP. That is, the bit line pitch P_BL (bit line width + bit line spacing) is one-quarter of the memory hole pitch P_MH (diameter of memory hole MH + spacing between adjacent memory holes in the D2 direction).

[0078] Furthermore, the number of string units (SU) constituting a block (BLK) or the number of memory columns (MPL) constituting a string unit (SU) can be arbitrarily set. For example, in an eight-linked zigzag memory column MP, a block (BLK) can contain four string units (SU), and a string unit (SU) can contain two memory columns. Figure 4B Another schematic diagram of a storage cell array is shown in the figure. Figure 4B In the shown memory cell array, the multiple memory columns MP of each string cell SU are arranged in a two-row sawtooth configuration facing the D2 direction. Four string cells SU0 to SU3 constituting one block BLK are arranged between slits SL1 and SL2, and four string cells SU0 to SU3 constituting another block BLK are arranged between slits SL2 and SL3.

[0079] Serial cell SU0 includes two select gate lines SGD0_1 and SGD0_2. Select gate lines SGD0_1 and SGD0_2 are electrically connected to wiring VL0 via via VA. Similarly, select gate lines SGD1_1 and SGD1_2 are electrically connected to wiring VL1, select gate lines SGD2_1 to SGD2_2 are electrically connected to wiring VL2, and select gate lines SGD3_0 and SGD3_1 are electrically connected to wiring VL3 via via VA. This means that independent voltages can be applied to the different select gate lines SGD of the respective serial cell SU. Furthermore, in each serial cell SU, when multiple memory pillars MP are arranged in a two-row sawtooth configuration, the width of each bit line BL is such that one bit line BL can be positioned above one memory pillar MP. That is, the bit line pitch P_BL is half the memory via pitch P_MH. Therefore, compared to... Figure 4A The structure shown is as follows: Figure 4B The bit lines in the configuration shown are made wider.

[0080] Figure 4C ,and Figure 4D Another schematic diagram of a storage cell array is shown in the figure. Figure 4C The diagram illustrates the following situation: in an eight-linked zigzag memory column MP, one block BLK contains eight serial units SU, and one serial unit SU contains two memory column columns. Figure 4D The diagram illustrates a scenario where, in an eight-column zigzag memory column (MP), one block (BLK) contains eight serial cells (SU), and one serial cell (SU) contains one column of memory columns. Furthermore, as... Figure 4D As shown, when multiple memory columns MP are arranged in a sawtooth configuration within each string cell SU, the width of each bit line BL is such that one bit line BL can be positioned above two memory columns MP. In other words, the bit line spacing P_BL is the same as the memory hole spacing P_MH. This allows the number of string cells SU constituting one block BLK, or the number of memory column columns MPL constituting one string cell SU, to be arbitrarily set.

[0081] Additionally, the memory pillars MP can be arranged in other patterns besides a zigzag configuration. Regardless of the arrangement of the memory pillars MP, the select gate line SGD of each string cell SU is formed in a specified direction (in... Figures 4A to 4D In the case of D2 direction, it extends and passes through multiple memory pillars MP arranged in the same direction as the select gate line SGD within the string cell SU.

[0082] (1-5. Cross-sectional structure of non-volatile memory)

[0083] Next, regarding the cross-sectional structure of the memory cell array, we will use... Figure 5A Please provide an explanation. Figure 5A It is a cross-sectional view of a portion of a three-dimensional storage cell array, and is a cross-sectional view along line A1-A2 in Figure 4.

[0084] The storage cell array 23 has a three-dimensional structure. For example... Figure 5A As shown, multiple NAND strings NS are formed on the p-well region. That is, multiple wiring layers 633, functioning as select gate lines (SGS), are stacked on the p-well region. Furthermore, multiple wiring layers 632, functioning as word lines (WLi), are stacked on top of these wiring layers 633. An insulating layer (not shown) is provided between adjacent wiring layers 632 and 633 in the D3 direction. In Figure 4, for ease of explanation, a structure consisting of eight stacked wiring layers 632, functioning as word lines (WLi), is shown; however, more wiring layers 632 can also be stacked.

[0085] Furthermore, memory pillars 634 are formed that penetrate these wiring layers 633 and 632 and reach the p-type well region. A barrier insulating film 635, a charge accumulation layer 636, and a tunnel insulating film 637 are sequentially formed on the side of the memory pillar 634, and a semiconductor pillar 638 is embedded within the memory hole 634. The semiconductor pillar 638, for example, contains polysilicon and functions as a channel forming region when the memory cell transistors MT and select gate transistors ST1 and ST2 contained in the NAND string NS are activated. For example, the portion where the memory pillar 634 intersects with the wiring layer 633 functions as the select gate transistor ST2. The portions where the memory pillar 634 intersects with the wiring layer 632 respectively function as the memory cell transistor (memory cell) MT.

[0086] Furthermore, a core layer 638a is embedded inside the semiconductor pillar 638. The upper surface of the core layer 638a is formed at a position in the D3 direction that is lower than the upper surface of the memory pillar 634 by a predetermined distance and higher than the upper surface of the wiring layer 632 at its highest position by a predetermined distance. The semiconductor pillar 638 is located on the core layer 638a. That is, the core layer 638a is surrounded by the semiconductor pillar 638 in the D1, D2, and D3 directions. The portion of the memory pillar 634 above the core layer 638a passes through the central axis of the semiconductor pillar 638, forming a slit SLS extending in the D2 direction. A select gate transistor ST1 is formed in this slit SLS.

[0087] Above the wiring layer 632, and more specifically between the uppermost surface of the wiring layer 632 and the upper surface of the memory pillar 634, a plurality of wiring layers 631 (second wirings) extending in the D2 direction are formed. The plurality of wiring layers 631, which function as select gate lines (SGD), are arranged at intervals in the D1 direction. The length of the wiring layer 631 in the D1 direction is shorter than the length of the semiconductor pillar 638 in the D1 direction. Furthermore, the length of the wiring layer 631 in the D3 direction is longer than the length of the wiring layer 631 in the D1 direction. The length of the wiring layer 631 in the D3 direction is set to a length corresponding to the critical characteristics required by the select gate transistor ST1, for example, to a thickness equivalent to 3 to 4 wirings 632 in the D3 direction. Each wiring layer 631 is arranged within a slit SLS of a plurality of memory pillars 634 disposed at the same position in the D1 direction. Figure 4A A gate insulating film 641 is formed on the surface of the semiconductor pillar 638 facing the wiring layer 631. A conductive layer (not shown) that serves as a barrier metal is formed between the wiring layer 631 and the gate insulating film 641. An insulating layer 642 is filled in the slit SLS located above the upper surface of the wiring layer 631.

[0088] In addition, such as Figure 5BAs shown, it can also be structured as follows: no semiconductor pillars 638 are provided on the core layer 638a, and the upper surface of the core layer 638a is directly connected to the lower surface of the gate insulating film 641. Figure 5B This is another cross-sectional view of a portion of a three-dimensional storage cell array.

[0089] The barrier insulating film 635, tunnel insulating film 637, gate insulating film 641, core layer 638a, and insulating layer 642 are formed, for example, from a silicon oxide film. The charge accumulation layer 636 is formed, for example, from a silicon nitride film.

[0090] A wiring layer 643 is disposed on a layer higher than the upper surface of the memory cylinder 634, separated by an insulating layer. The wiring layer 643, extending in the D1 direction, is formed in a strip shape, corresponding to the bit line BL. Multiple wiring layers 643 are arranged at intervals in the D2 direction. Figure 4A ).

[0091] A first contact plug 639 is provided at the upper end of the semiconductor pillar 638. A second contact plug 640 is then provided at the upper end of the first contact plug. The first contact plug 639 and the second contact plug 640 are formed of a conductive material such as tungsten, and electrically connect the semiconductor pillar 638 to the wiring layer 643. Specifically, the wiring layer 643 is electrically connected to the semiconductor pillar 638 of one memory pillar 634 corresponding to each string unit SU via the first contact plug 639 and the second contact plug 640. Furthermore, this configuration is not limited to this; the semiconductor pillar 638 within the memory pillar 634 and the wiring layer 643 may also be connected via multiple contacts or wiring.

[0092] (2. Manufacturing method)

[0093] Next, an example of the manufacturing method of the memory cell array 23 in this embodiment will be described. Figures 6-10 A top view of a memory cell array and a cross-sectional view (section A1-A2) along line A1-A2 are shown, illustrating an example of the manufacturing steps of the memory cell array according to the embodiment. Figures 6-10 The cross-sectional view shows the area above the second layer (WL6) from the top in wiring layer 632 and below the first contact plug 639.

[0094] The following describes a method for forming wiring layers 632 and 633, in which the sacrificial layer is used to form a structure equivalent to wiring layers 632 and 633, and then the sacrificial layer is removed and replaced with a conductive material (hereinafter referred to as "replacement").

[0095] First, on the semiconductor substrate 71, an insulating layer and four sacrificial layers corresponding to the wiring layer 633 are alternately deposited using CVD (Chemical Vapor Deposition). Next, an insulating layer 651 and eight sacrificial layers 632a corresponding to the wiring layer 632 are alternately deposited. The sacrificial layers 632a use a material with a high selectivity for the wet etching of the insulating layer 651. For example, if the insulating layer 651 is formed of a silicon oxide film, the sacrificial layer 632a uses a silicon nitride film.

[0096] Next, memory pillars (MPs) are formed. Specifically, first, a hard mask is formed on the upper surface of the top insulating layer 651, and then the hard mask for forming the memory pillar (MP) region is removed. That is, the hard mask is patterned such that only the insulating layer 651 of the region where the memory pillar (MP) is formed is exposed. Next, anisotropic etching is used to form a deep hole (via) that penetrates 12 sacrificial layers 632a and the insulating layer, and whose bottom surface reaches the semiconductor substrate 71, which serves as the source line. After removing the hard mask, a barrier insulating film 635, a charge accumulation layer 636, and a tunnel insulating film 637 are sequentially deposited.

[0097] Then, using anisotropic etching or similar methods, the uppermost insulating layer 651, the barrier insulating film 635, the charge accumulation layer 636, and the tunnel insulating film 637 on the bottom surface of the hole are removed, exposing the semiconductor substrate 71 on the bottom surface of the hole. After sequentially depositing a polysilicon film and a silicon oxide film across the entire surface using CVD or similar methods, a back-etching process is performed (anisotropic etching is used to etch the exposed portion on the upper surface without using a hard mask) to embed the semiconductor pillar 638 and the core layer 638a into the hole. Then, the core layer 638a within the hole is removed until it is a predetermined distance above the uppermost sacrificial layer 632a. After depositing a polysilicon film across the entire surface using CVD or similar methods, a back-etching process is performed to embed the semiconductor pillar 638 into the upper part of the hole.

[0098] In the portion of the semiconductor pillar 638 extending from the upper surface of the core layer 638a to a predetermined depth from the upper surface of the hole, p-type impurities (e.g., boron (B)) are implanted and diffused using ion implantation and diffusion techniques to form a p-type impurity layer 638_1. Then, in the portion of the semiconductor pillar 638 extending to a predetermined depth from the upper surface of the hole, n-type impurities (e.g., arsenic (As)) are implanted and diffused using ion implantation and diffusion techniques to form an n-type impurity layer 638_2. The p-type impurity layer 638_1 serves as the region for forming the channel of the select gate transistor ST1. The n-type impurity layer 638_2 reduces the connection resistance between the subsequently formed first contact plug 639 and the semiconductor pillar 638. Then, an insulating layer 651 is deposited over the entire upper surface using CVD or the like. By performing the above sequence, an... Figure 6 The structure shown.

[0099] Next, using CVD or similar methods, an etch stop layer 652, a bottom layer 653, and an insulating layer 654 are sequentially deposited across the entire surface. The etch stop layer 652 is formed from a film with a higher etch selectivity than the film forming the insulating layer 642 to be formed later. For example, if the insulating layer 642 is formed from a silicon oxide film, the etch stop layer 652 is formed from a silicon nitride film. The bottom layer 653 is formed, for example, from a carbon-containing film (SOC (Spin On Carbon) film, etc.). The insulating layer 654 is formed, for example, from an SOG (Spin On Glass) film. A hard mask 655 is formed on the upper surface of the insulating layer 654, and the hard mask 655 forming the slit SLS region is removed. That is, the hard mask 655 is patterned such that only the insulating layer 654 in the slit SLS formation region is exposed. By performing the above sequence, a slit SLS is formed. Figure 7 The structure shown.

[0100] Then, anisotropic etching is used to etch the insulating layer 654, the bottom layer 653, the etch stop layer 652, the insulating layer 651, and the semiconductor pillar 638 in the area where the hard mask 655 is not formed, to form a slit SLS. Then, the hard mask 655, the insulating layer 654, and the bottom layer 653 are removed sequentially by ashing or wet etching (isotropic etching using a solution, etc.). By performing the above sequence, a slit SLS is formed to embed the wiring layer 631, which serves as the gate of the select gate transistor ST1, thereby forming... Figure 8 The structure is shown. Furthermore, when the width of the slit SLS (in the D1 direction) is wider, the distance between the slit SLS in the D1 direction and the tunnel insulating film 637 becomes shorter, thus the depth of the channel region of the selected gate transistor ST1 becomes shallower. Additionally, when the width of the slit SLS is wider, the area of ​​the semiconductor pillar 638 exposed on the upper part of the memory pillar MP becomes smaller. In this case, the contact area between the semiconductor pillar 638 and the first contact plug 639 becomes smaller, which may lead to higher resistance or wire breakage. To prevent this, the width of the slit SLS is ideally formed to be the same as the width of the core layer 638a.

[0101] Because of the difference in etching rates between the insulating layer 651 and the semiconductor pillar 638, the bottom height of the slit SLS can sometimes differ between the memory pillar MP and other areas. Figures 11A to 11D This is a cross-sectional view illustrating an example of the machined shape of a slotted SLS, showing along... Figure 8 The cross section of line B1-B2 (cross section A1-A2). Figure 11A This illustrates a situation where the etching rate of the insulating layer 651 is higher than that of the semiconductor pillar 638. Figure 11B This illustrates a case where the etch rate of semiconductor pillar 638 is higher than that of insulating layer 651. Additionally, Figure 11C The use of Figure 11A The area above the second layer (WL6) from the top in the wiring layer 632 and below the first contact plug 639 in the memory cell array 23 manufactured by the structure shown. Figure 11D The use of Figure 11B The area above the second layer (WL6) from the top in the wiring layer 632 and below the first contact plug 639 in the memory cell array 23 manufactured by the structure shown.

[0102] When the etch rates of the insulating layer 651 and the semiconductor pillar 638 differ, such as Figure 11A , Figure 11B As shown, the bottom surface of a slit SLS can sometimes become uneven. Figure 11A In the shape shown, the upper surface of the semiconductor pillar 638 is higher than the upper surface of the insulating layer 651. Figure 11B In the shape shown, the upper surface of the semiconductor pillar 638 is lower than the upper surface of the insulating layer 651. Since the wiring layer 631, which functions as the select gate line SGD, is formed along the bottom surface of the slit SLS, the wiring layer 631 also forms irregularities in the height direction (D3 direction) when irregularities are formed on the bottom surface of the slit SLS. In this way, the lower surface of the wiring layer 631 in the D3 direction can also form an irregular shape.

[0103] Next, the polysilicon exposed on the inner wall of the slit SLS is oxidized by thermal oxidation or the like to form a gate oxide film 641. Alternatively, the gate oxide film 641 can also be formed by depositing a silicon oxide film using methods such as CVD. Then, after forming a conductive layer 656 (e.g., titanium nitride) as a barrier metal across the entire surface using sputtering or CVD, a conductive film (e.g., tungsten) serving as a wiring layer 631 is embedded into the slit SLS using CVD. The conductive film extending beyond a predetermined height from the bottom surface of the slit SLS is then etched using wet etching to form the wiring layer 631. An insulating layer 642 is formed across the entire upper surface using CVD or the like, and the insulating layer 642 is then filled into the slit SLS. By performing the above sequence, a [structure / component] is formed. Figure 9 The structure shown.

[0104] Figures 12A-12D This is a cross-sectional view illustrating an example of the fabricated shape of wiring layer 631, showing the result after wet etching and before embedding insulating layer 642. Figure 9 The area C1 is enclosed by a dashed line. Figure 12A This illustrates a case where the etching rate of the wiring layer 631 is higher than that of the conductive layer 656. Figure 12BThis illustrates a case where the etching rate of conductive layer 656 is higher than that of wiring layer 631. Figure 12C The use of Figure 12A The region above region C1 and below insulating layer 657 in the memory cell array 23 manufactured by the structure shown in the figure. Figure 12D The use of Figure 12B In the memory cell array 23 manufactured by the structure shown, the region is located above region C1 and below insulating layer 657. Due to the narrow width of the slit SLS, the wiring layer 631 may not be able to be formed flat when the conductive film is embedded as the wiring layer 631. That is, the wiring layer 631 may have a recess (groove) in the central part in the width direction (D1 direction).

[0105] In addition, Figure 12A In the shape shown, the upper surface of the conductive layer 656 is higher than the upper surface of the wiring layer 631. Figure 12B In the shape shown, the upper surface of the conductive layer 656 is lower than the upper surface of the wiring layer 631. In this case, a recess may be formed on the surface of the wiring layer 631, or there may be a height difference between the wiring layer 631 and the conductive layer 656, which serves as a barrier metal layer.

[0106] Then, using CMP (Chemical Mechanical Polishing), the insulating layer 642, located above the etch stop layer 652, is removed by grinding. In other words, the insulating layer 642 is embedded into the slits SLS using CMP, making the entire surface flat. After removing the etch stop layer 652 by wet etching or the like, a replacement operation is performed. Specifically, anisotropic etching is used to process the slits SL1 to SL3, whose bottom surface reaches the semiconductor substrate 71, at predetermined locations. Next, the sacrificial layer 632a is removed from the slits SL1 to SL3 by wet etching, forming voids. After embedding a conductive film (e.g., tungsten) into the voids, the conductive film formed within the slits SL1 to SL3 and on the uppermost insulating layer 651 is removed, forming wiring layers 632 and 633. Then, the insulating layer 645 is embedded into the slits SL1 to SL3. Thus, the replacement operation is completed, and wiring layer 633, which serves as the select gate line SGS, and wiring layer 622, which serves as the word line WL, are successfully formed.

[0107] Then, the first contact plug 639 is formed. First, an insulating layer 657 is deposited on the entire upper surface using CVD or the like. Then, a hard mask is formed on the upper surface of the insulating layer 657. Then, the hard mask in the area where the first contact plug 639 is formed is removed. That is, the hard mask is patterned so that only the insulating layer 657 in the area where the first contact plug 639 is formed is exposed. Then, the insulating layer 657 and the insulating layer 651 in the area where the hard mask is not formed are etched up to the upper surface of the memory cylinder MP by anisotropic etching, thereby forming a contact hole. After removing the hard mask by ashing or wet etching, a conductive film (e.g., tungsten) is embedded into the contact plug using CVD or the like. Finally, the conductive film formed on the uppermost insulating layer 657 is removed, thereby forming the first contact plug 639. By performing the above sequence, a first contact plug 639 is formed. Figure 10 The structure shown.

[0108] Then, after forming an insulating layer over the entire surface, a second contact plug 640 containing a conductive film is formed at a predetermined position on the first contact plug 639, and a wiring layer 643 is formed on top of the second contact plug 640, thereby forming the structure shown in FIG5.

[0109] Thus, according to this embodiment, a select gate line SGD is formed in such a way that it penetrates a semiconductor pillar 638 through a memory pillar MP. Specifically, the select gate line SGD includes multiple lines extending in a direction orthogonal to the bit line BL (D2 direction) and arranged in the D1 direction. Each select gate line SGD is configured to penetrate a memory pillar MP at an equal position in the D1 direction in the D2 direction.

[0110] For example, similar to word lines WL or select gate lines SGS, select gate lines SGD are sometimes formed by surrounding a cylindrical semiconductor pillar 638. In this case, the width of the select gate line SGD in the D1 direction is greater than the width of the semiconductor pillar 638 of the memory pillar MP in the D1 direction. Unlike select gate lines SGS or word lines WL, select gate lines SGD need to be separated for each string cell SU, with multiple select gate lines SGD configured on a single word line WL. Therefore, adjacent select gate lines SGD need to be spaced a certain distance from each other, which sometimes increases the area of ​​the memory cell array 23 in the D1 direction.

[0111] In this embodiment, since the select gate line SGD is formed as a semiconductor pillar 638 that penetrates the memory pillar MP, the width of the select gate line SGD in the D1 direction is smaller than the width of the semiconductor pillar 638 of the memory pillar MP in the D1 direction. Therefore, the distance between adjacent select gate lines SGD is sufficiently guaranteed, for example, preventing an increase in the chip area in the D1 direction.

[0112] Furthermore, according to this embodiment, a channel for the select gate transistor ST1 is formed in the semiconductor pillar 638 of the memory pillar MP. For example, after the select gate transistor ST2 and the memory transistor MT are formed in the memory pillar MP, a select gate transistor ST1 is formed above the memory pillar MP in advance according to each string cell SU, so that the channel forming region of the select gate transistor ST1 is in contact with the semiconductor pillar 638 of the memory pillar. In this case, the resistance of the contact connection portion may increase.

[0113] In this embodiment, the channels for the gate select transistor ST2, the memory transistor MT, and the gate select transistor ST1 are formed in the semiconductor pillar 638. Therefore, since there are no contact points between different semiconductor layers within the current path, resistance increase can be suppressed.

[0114] Furthermore, according to this embodiment, the select gate lines (SGDs) of the NAND strings included in the same string cell (SU) are configured such that they are connected to the same voltage supply line and supplied with the same voltage. In other words, according to this embodiment, the number of columns of memory pillars (MPs) included in one string cell (SU) can be arbitrarily set, increasing the design flexibility.

[0115] Furthermore, the semiconductor memory device of this embodiment is applicable regardless of the configuration of the memory cell array 23 and the peripheral circuits (components other than the memory cell array 23 constituting the non-volatile memory 2, such as the input / output circuit 22 or the logic control circuit 21). For example, it can be a structure in which the memory cell array 23 and the peripheral circuits are arranged horizontally side by side on the semiconductor substrate 71, or it can be a structure in which the peripheral circuits are formed on the semiconductor substrate 71 and the memory cell array 23 is formed above the peripheral circuits. Furthermore, it can also be a structure in which the memory cell array 23 and the peripheral circuits are formed on different chips and then bonded together.

[0116] Figure 13 This is a simplified cross-sectional view illustrating the structure of a semiconductor memory device formed by bonding array chips and circuit chips. For example... Figure 13As shown, the semiconductor memory device has a configuration in which an array chip 700 and a circuit chip 800 are bonded together. The array chip 700 has a memory cell array 23 and various wirings for connecting the memory cell array 23 and the circuit chip 800. The array chip 700 includes an array region and a peripheral region, and the memory cell array 23 is formed in the array region. As the memory cell array 23 formed in the array region, the memory cell array with the structure shown in FIG5 can be used. That is, the wiring layer 633 as the select gate line SGS and the wiring layer 632 as the word line WL are formed into a plate shape parallel to the surface of the semiconductor substrate 71. The plurality of wiring layers 631 as the select gate line SGD extend in a direction orthogonal to the extension direction (D1) of the wiring layer 643 as the bit line BL (D2 direction), and are arranged at predetermined intervals in the D1 direction. Each wiring layer 631 is formed such that it penetrates the memory pillar MP above the wiring layer 632. Wiring layer 643 is electrically connected to any bonding electrode 701 via a contact plug or other wiring layer. Bonding electrode 701 is used to connect to circuit chip 800.

[0117] The circuit chip 800 includes a logic control circuit 21, a sense amplifier 24, a line decoder 25, a register 26, a sequencer 27, a voltage generation circuit 28, etc. The gate, source, and drain electrodes of multiple transistors TR formed on the semiconductor substrate 81 are electrically connected to any of the bonding electrodes 801 via contact plugs or multiple wiring layers. The bonding electrode 801 is electrically connected to the opposite bonding electrode 701.

[0118] Multiple electrode pads PD are disposed on the upper surface of the circuit chip 800 in the D3 direction. The electrode pads PD are used to connect the semiconductor memory device 1 to external devices. The electrode pads PD are electrically connected to any of the bonding electrodes 801 via contact plugs or wiring layers. An insulating layer 82, which functions as a passivation film, is formed on the upper surface of the circuit chip 800 in the D3 direction. Openings corresponding to the electrode pads PD are provided in the insulating layer 82. For semiconductor memory devices with this bonding structure, by applying the above structure to the select gate line SGD of the NAND string, the increase in chip area and the increase in channel resistance of the NAND string can be suppressed.

[0119] Furthermore, such as Figure 14 As shown, the semiconductor memory device of the embodiment can also be applied to cases where the NAND string NS is formed by a two-layer structure. Figure 14 It is a cross-sectional view of a portion of a NAND string memory cell array containing two layers of structure.

[0120] The three-dimensional NAND memory cell array shown in Figure 5 can be formed by stacking a wiring layer 633 as the select gate line (SGS) and multiple wiring layers 632 as word lines, and then processing the memory pillar 634 in one step, while processing the wiring layer 631 as the select gate line (SGD) through the memory pillar 634. However, for example, in a three-dimensional NAND memory cell array with a large number of stacked layers, the aspect ratio becomes high when processing the memory pillar 634, and processing can sometimes become difficult. Therefore, sometimes the process of stacking the wiring layers 632 to form the memory pillar 634 is performed in multiple steps.

[0121] Here, a two-layer NAND string NS formed by stacking two wiring layers 632 and processing memory pillars 634 is used as an example for explanation. The two-layer NAND string NS has a structure in which a conductive layer 644, called a connector JT, is spaced between the lower layer (LT) and the upper layer (UT). That is, after stacking the wiring layer 633, which serves as the select gate line (SGS), and multiple wiring layers 632, which serve as part of the word lines, the memory pillars 634 are processed, and the wiring layer 631, which serves as the select gate line (SGD) for the lower layer, is processed through the memory pillars 634, thereby forming the lower layer LT. Then, after stacking the conductive layer 644, which serves as the connector JT, the remaining multiple wiring layers 633, which serve as word lines, are stacked, and then the memory pillars 634 are processed, and the wiring layer 631, which serves as the select gate line (SGD) for the upper layer, is processed through the memory pillars 634, thereby forming the upper layer UT. In this way, the above structure can also be applied to the select gate lines SGD in each layer of a two-layer NAND string NS. Furthermore, the conductive layer 644, which serves as the connector JT, can be omitted, allowing the lower layer LT and the upper layer UT to be directly connected.

[0122] The embodiments of the present invention described above are shown as examples and are not intended to limit the scope of the invention. This novel embodiment can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention and are included within the scope of the claims and their equivalents.

[0123] [Explanation of Symbols]

[0124] 1. Memory controller

[0125] 2. Non-volatile memory

[0126] 11 RAM

[0127] 12 processors

[0128] 13 Host Interface

[0129] 14 ECC Circuit

[0130] 15. Memory Interface

[0131] 16 Internal Bus

[0132] 21 Logic Control Circuit

[0133] 22 Input / Output Circuit

[0134] 23-cell storage array

[0135] 24 Sensing Amplifier

[0136] 24A Data Register

[0137] 24B Sensing Amplifier Unit Group

[0138] 25-line decoder

[0139] 26 Registers

[0140] 27 Sequencer

[0141] 28 Voltage Generation Circuit

[0142] 32 Input / Output Pads

[0143] 33 pads

[0144] 34 Logic Control Pads

[0145] 35 Power input terminal blocks

[0146] 71,81 Semiconductor substrates

[0147] 631, 632, 633, 643 Wiring layers

[0148] 632a Sacrificial Layer

[0149] 634 memory cylinders

[0150] 635 Barrier Insulating Film

[0151] 636 Charge Accumulation Layer

[0152] 637, 641 Gate insulating film

[0153] 638 Semiconductor Pillar

[0154] 638a Core Layer

[0155] 638_1 p-type impurity layer

[0156] 638_2 n-type impurity layer

[0157] 639 First Contact Plug

[0158] 640 Second Contact Plug

[0159] 82,642,651,654,657 Insulation layer

[0160] 644, 656 Conductive layer

[0161] 652 Etching stop layer

[0162] 653 Bottom Layer

[0163] 655 Hard Mask

[0164] 700 array chips

[0165] 701, 801 bonding electrodes

[0166] 800 circuit chip.

Claims

1. A semiconductor memory device comprising: Multiple first wirings are arranged above a first direction orthogonal to the semiconductor substrate; A memory column that extends through the plurality of first wirings in the first direction; A semiconductor layer is disposed inside the memory pillar and extends in the first direction; The second wiring extends in a second direction orthogonal to the first direction, is disposed above the first direction than the plurality of first wirings, penetrates the semiconductor layer, and is a conductive film, functioning as a select gate line; and A gate insulating film is disposed between the second wiring and the semiconductor layer.

2. The semiconductor memory device according to claim 1, comprising a plurality of memory pillars arranged in the second direction, wherein the second wiring passes through the plurality of memory pillars.

3. The semiconductor memory device of claim 1, wherein in a cross section orthogonal to the second direction, the length of the second wiring in the first direction is longer than the length of the second wiring in a third direction orthogonal to both the first and second directions.

4. The semiconductor memory device of claim 1, having a plurality of wiring groups comprising a plurality of the second wirings, wherein the second wirings belonging to the same wiring group are supplied with the same voltage.

5. A method for manufacturing a semiconductor memory device, comprising the following steps: Multiple first wirings in the form of plates are formed on a semiconductor substrate; A deep hole is formed in a first direction orthogonal to the semiconductor substrate, penetrating the plurality of first wirings; A semiconductor layer extending in the first direction is embedded into the interior of the deep hole; A second wiring is formed, which penetrates the semiconductor layer above the plurality of first wirings and extends in a second direction orthogonal to the first direction, and the second wiring is a conductive film that functions as a select gate line; and A gate insulating film is formed between the second wiring and the semiconductor layer.

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