Bipolar dual-gate regulated electrolyte neuromorphic device and preparation method thereof

Abstract

This invention belongs to the field of semiconductor technology and discloses a bipolar dual-gate controlled electrolyte neuromorphic device and its fabrication method. The bipolar dual-gate controlled neuromorphic device comprises, from bottom to top, a substrate, an electrolyte layer, an organic interface modification layer, an organic semiconductor layer, a gate, a source, and a drain. The organic semiconductor layer includes a p-type semiconductor layer and an n-type semiconductor layer, each divided into two parts formed directly above the organic interface modification layer. The semiconductor layer below the source and drain electrodes serves as the channel layer, and the semiconductor layer below the gate serves as the floating gate layer, with gaps between the p-type and n-type semiconductor layers. The source and drain are connected by a bridge structure, and the gate is located on the same plane as the source and drain. This neuromorphic device can achieve bipolar control of the channel current, and the control method based on the dual-planar gate structure can greatly enrich the device's functionality. Therefore, this bipolar dual-gate controlled electrolyte neuromorphic device is expected to be widely used in neuromorphic chips.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a bipolar dual-gate regulated electrolyte neuromorphic device and its fabrication method. Background Technology

[0002] With the development of the information age and the internet, the emerging fields of the Internet of Things (IoT) and artificial intelligence have attracted widespread attention from the academic community. To realize their complex functions, more diverse electronic hardware is required as support. Currently, in order to improve the diversity of functions, electronic hardware needs to design more complex circuits. However, this approach inadvertently increases the complexity of the circuits, which is not conducive to the integration of electronic components, and the hardware design and manufacturing costs will also increase accordingly.

[0003] Therefore, with the increasing demand for smaller hardware and the trend towards multifunctionality, the integration of multifunctional components into electronic hardware will become a future development trend. Transistors have revolutionized electronic devices due to their low cost and high flexibility, making them smaller, more efficient, and cheaper. Organic field-effect transistors, with their stable electrical performance, low cost, small device structure, and compatibility with flexible substrates, have become a current research hotspot.

[0004] Organic field-effect transistors (FETs) can be classified into p-type transistors, n-type transistors, and bipolar transistors (BJTs) according to their charge transport type. P-type and n-type transistors can only transport one type of charge, while BJTs can transport both electrons and holes simultaneously. In other words, a BJT is essentially a combination of p-type and n-type transistors integrated into a single device. Generally, unipolar transistors have limited functionality. To achieve multifunctional electronic devices, higher integration and more complex circuit structures are required, which is detrimental to device integration. Bipolar transistors, due to their versatility, can greatly simplify the integration of electronic hardware. For example, the ability of BJTs to transport two types of charge simultaneously simplifies the fabrication of complementary metal-oxide-semiconductor (CMOS) inverters. Furthermore, due to the similarity between the flow of neurotransmitters in the synaptic cleft and the action transport and capture operations of charge carriers, BJTs also hold great potential in artificial synaptic simulation and neuromorphic computing in artificial intelligence. In the past few years, research on bipolar transistor-type neuromorphic devices has focused on which materials can be used to achieve bipolar charge transport, while there has been little research on achieving bipolar modulation functions through device structure design. Therefore, it is of great significance to study electrolyte neuromorphic devices with bipolar modulation functions through device structure design.

[0005] In view of this, the present invention provides a bipolar dual-gate regulated electrolyte neuromorphic device and its fabrication method.

[0006] Based on the above analysis, the problems and shortcomings of the existing technology are as follows:

[0007] In the past few years, research on bipolar transistor-type neuromorphic devices has focused on what materials can be used to achieve bipolar charge transport, while there has been little research on achieving bipolar modulation functions through device structure. Summary of the Invention

[0008] To address the aforementioned technical problems of existing transistor-type neuromorphic devices, this invention proposes a bipolar dual-gate regulated electrolyte neuromorphic device and its fabrication method. By utilizing a bridge-structured source-drain electrode to integrate p-type and n-type semiconductors in the same transistor, bipolar electron and hole transport is achieved. A dual-planar gate structure is employed to enable flexible control of the channel current.

[0009] The present invention is implemented as follows: a bipolar dual-gate controlled electrolyte neuromorphic device, wherein the device is capable of bipolar charge transfer by adding n-type semiconductors and p-type semiconductors in the same transistor device and using a bridge design of source and drain to achieve bipolar control of electrons and holes by the transistor.

[0010] Furthermore, the device includes a source, a drain, a gate, an organic semiconductor layer, an organic interface modification layer, an electrolyte layer, and a substrate; the electrolyte layer is located directly above the substrate, the organic interface modification layer is located directly above the electrolyte layer, the organic semiconductor layer is located directly above the organic interface modification layer, and the gate, source, and drain are located directly above the organic semiconductor layer.

[0011] Furthermore, the main material of the electrolyte layer is chitosan, which is used to form an electric bilayer effect to regulate the charge density of the organic semiconductor layer.

[0012] Furthermore, the organic interface modification layer is polystyrene (PS), which is used to modify the interface of the electrolyte layer and help the organic semiconductor layer form a better crystalline state.

[0013] Furthermore, the organic semiconductor layer is a p-type semiconductor pentacene and an n-type semiconductor perfluorophthalocyanine copper (F16CuPc). The pentacene and perfluorophthalocyanine copper are formed in parallel directly above the organic interface modification layer. The semiconductor located below the source and drain electrodes serves as the channel layer, and the semiconductor located below the gate serves as the floating gate layer. A gap is left between the pentacene and perfluorophthalocyanine copper.

[0014] Furthermore, the gate, source, and drain are made of metallic copper. The gate is formed directly above the left side of the pentacene and perfluorocyanide copper, and the source and drain are connected by a bridge structure and formed directly above the right side of the pentacene and perfluorocyanide copper. The gate, source, and drain are on the same plane.

[0015] Furthermore, the substrate material is a single-polished silicon wafer containing a 50nm silicon oxide layer.

[0016] Furthermore, the organic interface modification layer and electrolyte layer are prepared by spin coating, and the organic semiconductor layer, source, drain, and gate are prepared by vacuum evaporation.

[0017] The present invention provides a method for fabricating a bipolar dual-gate regulated electrolyte neuromorphic device, comprising the following steps:

[0018] Step 1: Prepare polystyrene solution and chitosan solution with concentrations of 0.003 g / ml and 0.02 g / ml, respectively.

[0019] Step 2: Using a 50nm single-polished silicon oxide wafer as the device substrate, first place it in an ultrasonic cleaner for 1 hour. After cleaning, rinse it repeatedly with ethanol to ensure the surface is clean. Then, blow it dry with nitrogen and dry it in a forced-air drying oven for 30 minutes.

[0020] Step 3: First, spin-coat the sample treated in Step 2 with chitosan solution at a spin rate of 6000 r / min for 30 s. The chitosan solution should be filtered before spin-coating. After spin-coating, anneal at 110℃ for 8-10 min. Then, spin-coat the sample with polystyrene solution at a spin rate of 3000 r / min for 30 s. After spin-coating, anneal at 110℃ for 8-10 min.

[0021] Step 4: Sequentially deposit the following semiconductor layers in the sample processed in Step 3: a pentylene semiconductor layer, a copper perfluorocyanide semiconductor layer, a gate, a source, and a drain. The thickness of the semiconductor layer is controlled to be 30 nm, and the thickness of the gate, source, and drain is controlled to be 50 nm.

[0022] Step 5: Perform transistor electrical performance testing on the sample processed in Step 4.

[0023] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0024] First, addressing the technical problems existing in the prior art and the difficulty in solving them, this paper closely analyzes, in conjunction with the technical solution to be protected by this invention and the results and data obtained during the research and development process, how the technical solution of this invention solves the technical problems, and the inventive technical effects brought about by solving these problems. The specific description is as follows:

[0025] Most organic field-effect transistors (OFETs) currently employ only one charge mechanism, meaning each device can only transport one type of charge. This unipolar nature hinders the development of multifunctional and miniaturized electronic devices. Therefore, research on bipolar devices is crucial, but current research on bipolar transistor-based neuromorphic devices is limited. This invention proposes a device capable of bipolar charge transport. By integrating n-type and p-type semiconductors into the same transistor device and utilizing a bridge structure design between the source and drain, the transistor achieves bipolar control of electrons and holes. Test data shows that when the gate voltage is between 0 and -50V, the transport layer primarily transports holes; when the gate voltage is between 0 and 50V, the transport layer primarily transports electrons. This achieves two types of charge transport within a single device, effectively integrating both n-type and p-type transistors. Such a bipolar control device is highly advantageous for electronic hardware integration, significantly reducing the integration density and circuit design complexity of electronic devices. Furthermore, it can reduce the design and manufacturing costs of electronic devices.

[0026] Furthermore, the neuromorphic device of this invention adopts a dual floating gate structure. By applying a voltage to one of the gates, bipolar modulation can be achieved. The two floating gates combined together can achieve flexible and varied modulation methods. The flexible modulation method combined with the bipolar charge transport characteristics can achieve more complex functions than unipolar transistors. This multifunctional device is expected to be widely used in integrated circuits, promoting the development of integrated circuits towards multifunctionality, low integration, and low cost.

[0027] Finally, the device structure provided by this invention is simple, the fabrication method is compatible with current organic field-effect transistors, and the process is simple and easy to operate.

[0028] Second, considering the technical solution as a whole or from a product perspective, the technical effects and advantages of the technical solution to be protected by this invention are specifically described as follows:

[0029] This invention proposes a bipolar dual-gate regulated electrolyte neuromorphic device and its fabrication method. It utilizes a bridge structure to connect the source and drain electrodes, integrating p-type and n-type semiconductors in the same transistor to achieve bipolar charge transport of electrons and holes. It also employs a dual-plane floating gate structure to achieve flexible control of the channel current.

[0030] Compared to traditional unipolar control devices, this bipolar dual-gate neuromorphic device can achieve more complex functions, thus reducing device integration and design complexity, which is conducive to the development of electronic devices towards multifunctionality and small size.

[0031] Third, as supplementary evidence of the inventive step of the claims of this invention, it is also reflected in the following important aspects:

[0032] (1) The expected benefits and commercial value of the technical solution of this invention after transformation are as follows:

[0033] Bipolar dual-gate control devices enable simultaneous electron and hole transport and employ a dual-plane floating gate structure, allowing for more flexible control of electrical performance. Therefore, this device simplifies the fabrication of logic elements and reduces manufacturing costs. Furthermore, bipolar dual-gate control devices can achieve more complex functions, thus significantly reducing the integration density of integrated circuits and consequently lowering both design and manufacturing costs.

[0034] (2) The technical solution of this invention fills a technical gap in the industry both domestically and internationally:

[0035] This invention integrates n-type and p-type semiconductors into the same device and designs the source and drain electrodes into a novel dual-bridge structure to connect the two semiconductors. This allows for bipolar control of electrons and holes through the device's structural design. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of a bipolar dual-gate regulated electrolyte neuromorphic device provided in an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the structure of the p-type semiconductor electrolyte neuromorphic device provided in an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the structure of the n-type semiconductor electrolyte neuromorphic device provided in an embodiment of the present invention;

[0039] Figure 4 This is a transfer characteristic curve of the p-type semiconductor electrolyte neuromorphic device provided in the embodiments of the present invention;

[0040] Figure 5 This is a transfer characteristic curve of the n-type semiconductor electrolyte neuromorphic device provided in the embodiments of the present invention;

[0041] Figure 6 This is a transfer characteristic curve of a bipolar dual-gate modulated electrolyte neuromorphic device provided in an embodiment of the present invention, which applies a voltage to a p-type semiconductor gate.

[0042] Figure 7 This is a transfer characteristic curve of a bipolar dual-gate modulated electrolyte neuromorphic device provided in an embodiment of the present invention, which applies a voltage to an n-type semiconductor gate. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0044] This invention fabricates n-type and p-type semiconductor materials on a single field-effect transistor, designs a bridge-type source-drain electrode structure on the two semiconductor layers to enable bipolar modulation of the device, and designs a dual floating gate planar structure to diversify the modulation methods.

[0045] The technical solution provided by this invention is as follows: The bipolar dual-gate controlled electrolyte neuromorphic device comprises, from bottom to top: a substrate; a chitosan electrolyte layer formed on the substrate; an organic interface modification layer formed on the chitosan electrolyte layer; an organic semiconductor layer including a p-type semiconductor layer and an n-type semiconductor layer, the organic semiconductor layer being divided into two parts formed directly above the organic interface modification layer, the semiconductor layer below the source and drain electrodes serving as a channel layer, the semiconductor layer below the gate serving as a floating gate layer, and the p-type and n-type semiconductor layers each having a gap; the source and drain electrodes are formed in a bridge structure directly above the semiconductor layer, and the gate electrode is located on the same plane as the source and drain electrodes.

[0046] The above technical solution achieves bipolar modulation of organic field-effect transistors, namely: by applying a positive gate voltage to the gate, the n-type semiconductor plays a dominant role, and the transistor device mainly transports electrons; by applying a negative gate voltage to the gate, the p-type semiconductor plays a dominant role, and the transistor device mainly transports holes.

[0047] To enable those skilled in the art to fully understand how the present invention is specifically implemented, this section provides an explanatory description of the embodiments that expand upon the technical solutions of the claims.

[0048] Reference Figure 1 As shown, this invention provides a bipolar dual-gate controlled electrolyte neuromorphic device and its fabrication method. The device structure, from bottom to top, includes: a substrate; an electrolyte layer formed on the substrate; an organic interface modification layer formed on the electrolyte layer; an organic semiconductor layer formed on the organic interface modification layer; and a gate, a source, and a drain formed on the organic semiconductor. Specifically, the organic semiconductor layer includes a p-type semiconductor layer and an n-type semiconductor layer, each divided into two parts formed directly above the organic interface modification layer. The semiconductor layer below the source and drain electrodes serves as a channel layer, and the semiconductor layer below the gate serves as a floating gate layer. A gap is left between the p-type and n-type semiconductor layers. The source and drain are connected by a bridge structure, and the gate is located on the same plane as the source and drain electrodes.

[0049] This invention provides a method for fabricating a bipolar dual-gate regulated electrolyte neuromorphic device, comprising the following steps:

[0050] Step 1: Prepare polystyrene solution and chitosan solution with concentrations of 0.003 g / ml and 0.02 g / ml, respectively.

[0051] Step 2: Using a 50nm single-polished silicon oxide wafer as the device substrate, first place it in an ultrasonic cleaner for 1 hour. After cleaning, rinse it repeatedly with ethanol to ensure the surface is clean, then blow it dry with nitrogen and dry it in a forced-air drying oven for 30 minutes.

[0052] Step 3: First, spin-coat the sample treated in Step 2 with chitosan solution at a spin rate of 6000 r / min for 30 s. The chitosan solution should be filtered before spin-coating. After spin-coating, anneal at 110℃ for 8-10 min. Then, spin-coat the sample with polystyrene solution at a spin rate of 3000 r / min for 30 s. After spin-coating, anneal at 110℃ for 8-10 min.

[0053] Step 4: Sequentially deposit a pentaphenyl semiconductor layer, a perfluorocyanide copper semiconductor layer, a gate, a source, and a drain on the sample processed in Step 3. The thickness of the semiconductor layer is controlled to be 30 nm, and the thickness of the gate, source, and drain is controlled to be 50 nm.

[0054] Step 5: Perform transistor electrical performance testing on the sample processed in Step 4.

[0055] To demonstrate the inventiveness and technical value of the technical solution of this invention, this section provides specific product or related technology application examples of the technical solution claimed.

[0056] The bipolar dual-gate control function demonstrated by the test results of the embodiments of the present invention is expected to enable the application of this technical solution in a variety of products.

[0057] I. Electronic logic elements: Bipolar dual-gate controlled neuromorphic devices can achieve more diverse functions, making the manufacturing of many electronic logic elements simpler and thus reducing the manufacturing cost of electronic logic elements.

[0058] II. Biomimetic Synapses: Depending on the application scenarios and functions, biomimetic synapses have a wide range of applications. Bipolar transistors have a higher similarity to the charge transport of biological synapses, so bipolar transistors are more suitable for application in biomimetic synapses than unipolar transistors.

[0059] It should be noted that embodiments of the present invention can be implemented in hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the above-described devices and methods can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a carrier medium such as a disk, CD, or DVD-ROM, a programmable memory such as read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuitry such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field-programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of the above-described hardware circuitry and software, such as firmware.

[0060] The embodiments of the present invention have achieved some positive results during the research and development or use process, and have indeed great advantages compared with the prior art. The following content describes them in conjunction with the data, charts and other information of the experimental process.

[0061] In this invention, a single-layer polished silicon oxide wafer with an oxide layer thickness of 50 nm is used as the substrate; a chitosan solution is used as the electrolyte layer; a polystyrene solution is used as the organic interface modification layer; pentane is used as the p-type organic semiconductor layer; perfluorocyanate copper is used as the n-type organic semiconductor layer; and metallic copper is used as the forming material for the gate, source, and drain.

[0062] The specific fabrication steps of the device described in this embodiment are as follows:

[0063] Step (1): Prepare chitosan solution, take 0.04g of acetic acid and 0.04g of chitosan, add them to 2ml of ultrapure water, and sonicate for 4h; prepare polystyrene solution, take 0.003g of polystyrene, add it to 1ml of ultrapure water, and stir with a magnetic stirrer for 30min.

[0064] Step (2): Cut the single-layer polished silicon oxide wafer with an oxide layer thickness of 50nm into a substrate of 2cm×2cm. Then, clean it with decon solution and deionized water for 30min each. After cleaning, rinse it repeatedly with anhydrous ethanol to ensure that the surface is clean. Then, blow it dry with high-purity nitrogen. Place the dried sample into a forced-air drying oven and dry it at 80℃ for 30min.

[0065] Step (3): Filter the chitosan solution prepared in step (1) and then spin-coat it onto the sample prepared in step (2). The spin-coating rate is controlled at 6000 r / min and the spin-coating time is 30 s. After spin-coating, observe the film quality on the silicon wafer surface. If the film quality is poor, spin-coating should be performed again. The successfully spin-coated sample is annealed at 110℃ for 8-10 min.

[0066] Step (4): Spin-coat the sample treated in step (3) with polystyrene solution. The spin-coating rate is controlled at 3000 r / min and the spin-coating time is 30 s. After spin-coating, anneal at 110℃ for 8 to 10 min.

[0067] Step (5): Perform vacuum evaporation on the sample processed in step (4). First, deposit a p-type semiconductor layer through a mask using an organic evaporation source. The p-type semiconductor material is pentacene. Rotate the substrate during the evaporation process. Control the film thickness to 30 nm and the evaporation rate to [missing value]. Vacuum degree controlled at 5×10 -4 Below Pa; then, an n-type semiconductor layer is deposited through a mask using an organic evaporation source. The n-type semiconductor material is perfluorocyanate copper. The substrate is rotated during the evaporation process, the film thickness is controlled at 30 nm, and the evaporation rate is controlled at [value missing]. Vacuum degree controlled at 5×10 -4 Below Pa; then, the gate, source, and drain electrodes are vacuum-deposited using a mask, employing a metal evaporation source and copper as the deposition material. The substrate is not rotated during the deposition process, the film thickness is controlled to 50 nm, and the deposition rate is controlled to [value missing]. Vacuum degree controlled at 5×10 -4 Below Pa.

[0068] To better illustrate the charge regulation characteristics of the bipolar dual-gate controlled transistor, p-type semiconductor electrolyte neuromorphic devices and n-type semiconductor electrolyte neuromorphic devices were also fabricated in this embodiment of the invention. The fabrication steps of the above-mentioned bipolar dual-gate controlled electrolyte neuromorphic device, excluding the vacuum deposition of the n-type semiconductor layer, and only involving the deposition of a single gate on the semiconductor layer, constitute the fabrication process of the p-type semiconductor electrolyte neuromorphic device. The device structure is as follows... Figure 2 As shown; the fabrication steps of the above-mentioned bipolar dual-gate controlled electrolyte neuromorphic device, excluding the vacuum evaporation of the p-type semiconductor layer, and only depositing one gate on the semiconductor layer, constitute the fabrication process of the n-type semiconductor electrolyte neuromorphic device. The device structure is as follows. Figure 3 As shown.

[0069] Step (6): After the aforementioned steps are completed, the electrical performance of the device in this embodiment is characterized using a Keithley 2636B semiconductor analyzer. The characterization results are as follows: Figure 4-7 As shown.

[0070] Figure 4 The figure shows the transfer characteristic curve of a pentacene semiconductor transistor. When the gate voltage is swept from 0V to -50V, the current increases significantly, while the current is very small in the positive gate voltage region, which is a clear characteristic of a p-type transistor. This indicates that the transistor semiconductor layer mainly transports holes. Figure 5 The figure shows the transfer characteristic curve of the perfluorocyano copper transistor. When the gate voltage is swept from 0V to 50V, the current increases significantly, while the current is very small in the negative gate voltage region. This is a clear characteristic of an n-type transistor, indicating that the semiconductor layer of the transistor is mainly used for electron transport. Figure 6-7 It is the transfer characteristic curve of a bipolar transistor, such as... Figure 6 As shown, with pentacene as the floating gate layer, the current increases significantly when the gate voltage is swept from 0V to 50V or from 0V to -50V. Figure 7 As shown, with copper perfluorocyanate as the floating gate layer, when the gate voltage is swept from 0V to 50V or from 0V to -50V, the channel current also shows a significant increase, indicating that the bipolar transistor of the present invention can simultaneously transport electrons and holes.

[0071] All test results show that by simultaneously adding an n-type semiconductor layer and a p-type semiconductor layer to an electrolyte neuromorphic device, and then utilizing a bridge structure design of the source and drain, the present invention can achieve bipolar modulation of electrons and holes in a single transistor device. This bipolar modulation neuromorphic device can reduce the integration density of electronic hardware, which is conducive to the development of multifunctional electronic hardware. At the same time, the present invention adopts a dual-gate structure, and the bipolar modulation can be achieved by applying a gate voltage to either a pentene floating gate layer or a perfluorocyanide copper floating gate layer. This dual-gate structure is beneficial for enabling neuromorphic devices to achieve flexible and diverse modulation methods.

[0072] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A bipolar dual-gate regulated electrolyte neuromorphic device, characterized in that, The device is capable of bipolar charge transfer. By adding n-type and p-type semiconductors to the same crystalline neuromorphic device, the device achieves bipolar control of electrons and holes through a bridge structure design of the source and drain. The device includes a source, a drain, a gate, an organic semiconductor layer, an organic interface modification layer, an electrolyte layer, and a substrate; the electrolyte layer is located directly above the substrate, the organic interface modification layer is located directly above the electrolyte layer, the organic semiconductor layer is located directly above the organic interface modification layer, and the gate, source, and drain are located directly above the organic semiconductor layer. The organic semiconductor layer is pentacene and copper perfluorocyanide. The pentacene and copper perfluorocyanide are formed in parallel above the organic interface modification layer. The semiconductor below the source and drain electrodes serves as the channel layer, and the semiconductor below the gate serves as the floating gate layer. A gap is left between the pentacene and copper perfluorocyanide. The gate, source, and drain are made of metallic copper. The gate is formed directly above the left side of the pentacene and perfluorocyanide copper. The source and drain are connected by a bridge structure and formed directly above the right side of the pentacene and perfluorocyanide copper. The gate, source, and drain are on the same plane.

2. The bipolar dual-gate regulated electrolyte neuromorphic device according to claim 1, characterized in that, The main material of the electrolyte layer is chitosan, which is used to form an electric bilayer effect to regulate the charge density of the organic semiconductor layer.

3. The bipolar dual-gate regulated electrolyte neuromorphic device according to claim 1, characterized in that, The organic interface modification layer is polystyrene, which is used to modify the interface of the electrolyte layer and induce the organic semiconductor layer to form a better crystalline state.

4. The bipolar dual-gate regulated electrolyte neuromorphic device according to claim 1, characterized in that, The substrate material is a single-layer polished silicon wafer containing a 50nm silicon oxide layer.

5. The bipolar dual-gate regulated electrolyte neuromorphic device according to claim 1, characterized in that, The organic interface modification layer and electrolyte layer are prepared by spin coating, and the organic semiconductor layer, source, drain and gate are prepared by vacuum evaporation.

6. A method for fabricating a bipolar dual-gate regulated electrolyte neuromorphic device, characterized in that, Includes the following steps: Step 1: Prepare polystyrene solution and chitosan solution with concentrations of 0.003 g / ml and 0.02 g / ml, respectively; Step 2: Using a 50nm single-polished silicon oxide wafer as the device substrate, first place it in an ultrasonic cleaner for 1 hour, then rinse it repeatedly with ethanol to ensure the surface is clean, then blow it dry with nitrogen and dry it in a forced-air drying oven for 30 minutes. Step 3: First, spin-coat the sample treated in Step 2 with chitosan solution at a spin rate of 6000 r / min for 30 s. The chitosan solution should be filtered before spin-coating. After spin-coating, anneal at 110℃ for 8-10 min. Then, spin-coat the sample with polystyrene solution at a spin rate of 3000 r / min for 30 s. After spin-coating, anneal at 110℃ for 8-10 min as an interface modification layer. Step 4: Sequentially deposit a pentaphenyl semiconductor layer, a perfluorocyanide copper semiconductor layer, a gate, a source, and a drain on the sample processed in Step 3. The thickness of the semiconductor layer is controlled to be 30nm, and the thickness of the gate, source, and drain is controlled to be 50nm. Step 5: Perform transistor electrical performance testing on the sample processed in Step 4.

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