Display panel and display device

Abstract

A display panel has a main display area and a sub-display area, the main display area surrounds at least part of the sub-display area, the light transmittance of the main display area is less than that of the sub-display area; the display panel comprises a plurality of first pixel circuits in the sub-display area, the plurality of first pixel circuits are arranged in multiple rows and multiple columns, each row of first pixels is arranged along a first direction, and each column of first pixel circuits is arranged along a second direction; the first direction and the second direction intersect; the display panel comprises a substrate, a first gate conductive layer on the substrate, the first pixel circuit comprises a gate pattern on the first gate conductive layer, a first light-transmitting conductive layer on the first gate conductive layer and located in the sub-display area, the first light-transmitting conductive layer comprises a first type of signal line extending along the first direction; wherein the gate patterns of each first pixel circuit in the same row are electrically connected to the first type of signal line through a first via.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of display technology, full display with camera (FDC) has been gradually applied to display products due to its advantage of a large screen-to-body ratio. Full-screen display devices typically place optical components such as cameras under the display panel, greatly improving the screen-to-body ratio. Summary of the Invention

[0003] On one hand, a display panel is provided, including a main display area and a sub-display area, wherein the main display area surrounds at least a portion of the sub-display area, and the light transmittance of the main display area is less than that of the sub-display area. The display panel includes a plurality of first pixel circuits located in the sub-display area, the plurality of first pixel circuits being arranged in multiple rows and columns, with each row of first pixels arranged along a first direction and each column of first pixel circuits arranged along a second direction; the first direction and the second direction intersect. The display panel includes: a first conductive layer located on a substrate, the plurality of first pixel circuits including conductive patterns located on the first conductive layer; and a first signal line layer located on the side of the first conductive layer away from the substrate and located in the sub-display area, the first signal line layer including first type of signal lines extending along the first direction. Wherein, the conductive patterns of each first pixel circuit located in the same row along the first direction are electrically connected to the first type of signal lines through a first via, the first via being located on the side of the first pixel circuit along the first direction.

[0004] In some embodiments, each of the first pixel circuits is electrically connected to the first type of signal line through a first via, and the first vias of different first pixel circuits are all located on the same side of the first pixel circuit.

[0005] In some embodiments, the first conductive layer is a first gate conductive layer, the conductive pattern is a gate pattern, and the first signal line layer is a first transparent conductive layer.

[0006] In some embodiments, the first gate conductive layer includes a first via connection portion electrically connected to the gate pattern, the first via exposing the first via connection portion; the gate pattern is electrically connected to the first type of signal line through the first via connection portion. The first via connection portion is located on a side outside the area occupied by the first pixel circuit, or within the area occupied by the first pixel circuit.

[0007] In some embodiments, the first pixel circuit includes a plurality of gate patterns, which are arranged in multiple columns along the first direction and in multiple rows along the second direction. Each row of gate patterns includes at least two gate patterns, which are electrically connected to the same first type of signal line via the same first via connection portion.

[0008] In some embodiments, the at least two gate patterns are integrally formed; and / or, the at least two gate patterns and the first via connection portion electrically connected to the at least two gate patterns are integrally formed.

[0009] In some embodiments, the first type of signal line includes at least one of a gate line, a reset signal line, and an enable signal line.

[0010] In some embodiments, the first type of signal lines are located on the same layer in the sub-display area and are continuous traces, and the orthographic projection of the first type of signal lines on the substrate overlaps with the orthographic projection of at least one of the plurality of first pixel circuits on the substrate.

[0011] In some embodiments, the display panel further includes a plurality of second pixel circuits located in the main display area; the first gate conductive layer further includes a second type of signal line located in the main display area; the second type of signal line extends along the first direction and is electrically connected to at least a portion of the plurality of second pixel circuits; the first type of signal line and the second type of signal line transmitting the same electrical signal are electrically connected.

[0012] In some embodiments, the display panel further includes: a semiconductor layer located on the side of the first conductive layer near the substrate; and a second light-transmitting conductive layer located on the side of the first light-transmitting conductive layer away from the substrate and located in the sub-display area, the second light-transmitting conductive layer including: a fourth type of signal line extending along the second direction; the first pixel circuit further includes a third active pattern located on the semiconductor layer; wherein the third active patterns of each first pixel circuit located in the same column are electrically connected to the fourth type of signal line through a third via, the third via being located on one side of the first pixel circuit along the second direction.

[0013] In some embodiments, each of the first pixel circuits is electrically connected to the fourth type of signal line through a third via, and the third vias of different first pixel circuits are all located on the same side of the first pixel circuit.

[0014] In some embodiments, the fourth type of signal line is located on the same layer in the sub-display area and is a continuous trace, and the orthographic projection of the fourth type of signal line on the substrate overlaps with the orthographic projection of at least one of the plurality of first pixel circuits on the substrate.

[0015] In some embodiments, the semiconductor layer includes a third via connection to the third active pattern, the third via exposing the third via connection, and the third active pattern being electrically connected to the fourth type of signal line through the third via connection; wherein the third via connection is located on the side outside the area occupied by the first pixel circuit, or located within the area occupied by the first pixel circuit.

[0016] In some embodiments, the fourth type of signal line includes a data signal line.

[0017] In some embodiments, the display panel further includes: a second source / drain conductive layer located on the side of the second transparent conductive layer away from the substrate; the second source / drain conductive layer includes: a plurality of Type 5 signal lines located in the main display area; the plurality of Type 5 signal lines extend along the second direction and are electrically connected to at least a portion of the plurality of second pixel circuits; the Type 5 signal lines and the Type 4 signal lines are electrically connected.

[0018] In some embodiments, the display panel further includes: a second gate conductive layer located on the side of the first gate conductive layer away from the substrate; the first pixel circuit includes a capacitor pattern located on the second gate conductive layer; the first pixel circuit further includes a fourth active pattern located on the semiconductor layer; the second light-transmitting conductive layer further includes: a third connecting line; the third connecting line is located between two adjacent first pixel circuits along the second direction; the fourth active pattern of one of the two adjacent first pixel circuits is electrically connected to one end of the third connecting line through a fourth via; the capacitor pattern of the other of the two adjacent first pixel circuits is electrically connected to the other end of the third connecting line through another fourth via.

[0019] In some embodiments, the display panel further includes: a second source / drain conductive layer located on the side of the second transparent conductive layer away from the substrate; the second source / drain conductive layer includes a fourth connection line located in the sub-display area; along the second direction, the fourth connection line is located between two adjacent third connection lines and connects the two adjacent third connection lines.

[0020] In some embodiments, along the second direction, a plurality of the third connecting lines and a plurality of the fourth connecting lines are alternately arranged and connected sequentially, configured to transmit a first voltage signal.

[0021] In some embodiments, the display panel further includes a plurality of second pixel circuits located in the main display area. The area occupied by the plurality of second pixel circuits per unit area is larger than the area occupied by the plurality of first pixel circuits.

[0022] On the other hand, a display device is provided, comprising: a display panel as described in any of the above embodiments; and an optical element located on the non-light-emitting side of the display panel and in a sub-display area of ​​the display panel. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be considered as schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of this disclosure.

[0024] Figure 1 This is a structural diagram of a display device according to some embodiments of the present disclosure;

[0025] Figure 2 This is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0026] Figure 3 This is a structural diagram of a pixel circuit according to some embodiments of the present disclosure;

[0027] Figure 4a This is a structural diagram of another display panel according to some embodiments of the present disclosure;

[0028] Figure 4b This is a structural diagram of yet another display panel according to some embodiments of the present disclosure;

[0029] Figure 5 This is a structural diagram of yet another display device according to some embodiments of the present disclosure;

[0030] Figure 6 This is a top view of some film layers of a display panel according to some embodiments of the present disclosure;

[0031] Figure 7 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0032] Figure 8 This is a structural diagram of yet another display panel according to some embodiments of the present disclosure;

[0033] Figure 9a This is a top view of some film layers in a display panel in one implementation method;

[0034] Figure 9b This is a cross-sectional view of some of the film layers in a display panel in one implementation;

[0035] Figure 10a This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0036] Figure 10b This is a cross-sectional view of some of the film layers in a display panel according to some embodiments of the present disclosure;

[0037] Figure 10c This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0038] Figure 10d This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0039] Figure 11 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0040] Figure 12 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0041] Figure 13 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0042] Figure 14 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0043] Figure 15 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0044] Figure 16 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0045] Figure 17 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0046] Figure 18 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0047] Figure 19 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0048] Figure 20 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0049] Figure 21 This is a schematic diagram showing the connection between a third type of signal line and an initial signal line in a display panel according to some embodiments of the present disclosure;

[0050] Figure 22 This is a schematic diagram showing the connection between a first type of signal line and a second type of signal line in a display panel according to some embodiments of the present disclosure;

[0051] Figure 23 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0052] Figure 24 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0053] Figure 25 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0054] Figure 26 This is a schematic diagram showing the connection between a fourth type signal line and a fifth type signal line in a display panel according to some embodiments of the present disclosure;

[0055] Figure 27 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0056] Figure 28 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0057] Figure 29 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0058] Figure 30 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0059] Figure 31 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0060] Figure 32 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0061] Figure 33 This is a top view of some film layers in a display panel according to some embodiments of the present disclosure;

[0062] Figure 34This is a top view of some film layers in a display panel according to some embodiments of the present disclosure. Detailed Implementation

[0063] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0064] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0065] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0066] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0067] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0068] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0069] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0070] As used herein, "perpendicular" and "equal" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity could be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality could be, for example, a difference between the two equalities less than or equal to 5% of either one.

[0071] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0072] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0073] like Figure 1As shown, some embodiments of this disclosure provide a display device 1. This display device 1 can be any display device that displays either moving (e.g., video) or stationary (e.g., still images), and whether it is text or an image. More specifically, the display device of the described embodiments is contemplated for implementation in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0074] In some examples, the aforementioned display device 1 may be, for example, an OLED (Organic Light Emitting Diode) display device.

[0075] For example, the display device 1 includes: a frame, a display driver IC (Integrated Circuit), and other electronic components.

[0076] In some examples, such as Figure 1 As shown, the above-mentioned display device 1 also includes a display panel 10.

[0077] For example, such as Figure 2 As shown, the display panel 10 includes: a substrate 20, a plurality of pixel circuits 30 disposed on one side of the substrate 20, and a plurality of light-emitting devices 40 disposed on the side of the plurality of pixel circuits 30 away from the substrate 20.

[0078] Figure 2 The Z-direction is the thickness direction of substrate 20.

[0079] For example, the substrate 20 described above can be a flexible substrate or a rigid substrate.

[0080] For example, when the substrate 20 is a flexible substrate, the material of the substrate 20 can be a highly elastic material such as dimethylsiloxane, PI (polyimide), or PET (polyethylene terephthalate).

[0081] For example, if the substrate 20 is a rigid substrate, the material of the substrate 20 can be glass or the like.

[0082] In some examples, the aforementioned pixel circuits 30 are electrically connected to the aforementioned plurality of light-emitting devices 40.

[0083] For example, the aforementioned multiple pixel circuits 30 and multiple light-emitting devices 40 can be electrically connected in a one-to-one correspondence. Alternatively, one pixel circuit 30 can be electrically connected to multiple light-emitting devices 40, or multiple pixel circuits 30 can be electrically connected to one light-emitting device 40.

[0084] The present disclosure will now illustrate the structure of the display panel 10 by taking the example of an electrical connection between a pixel circuit 30 and a light-emitting device 40.

[0085] For example, in the display panel 10, each light-emitting device 40 can emit light under the driving action of the corresponding pixel circuit 30, and the light emitted by multiple light-emitting devices 40 cooperates with each other, thereby enabling the display panel 10 to realize the display function.

[0086] For example, the light-emitting device 40 may include an anode, a light-emitting functional layer, a cathode, etc., stacked sequentially. The light-emitting functional layer may include a light-emitting layer. Optionally, the light-emitting functional layer may also include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0087] By applying a common voltage to the cathode of the light-emitting device 40 and applying a driving voltage to the anode of the light-emitting device 40 using the corresponding pixel circuit 30, an electric field can be formed between the anode and the cathode. This electric field can drive charge carriers (i.e., holes and electrons) to recombine in the light-emitting layer, thereby causing the light-emitting device 40 to emit light.

[0088] In some examples, the structure of the pixel circuit 30 includes various configurations, which can be selected and configured according to actual needs. For example, the structure of the pixel circuit 30 may include "6T1C", "7T1C", "6T2C", or "7T2C". Here, "T" represents a transistor, and the number before "T" indicates the number of transistors; "C" represents a storage capacitor, and the number before "C" indicates the number of storage capacitors.

[0089] For example, this disclosure uses a "7T1C" structure for the pixel circuit 30 as an example for illustration. Wherein, Figure 3 An equivalent circuit diagram of pixel circuit 30 is shown.

[0090] Understandably, during the operation of the pixel circuit 30, signal lines are required to provide corresponding electrical signals.

[0091] For example, the display panel 10 further includes: multiple gate lines (Gate), multiple data lines (Data), multiple reset signal lines (Reset), multiple first voltage signal lines (VDD), multiple initial signal lines (Vinit), and multiple enable signal lines (EM). The gate lines (Gate) are used to transmit scan signals, the data lines (Data) are used to transmit data signals, the reset signal lines (Reset) are used to transmit reset signals, the first voltage signal lines (VDD) are used to transmit first voltage signals, the initial signal lines (Vinit) are used to transmit initial signals, and the enable signal lines (EM) are used to transmit enable signals.

[0092] For example, the aforementioned multiple gate lines (Gate), multiple reset signal lines (Reset), multiple initial signal lines (Vinit), and multiple enable signal lines (EM) can all extend along the first direction X, and the aforementioned multiple first voltage signal lines (VDD) and multiple data lines (Data) can extend along the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0093] For example, the display panel 10 also includes a plurality of second voltage signal lines VSS, which are used to transmit second voltage signals, such as a common voltage signal.

[0094] For example, such as Figure 3 As shown, the pixel circuit 30 includes: a first reset transistor T1, a second reset transistor T2, a switching transistor T3, a driving transistor T4, a compensation transistor T5, a first light-emitting control transistor T6, a second light-emitting control transistor T7, and a storage capacitor Cst.

[0095] For example, such as Figure 3 As shown, the gate of the first reset transistor T1 is electrically connected to the reset signal line Reset, the first terminal of the first reset transistor T1 is electrically connected to the initial signal line Vinit, and the second terminal of the first reset transistor T1 is electrically connected to the fourth node N4, which is also electrically connected to the second terminal of the compensation transistor T5. The first reset transistor T1 is configured to turn on under the control of the reset signal transmitted by the reset signal line Reset, transmitting the first initial signal received at the initial signal line Vinit to the fourth node N4 to reset the fourth node N4.

[0096] For example, such as Figure 3As shown, the gate of the second reset transistor T2 is electrically connected to the reset signal line Reset, the first terminal of the second reset transistor T2 is electrically connected to the initial signal line Vinit, and the second terminal of the second reset transistor T2 is electrically connected to the first node N1, that is, electrically connected to the light-emitting device 40. The second reset transistor T2 is configured to conduct under the control of the reset signal transmitted by the reset signal line Reset, transmitting the initial signal received at the initial signal line Vinit to the first node N1 to reset the first node N1.

[0097] For example, such as Figure 3 As shown, the gate of switching transistor T3 is electrically connected to the gate line Gate, the first terminal of switching transistor T3 is electrically connected to the data line Data, and the second terminal of switching transistor T3 is electrically connected to the second node N2, which is also electrically connected to the first terminal of driving transistor T4. Switching transistor T3 is configured to conduct under the control of the scan signal transmitted through the gate line Gate, transmitting the data signal received at the data line Data to the second node N2.

[0098] For example, such as Figure 3 As shown, the gate of driving transistor T4 is electrically connected to the fourth node N4, the first terminal of driving transistor T4 is electrically connected to the second node N2, and the second terminal of driving transistor T4 is electrically connected to the third node N3. Driving transistor T4 is configured to conduct under the control of the voltage at the fourth node N4, transmitting a signal (e.g., a data signal) from the second node N2 to the third node N3.

[0099] For example, such as Figure 3 As shown, the gate of compensation transistor T5 is electrically connected to the gate line, the first terminal of compensation transistor T5 is electrically connected to the third node N3, which is also electrically connected to the second terminal of driving transistor T4, and the second terminal of compensation transistor T5 is electrically connected to the fourth node N4, which is also electrically connected to the gate of driving transistor T4. Compensation transistor T5 is configured to be turned on under the control of the scan signal transmitted through the gate line, transmitting the electrical signal (e.g., a data signal) from the third node N3 to the fourth node N4.

[0100] For example, such as Figure 3 As shown, the gate of the first light-emitting control transistor T6 is electrically connected to the enable signal line EM, the first terminal of the first light-emitting control transistor T6 is electrically connected to the first voltage signal line VDD, and the second terminal of the first light-emitting control transistor T6 is electrically connected to the second node N2. The first light-emitting control transistor T6 is configured to conduct under the control of the enable signal transmitted through the enable signal line EM, transmitting the voltage signal received at the first voltage signal line VDD to the second node N2.

[0101] For example, such as Figure 3 As shown, the gate of the second light-emitting control transistor T7 is electrically connected to the enable signal line EM, the first terminal of the second light-emitting control transistor T7 is electrically connected to the third node N3, and the second terminal of the second light-emitting control transistor T7 is electrically connected to the first node N1. The second light-emitting control transistor T7 is configured to conduct under the control of the enable signal transmitted through the enable signal line EM, transmitting an electrical signal (e.g., a voltage signal) from the third node N3 to the first node N1.

[0102] For example, such as Figure 3 As shown, the second terminal (or second plate) of the storage capacitor Cst is electrically connected to the fourth node N4, and the first terminal (or first plate) of the storage capacitor Cst is electrically connected to the first voltage signal line VDD.

[0103] For example, the operation of the pixel circuit 30 includes a reset phase, a data writing and compensation phase, and a light emission phase performed sequentially.

[0104] For example, during the reset phase, under the control of the reset signal, the first reset transistor T1 is turned on, transmitting the first initial signal to the fourth node N4 to reset the fourth node N4. Since the fourth node N4 is electrically connected to the first terminal of the storage capacitor Cst, the gate of the driving transistor T4, and the second terminal of the compensation transistor T5, resetting the fourth node N4 can simultaneously reset the first terminal of the storage capacitor Cst, the gate of the driving transistor T4, and the second terminal of the compensation transistor T5. The driving transistor T4 can be turned on under the control of the initial signal. Next, under the control of the reset signal, the second reset transistor T2 is turned on, transmitting the initial signal to the first node N1 to reset the first node N1. Since the first node N1 is electrically connected to the anode of the light-emitting device 40, resetting the first node N1 can simultaneously reset the anode of the light-emitting device 40.

[0105] For example, during the data writing and compensation phase, switching transistor T3 is turned on under the control of the scan signal, and compensation transistor T5 is also turned on under the control of the scan signal. Switching transistor T3 transmits the data signal to the second node N2, and driving transistor T4 transmits the data signal from the second node N2 to the third node N3. Compensation transistor T5 transmits the data signal from the third node N3 to the fourth node N4, charging driving transistor T4 until the threshold voltage of driving transistor T4 is compensated.

[0106] For example, during the light-emitting phase, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are simultaneously turned on under the control of the enable signal. The first light-emitting control transistor T6 transmits the voltage signal to the second node N2. The driving transistor T4 transmits the voltage signal from the second node N2 to the third node N3. The second light-emitting control transistor T7 transmits the voltage signal from the third node N3 to the first node N1.

[0107] The light-emitting device 40 emits light under the influence of the voltage signal from the first node N1 and the common voltage from the common voltage line VSS.

[0108] In some embodiments, such as Figure 4a and Figure 4b As shown, the display panel 10 has a display area A and a peripheral area B.

[0109] For example, peripheral area B can be located around the periphery of display area A. Peripheral area B can be used to set up shift registers, provide the necessary electrical signals to display area A, etc.

[0110] For example, display area A includes a main display area A1 and a secondary display area A2, with the main display area A1 surrounding at least a portion of the secondary display area A2.

[0111] For example, such as Figure 4a As shown, along the first direction X, the sub-display area A2 can be located in the center of the main display area A1. Alternatively, as... Figure 4b As shown, along the first direction X, the sub-display area A2 can be located on one side of the main display area A1.

[0112] For example, the portion of the display panel 10 located in the main display area A1 and the portion located in the sub-display area A2 can both be used for screen display.

[0113] For example, the transmittance of the main display area A1 is less than that of the secondary display area A2.

[0114] In some examples, such as Figure 5 As shown, the display device 1 also includes an optical element 50 located on the non-light-emitting side of the display panel 10 and in the sub-display area A2 of the display panel 10.

[0115] For example, the light-emitting side of the display panel 10 is the side on which the display panel 10 displays the image, and the non-light-emitting side of the display panel 10 refers to the side opposite to the light-emitting side of the display panel 10.

[0116] In some examples, the optical element 50 is located in the sub-display area A2. In this way, external light can pass through the portion of the display panel 10 located in the sub-display area A2, enter the optical element 50, be collected by the optical element 50, and thus enable the optical element 50 to work normally.

[0117] For example, the optical element 50 mentioned above can be a camera, a fingerprint recognition sensor, or an infrared sensor, etc.

[0118] This embodiment of the invention uses an optical element 50 as an example, which is a camera.

[0119] For example, during camera operation, ambient light can pass through the portion of the display panel 10 located in the secondary display area A2. The camera can then collect this light to take a picture. For instance, when the camera is working (e.g., taking a selfie), the secondary display area A2 can display a black screen, while the main display area A1 displays the selfie, clearly showing the camera's location. Alternatively, both the main display area A1 and the secondary display area A2 can display the selfie, without showing the camera's location.

[0120] For example, when the camera is not working, the portions of the display panel 10 located in the main display area A1 and the sub-display area A2 can both be displayed, so that the display panel 10 and the display device 1 as a whole can display images.

[0121] For example, when the display is in the sub-display area A2, the optical element 50 can also operate.

[0122] By setting the light transmittance of the portion of the display panel 10 located in the sub-display area A2 and placing the optical element 50 in the sub-display area A2, it is possible to ensure that the optical element 50 can work normally and to increase the display area of ​​the display panel 10 and the display device 1, thereby increasing the screen-to-body ratio.

[0123] In some examples, such as Figure 6 and Figure 7 As shown, the display panel 10 includes: a semiconductor layer Poly, a first gate conductive layer GT1, a second gate conductive layer GT2, a first source / drain conductive layer SD1, and an anode layer AND, which are sequentially stacked on one side of the substrate 20.

[0124] Of course, the display panel 10 may also include a second source-drain conductive layer disposed between the first source-drain conductive layer SD1 and the anode layer AND.

[0125] For example, a first gate insulating layer may be disposed between the semiconductor layer Poly and the first gate conductive layer GT1, a second gate insulating layer may be disposed between the first gate conductive layer GT1 and the second gate conductive layer GT2, an interlayer dielectric layer may be disposed between the second gate conductive layer GT2 and the first source-drain conductive layer, a planarization layer may be disposed between the first source-drain conductive layer SD1 and the second source-drain conductive layer, and a passivation layer may be disposed between the second source-drain conductive layer and the anode layer AND, etc.

[0126] For example, the materials of the first insulating layer GI1 and the second insulating layer GI2 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0127] For example, the passivation layer can be made of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0128] To make it easier to see the pattern structure of other film layers, the first insulating layer, the second insulating layer, the interlayer dielectric layer, the passivation layer, etc. are not shown.

[0129] For example, the material of the semiconductor layer Poly may include amorphous silicon, monocrystalline silicon, polycrystalline silicon, or metal oxide semiconductor material.

[0130] For example, the first gate conductive layer GT1, the second gate conductive layer GT2, the first source / drain conductive layer SD1, and the second source / drain conductive layer are all made of conductive materials. The materials of the first gate conductive layer GT1 and the second gate conductive layer GT2 can be the same, for example, and the materials of the first source / drain conductive layer SD1 and the second source / drain conductive layer can be the same, for example.

[0131] For example, the material of the first gate conductive layer GT1, the second gate conductive layer GT2, the first source / drain conductive layer SD1, or the second source / drain conductive layer SD2 can be a metallic material, such as one or more combinations of Al (aluminum), Ag (silver), Cu (copper), Cr (chromium), molybdenum (Mo), and titanium (Ti).

[0132] It should be noted that the orthographic projection of the semiconductor layer Poly onto the substrate 20 overlaps with the orthographic projection of the first gate conductive layer GT1 onto the substrate. After the first gate conductive layer GT1 is formed on the side of the semiconductor layer Poly away from the substrate, it can be used as a mask to dope the semiconductor layer Poly. This results in the portion of the semiconductor layer Poly covered by the first gate conductive layer GT1 forming the active pattern (i.e., the channel region) of each transistor, and the portion of the semiconductor layer Poly not covered by the first gate conductive layer GT1 forming a conductor, which can serve as the first or second electrode of each transistor. The overlapping portion of the first gate conductive layer GT1 and the semiconductor layer Poly forms the gate pattern (i.e., the gate) of each transistor.

[0133] It is understandable that the first source / drain conductive layer SD1, the second source / drain conductive layer SD2, the semiconductor Poly, the first gate conductive layer GT1, and the second gate conductive layer GT2 form multiple pixel circuits 30.

[0134] For example, the relative positional relationships between the transistors and storage capacitors included in the pixel circuit 30 are as follows: Figure 6As shown. The first light-emitting control transistor T6 and the second light-emitting control transistor T7 are arranged sequentially along the first direction X. The first reset transistor T1, the switching transistor T3 and the first light-emitting control transistor T6 are arranged sequentially along the second direction Y. The second reset transistor T2 and the second light-emitting control transistor T7 are arranged sequentially along the second direction Y.

[0135] A first reference plane is defined as the surface perpendicular to the substrate 20 of the display panel 10 and along the first direction X. In the orthographic projection onto the first reference plane, the driving transistor T4 is located between the compensation transistor T5 and the switching transistor T3. A second reference plane is defined as the surface perpendicular to the substrate 20 of the display panel 10 and along the second direction Y. In the orthographic projection onto the second reference plane, the driving transistor T4 is located between the switching transistor T3 and the first light-emitting control transistor T6.

[0136] Along the second direction Y, the second reset transistor T2 is also located on the side of the driving transistor T4 away from the second light-emitting control transistor T7. The storage capacitor Cst is located at the same position as the driving transistor T4.

[0137] By adopting the above configuration, the pixel circuit 30 can be arranged in a more regular manner, which facilitates the fabrication of the display panel 10.

[0138] In some examples, such as Figure 8 As shown, the display panel 10 includes a plurality of first pixel circuits 31 located in the sub-display area A2. The plurality of first pixel circuits 31 are arranged in multiple rows and columns. Each row of first pixel circuits 31 is arranged along a first direction X, and each column of first pixel circuits 31 is arranged along a second direction Y. The display panel 10 also includes a plurality of second pixel circuits 32 located in the main display area A1. The plurality of second pixel circuits 32 are arranged in multiple rows and columns. Each row of second pixel circuits 32 is arranged along a first direction X, and each column of second pixel circuits 32 is arranged along a second direction Y.

[0139] It is understandable that the circuit structures of the first pixel circuit 31 and the second pixel circuit 32 can both be the above-mentioned "7T1C" structure.

[0140] For example, the first direction X intersects the second direction Y.

[0141] For example, the angle between the first direction X and the second direction Y is 85°, 90°, 95°, etc.

[0142] For ease of description, the embodiments in this disclosure are illustrated using an example where the angle between the first direction X and the second direction Y is 90°.

[0143] For example, a plurality of first pixel circuits 31 and a plurality of second pixel circuits 32 are arranged in an array.

[0144] For example, in a row of pixel circuits 30, all of them can be the first pixel circuits 31.

[0145] For example, in a row of pixel circuits 30, some pixel circuits can be the first pixel circuit 31, and the other part of the pixel circuits can be the second pixel circuit 32.

[0146] For example, there is a gap between two adjacent first pixel circuits 31, and external light can enter the optical element 50 through the gap, so that the optical element 50 can collect enough light to realize the photo-taking function, etc.

[0147] For example, such as Figure 2 As shown, the plurality of light-emitting devices 40 includes a plurality of first light-emitting devices 41 and a plurality of second light-emitting devices 42.

[0148] For example, multiple second light-emitting devices 42 are located in the main display area A1, and multiple first light-emitting devices 41 are located in the sub-display area A2.

[0149] For example, multiple first light-emitting devices 41 are electrically connected to multiple first pixel circuits 31, and multiple second light-emitting devices 42 are electrically connected to multiple second pixel circuits 32.

[0150] To improve the light transmittance of the secondary display area, such as Figure 7 As shown, the anode AD' of the first light-emitting device is typically arranged to cover the first pixel circuit electrically connected to it. Due to limitations in the pixel circuit fabrication process, the first pixel circuit cannot be completely hidden under the corresponding anode AD'. When external light enters the optical element through the gap between two adjacent first pixel circuits, diffraction occurs on the metal structures (such as the first gate conductive layer) of the first pixel circuit surrounding the gap, easily affecting the light collection of the optical element and causing severe photographic diffraction. Furthermore, the small gap between two adjacent first pixel circuits results in low transmittance of the sub-display area, affecting the amount of light collected by the optical element and consequently impacting its functionality.

[0151] Therefore, some embodiments of this disclosure, such as Figure 8As shown, the area occupied by multiple second pixel circuits 32 per unit area is greater than the area occupied by multiple first pixel circuits 31. For example, the number of first pixel circuits 31 per unit area is the same as the number of second pixel circuits 32 per unit area, but the area occupied by a single second pixel circuit 32 is greater than the area occupied by a single first pixel circuit 31. Compared to the main display area A1, the area of ​​the pixel circuits located in the sub-display area A2 is compressed. Therefore, the gap between two adjacent first pixel circuits 31 is larger, thereby increasing the light transmittance of the sub-display area A2, which increases the light intake of the optical element 50 and improves the image quality of the optical element 50. Furthermore, the above arrangement increases the proportion of the area of ​​the first pixel circuit 31 hidden under the anode of the corresponding first light-emitting device to the total area of ​​the first pixel circuit 31, and decreases the proportion of the area of ​​the first pixel circuit 31 exposed outside the anode to the total area of ​​the first pixel circuit 31. This reduces the probability of diffraction during image capture when external light enters the optical element 50, effectively mitigating the phenomenon of diffraction during image capture.

[0152] In one implementation, such as Figure 6 As shown, the display panel 10 further includes: a first light-transmitting conductive layer located on the first gate conductive layer GT1 and located in the sub-display area A2. Figure 6 (Not shown in the image).

[0153] For example, the first transparent conductive layer is located on the surface of the passivation layer on the side away from the substrate on the first gate conductive layer GT1.

[0154] It is understandable that the layers stacked sequentially on the side of the first gate conductive layer GT1 away from the substrate may include a second insulating layer, a second gate conductive layer, an interlayer dielectric layer, a first source / drain conductive layer SD1, a passivation layer, and a first transparent conductive layer.

[0155] The material of the first transparent conductive layer has both light-transmitting and electrical conductivity properties.

[0156] For example, the material of the first transparent conductive layer TC1 can be ITO (Indium Tin Oxide).

[0157] In some examples, the aforementioned first pixel circuit 31 (reference) Figure 8 It includes the gate pattern GP located in the first gate conductive layer GT1.

[0158] For example, the gate pattern GP forms the gate of the transistor in the first pixel circuit 31 described above. The gate of the transistor is connected to the signal line.

[0159] In another implementation, the gap between two adjacent first pixel circuits 31 in the sub-display area A2 is used for light transmission. The portion of a signal line (such as the gate line, reset signal line, enable signal line, etc. mentioned above, which is electrically connected to multiple first pixel circuits in a row of first pixel circuits) located between two adjacent first pixel circuits can be composed of a connecting line formed of a light-transmitting conductive material. Using a light-transmitting conductive connecting line to connect the signal line between the first pixel circuits in a row increases the light transmittance of the sub-display area.

[0160] Taking the aforementioned signal line as an example, this gate line is connected to the gate pattern of the pixel circuit. For example, as... Figure 9a As shown, the aforementioned connecting line CL' can be provided in the first transparent conductive layer TC1'. And as... Figure 9b As shown, since the gate line and gate pattern of the first pixel circuit are located in the first gate conductive layer GT1', and the connecting line CL' is located in the first light-transmitting conductive layer TC1', and the gate pattern GP' and the connecting line CL' are located in different film layers, the connecting line CL' needs to be electrically connected to the gate line and gate pattern GP' through a via (e.g., Figure 9b As shown, to make it easier to see the electrical connection between the gate pattern and the connecting lines, Figure 9b Only the passivation layer PVX between the first transparent conductive layer TC1' and the gate pattern GP' is shown in the diagram. Figure 9b (This is a cross-sectional view obtained by cutting along the extension direction of the gate line or connecting line CL'). Therefore, in a row of first pixel circuits, a via VH' needs to be provided on each side of the area occupied by each first pixel circuit (e.g., on opposite sides along the row direction of the first pixel circuit), to realize the connection between the gate line and gate pattern GP' and the connecting line CL'.

[0161] However, the aforementioned configuration results in a large number of vias in the sub-display area. This leads to diffraction of external light as it enters the optical element, affecting its light-gathering ability and causing issues such as photographic diffraction. Furthermore, since the via VH' occupies the area of ​​the gap GA' between two adjacent first pixel circuits, it occupies the area in the sub-display area used for external light transmission. This results in a smaller light-transmitting area and lower light transmittance in the sub-display area, thus reducing the amount of light received by the optical element and affecting its functionality. For example, with LTPS (low-temperature poly-silicon) pixel circuits at a pixel density of 400 PPI (Pixels Per Inch), the light-transmitting area ratio (or aperture ratio, which is the ratio of the light-transmitting area to the area of ​​the sub-display area A2) of the sub-display area is approximately 48.3%.

[0162] Some embodiments of this disclosure provide a display panel 10, such as Figure 10a and Figure 10b As shown, the display panel 10 also includes a first conductive layer CT located on the substrate, and a plurality of first pixel circuits 31 including conductive patterns CW located on the first conductive layer CT.

[0163] In some examples, the display panel 10 further includes a first signal line layer SN located on the side of the first conductive layer CT away from the substrate and located in the sub-display area A2, the first signal line layer SN including a first type of signal line SL1 extending along a first direction X.

[0164] For example, the first type of signal line SL1 is used to transmit electrical signals.

[0165] In some examples, the conductive patterns CW of each first pixel circuit 31 located in the same row along the first direction X are electrically connected to the first type of signal line SL1 through a first via VH1 located on one side of the first pixel circuit 31 along the first direction X.

[0166] For example, the first via VH1 corresponding to the conductive pattern CW of each first pixel circuit 31 is located on one of the opposite sides of the corresponding first pixel circuit 31 along the first direction X.

[0167] For example, such as Figure 10b As shown, the aforementioned first via VH1 refers to a film layer (e.g., a film layer formed between the first signal line layer SN and the first conductive layer CT) to achieve electrical connection between the conductive pattern CW and the first type of signal line SL1. Figure 10b The via (such as the passivation layer PVX, interlayer dielectric layer ILD, etc.) is a via. Due to limitations in the drilling process and film thickness, the first via VH1 can consist of multiple sub-vias connected sequentially along the Z direction. These sub-vias are approximately concentric or staggered. Each sub-via is located in a different film layer, and a conductive transition block is formed within each sub-via. The conductive transition block extends to the upper surface of the corresponding film layer (e.g., ...). Figure 10b The conductive transition blocks are formed using the material of the first source-drain conductive layer SD1. Each conductive transition block passes through a sub-hole to achieve electrical connection between the conductive pattern CP and the first type of signal line SL1.

[0168] In some embodiments of this disclosure, a first signal line layer SN is provided in the sub-display area A2. The first signal line layer SN includes a first type of signal line SL1. The first type of signal line SL1 extends along a first direction X, and the conductive pattern CW of the first pixel circuit 31 in the same row of the sub-display area A2 is electrically connected to the first type of signal line SL1 through a first via VH1. The first via VH1 is located on one side of the first pixel circuit 31 along the first direction X, thereby reducing the number of first via VH1 around or inside the area occupied by a first pixel circuit 31. Compared with one implementation, the number of first via VH1 around or inside the area occupied by each first pixel circuit 31 is reduced, thereby reducing the number of vias in the sub-display area A2. This alleviates the diffraction phenomenon of external light during incident on the optical element 50, and to a certain extent avoids the photographic diffraction phenomenon of the optical element 50. Furthermore, the number of first vias VH1 is reduced, allowing for a larger gap GA between two adjacent first pixel circuits 31 in the sub-display area A2. This means the area originally used to form the first via VH1 can now be used as an incident and transmitted area for external light, i.e., a light-transmitting area. This increases the light-transmitting area in the sub-display area A2, thereby increasing its transmittance and ensuring sufficient light collection by the optical element 50. Taking an LTPS type pixel circuit as an example, with a pixel density of 400 PPI, the light-transmitting area ratio (or aperture ratio, which is the ratio of the area of ​​the light-transmitting region to the area of ​​the sub-display area A2) of the sub-display area A2 is approximately 52.5%. The light-transmitting area ratio of the sub-display area A2 increases by 4.2%, significantly increasing the light-transmitting area of ​​the sub-display area A2 and mitigating the diffraction phenomenon during image capture by the optical element.

[0169] In some embodiments, each first pixel circuit 31 is electrically connected to a first type of signal line SL1 through a first via VH1. It is understood that the relative positional relationship between the first via VH1 and the corresponding first pixel circuit 31 can be varied and can be configured according to actual needs; this disclosure does not impose any limitations on this.

[0170] For example, in the same row of first pixel circuits 31, the first via VH1 corresponding to each first pixel circuit 31 can be located on different sides of each first pixel circuit 31 along the first direction X.

[0171] For example, in the same row of first pixel circuits 31, the first vias VH1 corresponding to different first pixel circuits 31 are all located on the same side of the first pixel circuit 31.

[0172] By adopting the above configuration, the arrangement of the first via VH1 in the display panel can be made more regular, thereby reducing the manufacturing difficulty of the display panel.

[0173] In some embodiments, the first conductive layer CT includes a first gate conductive layer GT1, the conductive pattern CP includes a gate pattern GP, ​​and the first signal line layer SN includes a first transparent conductive layer TC1.

[0174] For example, the material of the first transparent conductive layer TC1 has both light-transmitting and conductive properties. The material of the first transparent conductive layer TC1 can be ITO (Indium Tin Oxide).

[0175] For example, a first-class signal line SL1 is electrically connected to a row of first pixel circuits 31.

[0176] For example, a first-class signal line SL1 is electrically connected to the gate pattern GP of the corresponding row of first pixel circuit 31 and transmits an electrical signal to the corresponding row of first pixel circuit 31.

[0177] In some embodiments, such as Figure 10a and Figure 10b As shown, the first type of signal line SL1 is located on the same layer in the sub-display area A2 and is a continuous trace. The orthographic projection of the first type of signal line SL1 on the substrate overlaps with the orthographic projection of at least one of the multiple first pixel circuits 31 on the substrate.

[0178] For example, the first type of signal lines SL1 are formed from a single, unbroken strip pattern generally along a first direction. All of the first type of signal lines SL1 are located in the same layer within the sub-display area, specifically in the first transparent conductive layer TC1. This simplifies the manufacturing process of the display panel.

[0179] For example, a portion of a first type signal line SL1 is located in the gap between two adjacent first pixel circuits 31, and another portion of the first type signal line SL1 covers a portion of the corresponding first pixel circuit 31.

[0180] For example, the orthographic projection of a first-type signal line SL1 on the substrate 20 partially overlaps with the orthographic projection of each first pixel circuit 31 in the corresponding row of first pixel circuits 31 on the substrate 20.

[0181] In some embodiments, such as Figure 10b , Figure 10c , Figure 10d As shown, the first gate conductive layer GT1 includes a first via connection portion HP1 electrically connected to the gate pattern GP, ​​and the first via VH1 exposes the first via connection portion HP1; the gate pattern GP is electrically connected to the first type signal line SL1 through the first via connection portion HP1.

[0182] For example, the first via connection HP1 is in the same layer and made of the same material as the gate pattern GP.

[0183] For example, the first via VH1 can expose a portion of the first via connection HP1.

[0184] For example, the first via connection HP1 is located on the side outside the area occupied by the first pixel circuit 31 where the gate pattern GP is connected, or it is located within the area occupied by the first pixel circuit 31 where the gate pattern GP is connected.

[0185] Figure 10c In the diagram, the area defined by the dashed box PP is the area occupied by the first pixel circuit 31.

[0186] For example, the first via connection HP1 is located in the peripheral area outside the area occupied by the first pixel circuit 31.

[0187] For example, the orthographic projection of the first via connection HP1 on the substrate 20 is located within the range of the orthographic projection of the first pixel circuit 31 on the substrate 20. This reduces the area of ​​the light-transmitting region in the sub-display area A2 occupied by the first via, resulting in a larger light-transmitting region in the sub-display area A2. This increases the light transmittance of the sub-display area A2, increases the light intake of the optical element 50, and ensures the normal operation of the optical element 50.

[0188] For example, the first type of signal line SL1 can cover at least a portion of the corresponding first via VH1.

[0189] By adopting the above-described configuration, the gate pattern GP and the first type signal line SL1 are electrically connected through a first via connection HP1. This avoids the limitation imposed by the relative position of the gate pattern GP's orthographic projection on the substrate, thus preventing the orthographic projection of the first type signal line SL1 from partially overlapping with the orthographic projection of the gate pattern GP, ​​or from being located around the periphery of the orthographic projection of the gate pattern GP. This facilitates the electrical connection between the gate pattern GP and the first type signal line SL1. When there are a large number of first type signal lines SL1 on the first transparent conductive layer TC1, the above configuration allows for convenient arrangement of the relative positions of multiple first type signal lines SL1 on the first transparent conductive layer TC1. This avoids interference between the electrical signals on adjacent first type signal lines SL1 due to small spacing, thereby improving the accuracy of the electrical signals transmitted by the first type signal lines SL1 and ultimately improving the display quality of the image displayed on the display panel 10.

[0190] Understandable Figure 11The diagram illustrates the top view of the semiconductor layer Poly, the first gate conductive layer GT1, the second gate conductive layer GT2, the first source / drain conductive layer SD1, the second source / drain conductive layer SD2, and the anode layer AND in the sub-display area A2, which are stacked sequentially. Figure 12 The diagram illustrates the top view of the Poly semiconductor layer in the sub-display area A2. Figure 13 The diagram illustrates the top view of the semiconductor layer Poly and the first gate conductive layer GT1 stacked sequentially in the sub-display area A2. Figure 14 The diagram illustrates the top view of the structure after the first gate conductive layer Gate1 and the second gate conductive layer Gate2 are stacked sequentially in the sub-display area A2. Figure 15 The diagram illustrates the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, and the interlayer dielectric layer ILD in the sub-display area A2. Figure 15 The diagram only shows the positions of the vias on the interlayer dielectric layer (ILD) in the sub-display area A2. This is a top view of the structure after the layers are stacked sequentially. Figure 16 The diagram illustrates the interlayer dielectric layer (ILD) in sub-display area A2. Figure 16 The diagram only shows the location of the vias on the interlayer dielectric layer (ILD) in the sub-display area A2, and the top view of the structure after the first source and drain conductive layers (SD1) are stacked in sequence. Figure 17 The diagram illustrates the first source / drain conductive layer SD1 and the passivation layer PVX in the sub-display area A2. Figure 17 The diagram only shows the position of the vias on the passivation layer PVX in the sub-display area A2. This is a top view of the structure after the layers are stacked sequentially. Figure 18 The passivation layer PVX in the sub-display area A2 is shown. Figure 18 The diagram only shows the location of the vias on the passivation layer PVX in the sub-display area A2, and the top view of the structure after the first transparent conductive layer TC1 is stacked in sequence. Figure 19 The diagram illustrates the first source / drain conductive layer SD1 and the passivation layer PVX in the sub-display area A2. Figure 19 The diagram only shows the location of the vias on the passivation layer PVX in the sub-display area A2, and the top view of the structure after the first transparent conductive layer TC1 is stacked in sequence.

[0191] Of course, the semiconductor layer Poly is located on one side of the substrate. Other films may also be present between the substrate and the first transparent conductive layer TC1, which can be configured according to actual needs, and this disclosure does not impose any limitations on this.

[0192] In some embodiments, such as Figure 13 and Figure 20 As shown, the first pixel circuit 31 includes multiple gate patterns GP, which are arranged in multiple columns along the first direction X and in multiple rows along the second direction Y.

[0193] For example, multiple gate patterns GP are arranged in an array.

[0194] For example, a first pixel circuit 31 includes a plurality of transistors, each transistor having at least one gate pattern GP.

[0195] For example, such as Figure 20 As shown, the same row of gate patterns GP includes at least two gate patterns GP, and the at least two gate patterns GP are electrically connected to the same Class 1 signal line SL1.

[0196] For example, the gate patterns GP of at least two transistors located in the same row are also located in the same row. When at least two transistors are turned on or off under the control of the same electrical signal, the gate patterns GP of the at least two transistors can be connected to the same signal line, such as the same first-type signal line SL1.

[0197] For example, the same row of gate patterns GP includes two gate patterns GP, which can be electrically connected to each other, and the two gate patterns GP are electrically connected to the same Class 1 signal line SL1.

[0198] For example, the same row of gate patterns GP includes four gate patterns, which can be electrically connected to each other. These four gate patterns GP are electrically connected to the same Class 1 signal line SL1.

[0199] By adopting the above configuration, multiple gate patterns GP in the same row can be electrically connected to the first type of signal line SL1, thereby reducing the number of first vias VH1. This reduces the diffraction phenomenon that occurs at the first via VH1 when external light is incident on the optical element 50, thus avoiding affecting the function of the optical element 50.

[0200] In some embodiments, such as Figure 14 and Figure 20 As shown, at least two gate patterns GP are electrically connected to the first type of signal line SL1 through the same first via connection HP1.

[0201] For example, two gate patterns GP located in the same row can be electrically connected to each other, and one of the two gate patterns GP can be electrically connected to the first via connection HP1, so that the two gate patterns GP are electrically connected to the same first type signal line SL1 through a via connection HP1, thereby reducing the number of first vias VH1, thereby reducing the diffraction phenomenon that occurs at the first via VH1 when external light is incident on the optical element 50, and thus avoiding affecting the function of the optical element 50.

[0202] For example, four gate patterns GP located in the same row can be electrically connected to each other, and one of the four gate patterns GP can be electrically connected to the first via connection HP1. This allows the four gate patterns GP5 to be electrically connected to the same first type signal line SL1 through a via connection HP1, thereby reducing the number of first vias VH1. This reduces the diffraction phenomenon that occurs at the first via VH1 when external light enters the optical element 50, thus avoiding affecting the function of the optical element 50.

[0203] In some embodiments, such as Figure 14 As shown, the above-mentioned at least two gate patterns GP are integrally structured;

[0204] And / or, the above-mentioned at least two gate patterns GP and the first through-hole connection portion HP1 electrically connected to the at least two gate patterns GP are integrally structured.

[0205] For example, two gate patterns GP located in the same row are integrated into one structure.

[0206] For example, four gate patterns GP located in the same row form a single structure.

[0207] For example, two gate patterns GP located in the same row and a first via connection HP1 electrically connected to the two gate patterns GP are integrated into one structure.

[0208] 5. For example, four gate patterns GP located in the same row and a first via connection HP1 electrically connected to the four gate patterns GP are integrated into one structure.

[0209] The aforementioned integrated structure refers to two connected patterns arranged on the same layer, and these two patterns are continuous and not separated. This simplifies the structure and manufacturing process of the first pixel circuit 31 and the display panel 10.

[0210] 0 In some embodiments, such as Figure 18 and Figure 20 As shown, the first type of signal line SL1 includes at least one of the above-mentioned gate line Gate, reset signal line Reset, and enable signal line EM.

[0211] For example, the first type of signal line SL1 mentioned above includes a gate line. The gate pattern GP mentioned above can be the gate pattern of the compensation transistor T5 and the gate pattern of the switching transistor T3.

[0212] For example, the first type of signal line SL1 mentioned above includes a reset signal line Reset. The gate pattern GP mentioned above can be the gate pattern of the first reset transistor T1 and the gate pattern of the second reset transistor T2.

[0213] For example, the first type of signal line SL1 mentioned above includes an enable signal line EM. The gate pattern GP mentioned above can be the gate pattern of the first light-emitting control transistor T6 and the gate pattern of the second light-emitting control transistor T7.

[0214] For example, the first type of signal line SL1 mentioned above includes the gate line Gate and the reset signal line Reset.

[0215] For example, the first type of signal line SL1 mentioned above includes the gate line Gate and the enable signal line EM.

[0216] For example, the first type of signal line SL1 mentioned above includes the reset signal line Reset and the enable signal line EM.

[0217] For example, the first type of signal line SL1 mentioned above includes the gate line Gate, the reset signal line Reset, and the enable signal line EM.

[0218] By adopting the above configuration, at least one of the gate line, reset signal line, and enable signal line EM can be electrically connected to the first pixel circuit 31 of a row through a first via VH1. This reduces the number of vias in the sub-display area A2, thereby mitigating the diffraction phenomenon of external light as it enters the optical element 50, and to a certain extent avoiding the photographic diffraction phenomenon of the optical element 50. Furthermore, the reduction in the number of first vias VH1 increases the gap between two adjacent first pixel circuits 31 in the sub-display area A2. In other words, the area originally used to form the first via VH1 can be used as the incident and transmission area of ​​external light, thus increasing the area of ​​the light-transmitting region. This increases the light transmittance of the sub-display area A2, ensuring the amount of light collected by the optical element 50.

[0219] In some embodiments, such as Figure 22 As shown, the first gate conductive layer GT1 also includes a second type signal line SL2 located in the main display area A1. The second type signal line SL2 extends along the first direction X and is electrically connected to at least a portion of the second pixel circuits 32 in the plurality of second pixel circuits. Figure 22 The dashed box in the middle indicates the area where the second pixel circuit 32 is located.

[0220] For example, the second type signal line SL2 is electrically connected to one row of second pixel circuits 32 among a plurality of second pixel circuits 32.

[0221] In some examples, the first type signal line SL1 and the second type signal line SL2, which transmit the same electrical signal, are electrically connected, and the corresponding first pixel circuits 31 and second pixel circuits 32 are located in the same row.

[0222] For example, the type of electrical signal transmitted by the second type signal line SL2 to the corresponding second pixel circuit 32 in the same row can be a scan signal, a reset signal, or an enable signal.

[0223] In some examples, the second type of signal line SL2, which transmits the scan signal, is electrically connected to the first type of signal line SL1, which also transmits the scan signal. Furthermore, the second pixel circuit 32 corresponding to the second type of signal line SL2 is located in the same row as the first pixel circuit 31 corresponding to the first type of signal line SL1. Therefore, by inputting an electrical signal to either the first type of signal line SL1 or the second type of signal line SL2, both lines can transmit the same electrical signal to the pixel circuits 30 in the same row, thus simplifying the design of the display panel 10.

[0224] Understandable Figure 22 Only the three Type II signal lines SL2 of the first gate conductive layer GT1 and the three Type I signal lines SL1 of the first transparent conductive layer TC1 are shown. Figure 22 The pattern shape of the second type signal line SL2 is only for illustration. There are various patterns and shapes for the second type signal line SL2, and some embodiments of this disclosure do not limit this.

[0225] In some embodiments, such as Figure 12 and Figure 20 As shown, the first pixel circuit 31 also includes a first active pattern AP1 and a second active pattern AP2 located in the semiconductor layer Poly and spaced apart along the first direction X.

[0226] It is understandable that the semiconductor layer Poly is located between the substrate 20 and the first gate conductive layer GT1.

[0227] For example, there is a gap between the first active pattern AP1 and the second active pattern AP2, and they are not electrically connected.

[0228] In some examples, such as Figures 18-20 and Figure 23 As shown, the first transparent conductive layer TC1 further includes: a first connecting line CL1; along the first direction X, the first connecting line CL1 is located between two adjacent first pixel circuits 31.

[0229] For example, the first connecting line CL1 extends along the first direction X.

[0230] In some examples, the first active pattern AP1 of one of the two adjacent first pixel circuits 31 is electrically connected to one end of the first connecting line CL1 through a second via VH2. The second active pattern AP2 of the other of the two adjacent first pixel circuits 31 is electrically connected to the other end of the first connecting line CL1 through another second via VH2.

[0231] In some embodiments, such as Figures 16-17 As shown, the first source / drain conductive layer SD1 includes a second connection line CL2 located in the sub-display area A2. (As indicated...) Figure 19 As shown, along the first direction X, the second connecting line CL2 is located between two adjacent first connecting lines CL1 and connects the two adjacent first connecting lines CL1.

[0232] like Figure 33 As shown, the first source / drain conductive layer SD1 is located between the second gate conductive layer GT2 and the first transparent conductive layer TC1.

[0233] For example, the second connecting line CL2 extends approximately along the first direction X.

[0234] For example, such as Figure 19 As shown, the first connection line CL1 can be connected to the second connection line CL2 through the via VH located on the passivation layer PVX.

[0235] By adopting the above configuration, two adjacent first connection lines CL1 can be connected together, and multiple first connection lines CL1 connected to a row of first pixel circuits 31 can be interconnected through second connection lines CL2. This makes it easier to transmit signals on the first connection lines CL1 to the corresponding row of first pixel circuits 31, simplifies the design of the display panel 10, and avoids sending electrical signals to each first connection line CL1 in the same row of first connection lines separately.

[0236] In some embodiments, such as Figure 19 As shown, along the first direction X, multiple first connecting lines CL1 and multiple second connecting lines CL2 are alternately arranged and connected in sequence to form the initial signal line Vinit.

[0237] For example, the initial signal line Vinit extends along the first direction X.

[0238] For example, the initial signal line Vinit is electrically connected to the first pixel circuit 31 of a row and transmits the initial signal to the first pixel circuit 31 of a row.

[0239] For example, when multiple first connection lines CL1 and multiple second connection lines CL2 are connected sequentially to form an initial signal line Vinit, the aforementioned first active pattern AP1 can be an active pattern of the first reset transistor T1, and the aforementioned second active pattern AP2 can be an active pattern of the second reset transistor T2. The initial signal line Vinit transmits an initial signal to the first reset transistor T1 through the first active pattern AP1, and transmits an initial signal to the second reset transistor T2 through the second active pattern AP2.

[0240] In some embodiments, such as Figure 21 As shown, the second gate conductive layer GT2 includes multiple third-type signal lines SL3 located in the main display area A1. The multiple third-type signal lines SL3 extend along the first direction X and are electrically connected to each second pixel circuit 32 located in the same row.

[0241] For example, the second conductive layer GT2 is located between the first gate conductive layer GT1 and the first transparent conductive layer TC1.

[0242] For example, the third type signal line SL3 and the initial signal line Vinit are electrically connected, and the five first pixel circuits 31 and the five second pixel circuits 32 corresponding to them are located in the same row. Figure 21 The dashed box in the image indicates the location of the first pixel circuit and the second pixel circuit.

[0243] For example, the third type signal line SL3 is used to transmit an initial signal to the second pixel circuit 32 of a row. This third type signal line SL3 is electrically connected to the initial signal line Vinit, thereby enabling the same row of pixels in the display panel 10 to transmit an initial signal.

[0244] The initial signals received by the pixel circuit 30 are the same, so that the light-emitting devices 0 40 corresponding to the same row of pixel circuit 30 have the same initial state before emitting light, thereby enabling the display panel 10 to display the image normally.

[0245] Understandable Figure 21 Only the two third-type signal lines SL3 of the second gate conductive layer GT2 and the two initial signal lines Vinit are shown. Figure 21 The pattern shape of the third type signal line SL3 is for illustrative purposes only. There are various patterns and shapes for the third type signal line SL3, and this disclosure does not limit them.

[0246] In some embodiments, such as Figure 24 , Figure 25 and Figure 27 As shown, the display panel 10 also includes a second light-transmitting conductive layer TC2 located on the first light-transmitting conductive layer TC1 and located in the sub-display area A2. The second light-transmitting conductive layer TC2 includes a fourth type signal line SL4 extending along the second direction Y.

[0247] It is understandable that, such as Figure 23 and Figure 24 As shown, a first planarization layer PLN1 is disposed between the second transparent conductive layer TC2 and the first transparent conductive layer TC1.

[0248] For example, the material of the second transparent conductive layer TC2 has both light-transmitting and conductive properties. Alternatively, the materials of the first transparent conductive layer TC1 and the second transparent conductive layer TC2 can be the same.

[0249] For example, the material of the second transparent conductive layer TC1 can be ITO (Indium Tin Oxide).

[0250] In some examples, such as Figure 12 and Figure 29 As shown, the first pixel circuit 31 also includes a third active pattern AP3 located on the semiconductor layer Poly. The third active patterns AP3 of each first pixel circuit 31 located in the same column are electrically connected to a fourth type signal line SL4 through a third via VH3. The third via VH3 is located on one side of the first pixel circuit 31 along the second direction Y.

[0251] In some embodiments, each first pixel circuit 31 is electrically connected to a fourth type signal line SL4 through a third via VH3. It is understood that the relative positional relationship between the third via VH3 and the corresponding first pixel circuit 31 can be varied and can be configured according to actual needs; this disclosure does not impose any limitations on this. For example, in the same column of first pixel circuits 31, the third via VH3 corresponding to different first pixel circuits 31 can be located on different sides of each first pixel circuit 31 along the second direction Y.

[0252] For example, in the same column of first pixel circuits 31, the third vias VH3 corresponding to different first pixel circuits 31 are all located on the same side of the first pixel circuit 31 along the second direction Y.

[0253] By adopting the above configuration, the arrangement of the third via VH3 in the display panel can be made more regular, thereby reducing the manufacturing difficulty of the display panel.

[0254] For example, a Class 4 signal line SL4 is electrically connected to a column of first pixel circuits 31.

[0255] In some examples, the fourth type signal line SL4 is located on the same layer as the sub-display area A2 and is a continuous trace. The orthographic projection of the fourth type signal line SL4 on the substrate overlaps with the orthographic projection of at least one of the plurality of first pixel circuits 31 on the substrate.

[0256] For example, the orthographic projection of the fourth type signal line SL4 onto the substrate overlaps with the orthographic projection of a first pixel circuit 31 onto the substrate.

[0257] For example, the orthographic projection of the fourth type signal line SL4 onto the substrate overlaps with the orthographic projection of multiple first pixel circuits 31 onto the substrate.

[0258] For example, such as Figure 29 As shown, a portion of the aforementioned fourth type signal line SL4 is located in the gap between two adjacent first pixel circuits 31 in a column of first pixel circuits 31, while the other portion covers the corresponding first pixel circuit 31.

[0259] For example, the fourth type of signal line SL4 is formed by a monolithic, unbroken strip pattern generally along the second direction Y. The entire fourth type of signal line SL4 is located in the same layer within the sub-display area, specifically in the second transparent conductive layer TC2. This simplifies the manufacturing process of the display panel.

[0260] For example, such as Figure 29 As shown, the aforementioned third via VH3 refers to a via formed to achieve electrical connection between the third active pattern AP3 and the fourth type signal line SL4, penetrating the film layer (e.g., the first planarization layer PLN1, passivation layer PVX, interlayer dielectric layer ILD, second insulating layer, first insulating layer, etc.) between the second transparent conductive layer TC2 and the semiconductor layer Poly. Due to limitations in the drilling process and film thickness, the third via VH3 can be composed of multiple sub-vias connected sequentially along the Z direction. These sub-vias are approximately concentric or staggered. Each sub-via is located in a different film layer, and a conductive transition block is formed within each sub-via. The conductive transition block extends to the upper surface of the film layer containing the corresponding sub-via (e.g., the conductive transition block can be formed using the material of the first source / drain conductive layer). Each conductive transition block passes through its respective sub-via, achieving electrical connection between the third active pattern AP3 and the fourth type signal line SL4.

[0261] For example, the orthographic projection of a fourth type signal line SL4 on the substrate 20 partially overlaps with the orthographic projection of each first pixel circuit 31 in a corresponding column of first pixel circuits 31 on the substrate 20.

[0262] In some embodiments of this disclosure, a second light-transmitting conductive layer TC2 is provided in the sub-display area A2. The second light-transmitting conductive layer TC2 includes a fourth type signal line SL4. The fourth type signal line SL4 extends along the second direction Y. The third active pattern AP3 of the first pixel circuit 31 in the same column of the sub-display area A2 is electrically connected to the fourth type signal line SL4 through a third via VH3. This reduces the number of fourth type signal lines SL4 around or inside the area occupied by a first pixel circuit 31. Compared with one implementation, the number of fourth type signal lines SL4 around or inside the area occupied by each first pixel circuit 31 is reduced, thereby reducing the number of vias in the sub-display area A2. This alleviates the diffraction phenomenon of external light during incident on the optical element 50 and reduces the phenomenon of photographic diffraction of the optical element 50 to a certain extent. Furthermore, the number of the fourth type of signal lines SL4 is reduced, which increases the gap between two adjacent first pixel circuits 31 in the sub-display area A2. In other words, the area originally used to form the first via VH1 can be used as the incident and transmission area of ​​external light, i.e., the light-transmitting area, which increases the light-transmitting area in the sub-display area A2, thereby increasing the light transmittance of the sub-display area A2 and ensuring the amount of light collected by the optical element 50.

[0263] Understandable Figure 20 The diagram illustrates the top view of the structure of the sub-display area A2 after the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, and the first light-transmitting conductive layer TC1 are stacked in sequence. Figure 23 The diagram illustrates the first light-transmitting conductive layer TC1 and the first planarization layer PLN1 in the sub-display area A2. Figure 23 The diagram only shows the position of the vias on the first flat layer PLN1 in the sub-display area A2. This is a top view of the structure after the layers are stacked sequentially. Figure 24 The diagram illustrates the first planarization layer PLN1 in the sub-display area A2. Figure 24 The diagram only shows the position of the via on the first planarization layer PLN1 in the sub-display area A2 and the top view of the structure after the second light-transmitting conductive layer TC2 is stacked in sequence. Figure 25 The diagram illustrates the top view of the second transparent conductive layer TC2 in the sub-display area A2. Figure 27 The diagram illustrates the second transparent conductive layer TC2 and the second planarization layer PLN2 in the sub-display area A2. Figure 27 The diagram only shows the position of the vias on the second flat layer PLN2 in the sub-display area A2. This is a top view of the structure after the layers are stacked sequentially. Figure 28 The diagram shows the top view of the second source / drain conductive layer SD2 in the sub-display area A2. Figure 29The diagram illustrates the top view of the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the second light-transmitting conductive layer TC2, and the second source / drain conductive layer SD2 stacked sequentially in the sub-display area A2. Figure 30 The diagram illustrates the second source / drain conductive layer SD2 and the third planarization layer PLN3 in the sub-display area A2. Figure 30 The diagram only shows the position of the vias on the third flat layer PLN3 in the sub-display area A2. This is a top view of the structure after the layers are stacked sequentially. Figure 31 The diagram illustrates the second transparent conductive layer TC2, the second source / drain conductive layer SD2, and the third planarization layer PLN3 in the sub-display area A2. Figure 31 The diagram only shows the position of the vias on the third flat layer PLN3 in the sub-display area A2. This is a top view of the structure after the layers are stacked sequentially. Figure 33 The diagram illustrates the top view of the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the first source / drain conductive layer SD1, the first light-transmitting conductive layer TC1, the second light-transmitting conductive layer TC2, and the second source / drain conductive layer SD2 stacked sequentially in the sub-display area A2. Figure 34 The diagram illustrates the top view of the anode layer AND in the sub-display area A2.

[0264] The materials of the first planarization layer PLN1, the second planarization layer PLN2, and the third planarization layer PLN3 can be the same.

[0265] For example, the material of the first planarization layer PLN1 can be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0266] For example, the films sequentially stacked on the side of the first transparent conductive layer TC1 away from the substrate may include a first planarization layer PLN1, a second transparent conductive layer TC2, a second planarization layer PLN2, a second source / drain conductive layer SD2, a third planarization layer PLN3, and an anode layer AND.

[0267] Of course, there may be other film layers between the substrate and the anode layer AND, which can be set according to actual needs, and this disclosure does not limit this.

[0268] In some embodiments, such as Figure 12 and Figure 29 As shown, the semiconductor layer Poly includes a third via connection portion HP3 connected to the third active pattern AP3. The third via VH3 exposes the third via connection portion HP3, and the third active pattern AP3 is electrically connected to the fourth type signal line SL4 through the third via connection portion HP3.

[0269] The third via connection HP3 is located on the side outside the area occupied by the first pixel circuit 31, or within the area occupied by the first pixel circuit 31.

[0270] For example, the third via VH3 can expose a portion of the third via connection HP3.

[0271] For example, the third active pattern AP3 and the third via connection HP3 are in the same layer and made of the same material.

[0272] For example, the third via connection HP3 is located in the peripheral area outside the area occupied by the first pixel circuit 31 where the third active pattern AP3 is electrically connected to it.

[0273] For example, the orthographic projection of the third via connection HP3 on the substrate 20 is located within the orthographic projection range of the first pixel circuit 31, where the third active pattern AP3 is electrically connected, on the substrate 20. This reduces the area of ​​the light-transmitting region in the sub-display area A2 occupied by the third via VH3, resulting in a larger light-transmitting region in the sub-display area A2. This increases the light transmittance of the sub-display area A2, increases the light intake of the optical element 50, and ensures the normal operation of the optical element 50.

[0274] For example, the fourth type signal line SL4 covers the aforementioned third via VH3.

[0275] By adopting the above configuration, the third active pattern AP3 and the fourth type signal line SL4 are electrically connected through a third via connection HP3. This avoids the limitation of the relative position of the orthographic projection of the third active pattern AP3 on the substrate, thus avoiding the need for the orthographic projection of the fourth type signal line SL4 on the substrate to partially overlap with the orthographic projection of the third active pattern AP3 on the substrate, or the need for the orthographic projection of the fourth type signal line SL4 to be located around the orthographic projection of the third active pattern AP3 on the substrate, thereby facilitating the electrical connection between the third active pattern AP3 and the fourth type signal line SL4.

[0276] Furthermore, when there are a large number of Type IV signal lines SL4 on the second transparent conductive layer TC2, the relative positions of multiple Type IV signal lines SL4 on the second transparent conductive layer TC2 can be easily arranged. The third active pattern AP3 and the Type IV signal lines SL4 are electrically connected through a third via connection HP3. This avoids interference between the electrical signals on adjacent Type IV signal lines SL4 due to small spacing, thereby improving the accuracy of the electrical signals transmitted by the Type IV signal lines SL4 and thus improving the display quality of the image displayed on the display panel 10.

[0277] In some embodiments, such as Figure 25 As shown, the fourth type of signal line SL4 includes the data signal line Data.

[0278] For example, the data signal line Data is electrically connected to a column of first pixel circuits 31 and transmits data signals to the column of first pixel circuits 31.

[0279] For example, such as Figure 33 As shown, when the fourth type of signal line SL4 includes the data signal line Data, the aforementioned third active pattern AP3 can be the active pattern of the switching transistor T3 in the first pixel circuit 31.

[0280] By adopting the above configuration, the data signal line Data can be electrically connected to a column of first pixel circuits 31 through a third via VH3. This reduces the number of vias in the sub-display area A2, thereby mitigating the diffraction phenomenon of external light as it enters the optical element 50, and to a certain extent avoiding the photographic diffraction phenomenon of the optical element 50. Furthermore, the reduced number of third vias VH3 increases the gap between adjacent first pixel circuits 31 in the sub-display area A2. In other words, the area originally used to form the third via VH3 can be used as an incident and transmission area for external light, thus increasing the area of ​​the light-transmitting region. This increases the light transmittance of the sub-display area A2, ensuring sufficient light collection by the optical element 50.

[0281] In some embodiments, such as Figure 26 As shown, the second source / drain conductive layer SD2 includes multiple Type 5 signal lines SL5 located in the main display area A1. The multiple Type 5 signal lines SL5 extend along the second direction Y and are electrically connected to each of the second pixel circuits 32 located in the same column.

[0282] For example, multiple Category 5 signal lines (SL5) are arranged at intervals.

[0283] For example, the fifth type signal line SL5 is electrically connected to a column of second pixel circuits 32. Figure 26 The dashed box indicates the area where the second pixel circuit is located. When the fourth type signal line SL4 includes a data signal line, the fifth type signal line SL5 transmits a data signal to a column of second pixel circuits 32 that are electrically connected to it.

[0284] In some examples, the fifth type signal line SL5 and the fourth type signal line SL4 are electrically connected, and the corresponding first pixel circuits 31 and second pixel circuits 32 are located in the same column. Therefore, an electrical signal, such as a data signal, can be input to one of the fourth type signal line SL4 and the fifth type signal line SL5, allowing the same electrical signal to be transmitted to the same row of pixel circuits 30 using both lines, thus simplifying the design of the display panel 10.

[0285] Understandable Figure 26Only two Type 5 signal lines SL5 of the second source-drain conductive layer SD2 and two Type 4 signal lines SL4 of the second transparent conductive layer TC2 are shown. Figure 26 The pattern shape of the Category 5 signal line SL5 is for illustrative purposes only. There are various patterns and shapes for the Category 5 signal line SL5, and this disclosure does not limit them.

[0286] In some embodiments, such as Figure 14 As shown, the first pixel circuit 31 includes a capacitor pattern CP located on the second gate conductive layer GT2.

[0287] In some examples, such as Figure 12 As shown, the first pixel circuit 31 also includes a fourth active pattern AP4 located in the semiconductor layer Poly.

[0288] In some examples, such as Figure 25 , Figure 29 and Figure 33 As shown, the second transparent conductive layer TC2 also includes a third connecting line CL3; along the second direction Y, the third connecting line CL3 is located between two adjacent first pixel circuits 31.

[0289] For example, the fourth active pattern AP4 of one of two adjacent first pixel circuits 31 is electrically connected to one end of the third connection line CL3 through a fourth via VH4. The capacitor pattern CP of the other of the two adjacent first pixel circuits 31 is electrically connected to the other end of the third connection line CL3 through another fourth via VH4.

[0290] For example, the third connecting line CL3 extends along the second direction Y.

[0291] A third connecting line CL3 connects the fourth active pattern AP4 of the first pixel circuit 31 and the capacitor pattern CP of the first pixel circuit 31 adjacent to it along the second direction Y. Since the third connecting line CL3 is a light-transmitting material, the light transmittance of the gap between two adjacent first pixel circuits 31 along the second direction Y is high, resulting in high light transmittance of the sub-display area A2. This allows the optical element 50 to receive sufficient light, thereby improving image quality. Furthermore, this arrangement allows both the fourth active pattern AP4 and the capacitor pattern CP in the first pixel circuit 31 to be electrically connected to the third connecting line CL3, enabling them to receive electrical signals from the third connecting line CL3, and ensuring that both receive the same electrical signal from the third connecting line CL3.

[0292] In some embodiments, such as Figures 28-31As shown, the second source / drain conductive layer SD2 includes a fourth connection line CL4 located in the sub-display area A2. Along the second direction Y, the fourth connection line CL4 is located between two adjacent third connection lines CL3 and connects the two adjacent third connection lines CL3.

[0293] For example, the fourth connecting line CL4 extends along the second direction Y.

[0294] For example, the third connecting line CL3 can be connected to the fourth connecting line CL4 through a via.

[0295] By adopting the above configuration, two adjacent third connection lines CL3 can be connected together, and multiple third connection lines CL3 connected to a column of first pixel circuits 31 can be interconnected through a fourth connection line CL4. This makes it easier to transmit signals on the third connection line CL3 to the corresponding column of first pixel circuits 31, simplifies the design of the display panel 10, and avoids sending electrical signals to each third connection line CL3 in the same column of first connection lines separately.

[0296] In some embodiments, such as Figure 31 As shown, along the second direction Y, multiple third connection lines CL3 and multiple fourth connection lines CL4 are alternately arranged and connected in sequence, configured to transmit a first voltage signal.

[0297] For example, the aforementioned multiple third connection lines CL3 and multiple fourth connection lines CL4 are connected in sequence to form the first voltage signal line VDD.

[0298] For example, the first voltage signal line VDD extends along the second direction Y. The first voltage signal line VDD is electrically connected to a column of first pixel circuits 31 through the fourth active pattern AP4 and the capacitor pattern CP, and transmits the first voltage signal to the column of first pixel circuits 31.

[0299] like Figure 33 As shown, when multiple third connection lines CL3 and multiple fourth connection lines CL4 are alternately arranged along the second direction Y to form the first voltage signal line VDD, the aforementioned fourth active pattern AP4 can be the active pattern of the first light-emitting control transistor T6, and the capacitor pattern CP can be the first plate of the aforementioned storage capacitor Cst.

[0300] In some embodiments, such as Figure 32 As shown, the first source / drain conductive layer SD1 further includes multiple Type 5 signal lines SL5 located in the main display area A1. The multiple Type 5 signal lines SL5 extend along the second direction Y and are electrically connected to each of the second pixel circuits 32 located in the same column.

[0301] In some examples, the fifth type signal line SL5 is connected to the first voltage signal line VDD, and the corresponding first pixel circuits 31 and second pixel circuits 32 are located in the same column.

[0302] For example, the fifth type signal line SL5 is used to transmit a first voltage signal to a column of second pixel circuits 32.

[0303] For example, the fifth type signal line SL5 is used to transmit an initial signal to a column of second pixel circuits 32. The fifth type signal line SL5 is electrically connected to the first voltage signal line VDD, so that the first voltage signal received by the same column of pixel circuits 30 in the display panel 10 is the same, and the light-emitting device 40 corresponding to the same column of pixel circuits 30 receives the same driving voltage, so that the display panel 10 can display the image normally.

[0304] For example, such as Figure 29 As shown, the second transparent conductive layer TC2 also includes a fifth connecting line CL5. The fifth connecting line CL5 is located between two adjacent first pixel circuits 31 in the second direction Y, and is used to connect the second terminal of the second reset transistor T2 of one of the first pixel circuits 31 to the second terminal of the second light-emitting control transistor T7 of the other first pixel circuit 31.

[0305] For example, such as Figure 34 As shown, the anode layer AND located in the sub-display area A2 includes multiple anodes AD.

[0306] For example, multiple anode ADs are electrically connected to corresponding multiple first pixel circuits 31. Specifically, the anode ADs are electrically connected to the second electrode of the second reset transistor T2 in the first pixel circuit 31, and the anode ADs are also electrically connected to the second electrode of the second light-emitting control transistor T7.

[0307] Of course, the aforementioned anode layer is also located in the main display area. Multiple anodes located in the main display area are electrically connected to the corresponding second pixel circuits. Specifically, the anodes are electrically connected to the second electrode of the second reset transistor T2 in the second pixel circuit, and are also electrically connected to the second electrode of the second light-emitting control transistor T7.

[0308] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, The display panel includes a main display area and a secondary display area, the main display area surrounding at least a portion of the secondary display area, and the light transmittance of the main display area being less than that of the secondary display area; The display panel includes a plurality of first pixel circuits located in the sub-display area. The plurality of first pixel circuits are arranged in multiple rows and columns, with each row of first pixel circuits arranged along a first direction and each column of first pixel circuits arranged along a second direction. The first direction and the second direction intersect; The display panel includes: Substrate; A first conductive layer is located on the substrate, and the plurality of first pixel circuits include conductive patterns located on the first conductive layer; A first signal line layer is located on the side of the first conductive layer away from the substrate and in the sub-display area. The first signal line layer includes a first type of signal line extending along the first direction. The first type of signal line is a continuous trace. The conductive pattern of each first pixel circuit located in the same row along the first direction is electrically connected to the same first type of signal line through a first via, wherein the first via is located on one side of the first pixel circuit along the first direction.

2. The display panel according to claim 1, characterized in that, The first vias corresponding to different first pixel circuits are all located on the same side of the first pixel circuit.

3. The display panel according to claim 1, characterized in that, The first conductive layer is a first gate conductive layer, the conductive pattern is a gate pattern, and the first signal line layer is a first transparent conductive layer.

4. The display panel according to claim 3, characterized in that, The first gate conductive layer includes a first via connection portion electrically connected to the gate pattern, the first via exposing the first via connection portion; the gate pattern is electrically connected to the first type of signal line through the first via connection portion; The first via connection portion is located on the side outside the area occupied by the first pixel circuit, or within the area occupied by the first pixel circuit.

5. The display panel according to claim 4, characterized in that, The first pixel circuit includes multiple gate patterns, and the multiple gate patterns are arranged in multiple columns along the first direction and in multiple rows along the second direction; The same row of gate patterns includes at least two gate patterns, which are electrically connected to the same first type of signal line through the same first via connection portion.

6. The display panel according to claim 5, characterized in that, The at least two gate patterns are integrally structured; and / or, The at least two gate patterns and the first via connection portion electrically connected to the at least two gate patterns are integrally structured.

7. The display panel according to claim 1, characterized in that, The first type of signal line includes at least one of a gate line, a reset signal line, and an enable signal line.

8. The display panel according to claim 1, characterized in that, The first type of signal line is located on the same layer in the sub-display area and is a continuous trace. The orthographic projection of the first type of signal line on the substrate overlaps with the orthographic projection of at least one of the plurality of first pixel circuits on the substrate.

9. The display panel according to claim 1, characterized in that, The first conductive layer is a first gate conductive layer; The display panel further includes a plurality of second pixel circuits located in the main display area; the first gate conductive layer further includes a second type of signal line located in the main display area; the second type of signal line extends along the first direction and is electrically connected to at least a portion of the plurality of second pixel circuits; First-class signal lines and second-class signal lines that transmit the same electrical signal are electrically connected.

10. The display panel according to claim 1, characterized in that, The display panel further includes: a semiconductor layer located on the side of the first conductive layer near the substrate; and a second light-transmitting conductive layer located on the side of the first signal line layer away from the substrate and located in the sub-display area, the second light-transmitting conductive layer including: a fourth type of signal line extending along the second direction; The first pixel circuit also includes a third active pattern located in the semiconductor layer; The third active pattern of each first pixel circuit located in the same column is electrically connected to the fourth type of signal line through a third via, the third via being located on one side of the first pixel circuit along the second direction.

11. The display panel according to claim 10, characterized in that, Each of the first pixel circuits is electrically connected to the fourth type of signal line through a third via, and the third vias of different first pixel circuits are all located on the same side of the first pixel circuit.

12. The display panel according to claim 10, characterized in that, The fourth type of signal line is located on the same layer in the sub-display area and is a continuous trace. The orthographic projection of the fourth type of signal line on the substrate overlaps with the orthographic projection of at least one of the plurality of first pixel circuits on the substrate.

13. The display panel according to claim 10, characterized in that, The semiconductor layer includes a third via connection portion electrically connected to the third active pattern, the third via exposing the third via connection portion, and the third active pattern being electrically connected to the fourth type of signal line through the third via connection portion; The third via connection portion is located on the side outside the area occupied by the first pixel circuit, or within the area occupied by the first pixel circuit.

14. The display panel according to claim 10, characterized in that, The fourth type of signal line includes data signal lines.

15. The display panel according to claim 10, characterized in that, The display panel further includes: a plurality of second pixel circuits located in the main display area, and a second source / drain conductive layer located on the side of the second light-transmitting conductive layer away from the substrate; The second source / drain conductive layer includes: a plurality of Type 5 signal lines located in the main display area; the plurality of Type 5 signal lines extend along the second direction and are electrically connected to at least a portion of the plurality of second pixel circuits; The fifth type of signal line and the fourth type of signal line are electrically connected.

16. The display panel according to claim 10, characterized in that, The first conductive layer is a first gate conductive layer; The display panel further includes: a second gate conductive layer located on the side of the first gate conductive layer away from the substrate; the first pixel circuit includes a capacitor pattern located on the second gate conductive layer. The first pixel circuit also includes a fourth active pattern located in the semiconductor layer; The second transparent conductive layer further includes: a third connecting line; along the second direction, the third connecting line is located between two adjacent first pixel circuits; The fourth active pattern of one of the two adjacent first pixel circuits is electrically connected to one end of the third connecting line through a fourth via. The capacitor pattern of the other of the two adjacent first pixel circuits is electrically connected to the other end of the third connecting line through another fourth via.

17. The display panel according to claim 16, characterized in that, The display panel further includes: a second source / drain conductive layer located on the side of the second transparent conductive layer away from the substrate; wherein the second source / drain conductive layer includes a fourth connection line located in the sub-display area; Along the second direction, the fourth connecting line is located between two adjacent third connecting lines and connects the two adjacent third connecting lines.

18. The display panel according to claim 17, characterized in that, Along the second direction, multiple third connecting lines and multiple fourth connecting lines are alternately arranged and connected in sequence, configured to transmit a first voltage signal.

19. The display panel according to any one of claims 1 to 18, characterized in that, The display panel also includes a plurality of second pixel circuits located in the main display area; Within a unit area, the area occupied by multiple second pixel circuits is greater than the area occupied by multiple first pixel circuits.

20. A display device, characterized in that, The display device includes: a display panel as described in any one of claims 1 to 19; And optical elements located on the non-light-emitting side of the display panel and in the sub-display area of ​​the display panel.

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