Apparatus and method

Abstract

The present disclosure relates to an apparatus and a method. The apparatus comprises address processing circuitry for detecting information related to an input memory address by reference to a respective chain of information entries provided by an address information table in a respective hierarchical table level of an ordered plurality of hierarchical table levels; the address processing circuitry is configured to select an address information table of a given table level in dependence on a base address, the base address depending on an earlier information entry in an address information table of an earlier table level of the ordered plurality of table levels earlier than the given table level; and the address processing circuitry is configured to select an information entry in the selected address information table in dependence on an offset component, the offset component depending on at least a portion of the input memory address applicable to the given table level, the offset component being defined such that successive instances of the portion of the input memory address indicate successive addressed information entries; the address processing circuitry comprises detector circuitry for detecting whether indicator data is set to indicate whether a set of one or more successive addressed information entries in the selected address information table provides at least one base address, the at least one base address indicating a position within a continuously addressed region of a plurality of address information tables including a later table level.

Description

Background Technology

[0001] This disclosure relates to data processing.

[0002] Memory management allows the construction of data processing systems with multiple virtual address mappings, enabling each application running on the operating system to have its own virtual memory mapping. Each application resides in a separate address space within physical memory. The MMU uses translation tables to map the memory addresses used by the applications (called virtual addresses) to physical addresses in memory. Translation tables can be, for example, hierarchical tree-like data structures created by software in memory.

[0003] MMU hardware typically traverses a translation table to perform virtual address translation. Traversing the translation table may involve performing several memory accesses to read the translation table.

[0004] Instead of transforming the data, a similar structure can be used to provide other information, such as attribute and / or permission data. Summary of the Invention

[0005] In one exemplary arrangement, an apparatus is provided, the apparatus comprising: An address processing circuit is used to detect information related to the input memory address by referring to a chain of corresponding information entries provided by address information tables in a plurality of ordered hierarchical levels. The address processing circuitry is configured to select an address information table for a given table level based on a base address, which depends on an earlier information entry in an address information table that is earlier than the given table level among a plurality of ordered table levels. Furthermore, the address processing circuit is configured to select an information entry in the selected address information table based on an offset component, which depends on at least a portion of the input memory address applicable to a given table level. The offset component is defined such that consecutive instances of portions of the input memory address indicate consecutively addressed information entries. The address processing circuit includes a detector circuit for detecting whether indicator data is set to indicate whether a group of one or more consecutively addressed information entries in a selected address information table provides at least one base address, which indicates a location within a region of consecutive addressing of multiple address information tables, including later table levels.

[0006] In another exemplary arrangement, a method is provided that includes: Information related to the input memory address is detected by referring to the chain of corresponding information entries provided by address information tables in an ordered hierarchical table system. For a given address information table at a given table level, information entries in the address information table of a table level later than the given level in the ordered plurality of hierarchical table levels are selected by a pointer defined by a base address and an offset component depending on at least a portion of the input memory address, the base address depending on the information entries in the given address information table, and the pointer being defined such that consecutive instances of the portion of the input memory address indicate consecutively addressed information entries; and The detection indicator data is set to indicate whether a set of one or more consecutive table entries in a given address information table provides the base address for a specified contiguously addressed region, which includes multiple address information tables at later table levels.

[0007] In another exemplary arrangement, a method is provided that includes: Generate information related to the input memory address; An address information table is generated in an ordered plurality of hierarchical table levels to provide information related to an input memory address, wherein, for a given address information table of a given table level, the address information table of the given table level can be selected by a base address, which depends on an earlier information entry in the address information tables of the ordered plurality of table levels prior to the given table level, and the information entry in the selected address information table can be selected according to an offset component, which depends on at least a portion of the input memory address applicable to the given table level, the offset component being defined such that consecutive instances of that portion of the input memory address indicate information for consecutive addressing, the generation step comprising: The detection can be used to store a certain amount of memory with multiple ordered hierarchical table levels to provide information related to the input memory address; The test checks whether a group of multiple address information tables at the same table level can be stored in contiguous memory regions within the detected memory; and When multiple address information tables of the same table level can be stored in contiguous memory regions, a set of one or more consecutive table entries is generated at a higher table level to provide the base address of the specified contiguously addressed region; and Store the address information table in memory.

[0008] In another exemplary arrangement, an apparatus is provided that includes: A processor circuit is configured to generate information related to an input memory address and to generate an address information table in an ordered plurality of hierarchical table levels to provide information related to the input memory address, wherein, for a given address information table of a given table level, the address information table of the given table level can be selected by a base address, which depends on an earlier information entry in an address information table of an ordered plurality of table levels prior to the given table level, and the information entry in the selected address information table can be selected according to an offset component, which depends on at least a portion of the input memory address applicable to the given table level, the offset component being defined such that consecutive instances of that portion of the input memory address indicate information for consecutive addressing; The processor circuit is configured to detect a certain amount of memory available for storing multiple ordered hierarchical table levels to provide information related to the input memory address, and to detect whether a set of multiple address information tables at the same table level can be stored in a contiguous memory region within the detected amount of memory; and when the set of multiple address information tables at the same table level can be stored in a contiguous memory region, to generate a set of one or more consecutive table entries at a higher table level to provide the base address of the specified contiguously addressed region; and The memory is used to store the address information table.

[0009] In another exemplary arrangement, a computer program is provided for controlling a host data processing device to provide an instruction execution environment, and includes: An address processing circuit is used to detect information related to the input memory address by referring to a chain of corresponding information entries provided by address information tables in a plurality of ordered hierarchical levels. The address processing circuitry is configured to select an address information table for a given table level based on a base address, which depends on an earlier information entry in an address information table that is earlier than the given table level among a plurality of ordered table levels. Furthermore, the address processing circuit is configured to select an information entry in the selected address information table based on an offset component, which depends on at least a portion of the input memory address applicable to a given table level. The offset component is defined such that consecutive instances of portions of the input memory address indicate consecutively addressed information entries. The address processing circuit includes a detector circuit for detecting whether indicator data is set to indicate whether a group of one or more consecutively addressed information entries in a selected address information table provides at least one base address, which indicates a location within a region of consecutive addressing of multiple address information tables, including later table levels.

[0010] Further corresponding aspects and features of this technology are defined by the appended claims. Attached Figure Description

[0011] The present invention will be further described by way of example only, with reference to embodiments shown in the accompanying drawings, wherein: Figure 1 The data processing system is illustrated schematically. Figure 2 A two-stage MMU is schematically illustrated; Figure 3 The use of the memory management unit (MMU) and translation backup buffer (TLB) is illustrated schematically; Figure 4 This is a schematic flowchart illustrating one method; Figure 5 The so-called Page Table Walkthrough (PTW) process is illustrated schematically; Figure 6 This is a schematic flowchart illustrating one method; Figures 7 to 10 The table-level set is illustrated schematically; Figure 11 A portion of the input address is shown schematically; Figure 12 and Figure 13 It is a schematic flowchart illustrating the corresponding method; and Figure 14 The specific implementation of the simulator is illustrated schematically. Detailed Implementation

[0012] Before discussing the implementation scheme with reference to the accompanying drawings, the following description of the implementation scheme is provided.

[0013] An exemplary embodiment provides an apparatus comprising: An address processing circuit is used to detect information related to the input memory address by referring to a chain of corresponding information entries provided by address information tables in a plurality of ordered hierarchical levels. The address processing circuitry is configured to select an address information table for a given table level based on a base address, which depends on an earlier information entry in an address information table that is earlier than the given table level among a plurality of ordered table levels. Furthermore, the address processing circuit is configured to select an information entry in the selected address information table based on an offset component, which depends on at least a portion of the input memory address applicable to a given table level. The offset component is defined such that consecutive instances of portions of the input memory address indicate consecutively addressed information entries. The address processing circuit includes a detector circuit for detecting whether indicator data is set to indicate whether a group of one or more consecutively addressed information entries in a selected address information table provides at least one base address, which indicates a location within a region of consecutive addressing of multiple address information tables, including later table levels.

[0014] This disclosure provides a possible improvement to the way tables of the aforementioned type are generated and / or stored and / or accessed by providing indicator data that can be used to indicate the mapping between a consecutive set of one or more entries in a table and a consecutive region at a later table level. This can be used to improve the efficiency of caching, for example, information related to table access, by potentially allowing information associated with multiple entries to be covered by a smaller number (such as one) of cache entries. In some cases, the arrangement may allow one or more table levels to be omitted.

[0015] In an exemplary arrangement, the last information entry in the chain of information entries provided by the address information table of the last table level in an ordered plurality of hierarchical table levels defines information related to the input memory address.

[0016] This disclosure applies to various types of information associated with input memory addresses, which may be expressed in the form of an ordered hierarchical structure of tables. One example is a case where address processing circuitry includes address translation circuitry for performing address translation, wherein the information associated with the input memory addresses at least defines the address translation between the input memory address in the input address space and the translated output memory address in the output address space. In the context of memory address translation, this disclosure may be applied to any one or more stages of a single-stage or multi-stage translation, such that in an exemplary arrangement, the input memory address is one of a virtual memory address and an intermediate physical address; and the output memory address is one of an intermediate physical address and a physical address.

[0017] Another example is an address processing circuit that includes permission circuitry, where information related to the input memory address at least defines the access permissions associated with the input memory address.

[0018] In some examples, indicator data can be configured to indicate whether a set of one or more consecutive table entries in a selected address information table provides the corresponding base address, which indicates a set of consecutively addressed address information tables in an ordered hierarchy of table levels. This allows for potentially more efficient table access, especially when cached access information such as table base addresses is involved.

[0019] Therefore, these techniques are particularly suitable for arrangements with cache memory (such as so-called "walk-through cache") to store data representing information entries retrieved from an address information table by address processing circuitry, wherein the cache memory is configured to store data representing a single base address for a set of one or more consecutively addressed information entries, and to detect indicator data to be set for that set of one or more consecutively addressed information entries.

[0020] If the use of indicator data allows for the omission of one or more table levels, specific improvements in table storage and / or access can be achieved, for example, in an arrangement where the indicator data is configured to indicate whether an entry in a selected address information table provides a base address for a region of sequential addressing, which includes multiple address information tables of table levels following the next table level in an ordered plurality of hierarchical table levels. In such an example, address processing circuitry may be configured to select an entry in the address information table of the table level following the next table level in an ordered plurality of hierarchical table levels in response to accessing an entry in the selected table level that sets the indicator data. To correctly address the table at that later level, in an exemplary arrangement, the address processing circuitry is configured to select an entry in the address information table of the table level following the next table level after the given level based on an offset component that depends at least on a corresponding portion of the input memory address associated with the given table level and the table level following the given table level.

[0021] Another exemplary implementation provides a method comprising: Information related to the input memory address is detected by referring to the chain of corresponding information entries provided by address information tables in an ordered hierarchical table system. For a given address information table at a given table level, information entries in the address information table of a table level later than the given level in the ordered plurality of hierarchical table levels are selected by a pointer defined by a base address and an offset component depending on at least a portion of the input memory address, the base address depending on the information entries in the given address information table, and the pointer being defined such that consecutive instances of the portion of the input memory address indicate consecutively addressed information entries; and The detection indicator data is set to indicate whether a set of one or more consecutive table entries in a given address information table provides the base address for a specified contiguously addressed region, which includes multiple address information tables at later table levels.

[0022] Another exemplary implementation provides a method comprising: Generate information related to the input memory address; An address information table is generated in an ordered plurality of hierarchical table levels to provide information related to an input memory address, wherein, for a given address information table of a given table level, the address information table of the given table level can be selected by a base address, which depends on an earlier information entry in the address information tables of the ordered plurality of table levels prior to the given table level, and the information entry in the selected address information table can be selected according to an offset component, which depends on at least a portion of the input memory address applicable to the given table level, the offset component being defined such that consecutive instances of that portion of the input memory address indicate information for consecutive addressing, the generation step comprising: The detection can be used to store a certain amount of memory with multiple ordered hierarchical table levels to provide information related to the input memory address; In the memory of the detected quantity, a set of multiple address information tables at the same table level can be stored in contiguous memory regions; and When multiple address information tables of the same table level can be stored in contiguous memory regions, a set of one or more consecutive table entries is generated at a higher table level to provide the base address of the specified contiguously addressed region; and Store the address information table in memory.

[0023] Another exemplary embodiment provides an apparatus comprising: A processor circuit is configured to generate information related to an input memory address and to generate an address information table in an ordered plurality of hierarchical table levels to provide information related to the input memory address, wherein, for a given address information table of a given table level, the address information table of the given table level can be selected by a base address, which depends on an earlier information entry in an address information table of an ordered plurality of table levels prior to the given table level, and the information entry in the selected address information table can be selected according to an offset component, which depends on at least a portion of the input memory address applicable to the given table level, the offset component being defined such that consecutive instances of that portion of the input memory address indicate information for consecutive addressing; The processor circuit is configured to detect a certain amount of memory available for storing multiple ordered hierarchical table levels to provide information related to the input memory address, and to detect whether a set of multiple address information tables at the same table level can be stored in a contiguous memory region within the detected amount of memory; and when the set of multiple address information tables at the same table level can be stored in a contiguous memory region, to generate a set of one or more consecutive table entries at a higher table level to provide the base address of the specified contiguously addressed region; and The memory is used to store the address information table.

[0024] Another exemplary embodiment provides a computer program for controlling a host data processing device to provide an instruction execution environment, and includes: An address processing circuit is used to detect information related to the input memory address by referring to a chain of corresponding information entries provided by address information tables in a plurality of ordered hierarchical levels. The address processing circuitry is configured to select an address information table for a given table level based on a base address, which depends on an earlier information entry in an address information table that is earlier than the given table level among a plurality of ordered table levels. Furthermore, the address processing circuit is configured to select an information entry in the selected address information table based on an offset component, which depends on at least a portion of the input memory address applicable to a given table level. The offset component is defined such that consecutive instances of portions of the input memory address indicate consecutively addressed information entries. The address processing circuit includes a detector circuit for detecting whether indicator data is set to indicate whether a group of one or more consecutively addressed information entries in a selected address information table provides at least one base address, which indicates a location within a region of consecutive addressing of multiple address information tables, including later table levels.

[0025] Data processing using memory address translation Now refer to the attached diagram, Figure 1 A data processing system is schematically illustrated. A processing element (PE) 100 with local cache memory 105 is arranged to access data stored in main memory 110 via interconnect 120. A memory management unit (MMU) 130 is connected to interconnect 120 to handle memory address translation. The MMU is associated with a translation table base address (TTBR) register 135, a translation control unit (TCU) 132, and a walkthrough cache 137, which will be discussed further below.

[0026] PE 100 and / or MMU utilize a conversion backup buffer (TLB). In this example of the invention, TLB 102 is provided as part of PE 100. Figure 1 During system operation, there are routines that require access to system memory. For internal processing within the PE100 modules, memory addresses are represented as virtual addresses (VAs). To actually access system memory, the VA needs to be translated into a physical address (PA), through which the system memory is addressed at levels. This translation is performed by the TLB, but if the TLB cannot service a particular translation, it obtains information from the MMU, as described below. (Refer to...) Figure 2 and Figure 3 The operation of the TLB is discussed further. TLB 102 provides an example of a translation buffer used to store data that defines one or more address translations between the virtual address space and the physical address space.

[0027] It should be noted that although TLB is Figure 1 The TLB is shown as part of PE 100, but it can also be implemented as part of MMU 130, or in other implementations, TLB functionality can be provided at both PE 100 and MMU 130. In some examples, PE 100 may be associated with a so-called “micro” TLB local to that PE, and the MMU may be associated with a “master” TLB.

[0028] The L2 cache 140 provides a local and generally slightly faster storage area for selected content in the main system memory. Recently or frequently accessed portions of the main system memory, or portions of the main system memory expected to be needed in the near future, such as portions adjacent to recently accessed portions, are copied into the L2 cache 140 so that those portions can be quickly accessed when needed. If the required portion is not currently held in the L2 cache 140, it is retrieved from the main system memory when needed. In these respects, the L2 cache 140 operates according to established principles associated with such cache memories, and therefore details of its operation will not be described unless they are relevant to the discussion of this invention. It should be noted that the contents of the L2 cache memory 140 are accessed according to their physical addresses.

[0029] like Figure 2 As shown, MMU 130 can be a two-stage MMU (as an example of a multi-stage MMU), comprising a stage 1 MMU 134 and a stage 2 MMU 136. Virtual addresses (VAs) required by the executor or other system modules such as PE 100 are translated into intermediate physical addresses (IPAs) by the stage 1 MMU. Memory accesses are schematically shown for performing page table walkthroughs, etc. IPAs are translated into physical addresses (PAs) by the stage 2 MMU. One reason for using multi-stage translation is for information processing security when multiple operating systems (OSs) can be used on corresponding "virtual machines" running on the same processor. A specific OS is exposed to the VA-to-IPA translation, while only the hypervisor (the software monitoring the operation of the virtual machine) has supervision over the stage 2 (IPA-to-PA) translation.

[0030] It should be noted that, although Figure 2 The concept shows how a two-stage MMU operates, but in practice, a single circuit structure (represented by dashed box 138) can perform the two transition stages, for example, by implementing a state machine capable of handling both.

[0031] In some examples (not shown here), the third or other stages may also use techniques similar to those discussed, since page table-based methods can be used to obtain permission data, attribute data, or other data associated with the translated address or other addresses. Therefore, in general, the technology of this invention can be considered to relate to address processing circuitry for detecting information associated with an input memory address, where the "information" can be a fully or partially translated or other information such as permission data, attribute data, or other data, and the "input memory address" can be PA, IPA, VA, or other input address, and (in the case of translation) the output memory address can be IPA or PA.

[0032] A key reason for needing the MMU 130 is its ability to handle address translations not currently stored in the TLB 102. The method for performing this operation will be discussed further below. For more information on handling these issues, please refer to [link to relevant documentation]. Figure 3 MMU 130 receives request 222 from TLB via interconnect 120 and returns response 232 to TLB again via interconnect 120.

[0033] As part of the operation of PE 100 or other arrangements associated with TLB 102, TLB 102 receives VA 200 associated with a desired memory access. This can, of course, be a read or write memory access; the type of memory access being performed is not important to the present discussion. TCU 132 handles translations not in TLB 102, for example, by initiating a so-called page table walkthrough.

[0034] See also Figure 4 (This diagram is a schematic flowchart illustrating the operation of the TLB), supplying VA 200 to TLB 102 forms a request for the corresponding PA 210. Figure 4 (This is shown as step 400).

[0035] At least in the context of an exemplary single-stage MMU, the TLB contains a cache or repository of translations between VA and PA. The criteria for the TLB to store specific VA-to-PA translations can be established based on known techniques for operating the TLB. Cached translations may include recently used translations, frequently used translations, and / or translations expected to be needed soon (such as translations related to VAs close to the most recently accessed VA). In short, the situation is that the TLB contains a cache of a subset of all possible VA-to-PA translations, such that when a specific VA-to-PA translation is needed, it can be found that the translation has already been stored in the cache at the TLB, or that the translation may not need to be stored. Note that in a two-stage MMU, there may be one or more TLBs for VA-to-PA translations, VA-to-IPA translations, and IPA-to-PA translations.

[0036] Therefore, at the next step 410, the TLB checks whether the required translation is indeed currently cached by the TLB (“hit”). If the answer is “yes”, control is passed to step 440, where PA is returned for the required memory access.

[0037] If the answer is "no", control is passed to step 420, where TLB 102 sends a request including the required VA 222 to MMU 130 (if TLB 102 is outside MMU 130) and specifically to TCU 132. TCU 132 derives the required VA to PA translation (e.g., by accessing the data stored in memory using the so-called Page Table Walkthrough (PTW) technique discussed below) and at least sends the PA 232 corresponding to VA 222 back to TLB 102, where it is stored at step 430.

[0038] Finally, at step 440, TLB 102 applies the conversion stored at TLB 102 to provide output PA 210.

[0039] In the context of a multi-stage MMU, a single TLB can be provided for the overall VA to PA transition, and / or individual TLBs can be provided for each MMU stage. In either case, the operation of the TLB can correspond to... Figure 4 The operation is shown in the TLB, which contains other information about type conversion or cache.

[0040] Therefore, in these implementations, the MMU provides examples of "address processing circuitry" that includes address translation circuitry for performing address translation, wherein information associated with the input memory address at least defines the address translation between the input memory address in the input address space and the translated output memory address in the output address space. In other examples, the "address processing circuitry" may include access control circuitry, wherein information associated with the input memory address at least defines the access permissions associated with the input memory address.

[0041] Page List Review The PTW process involves traversing a hierarchical set of so-called page tables to reach a specific VA. In the case of single-stage memory translation, the output can be a PA. In the case of multi-stage memory address translation, the process can be more complex. Accessing the page table itself requires a PA, so a translation stage may be needed to obtain the PA of the next required table at each access to the next table in the hierarchy. As mentioned above, Figure 5 An example of a Phase 1 Page Walkthrough (PTW) process is illustrated schematically, and Figure 6This is a schematic flowchart illustrating the PTW process.

[0042] In this example, the VA 222 that needs to be converted is formed as a 48-bit value. Different parts of VA 222 are used at different levels during the PTW process. Figure 5 The partitions of these sections are shown only through illustrative examples.

[0043] In the context of the process described below, walkthrough cache 137 may store information obtained from previously implemented page table access instances (e.g., for a multi-stage MMU, that is, its storage of IPA, PA, or both). Therefore, before initiating any particular page table access, the walkthrough cache (or a portion of the walkthrough cache or a dedicated, separate walkthrough cache associated with the page table level in question) can be consulted, and if the information to be obtained from that page table access is already in the walkthrough cache, this avoids the need to perform a specific access to memory.

[0044] To obtain the first entry in the page table hierarchy, in "Level 0 Table" 310, in step 600 ( Figure 6 Obtain the storage at the corresponding location Figure 1 The base address register 300 of the TTBR 135 ( Figure 5 The base address in the table is used. At step 610, the first part 312 of VA 222, which is, for example, the nine most significant bits, is added as an offset to the base address to provide the IPA of entry 314 in table 310. However, in order to access entry 314 indicated by this IPA, a PA indicating the location of the entry in physical memory is required. Therefore, at step 620, the IPA of page table entry 314 is supplied to the stage 2 translation process to be translated into the corresponding PA. When the corresponding PA is received, at step 630, the relevant page table entry is searched in physical memory or in the level 2 walkthrough cache 137 (if the relevant page is cached).

[0045] At step 640, it is checked whether "Level 3" has been reached in the page table hierarchy. If "No," as in the current case, control is passed to step 650, where the retrieved page table entry is used as the base address of the next table in the hierarchy. Therefore, page table entry 314 provides the base address to the next-level table "Level 1 table" 320 in the hierarchy. Control returns to step 610.

[0046] In the second iteration of step 610, another portion 322 of VA 222, for example, the next 9 bits [38:30] of VA 222, forms an offset relative to the base address of table 320 to provide the IPA for entry 324 in table 320. Again, this IPA undergoes a stage 2 transformation to provide a PA that can be looked up to obtain the base address of “level 2 table” 330, which in turn (by the same process) provides the base address of “level 3 table” 340. Portions 332 and 342 of VA form offsets in the level 2 and level 3 tables, respectively.

[0047] When steps 630 and 640 are performed with respect to the page table entry defined by IPA 344 in Table 340, the response to the detection at step 640 is "yes". The page table entry indicated by IPA 344 provides the page address and access permissions associated with the physical memory page. The remaining portion 352 of VA 222 (e.g., the least significant 12 bits [11:0]) provides a page offset 502 to the target address 500 within the memory page defined by the page table entry at IPA 344, but in an exemplary system where information is stored as a contiguous four-byte (e.g., 32-bit) portion, it may be a portion [11:2] providing the required offset to the address of the appropriate 32-bit word. Therefore, the combination of the least significant portion of VA 222 and the final page table entry (in this case, from "Level 3 Table" 340) (at step 660) provides (at step 670) IPA 250 as a translation of VA 222. It should be noted that, as generally described herein, the PTW procedure returns an IPA for PTW performed with respect to the Phase 1 MMU, and returns a PA separately for PTW performed with respect to the Phase 2 MMU.

[0048] The page entry indicated by IPA 344 provides an example of the last information entry in the information entry chain, provided by the address information table of the last table level in an ordered series of hierarchical table levels, which defines information related to the input memory address (in this example, translation).

[0049] In exemplary embodiments, including some embodiments discussed below, a first MMU level is configured to access a hierarchical structure of page tables such that higher page tables in the hierarchy provide information for address translation by a second-level MMU to point to lower page tables in the hierarchy, and the lowest page table in the hierarchy provides a set of two or more intermediate memory addresses including corresponding intermediate memory addresses.

[0050] However, it should be understood that a comparison can be made. Figure 5 and Figure 6 The number of PTW levels shown is either more or less.

[0051] Figure 7 It is by Figure 5 This diagram illustrates a portion of the chain of information entries provided by the address information tables in adjacent levels of the hierarchical table.

[0052] As described above, a given table-level address information table or page table can be selected based on a base address, which depends on an earlier information entry in an ordered set of page tables. Therefore, for example, in... Figure 5 In this context, the address given by entry 314 provides the base address for table 320, and the address given by entry 324 provides the base address for table 330, and so on.

[0053] Within the selected table, information entries or page table entries can be selected based on an offset component (relative to the base address) that depends on at least a portion of the input memory address. This portion can be applied to a given table level; for example, portion 312 can be applied to... Figure 5 The level 0 table in the 322 table is partially applicable. Figure 5 The first-level table, etc. An offset component is defined such that consecutive instances of that portion of the input memory address indicate consecutively addressed information entries. Note here that the addressing of an information entry or page table entry can refer to the physical address of that page table entry (e.g., in...). Figure 5 (as in the example), or it could refer to the IPA of the page table entry, which itself requires another level of transformation.

[0054] See Figure 7 The example shows table 700 at a specific table level (n). Here, in a four-level (0…3) system, n can be, for example, 0, 1, or 2. Each entry 710 in table 700 points to the corresponding table at the next level (n+1) and provides the base addresses 720, 722, 724, 726 of the corresponding tables 730, 732, 734, 736 at level n+1 (possibly undergoing stage 2 transformation). Figure 7 For clarity, only four such associations between entry 710 and base addresses 720…726 are shown, but the situation may be that each entry 710 in table 700 links to the corresponding next-level table.

[0055] Based on the base address 705 of the table for level (n), the offset component 712 determines which entry 710 to query. The offset component is derived from at least a portion of the input memory address applicable to level (n). Similarly, the offset 740 applicable to selecting an entry in any of the tables 730…736 is derived from at least a portion of the input memory address applicable to level (n+1).

[0056] Example - Indicator data for adjacent table levels Figure 8 An example of using so-called indicator data in the context of adjacent table levels is illustrated.

[0057] exist Figure 8 In the middle, it is shown that... Figure 7 The same four tables 730…736 are used, but the difference here is that they are pointed to by consecutive table entries 800 in table 700 of level (n). In addition, tables 730…736 of level (n+1) are addressed consecutively, such that base address 722 is located after the last entry of table 730, and so on.

[0058] Indicator data 810, schematically shown as data fields (such as one or more bits at predetermined bit positions) within each table entry of table 700, can be set to indicate this condition. Here, "settable" means that the indicator data can be set to a specific state to indicate that the condition applies, and set to another state to indicate that the condition does not apply. It should also be noted that the indicator can be a single bit used to indicate that a predetermined number of entries are consecutive, or it can be selected from one of several different consecutive ranges, such as a power of 2, or a count of the number of consecutive entries. Thus, in one example, a group of table entries comprising four table entries 800 in table 700 may contain at least the following information. Surrounding table entries 801, 804 are also shown, where entries are... Figure 8 The vertical order shown is given below:

[0059] This in itself will not necessarily reduce the number of entries provided for Table 700. However, the potential benefits are as follows.

[0060] If no indicator data is detected, each entry in table 700 will occupy the corresponding entry in the walkthrough cache (or the walkthrough cache or a portion of the walkthrough cache applicable to level (n)) upon its first access. TCU 132 can be responsible for writing data to walkthrough cache 137 and controlling the reading of walkthrough cache 137 when the table needs to be accessed. For example, a walkthrough cache entry for a table entry in table entry 800 can indicate...

[0061] When a particular offset portion requires PTW, a lookup in the walkthrough cache indicates the base address required by the next-level table.

[0062] However, in response to the detection of indicator data, this set of entries 800 can be represented by a single entry in the walkthrough cache, as shown below:

[0063] This provides an example in which a cache memory (in this example, a walkthrough cache) is arranged to store data representing information entries retrieved from an address information table by address processing circuitry; wherein the cache memory is configured to store data representing a single base address for a set of one or more consecutively addressed information entries, and to detect that indicator data will be set for the set of one or more consecutively addressed information entries.

[0064] Therefore, when any entry in entry 800 requires a PTW walkthrough, a single walkthrough cache entry indicates the range of offset components for accessing any entry in entry 800, and the corresponding range of table addresses at level (n+1) applies. Thus, for a group of consecutive entries 800 in the table at level (n), only a single walkthrough cache entry is required.

[0065] By using the walkthrough cache more effectively, the probability of a cache hit can be increased for a given size. An increased probability of cache hits means that a larger proportion of PTW operations can be performed from the walkthrough cache rather than from more expensive memory accesses, and thus can improve overall system efficiency and / or throughput and / or power consumption.

[0066] Therefore, in this context, this provides an example where indicator data can be set to indicate whether a group 800 of one or more consecutively addressed information entries in a particular table 700 provides at least one base address indicating a location within a consecutively addressed region 820, which includes multiple address information tables at later table levels (level (n+1) in this example).

[0067] Example - Indicator data references a later table level Now for reference Figure 9 An exemplary table 900 of level (m) contains an exemplary entry 905 that provides the base address 910 of the next level (m+1) table 920. Here, in a four-level (0…3) system, m can be, for example, 0 or 1.

[0068] Each entry 925 in table 920 points to a corresponding table 930 at another next level (m+2). The arrangement is such that consecutive entries 925 point to corresponding consecutively addressed instances of table 930, and each entry 925 points to a corresponding table 930 in the address space region containing that set of tables 930.

[0069] Reference Figure 10A variation of this arrangement is described, wherein indicator data is configured to indicate whether an information entry in a selected address information table provides a base address for a region that is consecutively addressed, the region comprising multiple address information tables in an ordered hierarchy of table levels, the next table level following the previous table level.

[0070] Specifically, the technology of the present invention can provide a rationalization of the table structure because, in table 900 at level (m), a single entry 1000 can provide a pointer 1010 to the base address 1020 of the entire region 1030 of level (m+2) containing all consecutively addressed tables 930.

[0071] Offset 1040 from base address 1020 is derived as follows: Offset = [Address portion applicable to level (m)] cascade [Address portion applicable to level (m+1)] The following will refer to Figure 11 Provide and describe specific examples.

[0072] An example of the content of entry 1000, which includes configurable indicator data, is as follows:

[0073] Here, the indicator data is configured to indicate whether a set of one or more consecutive table entries (level (n)) in the selected address information table provides a corresponding base address, which indicates a set of consecutively addressed address information tables in the next table level (n+1) of an ordered plurality of hierarchical table levels.

[0074] This provides another example in which a cache memory (in this example, a walkthrough cache) is arranged to store data representing information entries retrieved from an address information table by address processing circuitry; wherein the cache memory is configured to store data representing a single base address for a set of one or more consecutively addressed information entries, and to detect that indicator data will be set for the set of one or more consecutively addressed information entries.

[0075] Therefore, when entry 1000 requires a PTW walkthrough, the single walkthrough cache entry indicating the next level (m+1) table is completely omitted. Thus, only a single walkthrough cache entry is needed for entry 1000 to provide the base address of all tables 1030 at level (m+2). In other words, the address processing circuitry is configured to, in response to accessing the information entry containing the set indicator data in the selected table level, select the information entry in the address information table of the next table level after the given level from a plurality of ordered hierarchical table levels.

[0076] By using the walkthrough cache more effectively, the probability of a cache hit can be increased for a given size. An increased probability of cache hits means that a larger proportion of PTW operations can be performed from the walkthrough cache rather than from more expensive memory accesses, and thus can improve overall system efficiency and / or throughput and / or power consumption.

[0077] Therefore, this arrangement provides an example in which indicator data is set to indicate whether a group of one or more consecutively addressed information entries (in this example, a single entry 1000) in table 900 provides at least one base address 1020, which indicates a location within a consecutively addressed region 1030 including multiple address information tables at the later (m+2) table level.

[0078] It should also be noted that these two techniques can be combined; for example, indicator data identifiers can also skip a set of consecutive entries at one or more table levels.

[0079] As a working example of the aforementioned offset addressing. Figure 11 Provided similar Figure 5 The representation shown in 222, where the first part 312 of the input address forms an index to the level 0 table, and the second part 322 provides an index to the level 1 table, in this example, the index has a similar structure to... Figure 10 The entry 1000 in the table at level (m) is shown. Therefore, the offset provided by the level 1 index points to entry 1000. The indicator data set for entry 1000 omits level 2, such that the address provided by entry 1000 provides pointer 1010 to the base address 1020 of the level 3 table (level m+2).

[0080] In these examples, the address processing circuitry is configured to select an information entry in the address information table of the next table level (m+1) after a given level (m) (such as m+2 or even further) based on an offset component, which depends at least on the corresponding portion of the input memory address associated with the given table level and the table level following that given table level.

[0081] Therefore, instead Figure 5 The separated portions 322 and 342, and portion 346 (i.e., bits [29:12]) are used as offset 1040 within the region 1030 defined by pointer 1010, which is consistent with... Figure 5 The cascade of the 2nd and 3rd level related parts 332 and 342.

[0082] It should be understood that this arrangement can be used to skip or omit more than one level, such that (in an exemplary four-level (0…3) system) a level 0 table entry can be accompanied by indicator data to indicate the address of, for example, a level 3 table. In this case, the relevant offset will be formed by the TCU as follows: Offset = [address portion applicable to level (0)] cascade [address portion applicable to level (1)] cascade [address portion applicable to level (2)] (or Figure 5 The VA bit in the representation [47:21]) Figure 12 This is a schematic flowchart illustrating an exemplary method for generating and storing page table data, wherein indicator data as described above is optionally used. See also Figure 12 Step 1200 involves generating information associated with the input memory address. In this example, the information relates to address mapping, but any other data that can be represented as a page table hierarchy may be applied alternatively or additionally. Step 1200 also includes generating a table representation, for example, involving generating an address information table in an ordered plurality of hierarchical table levels to provide information associated with the input memory address, wherein, for a given address information table of a given table level, the address information table of the given table level can be selected by a base address that depends on an earlier information entry in the address information tables of the ordered plurality of table levels prior to the given table level, and the information entries in the selected address information table can be selected according to an offset component that depends on at least a portion of the input memory address applicable to the given table level, the offset component being defined such that consecutive instances of that portion of the input memory address indicate information of consecutive addressing. The generation process may include step 1220, which involves detecting a certain amount of memory available for storing multiple ordered hierarchical table levels to provide information related to input memory addresses, and detecting whether, within the detected amount of memory, a set of multiple address information tables of the same table level can be stored in contiguous memory regions.

[0083] The result of step 1220 can be "No". In this case, control is passed to step 1230, and... Figure 7 Generate page tables in the specified format.

[0084] However, if the answer at step 1220 is "yes", then one or both steps 1240 and 1250 can be applied, for example, to different corresponding groups of tables and / or levels within the entire structure. These steps all involve the use of indicator data: step 1240 uses... Figure 8 The technology, and step 1250 uses Figure 10These technologies share the following characteristics: when multiple address information tables of the same table level can be stored in contiguous memory regions, a set of one or more consecutive table entries is generated at a higher table level to provide the base address of the specified contiguously addressed region.

[0085] Finally, in step 1260, the address information table is stored in memory.

[0086] For example, Figure 12 The process can be performed by PE 100 at, for example, startup time. In this regard, PE 100, in conjunction with memory 110, provides an example of processor circuitry for generating information related to input memory addresses and generating address information tables in an ordered plurality of hierarchical table levels to provide information related to input memory addresses, wherein, for a given address information table of a given table level, the address information table of the given table level can be selected by a base address, which depends on an earlier information entry in the address information tables of the ordered plurality of table levels prior to the given table level, and the information entry in the selected address information table can be selected according to an offset component, which depends on at least a portion of the input memory address applicable to the given table level, the offset component being defined such that consecutive instances of that portion of the input memory address indicate information for consecutive addressing; The processor circuit is configured to detect a certain amount of memory available for storing multiple ordered hierarchical table levels to provide information related to the input memory address, and to detect whether a set of multiple address information tables at the same table level can be stored in a contiguous memory region within the detected amount of memory; and when the set of multiple address information tables at the same table level can be stored in a contiguous memory region, to generate a set of one or more consecutive table entries at a higher table level to provide the base address of the specified contiguously addressed region; and The memory is used to store the address information table.

[0087] Figure 13 This is a schematic flowchart illustrating an application that includes a possible combination of the above-described techniques. This forms part of a method for detecting information related to an input memory address by referring to a chain of corresponding information entries provided by address information tables in an ordered hierarchy of tables.

[0088] It should be understood that Figure 8 The indicator data can be compared with Figure 10 The indicator data can be used together or not used with the indicator data of the diagram, so that each arrangement is available on its own without using other arrangements. Figure 13 The example provides two types of indicator data, such as different indicator values ​​as public indicator data fields.

[0089] exist Figure 13 In step 1300, a specific table entry is detected. This may involve, for a given address information table at a given table level, selecting an information entry in the address information table of a table level later than the given level in an ordered plurality of hierarchical table levels by means of a pointer defined by a base address and an offset component depending on at least a portion of the input memory address, the base address depending on the information entry in the given address information table, the pointer being defined such that consecutive instances of that portion of the input memory address indicate consecutively addressed information entries.

[0090] At step 1310, it is checked whether indicator data is set. The results here are: indicator data is not set (path 1312), indicator data is set to indicate a set of consecutive entries (result 1314), or indicator data is set to indicate skipping or omitting one or more levels (result 1316). This means checking whether indicator data is set to indicate whether a set of one or more consecutive table entries in a given address information table provides an example of the base address of a specified contiguously addressed region, which includes multiple address information tables at later table levels.

[0091] In the case of result 1312, the entry of the known type is stored in the walkthrough cache at step 1320, and the next table level is accessed at step 1330.

[0092] Based on result 1314, at step 1340, refer to the above. Figure 8 One or more entries of the type discussed in the description are stored in the walkthrough cache, and control is passed to step 1330.

[0093] Result 1316 leads to step 1350, where the entry indicating the state of the current table entry and indicator data is stored in the walkthrough cache, and in step 1360, the above reference is used. Figure 10 The described technique is used to access other table levels (beyond the next table level).

[0094] Figure 14A specific implementation of a usable simulator is illustrated. While the previously described embodiments implement the invention in terms of means and methods for operating specific processing hardware supporting the technologies involved, an instruction execution environment according to the embodiments described herein can also be provided, which is implemented using a computer program. Such computer programs are generally referred to as simulators, in part because they provide a software-based implementation of a hardware architecture. Types of simulator computer programs include emulators, virtual machines, models, and binary converters, including dynamic binary converters. Typically, a simulator implementation can run on a host processor 1730 that supports the simulator program 1710, which optionally runs a host operating system 720. In some arrangements, multiple emulation layers may exist between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors were required to provide simulator implementations that execute at a reasonable speed, but this approach may be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, a simulator implementation may provide additional functionality to the instruction execution environment that is not supported by the host processor hardware, or provide an instruction execution environment that is typically associated with a different hardware architecture. An overview of the simulation is given in the following literature: “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0095] With respect to embodiments previously described with reference to specific hardware constructions or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructions or features. For example, a particular circuit system may be implemented as computer program logic in a simulated embodiment. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in a simulated embodiment. One or more of the hardware elements referenced in the previously described embodiments are present in an arrangement on host hardware (e.g., host processor 1730), and where appropriate, some simulated embodiments may utilize the host hardware.

[0096] The emulator program 1710 can be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 1700 (which may include application programs, operating systems, and management programs). This virtual hardware interface is identical to the interface of the hardware architecture modeled by the emulator program 1710. Therefore, the emulator program 1710 can be used to execute program instructions of the target code 1700 from within the instruction execution environment, including the aforementioned features, so that a host computer 1730, which does not actually possess the hardware features of the aforementioned device, can emulate these features.

[0097] therefore, Figure 14 The arrangement provides an example of a computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising: An address processing circuit is used to detect information related to the input memory address by referring to a chain of corresponding information entries provided by address information tables in a plurality of ordered hierarchical levels. The address processing circuitry is configured to select an address information table for a given table level based on a base address, which depends on an earlier information entry in an address information table that is earlier than the given table level among a plurality of ordered table levels. Furthermore, the address processing circuit is configured to select an information entry in the selected address information table based on an offset component, which depends on at least a portion of the input memory address applicable to a given table level. The offset component is defined such that consecutive instances of portions of the input memory address indicate consecutively addressed information entries. The address processing circuit includes a detector circuit for detecting whether indicator data is set to indicate whether a group of one or more consecutively addressed information entries in a selected address information table provides at least one base address, which indicates a location within a region of consecutive addressing of multiple address information tables, including later table levels.

[0098] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operations. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform a function, in which case the software or program instructions for performing that function, and the medium for providing (e.g., storing) such software or program instructions, such as a non-transitory machine-readable medium, are considered to represent embodiments of this disclosure. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operations.

[0099] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims. For example, features of dependent claims may be combined with features of independent claims in various ways without departing from the scope of the invention.

Claims

1. An apparatus comprising: An address processing circuit is used to detect information related to the input memory address by referring to a chain of corresponding information entries provided by address information tables in a plurality of ordered hierarchical levels. The address processing circuit is configured to select an address information table of a given table level based on a base address, the base address depending on an information entry in the address information table of the ordered plurality of table levels that is earlier than the given table level. Furthermore, the address processing circuit is configured to select an information entry in the selected address information table based on an offset component, the offset component depending on at least a portion of the input memory address applicable to the given table level, the offset component being defined such that consecutive instances of the portion of the input memory address indicate consecutively addressed information entries. The address processing circuit includes a detector circuit for detecting whether indicator data is set to indicate whether a group or more consecutively addressed information entries in a selected address information table provide at least one base address, the at least one base address indicating a location within a region of consecutively addressed address information tables including table levels later than the given table level.

2. The apparatus of claim 1, wherein the last information entry in the chain of information entries provided by the address information table of the last table level in the ordered plurality of hierarchical table levels defines the information associated with the input memory address.

3. The apparatus of claim 1 or claim 2, wherein the address processing circuitry includes an address translation circuitry for performing address translation, wherein the information associated with the input memory address at least defines the address translation between the input memory address in the input address space and the translated output memory address in the output address space.

4. The apparatus according to claim 3, wherein: The input memory address is one of a virtual memory address and an intermediate physical address; and The output memory address is one of the intermediate physical address and the physical address.

5. The apparatus according to claim 1 or claim 2, wherein the address processing circuitry includes an access control circuitry, wherein the information associated with the input memory address at least defines access permissions associated with the input memory address.

6. The apparatus according to claim 1 or claim 2, wherein the indicator data is configured to indicate whether the set of one or more consecutive table entries in the selected address information table provides a corresponding base address, the corresponding base address indicating a set of consecutively addressed address information tables in the next table level of the ordered plurality of hierarchical table levels.

7. The apparatus according to claim 6, comprising: A cache memory for storing data representing information entries retrieved from the address information table by the address processing circuit; The cache memory is configured to store data representing a single base address for a set of one or more consecutively addressed information entries, and it is detected that the indicator data will be set for the set of one or more consecutively addressed information entries.

8. The apparatus of claim 1 or claim 2, wherein the indicator data is configured to indicate whether an information entry in the selected address information table provides a base address for a region indicating continuous addressing, the region including multiple address information tables of the next table level in the ordered plurality of hierarchical table levels.

9. The apparatus of claim 8, wherein the address processing circuitry is configured to select, in response to accessing an information entry in the selected table level that sets the indicator data, an information entry in the address information table of the next table level following the given table level in the ordered plurality of hierarchical table levels.

10. The apparatus of claim 9, wherein the address processing circuitry is configured to select, based on an offset component, an information entry in an address information table of a table level following the given table level, the offset component depending at least on a corresponding portion of the input memory address associated with the given table level and the table level following the given table level.

11. A method comprising: Information related to the input memory address is detected by referring to the chain of corresponding information entries provided by address information tables in an ordered hierarchical table system. For a given address information table at a given table level, an information entry in the address information table of a table level later than the given table level in the ordered plurality of hierarchical table levels is selected by a pointer defined by a base address and an offset component depending on at least a portion of the input memory address, the base address depending on the information entry in the given address information table, and the pointer being defined such that consecutive instances of the portion of the input memory address indicate consecutively addressed information entries. as well as The detection indicator data is set to indicate whether a set of one or more consecutive table entries in the given address information table provides the base address of a specified contiguously addressed region, the contiguously addressed region including multiple address information tables at table levels later than the given table level.

12. A method comprising: Generate information related to the input memory address; An address information table is generated in an ordered plurality of hierarchical table levels to provide the information associated with an input memory address, wherein, for a given address information table of a given table level, the address information table of the given table level can be selected by a base address, the base address depending on information entries in the address information tables of the ordered plurality of table levels earlier than the given table level, and the information entries in the selected address information tables can be selected according to an offset component, the offset component depending on at least a portion of the input memory address applicable to the given table level, the offset component being defined such that consecutive instances of the portion of the input memory address indicate information of consecutive addressing, the generation step comprising: The detector can use a certain amount of memory to store the ordered multiple hierarchical table levels to provide the information associated with the input memory address; The test checks whether a group of multiple address information tables at the same table level can be stored in contiguous memory regions within the detected memory; and When the set of multiple address information tables at the same table level can be stored in the contiguously addressed memory region, a set of one or more consecutive table entries at a table level earlier than the given table level is generated to provide the base address specifying the contiguously addressed region; and The address information table is stored in the memory.

13. An apparatus comprising: A processor circuit is configured to generate information related to an input memory address and to generate an address information table in an ordered plurality of hierarchical table levels to provide the information related to the input memory address, wherein, for a given address information table of a given table level, the address information table of the given table level can be selected by means of a base address, the base address depending on an information entry in the address information table of the ordered plurality of table levels earlier than the given table level, and the information entry in the selected address information table can be selected according to an offset component, the offset component depending on at least a portion of the input memory address applicable to the given table level, the offset component being defined such that consecutive instances of the portion of the input memory address indicate information of consecutive addressing; The processor circuitry is configured to detect a certain amount of memory available for storing the ordered plurality of hierarchical table levels to provide the information associated with the input memory address, and to detect whether, within the detected amount of memory, a set of multiple address information tables at the same table level can be stored in a contiguous memory region; and when the set of multiple address information tables at the same table level can be stored in the contiguous memory region, to generate a set of one or more consecutive table entries at a table level earlier than the given table level to provide a base address specifying the contiguously addressed region; and A memory, wherein the memory is used to store the address information table.

14. A computer program product for controlling a host data processing device to provide an instruction execution environment, and comprising: Address processing program logic, which is used to detect information related to the input memory address by referring to the chain of corresponding information entries provided by the address information tables in the corresponding hierarchical levels of the ordered hierarchical levels; The address processing logic is configured to select a given table-level address information table based on a base address, wherein the base address depends on an information entry in the address information table of the ordered plurality of table levels that is earlier than the given table level. Furthermore, the address processing logic is configured to select an information entry in the selected address information table based on an offset component, the offset component depending on at least a portion of the input memory address applicable to the given table level, the offset component being defined such that consecutive instances of the portion of the input memory address indicate consecutively addressed information entries. The address processing program logic includes detector program logic for detecting whether indicator data is set to indicate whether a group or more consecutively addressed information entries in the selected address information table provide at least one base address, the at least one base address indicating a location within a region of consecutively addressed address information tables including table levels later than the given table level.

Images