Techniques for performing neural network architecture search with federated learning

Abstract

Apparatuses, systems, and techniques for selecting a neural network architecture from a plurality of neural networks in a federated learning (FL) setting. In at least one embodiment, a neural network is trained by combining training results from different FL computing systems, where each of the different FL computing systems, for example, trains a different portion of the neural network.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 889,652, filed June 1, 2020, entitled “Technique to Perform Neural Network Architecture Search with Federate Learning,” the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] At least one embodiment involves using different computing systems in a federated learning (FL) setup to train a portion of a neural network. For example, at least one embodiment involves having different portions of the neural network trained on each of the different computing systems, and combining the results from training each of these different portions on each of the different computing systems to train the neural network. Background Technology

[0004] Training a neural network shared across multiple customers can be challenging due to data privacy concerns. For example, training data might include individual-specific medical imaging data. Furthermore, applying a static neural network to unknown inputs can lead to data inconsistencies during inference. In at least one embodiment, the performance of the neural network is improved by building an input-specific inference network for each customer. Attached Figure Description

[0005] Figure 1 A diagram is shown illustrating different parts of a neural network being trained in a joint learning (FL) setup according to at least one embodiment;

[0006] Figure 2 A diagram is shown illustrating, according to at least one embodiment, a neural network is determined for input in a joint learning (FL) setting;

[0007] Figure 3 A diagram illustrating the overall framework for selecting a neural network for input at a federated learning (FL) client site, according to at least one embodiment;

[0008] Figure 4 A diagram illustrating a sampling path formed in a joint learning (FL) setup according to at least one embodiment is shown;

[0009] Figure 5 The process of constructing a subnetwork for input at a federated learning (FL) client site according to at least one embodiment is illustrated;

[0010] Figure 6 The process of selecting a neural network at each federated learning (FL) client site using information from the inference input, according to at least one embodiment, is illustrated.

[0011] Figure 7 The process of selecting different neural networks at a federated learning (FL) client site using information from another input for inference, according to at least one embodiment, is illustrated.

[0012] Figure 8 A diagram illustrating experimental results of a neural network implemented in a joint learning (FL) setting to select information to be inferred, according to at least one embodiment;

[0013] Figure 9A The inference and / or training logic according to at least one embodiment is illustrated;

[0014] Figure 9B The inference and / or training logic according to at least one embodiment is illustrated;

[0015] Figure 10 The training and deployment of a neural network according to at least one embodiment are illustrated;

[0016] Figure 11 An example data center system according to at least one embodiment is shown;

[0017] Figure 12A An example of an autonomous vehicle according to at least one embodiment is shown;

[0018] Figure 12B The illustration shows an embodiment according to at least one of the embodiments. Figure 12A Examples of camera positions and field of view for autonomous vehicles;

[0019] Figure 12C This is an illustration based on at least one embodiment. Figure 12A A block diagram of an example system architecture for an autonomous vehicle;

[0020] Figure 12D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 12A A diagram of a system for communication between autonomous vehicles;

[0021] Figure 13 This is a block diagram illustrating a computer system according to at least one embodiment;

[0022] Figure 14 This is a block diagram illustrating a computer system according to at least one embodiment;

[0023] Figure 15A computer system according to at least one embodiment is shown;

[0024] Figure 16 A computer system according to at least one embodiment is shown;

[0025] Figure 17A A computer system according to at least one embodiment is shown;

[0026] Figure 17B A computer system according to at least one embodiment is shown;

[0027] Figure 17C A computer system according to at least one embodiment is shown;

[0028] Figure 17D A computer system according to at least one embodiment is shown;

[0029] Figure 17E and Figure 17F A shared programming model according to at least one embodiment is shown;

[0030] Figure 18 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown;

[0031] Figure 19A and Figure 19B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0032] Figure 20A and Figure 20B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0033] Figure 21 A computer system according to at least one embodiment is shown;

[0034] Figure 22A A parallel processor according to at least one embodiment is shown;

[0035] Figure 22B A partitioning unit according to at least one embodiment is shown;

[0036] Figure 22C A processing cluster according to at least one embodiment is shown;

[0037] Figure 22D A graphics multiprocessor according to at least one embodiment is shown;

[0038] Figure 23 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0039] Figure 24 A graphics processor according to at least one embodiment is shown;

[0040] Figure 25 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0041] Figure 26 A deep learning application processor according to at least one embodiment is shown;

[0042] Figure 27 A block diagram of an example neuromorphic processor is shown according to at least one embodiment;

[0043] Figure 28 At least a portion of a graphics processor according to one or more embodiments is shown;

[0044] Figure 29 At least a portion of a graphics processor according to one or more embodiments is shown;

[0045] Figure 30 At least a portion of a graphics processor according to one or more embodiments is shown;

[0046] Figure 31 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0047] Figure 32 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0048] Figure 33A and Figure 33B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0049] Figure 34 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0050] Figure 35 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0051] Figure 36 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0052] Figure 37 A streaming multiprocessor according to at least one embodiment is illustrated;

[0053] Figure 38 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0054] Figure 39 This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment;

[0055] Figure 40 Example illustrations of an advanced computing pipeline for processing imaging data according to at least one embodiment;

[0056] Figure 41A Includes example data flow diagrams of virtual instruments supporting ultrasound equipment according to at least one embodiment;

[0057] Figure 41B Includes example data flow diagrams of virtual instruments supporting CT scanners according to at least one embodiment;

[0058] Figure 42A A data flow diagram illustrating the process for training a machine learning model according to at least one embodiment is shown; and

[0059] Figure 42B This is an example illustration of a client-server architecture that utilizes a pre-trained annotation model to enhance an annotation tool, according to at least one embodiment. Detailed Implementation

[0060] In at least one embodiment, the systems and methods implemented according to this disclosure are used to train a neural network by combining training results from different computer systems that train different parts of the neural network. In at least one embodiment, joint learning (FL) is used in conjunction with dynamically selecting a neural network from a plurality of neural networks using information from at least one of the neural networks to be inferred. In at least one embodiment, at each FL client's computer system, a neural network is selected for the input (e.g., an image) to be inferred.

[0061] In at least one embodiment, the techniques described herein are applicable to situations where a neural network is selected from multiple neural networks for an image, more specifically, for a medical image; however, the techniques described herein are also applicable to other types of inputs for inference by neural networks (non-limiting examples include video, integers, audio, or characters). Medical imaging is performed in multiple locations (e.g., hospitals, clinics, and / or imaging centers), each with its own scanning / imaging equipment such as magnetic resonance imaging (MRI), computed tomography (CT), positional emission computed tomography (PET), X-rays, ultrasound, elastography, and echocardiography, etc. The scanning / imaging equipment and / or processes at these locations can vary, which often leads to data inconsistencies, such as scanners from different vendors, inconsistent scanning protocols, anatomical differences among different populations, artifacts introduced during imaging, variations caused by human involvement in the scanning process, and other related factors. Inconsistencies in image data pose challenges to computational processing or the deployment of machine learning models when faced with unknown data. For example, there are significant appearance differences among routine 3D T2-weighted MRI scans from different institutions and hospitals. Generally, the performance of machine learning models degrades significantly when deployed in unfamiliar image domains. Furthermore, building robust deep learning (DL)-based models requires vast amounts of training data. These datasets are often not easily combined due to patient privacy concerns or regulatory hurdles, especially when medical data is involved. That said, hospitals and other healthcare institutions often need to collaborate and host centralized databases to develop clinical-grade DL models. This can become extremely challenging due to data privacy and the various ethical issues associated with sharing medical data.

[0062] In at least one embodiment, the techniques described herein are suitable for improving image data inconsistency during computational processing and combating data sharing and privacy issues, such as combining joint learning (FL) with dynamically selected image-specific neural networks. In at least one embodiment, a processor with one or more circuits generates a supernet, which may also be referred to as a supernetwork or a neural network composed of multiple neural networks, to allow the mixing of candidate modules in parallel with multi-scale appearance features representing different network levels. In at least one embodiment, the processor executes a supernet training strategy performed within the FL setup. In at least one embodiment, the FL is configured to, after one round of local training, communicate model gradients to a central server at each FL client site, which aggregates the results and begins the next round of FL. In at least one embodiment, one or more processors at each individual FL client site specifically select neural networks for the images. In at least one embodiment, one or more processors at each FL client site then use the selected neural networks to train a portion of the supernet accordingly.

[0063] In at least one embodiment, once the supernet is fully trained, one or more processors at each FL customer site select a neural network. In at least one embodiment, the selected neural network is the optimal neural network, which may also be referred to as a subnetwork, and its optimal path is selected from multiple neural networks. In at least one embodiment, for each unseen data point, at each FL customer site, one or more processors, during inference, determine which neural network to select as the subnetwork under the guidance of an additional unsupervised loss function. In at least one embodiment, each domain, and even each input, is associated with a specific neural network during deployment. In at least one embodiment, feature representations from subnetworks are better suited to different inputs compared to the supernet. In at least one embodiment, the transferability of the neural network model is improved when processing unseen inputs.

[0064] In at least one embodiment, the supernet comprises multiple neural network models, each of which is adapted to an input or domain for a 3D medical image segmentation task. In at least one embodiment, one or more processors at a client server provide the supernet to each FL client site to increase multi-scale representation capabilities, and at each FL client site, a subnet is further determined for each input based on reconstruction accuracy at inference time.

[0065] Figure 1 Figure 100 illustrates different portions of a neural network 104 trained in a federated learning (FL) setup according to at least one embodiment. In at least one embodiment, a processor having one or more circuits associated with a client server 102 provides the neural network 104 to multiple clients. In at least one embodiment, the neural network 104 is a supernet, which may also be referred to as a supernetwork, model architecture, and / or a neural network comprising multiple neural networks. In at least one embodiment, in the federated learning (FL) setup, client A 106 and client B 108 are connected to or communicate with client server 102 via a network. In at least one embodiment, the various components shown in Figure 100 communicate with each other using any of a variety of different network types, including but not limited to local area networks (LANs) and / or wide area networks (WANs) via wired and / or wireless communication protocols. In at least one embodiment, the different network types will be discussed below. Figure 39 Detailed description is provided below. In at least one embodiment, client A 106 and / or client B 108 are FL client sites. In at least one embodiment, two or more clients connect to client server 102 (because...). Figure 1(The two clients shown are for illustrative purposes only; the technology described herein may use more than two clients.) In at least one embodiment, each client 106, 108 includes one or more computing devices that execute user-submitted instructions and / or instructions submitted by an automated program. In at least one embodiment, each client 106, 108 uses data points 110, 116 to locally train the supernet 104. In at least one embodiment, data points 110, 116 are unique to client A 106 and client B 108, respectively. In at least one embodiment, data points 110, 116 are not shared with client server 102, with each other, or with other clients. In at least one embodiment, data points 110, 116 are medical images (such as X-ray, CT, MRI images).

[0066] In at least one embodiment, once a number of clients 106, 108 have completed local training of a portion of the supernet 104 using their respective processors, results 114, 120 are sent from each client 106, 108 to client server 102. In at least one embodiment, the training portion of the supernet 104 is a selected neural network, which may also be referred to as the optimal neural network, and / or a sub-network of each FL client site (client A 106, client B 108). In at least one embodiment, results 114, 120 include updated model weights (or their gradients) from the supernet training portions from client A 112 and client B 118, and the updated model weights are sent to client server 102 for aggregation. In at least one embodiment, after aggregation, the new weights are redistributed to clients A 106 and B 108, and the next round of local training is performed. In at least one embodiment, another round of training of the supernet 104 is performed by one or more processors from each of clients A and B 106, 108. In at least one embodiment, after several rounds of training on one or more processors in an FL setting, the training portions from each client A 106 and client B 108 are converged. In at least one embodiment, each client 106, 108 is allowed to select the locally best model (e.g., a sub-network) by monitoring a certain performance metric on a locally maintained validation set.

[0067] In at least one embodiment, an algorithm is utilized that trains a high-quality model using relatively few rounds of communication by combining local stochastic gradient descent (SGD) on each client with a server performing model averaging. In at least one embodiment, FL minimizes the global loss function. It can be K local losses. The weighted combination of the local losses is calculated on the local data of client k. In at least one embodiment, FL is formulated as a task to find the model parameters φ that minimize L given some local data X.

[0068]

[0069] In at least one embodiment, regarding Equation 1, w k >0 represents the weight coefficient for each client k. In at least one embodiment, local data X i The model weights are not shared between different clients, but are only accumulated and aggregated on client server 102, as shown in Algorithm 1:

[0070]

[0071] In at least one embodiment, training different portions of the supernet 104 at each FL client site is performed by a processor at each FL client site passing data points through the supernet 104, resulting in the selection of a subnet from the supernet 104. In at least one embodiment, the selected subnet is the training portion of the supernet 104. In at least one embodiment, the supernet... Including various DL module candidates It is applicable to the 3D medical imaging tasks shown in Table 1 below.

[0072] Table 1: Candidates for Deep Neural Network Layers

[0073]

[0074] In at least one embodiment, these modules are optimized at multiple resolution levels to capture different levels of low-level and more semantic image features useful for segmentation tasks. In at least one embodiment, an encoder-decoder structure (such as...) is used. Figure 2 (shown and described in more detail below), which has skip connections that link the features of the encoder to their corresponding layers in the decoder path. In at least one embodiment, during training, at each client 106, 108, one or more processors from module candidates China follows a unified sampling scheme (such as...) Figure 3 (As shown and described in more detail below) Select any path m to define the path from the supernet. The sampled subnetwork s.

[0075] In at least one embodiment, Dice loss is applied as the loss function, which works well in segmentation tasks with an imbalance in the number of foreground / background regions.

[0076]

[0077] In at least one embodiment, p i It is the predicted probability of the final sigmoid activation output layer from the supernet f(X), g i This is the ground truth label map at a given voxel i. In at least one embodiment, once the supernet 104 is trained, subnetworks s0 are found at each client 106, 108 via the supernet 104, which effectively adapts the model to the target domain. In at least one embodiment, during adaptation, the model parameters φ remain fixed, and only the path weights are optimized for one epoch on the local validation set. In at least one embodiment, this leads to the optimal path. It defines the locally adapted subnetwork.

[0078] Figure 2 A diagram 200 illustrates a neural network determined for input (e.g., data points or images) 202 in a federated learning (FL) setup according to at least one embodiment. In at least one embodiment, one or more processors at each FL client site select sub-networks for image 202. In at least one embodiment, a processor of a client server executes instructions to construct a supernet 104. In at least one embodiment, supernet 204 is a combination of two or more networks with superblocks 106, including the selection of candidate blocks to form a larger network. In at least one embodiment, supernet 204 is a large Internet Protocol (IP) network composed of multiple smaller networks.

[0079] In at least one embodiment, after one or more processors at the client server generate the supernet, a second step includes training the supernet 204 so that it can be deployed for 3D medical image segmentation. In at least one embodiment, each FL client site receives the supernet 204, and one or more processors at each FL client site are capable of selecting subnetworks using data accessed individually by each FL client site (e.g., using data accessed only by each FL client site), effectively adapting the subnetworks to the target domain of each FL client site. In at least one embodiment, one or more processors construct the supernet 204, which has multiple superblocks 206 containing various module candidates in parallel at different levels / scales. In at least one embodiment, one or more processors train the supernet 204 with paths (which may be arbitrary) from samples (e.g., uniform sampling) of the module candidates 206. In at least one embodiment, the processors then train the supernet 204 with paths (which may be non-arbitrary) from random samples of the module candidates 206. In at least one embodiment, the processors train the supernet 204 using one path at least partially based on one type of input and another path at least partially based on different types of input. In at least one embodiment, once training is complete, one or more processors at each FL client site select a subnetwork for each image 202, wherein the selection is determined during deployment with auxiliary constraints during runtime (e.g., during inference).

[0080] In at least one embodiment, further reference is made to Figure 2 At the client server, one or more processors construct a supernet 204 with an encoder-decoder macrostructure. In at least one embodiment, one or more processors enable multi-level features of the encoder and decoder in the supernet 204 to be linked by skip connections. In at least one embodiment, skip connections are additional connections between blocks of different layers in the supernet 204, where one or more layers are skipped. In at least one embodiment, these additional connections provide a connection from the output of a block in one layer to the input of another block in another layer, where one or more layers are skipped between these connections. In at least one embodiment, the supernet 204 is a U-shaped network with one encoder branch and two decoder branches (in... Figure 4 (Shown in more detail below). In at least one embodiment, skip connections link multi-level features from the encoder to the decoder. In at least one embodiment, there are no skip connections between the encoder (from the supernet 204) and the reconstruction decoder 208 because the reconstruction process focuses on learning feature representations, similar to an autoencoder. In at least one embodiment, and as shown in Table 1 above regarding... Figure 1 As described and shown, six different convolution operations were selected as candidate layers for all search modules.

[0081] In at least one embodiment, one or more processors at each FL client site feed the input image 202 into the supernet 204, and the decoder (in) Figure 2 (Not depicted in the image) A segmentation mask is generated accordingly. In at least one embodiment, a reconstruction decoder 208 is added to the end of the encoder to recover the appearance of the input (e.g., the reconstructed image) 210. In at least one embodiment, adding such a reconstruction decoder 208 provides a better feature representation. In at least one embodiment, the loss function is optimized for both the decoder and the reconstruction decoder 208, and is defined as follows:

[0082]

[0083] In at least one embodiment, from Equation 3 above, Representing the entire Supernet 204, It is a sampling subnetwork from Supernet 204. In at least one embodiment, L in Equation 3 seg It is the soft dice loss for predicting the mask and segmentation labels, L seg This is the L2 loss used to quantify the similarity between the input image 202 and the reconstructed image 210. In at least one embodiment, instead of using a loss function, the loss is determined by using a local validation set.

[0084] In at least one embodiment, one or more processors search each layer of the supernet 204 as part of a selected path to the input image 202. In at least one embodiment, the searched layers are composed of encoders, because the encoder's feature maps capture low-level and high-level image context information, which is crucial for the model's capacity. In at least one embodiment, at each search layer, N candidates are searched in parallel with N individual paths. In at least one embodiment, each path has a positive weight w. n ∈N, and In at least one embodiment, the output of the search layer is a weighted sum, and the number of input and output channels of the layer is fixed. In at least one embodiment, the lower-level layers have fewer channels, and the number of feature maps per layer increases with the number of layers. In at least one embodiment, the spatial size remains constant through necessary padding operations. In at least one embodiment, the downsampling layer and upsampling layer in the supernet 204 are max pooling and trilinear interpolation, respectively.

[0085] In at least one embodiment, during training, one or more processors at each FL client site uniformly sample a path from each search layer of the superblock 206 of the supernet 204 in each iteration, and the parameters of the new subnetwork are updated during gradient backpropagation. In at least one embodiment, sampling of a path is achieved by setting the weights of the selected path to 1 and the rest to 0. In at least one embodiment, the path weights are fixed tensors during training and do not require gradients. In at least one embodiment, such operation significantly reduces the memory consumption of the graphics processing unit (GPU) because training large 3D networks is expensive in terms of time and computational resources. In at least one embodiment, all other weights in the encoder, decoder, and reconstruction decoder are jointly updated. In at least one embodiment, the weights of the paths are also updated during training. However, in at least one embodiment, the training of the supernet 204 is significantly biased because the weights also determine the likelihood of sampling each path. In at least one embodiment, paths with large weights will receive sufficient updates, while paths with smaller weights will not process enough training samples. In at least one embodiment, model initialization is critical and largely determines the final subnetwork.

[0086] Figure 3 A diagram 300 illustrates an overall framework for selecting a neural network (e.g., a subnetwork) for an input (e.g., a 3D image) 302 at a Joint Learning (FL) client site, according to at least one embodiment. In at least one embodiment, one or more processors select a subnetwork for the input 302 at each FL client site by passing the input (accessible only to each individual FL client site) through a supernet 304 and accordingly selecting the optimal path for constructing the subnetwork. In at least one embodiment, this selection of subnetworks utilizes the concept of Neural Architecture Search (NAS), which is used to automatically design neural networks with limited human heuristics to meet diverse user requirements (e.g., lightweight models, or low computational cost). In at least one embodiment, the supernet 304 is a neural network composed of multiple neural networks. In at least one embodiment, the supernet 304 is a large neural network whose candidate modules 312 are parallelized at different levels. In at least one embodiment, a subnetwork is selected for training using a reinforcement learning (RL) algorithm, a general algorithm, or uniform sampling, either jointly or with sampling paths / modules of the entire network. In at least one embodiment, the final neural network architecture at deployment time selects subnetworks of modules / paths from the supernet 304 based on the scalar weights of paths / modules. In at least one embodiment, a pool of candidate networks is collected during training, and at inference time, selection is performed for each data point according to certain criteria to find a subnetwork.

[0087] In at least one embodiment, the input and output of the convolution operation 306 share the same spatial shape. In at least one embodiment, the number of convolution kernels is doubled after the max-pooling layer 310, or halved after the upsampling layer 308. In at least one embodiment, as... Figure 3 As shown, the initial number of convolutional layers is 16, followed by 32, 64, and 128. In at least one embodiment, the activation functions for the terminal portions (e.g., the last) of the convolutional layers used for the decoder and the reconstruction decoder are softmax and linear functions.

[0088] Figure 4 A diagram 400 illustrates a sampling path for forming a neural network in a joint learning (FL) setup according to at least one embodiment. In at least one embodiment, Figure 4 The first line 402 shows three consecutive search modules (part of the supernet), and the second line 404 is a sampling path of the supernet used for training and validation. In at least one embodiment, Figure 4 The first row 402 is the baseline neural network, which is a U-shaped network with one encoder branch and two decoder branches. In at least one embodiment, during training of the graphics processing unit (with 32GB of memory), the network input is a patch of size 96×96×96 randomly cropped from an image. In at least one embodiment, the learning rate of the optimizer used for training is 0.001, and the learning rate for determining the final architecture (shown as λ in Equation 4 described below) is 0.1. In at least one embodiment, necessary data augmentation techniques (e.g., random intensity transfer) are used during training. In at least one embodiment, padding the input volume is necessary when the volume size is not a multiple of 16.

[0089] In at least one embodiment, after the supernet is trained on one or more processors at the client server, a unique subnetwork for each input is determined at each FL client's computing system during inference, guided by additional model constraints. In at least one embodiment, the model is tuned post-training based on the target data point or domain. In at least one embodiment, pre-deployment test images are not visible because the specially selected subnetworks minimize domain differences.

[0090] Figure 5A process 500 for constructing a sub-network of input at a federated learning (FL) client site is illustrated according to at least one embodiment. In at least one embodiment, a supernet is trained by aggregating training results from each FL client site, wherein each FL client site trains a different portion of the supernet. In at least one embodiment, the training results include model weights (parameters) passed from each FL client site to the client server. In at least one embodiment, once the client server receives and aggregates the training results, the trained supernet is provided to each FL client site 502. In at least one embodiment, after the supernet is trained by one or more processors, and after one or more data points (e.g., one or more test data points) are passed using the supernet at each FL client site, one or more processors at each FL client site select a sub-network 504 during runtime (e.g., during inference). In at least one embodiment, one or more processors at each FL client site infer one or more data points at least in part based on receiving multiple images (e.g., frames of a video or different pictures of the same object from different camera angles, different types of medical scans of the same object, etc.), wherein the multiple images include one or more test data points. In at least one embodiment, when each test data point is fed into the supernet, the optimal path for each search layer is simultaneously determined using additional constraints. In at least one embodiment, multiple images comprising multiple test data points are fed into the supernet, and multiple optimal paths for each search layer are determined for each of the multiple test data points. In at least one embodiment, the prediction for a particular data point is computed entirely based on a newly selected neural network with pre-trained weights. In at least one embodiment, each data point has its own neural network during inference, and data preferences learned from the search neural network are effectively applied.

[0091] In at least one embodiment, to implement runtime neural network selection, additional information from the reconstruction branch is utilized at each FL client site. In this embodiment, a summary of the implementation of runtime neural network selection is shown in the following algorithm (Algorithm 2):

[0092]

[0093] In at least one embodiment, Algorithm 2 instructs the first step to include feeding new test data points x into the supernet so that the reconstruction loss L can be calculated by the encoder and reconstruction decoder. reconIn at least one embodiment, the reconstruction loss is performed by comparing the reconstructed data points with the input data points using mean squared error or cross-entropy. In at least one embodiment, the loss 506 is determined using a local validation set. In at least one embodiment, data point x is not shared with other clients. In at least one embodiment, the loss indicates the similarity between the test data and the reconstructed test data. In at least one embodiment, the loss is updated by backpropagating gradients to previous layers. In at least one embodiment, the weights of all modules are fixed in the encoder, decoder, and reconstruction decoder, and the path weights w are fixed. n It can be trained. In at least one embodiment, some or all of w n It is updated after one iteration of training using specific test data points.

[0094]

[0095] In at least one embodiment, λ is the learning rate in Equation 4 above. In at least one embodiment, once the update is complete, the optimal path at each level is simply selected by choosing the path with the largest w. n The path 508 is selected. In at least one embodiment, a subnetwork is constructed using all the optimal paths determined for data point 510. In at least one embodiment, a prediction for that data point is then generated by feeding it into the finally determined network structure. In at least one embodiment, for subsequent data points, w n Reset to 512 Furthermore, the weight updates are repeated so that the decisions for each data-driven subnetwork are independent. In at least one embodiment, some or all path weights w n Reset to In at least one embodiment, after the subnetwork is constructed, the path weights from each FL client site are sent to the client server for aggregation to train the supernet.

[0096] In at least one embodiment, when updating path weight w n During this period, other modules in the supernet are not updated. In at least one embodiment, different data points in inference benefit from their own feature extractors. In at least one embodiment, the path weights w are updated. n This is effective because they are vector variables with layers that require gradient computation. In at least one embodiment, inference using subnetworks is much faster than inference using the entire supernet.

[0097] Figure 6A process 600 is illustrated, which uses information from the inference input to select a neural network at each Joint Learning (FL) client site according to at least one embodiment. In at least one embodiment, the technique described herein is a method for selecting a neural network after each FL client site obtains one or more data points (e.g., data points from a video or from an image) 602 during inference. In at least one embodiment, a processor having one or more circuits receives an image (from local data storage or remote storage accessible only by each individual FL client site and not shared between other FL client sites) and applies a trained neural network (e.g., a supernet) for inference. In at least one embodiment, information from the inference is used by the processor to select a subnet for the image. In at least one embodiment, one or more processors at each client FL site feed the input image into the trained supernet, and a reconstruction decoder generates a segmentation mask accordingly. In at least one embodiment, a reconstruction decoder is added to the end of the encoder to recover the appearance of the input (e.g., the reconstructed image). In at least one embodiment, during training, a path is sampled uniformly from each search layer from the superblock of the supernet at each iteration, and the parameters of the new subnet are updated during gradient backpropagation. In at least one embodiment, sampling of a path is achieved by setting the weight of the selected path to 1 and the rest to 0. In at least one embodiment, paths with large weights receive sufficient updates, while paths with small weights do not process enough training samples. In at least one embodiment, one or more processors at each FL client site select the optimal path based on the updated weights to form a subnetwork. In at least one embodiment, each FL client site includes a computing system comprising different scanning devices (CT scanners, MRI scanners, etc.) that vary in type, manufacturer, and other ways, thus generating different types of inputs. In at least one embodiment, each FL client site is a different computing system within the same hospital. In at least one embodiment, each FL client is a different computing system located in a different hospital.

[0098] In at least one embodiment, when performing a computer vision task, one or more processors at each FL client site process different images using different neural networks. In at least one embodiment, during inference, each layer of the underlying neural network performs numerous different operations (e.g., convolutions). In at least one embodiment, for each layer, all operations are performed, the results are averaged or otherwise combined, and fed into the next layer. In at least one embodiment, a weighted average is applied to the results before feeding them into the next layer. In at least one embodiment, the results are fed into a generator network for reconstructing the image. In at least one embodiment, a reconstruction loss function compares the reconstructed image with the original image, and the value of the reconstruction loss function (e.g., information from inference) indicates which operation is selected at each layer of network 604 to construct the neural network for that image (e.g., a sub-network for that image). In at least one embodiment, the reconstruction loss represents the similarity between the original and reconstructed images, and the loss is updated by backpropagating gradients to previous layers, where the path weights of each layer are updated. In at least one embodiment, cross-entropy or mean squared error is used to determine the loss between the reconstructed image and the input image. In at least one embodiment, the comparison results include selecting a subnetwork for the data point with the largest path weight. In at least one embodiment, the image is then passed through a neural network with this architecture 606 at the FL client site. In at least one embodiment, some or all of the path weights are reset for subsequent images (e.g., different data points) 608.

[0099] Figure 7 A process 700 is illustrated at a federated learning (FL) client site, according to at least one embodiment, for selecting different neural networks using information from another input for inference. In at least one embodiment, a processor having one or more circuits receives another input, such as a second image (also referred to as a second data point) 702, which is related to information about... Figure 6 The images described are different. In at least one embodiment, the second image is related to... Figure 6The images described are of the same type. In at least one embodiment, one or more processors at each FL client site pass a second image through a supernet comprising multiple neural networks, and information from inference is used to determine a neural network (e.g., a subnetwork) suitable for the second image 704. In at least one embodiment, the second image is fed into a trained supernet, and a reconstruction decoder generates a segmentation mask accordingly. In at least one embodiment, during training, a path is uniformly sampled from each search layer from a superblock of the supernet at each iteration, and the parameters of the new subnetwork are updated during gradient backpropagation. In at least one embodiment, sampling of a path is achieved by setting the weights of the selected path to 1 and the rest to 0. In at least one embodiment, paths with large weights receive sufficient updates, while paths with small weights do not process enough training samples. In at least one embodiment, a subnetwork (e.g., a path, an optimal neural network) is selected for the second image based on the updated weights.

[0100] In at least one embodiment, determining or selecting the neural network for the second image and how to perform [the operation] are related to [the specific actions taken]. Figure 6 The image is similarly processed. In at least one embodiment, the result from inference leads one or more processors at each FL client site to select a neural network suitable for the second image, which is associated with, as described above. Figure 6 The neural networks for the images differ 606. In at least one embodiment, the images are processed by a processor, and during inference, a neural network is selected for each respective image in the computing system of each FL client. In at least one embodiment, even if the images are of the same type, the neural network selected for each image may be different. In at least one embodiment, the second data point is of a different type than the first data point. In at least one embodiment, a neural network architecture is selected for the second data point, which is also different from the neural network architecture selected for the first data point.

[0101] Figure 8 The experimental results are shown in the figure, which illustrates the selection of information for inference neural network implemented in a joint learning (FL) setting according to at least one embodiment.

[0102] In at least one embodiment, regarding the dataset used, a prostate magnetic resonance imaging (MRI) dataset from four different publicly available data sources is utilized, labeled MSD Prostate. 1 PROMISE12 2 NCI-ISBI13 3 and ProstateX 4In at least one embodiment, for each dataset, the dataset is randomly split three times into a training set, a validation set, and a test set, at approximately 70%, 10%, and 20% of the total number of cases in each dataset. The number of cases in each dataset in at least one embodiment is shown in Table 2:

[0103] Table 2: Results for each dataset trained on the centralized dataset and in joint learning. The performance of the technique described in this paper was determined using supernets (SN). The average score of the local model (excluding the score of the centralized data) is shown.

[0104]

[0105]

[0106] In at least one embodiment, the results of the test segmentation for each random segmentation are averaged. In at least one embodiment, results are shown on a central dataset where all four datasets are combined. In at least one embodiment, the performance of models trained via joint learning and the test segmentation for each dataset is compared. In at least one embodiment, each image is resampled to a constant resolution of 0.5 mm × 0.5 mm × 1.0 mm, and all non-zero image intensities are normalized by subtracting their average and dividing by their standard derivative on a per-image basis.

[0107] In at least one embodiment, regarding implementation, the supernet is trained using patches of size 256×256×32 randomly cropped from the input images and labels. In at least one embodiment, a mini-batch size of 4 is used by selecting two random crops from any two random pairs of input images and labels. In at least one embodiment, NovoGrad is selected as the optimizer for training the supernet. In at least one embodiment, the learning rate used for training the supernet is set to 1e. -2 In at least one embodiment, in order to find the optimal path of the final subnetwork, a learning rate of 1e is used. -3 The Adam optimizer is used. In at least one embodiment, enhancement techniques such as random intensity shifting, contrast adjustment, and adding Gaussian noise are applied during training to avoid overfitting the training set. In at least one embodiment, both supernets are implemented using PyTorch. 5 It was implemented and trained on a GPU with 32GB of memory.

[0108] In at least one embodiment, regarding the results, Table 2 and above... Figure 8The performance of the hypothetical joint dataset is illustrated. In at least one embodiment, sometimes the locally optimal path... This corresponds to the cardinality used for model selection during supernet training (all paths m = [1, 1, ..., 1, 1] shown in Table 1). In at least one embodiment, Table 2 and Figure 8 The numbers before and after adaptation may be equal.

[0109] In at least one embodiment, Figure 800, excluding Table 2, shows that supernet training with local adaptation in FL (SN(fed.) + adapt.) achieves a high average Dice score on the local dataset. In at least one embodiment, the results demonstrate the feasibility of supernet training with a local model adapted to client data. In at least one embodiment, the performance of the local supernet model is improved when trained in the FL setting. In at least one embodiment, supernet model training can benefit from the larger effective training set size provided by FL without having to share any raw image data between clients.

[0110] Reasoning and training logic

[0111] Figure 9A Inference and / or training logic 915 is shown for performing inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Provide details about reasoning and / or training logic 915.

[0112] In at least one embodiment, inference and / or training logic 915 may include, but is not limited to, code and / or data storage 901 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, training logic 915 may include or be coupled to code and / or data storage 901 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 901 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters using aspects of training and / or inference in one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 901 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0113] In at least one embodiment, any portion of the code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 901 may be a cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 901 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0114] In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, code and / or data storage 905 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in one or more aspects of the embodiments. In at least one embodiment, during training and / or inference using one or more aspects of the embodiments, the code and / or data storage 905 stores weight parameters and / or input / output data for each layer of the neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 915 may include or be coupled to code and / or data storage 905 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, an arithmetic logic unit (ALU)).

[0115] In at least one embodiment, code (such as graph code) causes the architecture of the neural network corresponding to that code to load weights or other parameter information into the processor ALU. In at least one embodiment, any portion of the code and / or data storage 905 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 905 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 905 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0116] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be the same storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0117] In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 920, which are functions of input / output and / or weight parameter data stored in code and / or data storage 901 and / or code and / or data storage 905. In at least one embodiment, activations stored in activation storage 920 are generated based on linear algebra and / or matrix-based mathematics performed by ALU 910 in response to execution instructions or other code, wherein weight values ​​stored in code and / or data storage 905 and / or code and / or data storage 901 are used as operands, and other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, may be stored in code and / or data storage 905 or code and / or data storage 901 or other on-chip or off-chip storage.

[0118] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 910, while in another embodiment, one or more ALUs 910 may be external to the processor or other hardware logic device or the circuitry that uses them (e.g., a coprocessor). In at least one embodiment, ALUs 910 may be included within an execution unit of a processor, or otherwise included in an ALU bank accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 901, code and / or data storage 905, and activation storage 920 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 920 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0119] In at least one embodiment, the active memory 920 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 920 may be entirely or partially located within or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 920 is internal to or external to the processor, for example, or including DRAM, SRAM, flash memory, or certain other memory types, may depend on the available on-chip versus off-chip memory, the latency requirements for performing training and / or inference functions, the batch size of the data used in inference and / or training the neural network, or some combination of these factors.

[0120] In at least one embodiment, Figure 9A The inference and / or training logic 915 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM The inference processing unit (IPU) or from Intel. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9AThe inference and / or training logic 915 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware (such as field programmable gate array (“FPGA”)).

[0121] Figure 9B Inference and / or training logic 915 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, hardware logic, wherein computational resources are dedicated or otherwise exclusively used together with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 9B The inference and / or training logic 915 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as those from Google. Processing unit, from Graphcore TM The inference processing unit (IPU) or from Intel. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9B The inference and / or training logic 915 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, the inference and / or training logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 9B In at least one embodiment shown, each of code and / or data storage 901 and code and / or data storage 905 is associated with dedicated computing resources (e.g., computing hardware 902 and computing hardware 906), respectively. In at least one embodiment, each of computing hardware 902 and computing hardware 906 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) on the information stored in code and / or data storage 901 and code and / or data storage 905, respectively, with the results stored in active storage 920.

[0122] In at least one embodiment, each of the code and / or data storage 901 and 905 and the corresponding computing hardware 902 and 906 corresponds to a different layer of the neural network, such that an activation obtained from one storage / computation pair 901 / 902 of the code and / or data storage 901 and computing hardware 902 is provided as input to the next storage / computation pair 905 / 906 of the code and / or data storage 905 and computing hardware 906, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 901 / 902 and 905 / 906 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) may be included in the inference and / or training logic 915 after or in parallel with the storage / computation pairs 901 / 902 and 905 / 906.

[0123] Neural network training and deployment

[0124] Figure 10 Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 1006 is trained using a training dataset 1002. In at least one embodiment, the training framework 1004 is the PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008. In at least one embodiment, the weights can be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, training can be performed in a supervised, partially supervised, or unsupervised manner.

[0125] In at least one embodiment, supervised learning is used to train an untrained neural network 1006, wherein the training dataset 1002 includes inputs paired with desired outputs for input, or wherein the training dataset 1002 includes inputs with known outputs and the outputs of the neural network 1006 are manually graded. In at least one embodiment, the untrained neural network 1006 is trained in a supervised manner and processes inputs from the training dataset 1002, comparing the resulting outputs with a set of expected or desired outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 1006. In at least one embodiment, a training framework 1004 adjusts the weights controlling the untrained neural network 1006. In at least one embodiment, the training framework 1004 includes tools for monitoring the degree to which the untrained neural network 1006 converges to a model (such as a trained neural network 1008) suitable for generating correct answers (such as result 1014) based on input data (such as a new dataset 1012). In at least one embodiment, the training framework 1004 repeatedly trains the untrained neural network 1006 while adjusting the weights to refine the output of the untrained neural network 1006 using a loss function and tuning algorithms such as stochastic gradient descent. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 reaches the desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to implement any number of machine learning operations.

[0126] In at least one embodiment, unsupervised learning is used to train an untrained neural network 1006, wherein the untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1002 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 1006 can learn groupings within the training dataset 1002 and can determine how each input relates to the untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph in a trained neural network 1008, which is capable of performing operations useful for reducing the dimensionality of the new dataset 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 1012 that deviate from the normal patterns of the new dataset 1012.

[0127] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1002. In at least one embodiment, the training framework 1004 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1008 to adapt to a new dataset 1012 without forgetting the knowledge injected into the trained neural network 1008 during initial training.

[0128] Data Center

[0129] Figure 11 An example data center 1100 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0130] In at least one embodiment, such as Figure 11 As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources (“nodes CR”) 1116(1)-1116(N), where “N” represents a positive integer (which may be an integer “N” different from the integers used in other diagrams). In at least one embodiment, nodes CR 1116(1)-1116(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1118(1)-1118(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1116(1)-1116(N) may be servers having one or more of the aforementioned computing resources.

[0131] In at least one embodiment, the grouped computing resources 1114 may include individual groups of node CRs housed within one or more racks (not shown), or a plurality of racks housed within data centers (also not shown) in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resources 1114 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0132] In at least one embodiment, resource coordinator 1112 may be configured or otherwise control one or more nodes CR1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource coordinator 1112 may include a Software Design Infrastructure (“SDI”) management entity for data center 1100. In at least one embodiment, resource coordinator 1112 may include hardware, software, or some combination thereof.

[0133] In at least one embodiment, such as Figure 11 As shown, framework layer 1120 includes a job scheduler 1122, a configuration manager 1124, a resource manager 1126, and a distributed file system 1128. In at least one embodiment, framework layer 1120 may include a framework of software 1132 supporting software layer 1130 and / or one or more applications 1142 supporting application layer 1140. In at least one embodiment, software 1132 or application 1142 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1120 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark, which can leverage distributed file system 1128 for large-scale data processing (e.g., “big data”). TM(Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1132 may include a Spark driver for facilitating the scheduling of workloads supported by various layers of data center 1100. In at least one embodiment, the configuration manager 1124 may be able to configure different layers, such as software layer 1130 and framework layer 1120 including Spark and a distributed file system 1128 for supporting large-scale data processing. In at least one embodiment, the resource manager 1126 may be able to manage clustered or grouped computing resources mapped to or allocated to support the distributed file system 1128 and job scheduler 1122. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1114 at data center infrastructure layer 1110. In at least one embodiment, the resource manager 1126 may coordinate with resource coordinator 1112 to manage these mapped or allocated computing resources.

[0134] In at least one embodiment, the software 1132 included in software layer 1130 may include software used by at least portions of nodes CR1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1128 of framework layer 1120. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0135] In at least one embodiment, one or more applications 1142 included in application layer 1140 may include one or more types of applications used by at least portions of nodes CR1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1128 of framework layer 1120. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0136] In at least one embodiment, any of the configuration manager 1124, resource manager 1126, and resource coordinator 1112 can perform any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1100 and can prevent underutilization and / or poor performance of the data center.

[0137] In at least one embodiment, data center 1100 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1100. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1100 by using weight parameters calculated through one or more training techniques described herein.

[0138] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0139] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 is... Figure 11 It is used in systems for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0140] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0141] Autonomous vehicles

[0142] Figure 12AExamples of autonomous vehicles 1200 according to at least one embodiment are shown. In at least one embodiment, the autonomous vehicle 1200 (which may alternatively be referred to herein as "vehicle 1200") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle accommodating one or more passengers. In at least one embodiment, vehicle 1200 may be a semi-tractor-trailer truck for hauling goods. In at least one embodiment, vehicle 1200 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0143] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation, in their “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of that standard). In at least one embodiment, vehicle 1200 may be able to have one or more functions according to levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 1200 may be able to have conditional automation (level 3), high automation (level 4), and / or full automation (level 5), depending on the embodiment.

[0144] In at least one embodiment, vehicle 1200 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1200 may include, but is not limited to, propulsion system 1250, such as an internal combustion engine, a hybrid powertrain, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1250 may be connected to the drivetrain of vehicle 1200, which may include, but is not limited to, a transmission, for enabling propulsion of vehicle 1200. In at least one embodiment, propulsion system 1250 may be controlled in response to receiving a signal from throttle / accelerator 1252.

[0145] In at least one embodiment, when the propulsion system 1250 is operating (e.g., when the vehicle 1200 is in motion), the steering system 1254 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1200 (e.g., along a desired path or route). In at least one embodiment, the steering system 1254 may receive signals from the steering actuator 1256. In at least one embodiment, for fully automated (Level 5) functionality, the steering wheel may be optional. In at least one embodiment, the brake sensor system 1246 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1248 and / or brake sensors.

[0146] In at least one embodiment, one or more controllers 1236 may include, but are not limited to, one or more systems-on-a-chip (“SoC”). Figure 12A (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1200. For example, in at least one embodiment, one or more controllers 1236 may send signals to operate vehicle braking via brake actuator 1248, to operate steering system 1254 via one or more steering actuators 1256, and to operate propulsion system 1250 via one or more throttle / accelerators 1252. In at least one embodiment, one or more controllers 1236 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1200. In at least one embodiment, one or more controllers 1236 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the functions described above, and two or more controllers may handle a single function and / or any combination thereof.

[0147] In at least one embodiment, one or more controllers 1236 provide signals for controlling one or more components and / or systems of vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received from, for example, but not limited to, the following sensors: one or more Global Navigation Satellite System (“GNSS”) sensors 1258 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1260, one or more ultrasonic sensors 1262, one or more LIDAR sensors 1264, one or more inertial measurement unit (IMU) sensors 1266 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1296, one or more stereo cameras 1268, one or more wide-angle cameras 1270 (e.g., fisheye cameras), one or more infrared cameras 1272, one or more surround cameras 1274 (e.g., 360-degree cameras), remote cameras ( Figure 12A (not shown in the image), medium-range camera ( Figure 12A (not shown), one or more speed sensors 1244 (e.g., for measuring the speed of vehicle 1200), one or more vibration sensors 1242, one or more steering sensors 1240, one or more brake sensors (e.g., as part of brake sensor system 1246) and / or other sensor types.

[0148] In at least one embodiment, one or more controllers 1236 may receive input (e.g., represented by input data) from the dashboard 1232 of the vehicle 1200 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1234, a voice signaler, a speaker, and / or via other components of the vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 12A The HMI display 1234 may display information such as (not shown), location data (e.g., the location of vehicle 1200, for example on a map), direction, the location of other vehicles (e.g., occupying a grid), information about objects, and the state of objects perceived by one or more controllers 1236. For example, in at least one embodiment, the HMI display 1234 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers that have been, are being, or will be made (e.g., changing lanes now, reaching exit 34B within two miles, etc.).

[0149] In at least one embodiment, vehicle 1200 further includes a network interface 1224 that can communicate over one or more networks using one or more wireless antennas 1226 and / or one or more modems. For example, in at least one embodiment, network interface 1224 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1226 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (“LPWAN”) (such as LoRaWAN, SigFox, etc. protocols).

[0150] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 is... Figure 12A The system is used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0151] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0152] Figure 12B The illustration shows an embodiment according to at least one of the embodiments. Figure 12A Examples of camera positions and fields of view for the autonomous vehicle 1200. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1200.

[0153] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1200. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-to-clear-to-clear (“RCCC”) color filter array, a red-to-clear-to-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with an array of RCCC, RCCB and / or RBGC color filters, may be used to improve photosensitivity.

[0154] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0155] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (3D-printed) assembly, to remove stray light and reflected light from within the vehicle 1200 (e.g., reflected light from the dashboard reflected in the windshield mirror), which may interfere with the camera's image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated into four pillars at each corner of the cabin.

[0156] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including portions of the environment in front of the vehicle 1200 can be used for surround view to help identify the path and obstacles ahead, and to assist in providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path, with the help of one or more controllers 1236 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (such as traffic sign recognition).

[0157] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1270 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 12B Only one wide-angle camera 1270 is shown, but in other embodiments, the vehicle 1200 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 1298 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 1298 can also be used for object detection and classification, as well as basic object tracking.

[0158] In at least one embodiment, any number of stereo cameras 1268 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1268 may include an integrated control unit comprising a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of vehicle 1200, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1268 may include, but are not limited to, a compact stereo vision sensor that may include, but is not limited to, two camera lenses (one on each side) and an image processing chip that can measure the distance from vehicle 1200 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1268 may be used in addition to or instead of those described herein.

[0159] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including portions of the environment on the sides of the vehicle 1200 can be used for surround view, providing information for creating and updating the occupied grid, and generating a side impact collision warning. For example, in at least one embodiment, a surround camera 1274 (e.g., such as...) Figure 12B The four surround cameras shown can be positioned on vehicle 1200. In at least one embodiment, one or more surround cameras 1274 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be located at the front, rear, and sides of vehicle 1200. In at least one embodiment, vehicle 1200 can use three surround cameras 1274 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0160] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including portions of the environment behind the vehicle 1200 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras also suitable as one or more forward-facing cameras (e.g., long-range camera 1298 and / or one or more mid-range cameras 1276, one or more stereo cameras 1268, one or more infrared cameras 1272, etc.), as described herein.

[0161] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can... Figure 12B It is used in systems for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0162] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0163] Figure 12C It is shown that according to at least one embodiment Figure 12A A block diagram of an example system architecture for an autonomous vehicle 1200. In at least one embodiment, Figure 12C Each component, feature, and system of vehicle 1200 is shown as connected via bus 1202. In at least one embodiment, bus 1202 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network within vehicle 1200 used to assist in the control of various features and functions of vehicle 1200, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1202 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1202 may be read to locate steering wheel angle, ground speed, engine rotation speed ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1202 may be an ASIL B compliant CAN bus.

[0164] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, any number of buses forming bus 1202 may be present, including but not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1202 may communicate with any component of vehicle 1200, and two or more buses in bus 1202 may communicate with corresponding components. In at least one embodiment, each of any number of System-on-Chip (“SoC”) 1204 (e.g., SoC 1204(A) and SoC 1204(B)), each of one or more controllers 1236 and / or each computer within the vehicle can access the same input data (e.g., input from sensors of vehicle 1200) and can be connected to a common bus, such as a CAN bus.

[0165] In at least one embodiment, vehicle 1200 may include one or more controllers 1236, such as those described herein. Figure 12A As described above. In at least one embodiment, controller 1236 can be used for a wide variety of functions. In at least one embodiment, controller 1236 can be coupled to any of various other components and systems of vehicle 1200 and can be used to control vehicle 1200, artificial intelligence of vehicle 1200, infotainment and / or other functions of vehicle 1200.

[0166] In at least one embodiment, vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of the SoCs 1204 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1206, a graphics processing unit (“one or more GPUs”) 1208, one or more processors 1210, one or more caches 1212, one or more accelerators 1214, one or more data storage 1216, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1204 may be used to control vehicle 1200 on a wide variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 1204 may be combined with a high-definition (“HD”) map 1222 in a system (e.g., the system of vehicle 1200), the HD map 1222 being accessible from one or more servers via a network interface 1224. Figure 12C (Not shown in the image) Get map refresh and / or update.

[0167] In at least one embodiment, one or more CPUs 1206 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1206 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1206 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1206 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2-megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, which allows any combination of clusters of one or more CPUs 1206 to be active at any given time.

[0168] In at least one embodiment, one or more CPUs 1206 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware blocks to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; power gating of each core independently; clock gating of each core cluster independently when all cores are clock-gated or power-gated; and / or power gating of each core cluster independently when all cores are power-gated. In at least one embodiment, one or more CPUs 1206 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state to be input for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein the work is offloaded to the microcode.

[0169] In at least one embodiment, one or more GPUs 1208 may include integrated GPUs (which may alternatively be referred to herein as “iGPUs”). In at least one embodiment, one or more GPUs 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1208 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1208 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 (“L1”) cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 1208 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1208 may use one or more computation application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1208 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA’s CUDA model).

[0170] In at least one embodiment, one or more GPU 1208s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPU 1208s may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for employing a mix of computation and addressing operations to provide efficient execution of workloads. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0171] In at least one embodiment, one or more GPUs 1208 may include high-bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem, used in some examples to provide a peak memory bandwidth of approximately 900GB / s. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”), such as fifth-generation graphics double data rate type synchronous random access memory (“GDDR5”), may also be used.

[0172] In at least one embodiment, one or more GPUs 1208 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support can be used to allow one or more GPUs 1208 to directly access the page tables of one or more CPUs 1206. In at least one embodiment, when the memory management unit (“MMU”) of one or more GPUs 1208 experiences a miss, an address translation request can be sent to one or more CPUs 1206. In response, in at least one embodiment, two CPUs of one or more CPUs 1206 can look up the virtual-physical mapping of the address in their page tables and send the translation back to one or more GPUs 1208. In at least one embodiment, unified memory technology can allow a single unified virtual address space to be used for the memory of both one or more CPUs 1206 and one or more GPUs 1208, thereby simplifying the programming of one or more GPUs 1208 and the porting of applications to one or more GPUs 1208.

[0173] In at least one embodiment, one or more GPUs 1208 may include any number of access counters that can track the frequency with which one or more GPUs 1208 access the memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of sharing memory ranges among processors.

[0174] In at least one embodiment, one or more SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, one or more caches 1212 may include a Level 3 (“L3”) cache that can be used for both one or more CPUs 1206 and one or more GPUs 1208 (e.g., connected to one or more CPUs 1206 and one or more GPUs 1208). In at least one embodiment, one or more caches 1212 may include a write-back cache that can track the state of each row, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, depending on the embodiment, the L3 cache may include 4 MB of memory or more.

[0175] In at least one embodiment, one or more SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1204 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1208 and offload some tasks from one or more GPUs 1208 (e.g., to free up more cycles of one or more GPUs 1208 to perform other tasks). In at least one embodiment, one or more accelerators 1214 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0176] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, and post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, rapidly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphones; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for protection and / or safety-related events.

[0177] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1208, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 1208 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1208 and / or one or more accelerators 1214.

[0178] In at least one embodiment, one or more accelerators 1214 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, a PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1238, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, a PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0179] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, depending on the embodiment, the RISC core may use any of a variety of protocols. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0180] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1206. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0181] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly perform programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0182] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Therefore, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general computer vision algorithms, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or different portions of an image. In at least one embodiment, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code (“ECC”) memory for enhancing overall system security.

[0183] In at least one embodiment, one or more accelerators 1214 may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1214. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0184] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0185] In at least one embodiment, one or more SoCs 1204 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to rapidly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0186] In at least one embodiment, one or more accelerators 1214 may have broad applications for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1200, PVA may be designed to run classical computer vision algorithms, as they can be efficient in object detection and integer mathematical operations.

[0187] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure reconstruction from motion, pedestrian recognition, lane detection, etc.) during operation. In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0188] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, for example, the PVA is used to perform time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0189] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks, whose output is a measurement of confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence values. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1266 related to vehicle 1200 orientation, distance, and object 3D position estimates obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1264 or one or more RADAR sensors 1260).

[0190] In at least one embodiment, one or more SoCs 1204 may include one or more data stores 1216 (e.g., memory). In at least one embodiment, one or more data stores 1216 may be on-chip memory of one or more SoCs 1204, which may store neural networks to be executed on one or more GPUs 1208 and / or DLAs. In at least one embodiment, one or more data stores 1216 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data stores 1216 may include one or more L2 or L3 caches.

[0191] In at least one embodiment, one or more SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). In at least one embodiment, one or more processors 1210 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security execution. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1204 and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1204s, and / or power state management of one or more SoCs 1204s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1204s may use the ring oscillator to detect the temperature of one or more CPUs 1206s, one or more GPUs 1208s, and / or one or more accelerators 1214s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1204s into a lower power state and / or place the vehicle 1200 into a driver safe parking mode (e.g., bring the vehicle 1200 to a safe stop).

[0192] In at least one embodiment, one or more processors 1210 may further include a set of embedded processors that can be used as an audio processing engine, which may be an audio subsystem that provides full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0193] In at least one embodiment, one or more processors 1210 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, support for peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0194] In at least one embodiment, one or more processors 1210 may further include a security cluster engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In a secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1210 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1210 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0195] In at least one embodiment, one or more processors 1210 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video playback applications to generate final images for video post-processing functions required by the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1270, one or more surround cameras 1274, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1204, the neural network being configured to recognize in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular services and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0196] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for both spatial and temporal noise reduction. For example, in at least one embodiment, in the case of motion in the video, denoising appropriately weights spatial information to reduce the weight of information provided by adjacent frames. In at least one embodiment, in the case where the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0197] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereoscopic shot frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing, and does not require one or more GPUs 1208 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1208 are powered and active for 3D rendering, the video image compositor can be used to offload one or more GPUs 1208 to improve performance and responsiveness.

[0198] In at least one embodiment, one or more SoCs of SoC 1204 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1204 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0199] In at least one embodiment, one or more SoCs of SoC 1204 may further include extensive peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1204 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 1264, one or more RADAR sensors 1260, etc., which may be connected via Ethernet channels), data from bus 1202 (e.g., vehicle 1200 speed, steering wheel position, etc.), data from one or more GNSS sensors 1258 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 1204 may further include dedicated high-performance large-scale memory controllers, which may include their own DMA engines and may be used to free one or more CPUs of SoC 1206 from routine data management tasks.

[0200] In at least one embodiment, one or more SoCs 1204 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for a flexible, reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1204 can be faster, more reliable, and even more energy- and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1214, when combined with one or more CPUs 1206, one or more GPUs 1208, and one or more data storage 1216, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0201] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0202] The embodiments described herein allow for the simultaneous and / or sequential execution of multiple neural networks and allow for the combination of results to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1220) may include text and word recognition, thereby allowing the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing a semantic understanding of the signs, and passing this semantic understanding to a path planning module running on a CPU complex.

[0203] In at least one embodiment, multiple neural networks can run simultaneously for driving levels 3, 4, or 5. For example, in at least one embodiment, a warning sign stating "Caution: flashing lights indicate icy conditions," along with the lights, can be interpreted independently or jointly by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which informs the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within a DLA and / or on one or more GPUs 1208.

[0204] In at least one embodiment, the CNN for face recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1200. In at least one embodiment, a normally open sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in a safe mode, it can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 1204 provide protection against theft and / or carjacking.

[0205] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1204 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, such as those identified by one or more GNSS sensors 1258. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1262, to execute emergency vehicle safety routines, such as slowing the vehicle, pulling the vehicle to the side of the road, stopping, and / or idling the vehicle until the emergency vehicle passes.

[0206] In at least one embodiment, vehicle 1200 may include one or more CPUs 1218 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1204 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 1218 may include, for example, an x86 processor. One or more CPUs 1218 may be used to perform any of the various functions, such as arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 1204, and / or monitoring the status and health of one or more controllers 1236 and / or the on-chip infotainment system (“infotainment SoC”) 1230.

[0207] In at least one embodiment, vehicle 1200 may include one or more GPUs 1220 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 1204 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1220 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on inputs from sensors of vehicle 1200 (e.g., sensor data).

[0208] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include, but is not limited to, one or more wireless antennas 1226 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1224 may be used to enable wireless connectivity to Internet cloud services (e.g., with servers and / or other network devices), with other vehicles, and / or with computing devices (e.g., passenger client devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 1200 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles near vehicle 1200 (e.g., vehicles in front, to the side, and / or behind vehicle 1200). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1200.

[0209] In at least one embodiment, network interface 1224 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1236 to communicate over a wireless network. In at least one embodiment, network interface 1224 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0210] In at least one embodiment, vehicle 1200 may further include one or more data storage units 1228, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoC 1204) storage. In at least one embodiment, one or more data storage units 1228 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0211] In at least one embodiment, the vehicle 1200 may further include one or more GNSS sensors 1258 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including, for example, but not limited to, GPS sensors using a USB connector with an Ethernet-to-serial interface (e.g., RS-232) bridge.

[0212] In at least one embodiment, vehicle 1200 may further include one or more RADAR sensors 1260. In at least one embodiment, one or more RADAR sensors 1260 may be used by vehicle 1200 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1260 may use a CAN bus and / or bus 1202 (e.g., for transmitting data generated by one or more RADAR sensors 1260) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more RADAR sensors 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the RADAR sensors 1260 are pulse Doppler RADAR sensors.

[0213] In at least one embodiment, one or more RADAR sensors 1260 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1260 can help distinguish between static and moving objects and can be used by the ADAS system 1238 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1260 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, employing six antennas, the four central antennas can create a focused beammap designed to record the environment surrounding the vehicle 1200 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling them to quickly detect vehicles entering or leaving the lane of vehicle 1200.

[0214] In at least one embodiment, as an example, a mid-range RADAR system may include a range of up to 160m (front) or 80m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1260 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1238 for blind spot detection and / or lane change assistance.

[0215] In at least one embodiment, the vehicle 1200 may further include one or more ultrasonic sensors 1262. In at least one embodiment, one or more ultrasonic sensors 1262, which may be positioned at the front, rear, and / or sides of the vehicle 1200, may be used for parking assistance and / or creating and updating occupancy grids. In at least one embodiment, a wide variety of ultrasonic sensors 1262 may be used, and different ultrasonic sensors 1262 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1262 may operate at the ASIL B functional safety level.

[0216] In at least one embodiment, vehicle 1200 may include one or more LiDAR sensors 1264. In at least one embodiment, one or more LiDAR sensors 1264 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 1264 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1200 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1264 that can use Ethernet channels (e.g., to provide data to a Gigabit Ethernet switch).

[0217] In at least one embodiment, one or more LiDAR sensors 1264 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1264 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such an embodiment, one or more LiDAR sensors 1264 may include small devices that can be embedded in the front, rear, side, and / or corner locations of vehicle 1200. In at least one embodiment, one or more LiDAR sensors 1264, in such an embodiment, may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-mounted LiDAR sensors 1264 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0218] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the area around vehicle 1200 up to approximately 200m. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the propagation time of the laser pulse and the reflected light on each pixel, which in turn corresponds to the range from vehicle 1200 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

[0219] In at least one embodiment, vehicle 1200 may further include one or more IMU sensors 1266. In at least one embodiment, one or more IMU sensors 1266 may be located at the center of the rear axle of vehicle 1200. In at least one embodiment, one or more IMU sensors 1266 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1266 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1266 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0220] In at least one embodiment, one or more IMU sensors 1266 can be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1266 enable vehicle 1200 to estimate its heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1266, without requiring input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1266 and one or more GNSS sensors 1258 can be combined in a single integrated unit.

[0221] In at least one embodiment, vehicle 1200 may include one or more microphones 1296 placed inside and / or around vehicle 1200. In at least one embodiment, one or more microphones 1296 may be used for emergency vehicle detection and identification.

[0222] In at least one embodiment, vehicle 1200 may further include any number of camera types, including one or more stereo cameras 1268, one or more wide-angle cameras 1270, one or more infrared cameras 1272, one or more surround cameras 1274, one or more long-range cameras 1298, one or more mid-range cameras 1276, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1200. In at least one embodiment, the type of camera used depends on vehicle 1200. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1200. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may support, as an example but not limited to, gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, references previously made herein... Figure 12A and Figure 12B Each camera is described in more detail.

[0223] In at least one embodiment, the vehicle 1200 may further include one or more vibration sensors 1242. In at least one embodiment, the one or more vibration sensors 1242 may measure vibrations of components of the vehicle 1200 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1242 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0224] In at least one embodiment, vehicle 1200 may include ADAS system 1238. In at least one embodiment, ADAS system 1238 may include, but is not limited to, SoC in some examples. In at least one embodiment, ADAS system 1238 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control (“ACC”) system, cooperative adaptive cruise control (“CACC”) system, forward collision warning (“FCW”) system, automatic emergency braking (“AEB”) system, lane departure warning (“LDW”) system, lane keeping assist (“LKA”) system, blind spot warning (“BSW”) system, rear cross traffic warning (“RCTW”) system, collision warning (“CW”) system, lane centering (“LC”) system and / or other systems, features and / or functions.

[0225] In at least one embodiment, the ACC system may use one or more RADAR sensors 1260, one or more LIDAR sensors 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of vehicle 1200 and automatically adjusts the speed of vehicle 1200 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 1200 change lanes if necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0226] In at least one embodiment, the CACC system uses information from other vehicles, which may be received indirectly from other vehicles via a wireless link or through a network connection (e.g., via the Internet) via network interface 1224 and / or one or more wireless antennas 1226. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately ahead (e.g., a vehicle immediately in front of vehicle 1200 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles ahead of vehicle 1200, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0227] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual, haptic, and / or rapid braking pulses.

[0228] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply braking if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system can automatically apply braking to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or collision proximity braking.

[0229] In at least one embodiment, when vehicle 1200 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is not activated when the driver indicates intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1200 begins to leave its lane, the LKA system provides steering input or braking to correct vehicle 1200.

[0230] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of the car. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses turn signals. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback such as a display, speaker, and / or vibration components.

[0231] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when the vehicle 1200 detects an object outside the range of the rear camera while reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0232] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, vehicle 1200 decides for itself whether to follow the result of the main computer or auxiliary computer (e.g., the first or second controller in controller 1236). For example, in at least one embodiment, ADAS system 1238 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, output from ADAS system 1238 may be provided to a supervisory MCU. In at least one embodiment, if output from the main computer and output from the auxiliary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0233] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU, indicating the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0234] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU may learn when the FCW system is recognizing a metallic object that is not actually dangerous, such as a drain grille or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1204s.

[0235] In at least one embodiment, the ADAS system 1238 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and the not-quite-same software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can have greater confidence that the overall results are correct, and the vulnerability in the software or hardware on the host computer will not lead to a major error.

[0236] In at least one embodiment, the output of the ADAS system 1238 may be fed into the perception block and / or the dynamic driving task block of the main computer. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward collision warning due to an object directly ahead, the perception block may use the information when the object is identified. In at least one embodiment, as described herein, the assistance computer may have its own neural network, which is trained to reduce the risk of false alarms.

[0237] In at least one embodiment, vehicle 1200 may further include an infotainment SoC 1230 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1230 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1230 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1200. For example, the infotainment SoC 1230 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, in-vehicle computer, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1234, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1230 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1200, such as information from the ADAS system 1238, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0238] In at least one embodiment, the infotainment SoC 1230 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1230 may communicate with other devices, systems, and / or components of the vehicle 1200 via bus 1202. In at least one embodiment, the infotainment SoC 1230 may be coupled to a supervisory MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of one or more main controllers 1236 (e.g., the main computer and / or backup computer of the vehicle 1200). In at least one embodiment, the infotainment SoC 1230 may place the vehicle 1200 into a driver-to-safe parking mode, as described herein.

[0239] In at least one embodiment, vehicle 1200 may further include instrument panel 1232 (e.g., digital instrument panel, electronic instrument panel, digital instrument cluster, etc.). In at least one embodiment, instrument panel 1232 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1232 may include, but is not limited to, any number and combination of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1230 and instrument panel 1232. In at least one embodiment, instrument panel 1232 may be included as part of infotainment SoC 1230, or vice versa.

[0240] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 is... Figure 12C The system is used to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0241] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0242] Figure 12D It is based on at least one embodiment in one or more cloud-based servers and Figure 12AA diagram of a system 1276 for communication between autonomous vehicles 1200 is provided. In at least one embodiment, system 1276 may include, but is not limited to, one or more servers 1278, one or more networks 1290, and any number and type of vehicles, including vehicle 1200. In at least one embodiment, one or more servers 1278 may include, but is not limited to, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPU 1284), PCIe switches 1282(A)-1282(D) (collectively referred to herein as PCIe switch 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPU 1280). In at least one embodiment, GPU 1284, CPU 1280, and PCIe switch 1282 may be interconnected with high-speed interconnects, such as, for example, but not limited to, NVLink interface 1288 and / or PCIe connection 1286 developed by NVIDIA. In at least one embodiment, the GPU 1284 is connected via NVLink and / or NVSwitch SoC, and the GPU 1284 and PCIe switch 1282 are connected via PCIe interconnect. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1278 may include, but is not limited to, any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination. For example, in at least one embodiment, one or more servers 1278 may each include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0243] In at least one embodiment, one or more servers 1278 may receive image data representing images from vehicles via one or more networks 1290, the images showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 1278 may send updated neural network 1292 and / or map information 1294 to vehicles via one or more networks 1290, including but not limited to information about traffic and road conditions. In at least one embodiment, updates to map information 1294 may include, but are not limited to, updates to HD map 1222, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 1292 and / or map information 1294 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed at a data center (e.g., using one or more servers 1278 and / or other servers).

[0244] In at least one embodiment, one or more servers 1278 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., sent to the vehicle via one or more networks 1290, and / or the machine learning model may be used by one or more servers 1278 to remotely monitor the vehicle).

[0245] In at least one embodiment, one or more servers 1278 may receive data from the vehicle and apply the data to a state-of-the-art real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1278 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1284, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1278 may include a deep learning infrastructure in a data center using CPU power.

[0246] In at least one embodiment, the deep learning infrastructure of one or more servers 1278 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1200, such as image sequences and / or objects located by vehicle 1200 in the image sequences (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1200, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1200 is malfunctioning, one or more servers 1278 may signal to vehicle 1200, instructing vehicle 1200's fail-safe computer to take control, notify passengers, and complete a safe stopping operation.

[0247] In at least one embodiment, one or more servers 1278 may include one or more GPUs 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, servers driven by CPUs, FPGAs, and other processors may be used for inference, such as in situations where performance is less critical. In at least one embodiment, one or more hardware structures 915 are used to execute one or more embodiments. This document incorporates... Figure 9A and / or Figure 9B Provide details about the 915 hardware architecture.

[0248] Computer System

[0249] Figure 13 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include an execution unit for executing instructions. In at least one embodiment, according to this disclosure, such as in the embodiments described herein, computer system 1300 may include, but is not limited to, components such as processor 1302 for employing execution units (including logic) to execute algorithms for process data. In at least one embodiment, computer system 1300 may include a processor, such as those available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM The microprocessor can be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors can also be used. In at least one embodiment, the computer system 1300 can execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0250] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0251] In at least one embodiment, the computer system 1300 may include, but is not limited to, a processor 1302, which may include, but is not limited to, one or more execution units 1308 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1300 is a single-processor desktop or server system, but in another embodiment, the computer system 1300 may be a multiprocessor system. In at least one embodiment, the processor 1302 may include, but is not limited to, for example, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1302 may be coupled to a processor bus 1310, which can transmit data signals between the processor 1302 and other components in the computer system 1300.

[0252] In at least one embodiment, processor 1302 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to processor 1302. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1306 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0253] In at least one embodiment, an execution unit 1308, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1302. In at least one embodiment, the processor 1302 may also include a microcode (“ucode”) read-only memory (“ROM”) storing the microcode of certain macro instructions. In at least one embodiment, the execution unit 1308 may include logic for processing a packaged instruction set 1309. In at least one embodiment, by including the packaged instruction set 1309 in the instruction set of the general-purpose processor and the associated circuitry to be executed, operations used by numerous multimedia applications can be performed using packaged data in the processor 1302. In at least one embodiment, numerous multimedia applications can be accelerated and executed more efficiently by performing operations on packaged data using the full width of the processor's data bus, eliminating the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0254] In at least one embodiment, execution unit 1308 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1300 may include, but is not limited to, memory 1320. In at least one embodiment, memory 1320 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1320 may store one or more instructions 1319 and / or data 1321 represented by data signals executable by processor 1302.

[0255] In at least one embodiment, the system logic chip may be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1316, and the processor 1302 may communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 may provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 may direct data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals between the processor bus 1310, the memory 1320, and the system I / O interface 1322. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1316 can be coupled to memory 1320 via high-bandwidth memory path 1318, and graphics / video card 1312 can be coupled to MCH 1316 via Accelerated Graphics Port (“AGP”) interconnect 1314.

[0256] In at least one embodiment, the computer system 1300 may use the system I / O interface 1322 as a proprietary hub interface bus to couple the MCH 1316 to the I / O controller hub (“ICH”) 1330. In at least one embodiment, the ICH 1330 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1320, chipset, and processor 1302. Examples may include, but are not limited to, an audio controller 1329, a firmware hub (“Flash BIOS”) 1328, a wireless transceiver 1326, a data storage 1324, a conventional I / O controller 1323 including a user input and keyboard interface 1325, a serial expansion port 1327 (such as a Universal Serial Bus (“USB”) port), and a network controller 1334. In at least one embodiment, the data storage 1324 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0257] In at least one embodiment, Figure 13 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 13 An exemplary SoC can be shown. In at least one embodiment, Figure 13The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1300 are interconnected using a Compute Fast Link (CXL) interconnect.

[0258] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 can... Figure 13 Used in systems for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0259] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0260] Figure 14 This is a block diagram illustrating an electronic device 1400 for utilizing a processor 1410 according to at least one embodiment. In at least one embodiment, the electronic device 1400 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0261] In at least one embodiment, the electronic device 1400 may include, but is not limited to, a processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1410 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 14The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 14 An exemplary SoC can be shown. In at least one embodiment, Figure 14 The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 14 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0262] In at least one embodiment, Figure 14 It may include a display 1424, a touch screen 1425, a touchpad 1430, a near field communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, a fast chipset (“EC”) 1435, a trusted platform module (“TPM”) 1438, a BIOS / firmware / flash (“BIOS, FW Flash”) 1422, a DSP 1460, a drive 1420 (such as a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1450, a Bluetooth unit 1452, a wireless wide area network unit (“WWAN”) 1456, a global positioning system (GPS) unit 1455, a camera (“USB 3.0 camera”) 1454 (such as a USB 3.0 camera) and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented in, for example, the LPDDR3 standard. These components can each be implemented in any suitable way.

[0263] In at least one embodiment, other components may be communicatively coupled to processor 1410 via the components described herein. In at least one embodiment, accelerometer 1441, ambient light sensor (“ALS”) 1442, compass 1443, and gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, thermal sensor 1439, fan 1437, keyboard 1436, and touchpad 1430 may be communicatively coupled to EC 1435. In at least one embodiment, speaker 1463, earphone 1464, and microphone (“mic”) 1465 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1462, which in turn may be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1462 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1457 may be communicatively coupled to WWAN unit 1456. In at least one embodiment, components such as WLAN unit 1450, Bluetooth unit 1452, and WWAN unit 1456 may be implemented as next-generation form factors (“NGFF”).

[0264] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 is... Figure 14 Used in systems for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0265] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0266] Figure 15 A computer system 1500 according to at least one embodiment is shown. In at least one embodiment, the computer system 1500 is configured to implement various processes and methods described throughout this disclosure.

[0267] In at least one embodiment, the computer system 1500 includes, but is not limited to, at least one central processing unit (“CPU”) 1502 connected to a communication bus 1510 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Fast (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1500 includes, but is not limited to, main memory 1504 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data is stored in the main memory 1504, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1522 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using the computer system 1500.

[0268] In at least one embodiment, the computer system 1500 includes, but is not limited to, an input device 1508, a parallel processing system 1512, and a display device 1506, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”) display, plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1508 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each module described herein may reside on a single semiconductor platform to form the processing system.

[0269] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 is... Figure 15 The system is used to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0270] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0271] Figure 16 A computer system 1600 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1600 includes, but is not limited to, a computer 1610 and a USB flash drive 1620. In at least one embodiment, the computer 1610 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1610 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0272] In at least one embodiment, the USB flash drive 1620 includes, but is not limited to, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, the processing unit 1630 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1630 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1630 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1630 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1630 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0273] In at least one embodiment, the USB interface 1640 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1640 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1650 may include any amount and type of logic enabling the processing unit 1630 to interface with a device (e.g., computer 1610) via the USB connector 1640.

[0274] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 is... Figure 16 Used in systems for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0275] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0276] Figure 17A An exemplary architecture is illustrated in which multiple GPUs 1710(1)-1710(N) are communicatively coupled to multiple multi-core processors 1705(1)-1705(M) via high-speed links 1740(1)-1740(N) (e.g., bus, point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1740(1)-1740(N) support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, “N” and “M” represent positive integers, the values ​​of which may vary from figure to figure.

[0277] Furthermore, in at least one embodiment, two or more GPUs 1710 are interconnected via high-speed links 1729(1)-1729(2), which can be implemented using a protocol / link similar to or different from that used for high-speed links 1740(1)-1740(N). Similarly, two or more multi-core processors 1705 can be connected via high-speed link 1728, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used. Figure 17A This shows all communication between the various system components.

[0278] In at least one embodiment, each multi-core processor 1705 is communicatively coupled to processor memories 1701(1)-1701(M) via memory interconnects 1726(1)-1726(M), and each GPU 1710(1)-1710(N) is communicatively coupled to GPU memories 1720(1)-1720(N) via GPU memory interconnects 1750(1)-1750(N). In at least one embodiment, memory interconnects 1726 and 1750 may utilize similar or different memory access technologies. By way of example and not limitation, processor memories 1701(1)-1701(M) and GPU memories 1720 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In at least one embodiment, some portions of the processor memory 1701 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0279] As described herein, although the individual multi-core processors 1705 and GPUs 1710 can be physically coupled to specific memories 1701 and 1720 respectively, and / or can implement a unified memory architecture, in which the virtual system address space (also known as the “effective address” space) is distributed among the individual physical memories. For example, processor memories 1701(1)–1701(M) can each include 64 GB of system memory address space, and GPU memories 1720(1)–1720(N) can each include 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M = 2 and N = 4. Other values ​​for N and M are possible.

[0280] Figure 17B Additional details are shown regarding the interconnection between a multi-core processor 1707 and a graphics acceleration module 1746 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1746 may include one or more GPU chips integrated on a line card coupled to the processor 1707 via a high-speed link 1740 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1746 may alternatively be integrated on a package or chip having the processor 1707.

[0281] In at least one embodiment, the processor 1707 includes a plurality of cores 1760A-1760D, each core having a translation back cover buffer (“TLB”) 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, the cores 1760A-1760D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1762A-1762D may include Level 1 (L1) and Level 2 (L2) caches. Furthermore, one or more shared caches 1756 may be included in the caches 1762A-1762D and shared by the respective groups of cores 1760A-1760D. For example, one embodiment of the processor 1707 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1707 and the graphics acceleration module 1746 are connected to a system memory 1714, which may include... Figure 17A The processor memory in the memory is 1701(1)-1701(M).

[0282] In at least one embodiment, consistency of data and instructions stored in the various caches 1762A-1762D, 1756 and system memory 1714 is maintained via inter-core communication through the consistency bus 1764. In at least one embodiment, for example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1764 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 1764 to snoop on cache accesses.

[0283] In at least one embodiment, proxy circuitry 1725 communicatively couples graphics acceleration module 1746 to coherence bus 1764, thereby allowing graphics acceleration module 1746 to participate in cache coherence protocols as a peer of cores 1760A-1760D. Specifically, in at least one embodiment, interface 1735 provides connectivity to proxy circuitry 1725 via high-speed link 1740, and interface 1737 connects graphics acceleration module 1746 to high-speed link 1740.

[0284] In at least one embodiment, the accelerator integrated circuit 1736 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746. In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may alternatively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit (block transport) engines. In at least one embodiment, the graphics acceleration module 1746 may be a GPU having a plurality of graphics processing engines 1731(1)-1731(N), or the graphics processing engines 1731(1)-1731(N) may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0285] In at least one embodiment, the accelerator integrated circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1714. In at least one embodiment, the MMU 1739 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1738 may store commands and data for efficient access by graphics processing engines 1731(1)-1731(N). In at least one embodiment, a fetch unit 1744 may be used to keep data stored in cache 1738 and graphics memory 1733(1)-1733(M) consistent with core caches 1762A-1762D, 1756 and system memory 1714. As previously stated, this could mean that cache 1738 and memory 1733(1)-1733(M) are implemented via proxy circuit 1725 (e.g., sending updates related to the modification / access of cache lines on processor caches 1762A-1762D, 1756 to cache 1738 and receiving updates from cache 1738).

[0286] In at least one embodiment, a set of registers 1745 stores context data of threads executed by graphics processing engines 1731(1)-1731(N), and context management circuitry 1748 manages the thread context. For example, context management circuitry 1748 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1748 can store the current register value in a designated area of ​​memory (e.g., identified by a context pointer). The register value can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1747 receives and processes interrupts received from system devices.

[0287] In at least one embodiment, MMU 1739 translates virtual / effective addresses from graphics processing engine 1731 into real / physical addresses in system memory 1714. In at least one embodiment, accelerator integrated circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1746 may be dedicated to a single application executing on processor 1707, or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein resources of graphics processing engines 1731(1)-1731(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0288] In at least one embodiment, the accelerator integrated circuit 1736 acts as a bridge to the system of the graphics acceleration module 1746 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1736 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1731(1)-1731(N).

[0289] In at least one embodiment, since the hardware resources of the graphics processing engines 1731(1)-1731(N) are explicitly mapped to the real address space seen by the host processor 1707, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1736 is the physical separation of the graphics processing engines 1731(1)-1731(N), making them appear as independent units to the system.

[0290] In at least one embodiment, one or more graphics memories 1733(1)-1733(M) are coupled to each graphics processing engine 1731(1)-1731(N), where N = M. In at least one embodiment, the graphics memories 1733(1)-1733(M) store instructions and data being processed by each graphics processing engine 1731(1)-1731(N). In at least one embodiment, the graphics memories 1733(1)-1733(M) may be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0291] In at least one embodiment, to reduce data traffic on the high-speed link 1740, a biasing technique can be used to ensure that the data stored in the graphics memory 1733(1)-1733(M) is the data most frequently used by the graphics processing engine 1731(1)-1731(N), and preferably data that the cores 1760A-1760D do not use (or at least not frequently use). Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by the graphics processing engine 1731(1)-1731(N)) in the caches 1762A-1762D, 1756 and system memory 1714.

[0292] Figure 17C Another exemplary embodiment is shown, wherein the accelerator integrated circuit 1736 is integrated within the processor 1707. In this embodiment, the graphics processing engines 1731(1)-1731(N) communicate directly with the accelerator integrated circuit 1736 via a high-speed link 1740 through interfaces 1737 and 1735 (again, which can be any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 1736 can perform operations related to... Figure 17B The described operation is similar, but due to its close proximity to the coherence bus 1764 and caches 1762A-1762D, 1756, it may have higher throughput. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1736 and a programming model controlled by the graphics acceleration module 1746.

[0293] In at least one embodiment, graphics processing engines 1731(1)-1731(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1731(1)-1731(N), thereby providing virtualization within a VM / partition.

[0294] In at least one embodiment, graphics processing engines 1731(1)-1731(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1731(1)-1731(N) to allow access by each operating system. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1731(1)-1731(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1731(1)-1731(N) to provide access to each process or application.

[0295] In at least one embodiment, the graphics acceleration module 1746 or the individual graphics processing engine 1731(1)-1731(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1714 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1731(1)-1731(N) (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0296] Figure 17DAn exemplary accelerator integration slice 1790 is illustrated. In at least one embodiment, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit 1736. In at least one embodiment, the application is an effective address space 1782 in system memory 1714, which stores process element 1783. In at least one embodiment, process element 1783 is stored in response to a GPU call 1781 from an application 1780 executing on processor 1707. In at least one embodiment, process element 1783 contains the process state of the corresponding application 1780. In at least one embodiment, a job descriptor (WD) 1784 contained in process element 1783 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1784 is a pointer to a job request queue in the effective address space 1782 of the application.

[0297] In at least one embodiment, the graphics acceleration module 1746 and / or the various graphics processing engines 1731(1)-1731(N) may be shared by all processes or subsets of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1784 to the graphics acceleration module 1746 to begin operations in a virtualized environment.

[0298] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1746 or an individual graphics processing engine 1731. In at least one embodiment, when the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1746 is assigned, the operating system initializes the accelerator integrated circuit 1736 for the owned process.

[0299] In at least one embodiment, during operation, the WD acquisition unit 1791 in the accelerator integration slice 1790 acquires the next WD 1784, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1746. In at least one embodiment, data from the WD 1784 may be stored in register 1745 and used by the MMU 1739, interrupt management circuitry 1747, and / or context management circuitry 1748, as shown. For example, one embodiment of the MMU 1739 includes segment / page walk circuitry for accessing segment / page tables 1786 within the OS virtual address space 1785. In at least one embodiment, the interrupt management circuitry 1747 may process an interrupt event 1792 received from the graphics acceleration module 1746. In at least one embodiment, when performing graphics operations, a valid address 1793 generated by graphics processing engines 1731(1)-1731(N) is translated into a real address by the MMU 1739.

[0300] In at least one embodiment, register 1745 is copied for each graphics processing engine 1731(1)-1731(N) and / or graphics acceleration module 1746, and register 1745 may be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers may be included in accelerator integration slice 1790. Exemplary registers that may be initialized by a hypervisor are shown in Table 3.

[0301] Table 3 – Registers for Supervisor Initialization

[0302]

[0303] Table 6 shows exemplary registers that can be initialized by the operating system.

[0304] Table 6 – Operating System Initialization Registers

[0305]

[0306]

[0307] In at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731(1)-1731(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1731(1)-1731(N) to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0308] Figure 17EAdditional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1798, in which a list of process elements 1799 is stored. In at least one embodiment, the hypervisor real address space 1798 can be accessed via a hypervisor 1796, which virtualizes the graphics acceleration module engine for an operating system 1795.

[0309] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1746. In at least one embodiment, there are two programming models in which the graphics acceleration module 1746 is shared by multiple processes and partitions, namely time-slice sharing and graphics-oriented sharing.

[0310] In at least one embodiment, in this model, the hypervisor 1796 owns the graphics acceleration module 1746 and makes its functionality available to all operating systems 1795. In at least one embodiment, for the graphics acceleration module 1746 to support virtualization through the hypervisor 1796, the graphics acceleration module 1746 may comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1746 must provide a context saving and recovery mechanism, (2) the graphics acceleration module 1746 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1746 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, the fairness of the graphics acceleration module 1746 among processes must be ensured.

[0311] In at least one embodiment, application 1780 needs to make operating system 1795 system calls using the graphics acceleration module type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1746 and can take the form of graphics acceleration module 1746 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1746.

[0312] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1736 (not shown) and the graphics acceleration module 1746 does not support the User Rights Mask Overwrite Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1796 may selectively apply the current Rights Mask Overwrite Register (AMOR) value before placing the AMR into the process element 1783. In at least one embodiment, CSRP is one of the registers 1745 that contains the effective address of a region in the effective address space 1782 of the application for the graphics acceleration module 1746 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0313] Upon receiving a system call, the operating system 1795 can verify that the application 1780 has been registered and granted permission to use the graphics acceleration module 1746. Then, in at least one embodiment, the operating system 1795 uses the information shown in Table 5 to invoke the hypervisor 1796.

[0314] Table 5 – Operating System to Hypervisor Call Parameters

[0315]

[0316] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1796 verifies that operating system 1795 has been registered and granted permission to use graphics acceleration module 1746. Then, in at least one embodiment, hypervisor 1796 adds process element 1783 to a linked list of process elements of the corresponding graphics acceleration module 1746 type. In at least one embodiment, the process element may include the information shown in Table 6.

[0317] Table 6 – Process Element Information

[0318]

[0319] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1790 registers 1745.

[0320] like Figure 17FAs shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1701(1)-1701(N) and GPU memories 1720(1)-1720(N). In this implementation, operations performed on GPUs 1710(1)-1710(N) utilize the same virtual / effective memory address space to access processor memories 1701(1)-1701(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1701(1), a second portion to second processor memory 1701(N), a third portion to GPU memory 1720(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1701 and GPU memories 1720, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0321] In at least one embodiment, the bias / coherence management circuitry 1794A-1794E within one or more MMUs 1739A-1739E ensures cache coherence between one or more host processors (e.g., 1705) and the cache of the GPU 1710, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 17F Several instances of the bias / coherence management circuitry 1794A-1794E are shown, but the bias / coherence circuitry can be implemented within the MMU of one or more host processors 1705 and / or within the accelerator integrated circuit 1736.

[0322] One embodiment allows GPU memory 1720 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability of GPU memory 1720 to be accessed as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor 1705 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1720 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1710. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offloading.

[0323] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising 1 or 2 bits of memory pages attached per GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPU 1710, the bias table can be implemented over one or more stolen memory ranges of GPU memory 1720. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0324] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1720 is performed, resulting in the following operations: In at least one embodiment, a local request from GPU 1710 to find its page in the GPU bias is directly forwarded to the corresponding GPU memory 1720. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to processor 1705 (e.g., via the high-speed link described herein). In at least one embodiment, a request from processor 1705 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request for a page pointing to the GPU bias can be forwarded to GPU 1710. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed by a software-based mechanism, a hardware-assisted software mechanism, or, in a limited set of cases, by a purely hardware-based mechanism.

[0325] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn invokes the GPU's device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migrating from the host processor 1705 bias to the GPU bias, but not for the reverse migration.

[0326] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1705 cannot cache. In at least one embodiment, to access these pages, the processor 1705 may request access from the GPU 1710, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 1705 and the GPU 1710, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU rather than those needed by the host processor 1705, and vice versa.

[0327] One or more hardware structures 915 are used to execute one or more embodiments. This document may combine... Figure 9A and / or Figure 9B Provide details about one or more hardware architectures 915.

[0328] Figure 18Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which can be manufactured using one or more IP cores. In addition to those illustrated, at least one embodiment may also include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0329] Figure 18 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1800 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1800 includes one or more application processors 1805 (e.g., CPU), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1800 includes peripheral or bus logic, which includes a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an I... 2 S / I 2 C controller 1840. In at least one embodiment, integrated circuit 1800 may include a display device 1845 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1850 and a Mobile Industrial Processor Interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1870.

[0330] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in integrated circuit 1800 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0331] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0332] Figures 19A-19B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be fabricated using one or more IP cores. In addition to those illustrated, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0333] Figures 19A-19B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 19A An exemplary graphics processor 1910 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 19B An additional exemplary graphics processor 1940 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 19A The graphics processor 1910 is a low-power graphics processor core. In at least one embodiment, Figure 19B The graphics processor 1940 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1910, 1940 may be... Figure 18 A variant of the 1810 graphics processor.

[0334] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D to 1915N-1 and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic, such that the vertex processor 1905 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1905 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1915A-1915N use the primitive and vertex data generated by the vertex processor 1905 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1915A-1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0335] In at least one embodiment, the graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A-1920B, one or more caches 1925A-1925B, and one or more circuit interconnects 1930A-1930B. In at least one embodiment, the one or more MMUs 1920A-1920B provide virtual-to-physical address mapping for the graphics processor 1910 (including for the vertex processor 1905 and / or fragment processors 1915A-1915N), and may also reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 1925A-1925B. In at least one embodiment, one or more MMUs 1920A-1920B can be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1905, graphics processors 1915, and / or video processors 1920 of FIG. 19, such that each processor 1905-1920 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable the graphics processor 1910 to interface with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0336] In at least one embodiment, the graphics processor 1940 includes, as shown below: Figure 19BThe one or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F to 1955N-1 and 1955N) shown provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1955A-1955N and a tile unit 1958 to accelerate tile-based rendering operations, where scene rendering operations are subdivided in image space, for example, to utilize local spatial consistency within the scene or optimize the use of internal caches.

[0337] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 can... Figure 19A and / or Figure 19B The integrated circuits are used to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0338] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0339] Figures 20A-20B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 20A It shows that it can be included in Figure 18 The graphics core 2000 within the graphics processor 1810, and in at least one embodiment, may be as follows: Figure 19B The Unified Shader Cores 1955A-1955N are shown. Figure 20BA highly parallel general-purpose graphics processing unit (“GPGPU”) 2030 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0340] In at least one embodiment, the graphics core 2000 includes a shared instruction cache 2002, texture units 2018, and a cache / shared memory 2020, which are shared for execution resources within the graphics core 2000. In at least one embodiment, the graphics core 2000 may include multiple slices 2001A-2001N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2000. In at least one embodiment, slices 2001A-2001N may include supporting logic, including local instruction caches 2004A-2004N, thread schedulers 2006A-2006N, thread dispatchers 2008A-2008N, and a set of registers 2010A-2010N. In at least one embodiment, slices 2001A-2001N may include a set of additional functional units (AFU 2012A-2012N), floating-point units (FPU 2014A-2014N), integer arithmetic logic units (ALU 2016A-2016N), address calculation units (ACU 2013A-2013N), double-precision floating-point units (DPFPU2015A-2015N), and matrix processing units (MPU 2017A-2017N).

[0341] In at least one embodiment, the FPU 2014A-2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2015A-2015N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU2016A-2016N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2017A-2017N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2017A-2017N can perform various matrix operations to accelerate machine learning application frameworks, including enabling accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU2012A-2012N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric function operations (e.g., sine, cosine, etc.).

[0342] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9BDetails regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in graphics core 2000 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0343] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0344] Figure 20B A general-purpose processing unit (GPGPU) 2030 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 2030 can be directly linked to other instances of the GPGPU 2030 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 2030 includes a host interface 2032 for establishing a connection to a host processor. In at least one embodiment, the host interface 2032 is a PCI Express interface. In at least one embodiment, the host interface 2032 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 2030 receives commands from the host processor and uses a global scheduler 2034 to allocate execution threads associated with those commands to a group of compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, cache memory 2038 can be used as a higher-level cache than cache memory within computing clusters 2036A-2036H.

[0345] In at least one embodiment, the GPGPU 2030 includes memories 2044A-2044B coupled to the computing clusters 2036A-2036H via a set of memory controllers 2042A-2042B. In at least one embodiment, memories 2044A-2044B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0346] In at least one embodiment, each of the computing clusters 2036A-2036H includes a set of graphics cores, such as Figure 20A The graphics core 2000 may include various types of integer and floating-point logic units that can perform computational operations on a range of precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 2036A-2036H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0347] In at least one embodiment, multiple instances of GPGPU 2030 can be configured to operate as a compute cluster. In at least one embodiment, the communication used for synchronization and data exchange by compute clusters 2036A-2036H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2030 communicate via host interface 2032. In at least one embodiment, GPGPU 2030 includes an I / O hub 2039 that couples GPGPU 2030 to GPU link 2040, which provides direct connectivity to other instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 reside in a separate data processing system and communicate via a network device accessible via host interface 2032. In at least one embodiment, in addition to or as an alternative to host interface 2032, GPU link 2040 may also be configured to implement a connection to the host processor.

[0348] In at least one embodiment, the GPGPU 2030 can be configured to train a neural network. In at least one embodiment, the GPGPU 2030 can be used within an inference platform. In at least one embodiment, when using the GPGPU 2030 for inference, the GPGPU 2030 may include fewer compute clusters 2036A-2036H compared to when using the GPGPU 2030 to train a neural network. In at least one embodiment, the memory technology associated with memories 2044A-2044B can differ between inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2030 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0349] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in the GPGPU 2030 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0350] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0351] Figure 21This is a block diagram illustrating a computing system 2100 according to at least one embodiment. In at least one embodiment, the computing system 2100 includes a processing subsystem 2101 having one or more processors 2102 and system memory 2104 communicating via interconnect paths that may include a memory hub 2105. In at least one embodiment, the memory hub 2105 may be a separate component within a chipset assembly or may be integrated within one or more processors 2102. In at least one embodiment, the memory hub 2105 is coupled to an I / O subsystem 2111 via a communication link 2106. In at least one embodiment, the I / O subsystem 2111 includes an I / O hub 2107 that enables the computing system 2100 to receive input from one or more input devices 2108. In at least one embodiment, the I / O hub 2107 enables a display controller to provide output to one or more display devices 2110A, the display controller being included in one or more processors 2102. In at least one embodiment, one or more display devices 2110A coupled to the I / O hub 2107 may include local, internal, or embedded display devices.

[0352] In at least one embodiment, the processing subsystem 2101 includes one or more parallel processors 2112 coupled to the memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 may use one of any number of standards based on a communication link technology or protocol (such as, but not limited to, PCI Express), or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, one or more parallel processors 2112 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as integrated many-core (MIC) processors. In at least one embodiment, some or all of the parallel processors 2112 form a graphics processing subsystem that can output pixels to one or more display devices 2110A coupled via an I / O hub 2107. In at least one embodiment, one or more parallel processors 2112 may also include a display controller and a display interface (not shown) for implementing direct connection to one or more display devices 2110B.

[0353] In at least one embodiment, system storage unit 2114 may be connected to I / O hub 2107 to provide a storage mechanism for computing system 2100. In at least one embodiment, I / O switch 2116 may be used to provide an interface mechanism for enabling connectivity between I / O hub 2107 and other components, such as network adapter 2118 and / or wireless network adapter 2119 integrated into the platform, and various other devices that may be added via one or more additional devices 2120. In at least one embodiment, network adapter 2118 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2119 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless devices.

[0354] In at least one embodiment, the computing system 2100 may include other components, not explicitly shown, that may also be connected to the I / O hub 2107, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the interconnect can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (e.g., NV-Link high-speed interconnect or interconnect protocols). Figure 21 The communication paths of each component.

[0355] In at least one embodiment, one or more parallel processors 2112 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2112 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 2100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2112, a memory hub 2105, one or more processors 2102, and an I / O hub 2107 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 2100 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 2100 may be integrated into a multi-chip module (MCM), which may interconnect with other MCMs to a modular computing system.

[0356] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9Aand / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 is... Figure 21 The system 2100 is used for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0357] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0358] processor

[0359] Figure 22A A parallel processor 2200 according to at least one embodiment is illustrated. In at least one embodiment, the various components of the parallel processor 2200 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2200 is according to an exemplary embodiment. Figure 21 The variant of the parallel processor 2112 shown.

[0360] In at least one embodiment, the parallel processor 2200 includes a parallel processing unit 2202. In at least one embodiment, the parallel processing unit 2202 includes an I / O unit 2204 that enables communication with other devices, including other instances of the parallel processing unit 2202. In at least one embodiment, the I / O unit 2204 can be directly connected to other devices. In at least one embodiment, the I / O unit 2204 is connected to other devices via a hub or switch interface (e.g., a memory hub 2205). In at least one embodiment, the connection between the memory hub 2205 and the I / O unit 2204 forms a communication link 2213. In at least one embodiment, the I / O unit 2204 is connected to a host interface 2206 and a memory crossbar switch 2216, wherein the host interface 2206 receives commands for performing processing operations, and the memory crossbar switch 2216 receives commands for performing memory operations.

[0361] In at least one embodiment, when host interface 2206 receives a command buffer via I / O unit 2204, host interface 2206 can route work operations for executing those commands to front end 2208. In at least one embodiment, front end 2208 is coupled to scheduler 2210, which is configured to assign commands or other work items to processing cluster array 2212. In at least one embodiment, scheduler 2210 ensures that processing cluster array 2212 is correctly configured and in an active state before assigning tasks to clusters in processing cluster array 2212. In at least one embodiment, scheduler 2210 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2210 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing cluster array 2212. In at least one embodiment, host software can demonstrate workloads for scheduling on processing cluster array 2212 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing cluster array 2212 by the scheduler 2210 logic within the microcontroller, which includes the scheduler 2210.

[0362] In at least one embodiment, the processing cluster array 2212 may include up to "N" processing clusters (e.g., clusters 2214A, 2214B to 2214N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other diagrams). In at least one embodiment, each cluster 2214A-2214N of the processing cluster array 2212 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2210 may use various scheduling and / or work allocation algorithms to allocate work to clusters 2214A-2214N in the processing cluster array 2212, which may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2210, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2212. In at least one embodiment, different clusters 2214A-2214N in the processing cluster array 2212 may be assigned to process different types of programs or to perform different types of computations.

[0363] In at least one embodiment, the processing cluster array 2212 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2212 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0364] In at least one embodiment, the processing cluster array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2202 may transfer data from system memory via I / O unit 2204 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2222) and then written back to system memory.

[0365] In at least one embodiment, when the parallel processing unit 2202 is used to perform graphics processing, the scheduler 2210 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among multiple clusters 2214A-2214N in the processing cluster array 2212. In at least one embodiment, portions of the processing cluster array 2212 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2214A-2214N can be stored in a buffer to allow intermediate data to be transferred between the clusters 2214A-2214N for further processing.

[0366] In at least one embodiment, the processing cluster array 2212 may receive processing tasks to be executed via a scheduler 2210, which receives commands defining the processing tasks from a front end 2208. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2210 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2208. In at least one embodiment, the front end 2208 may be configured to ensure that the processing cluster array 2212 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0367] In at least one embodiment, each of one or more instances of the parallel processing unit 2202 may be coupled to the parallel processor memory 2222. In at least one embodiment, the parallel processor memory 2222 may be accessed via a memory crossbar switch 2216, which may receive memory requests from the processing cluster array 2212 and the I / O unit 2204. In at least one embodiment, the memory crossbar switch 2216 may be accessed via a memory interface 2218. In at least one embodiment, the memory interface 2218 may include a plurality of partition units (e.g., partition units 2220A, 2220B to 2220N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2222. In at least one embodiment, the number of partition units 2220A-2220N is configured to be equal to the number of memory units, such that the first partition unit 2220A has a corresponding first memory unit 2224A, the second partition unit 2220B has a corresponding second memory unit 2224B, and the Nth partition unit 2220N has a corresponding Nth memory unit 2224N. In at least one embodiment, the number of partition units 2220A-2220N may not be equal to the number of memory units.

[0368] In at least one embodiment, memory cells 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2224A-2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as framebuffers or texture maps may be stored across memory cells 2224A-2224N, allowing partitioning cells 2220A-2220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2222. In at least one embodiment, local instances of the parallel processor memory 2222 may be excluded to facilitate a unified memory design that utilizes system memory and local cache memory.

[0369] In at least one embodiment, any of clusters 2214A-2214N in the processing cluster array 2212 can process data to be written to any memory cell 2224A-2224N within the parallel processor memory 2222. In at least one embodiment, the memory crossbar switch 2216 can be configured to transfer the output of each cluster 2214A-2214N to any partition cell 2220A-2220N or another cluster 2214A-2214N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 2214A-2214N can communicate with the memory interface 2218 via the memory crossbar switch 2216 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar switch 2216 has a connection to a memory interface 2218 for communicating with I / O unit 2204, and a connection to a local instance of parallel processor memory 2222, enabling processing units within different processing clusters 2214A-2214N to communicate with system memory or other memory not local to parallel processing unit 2202. In at least one embodiment, the memory crossbar switch 2216 may use virtual channels to separate traffic flows between clusters 2214A-2214N and partition units 2220A-2220N.

[0370] In at least one embodiment, multiple instances of the parallel processing unit 2202 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2202 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2202 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system including one or more instances of the parallel processing unit 2202 or the parallel processor 2200 may be implemented in various configurations and form factors, including but not limited to desktop computers, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0371] Figure 22B This is a block diagram of partitioning unit 2220 according to at least one embodiment. In at least one embodiment, partitioning unit 2220 is... Figure 22A This is an example of one of the partitioning units 2220A-2220N. In at least one embodiment, the partitioning unit 2220 includes an L2 cache 2221, a frame buffer interface 2225, and a ROP 2226 (raster operation unit). In at least one embodiment, the L2 cache 2221 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 2216 and the ROP 2226. In at least one embodiment, the L2 cache 2221 outputs read misses and urgent write-back requests to the frame buffer interface 2225 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 2225. In at least one embodiment, the frame buffer interface 2225 communicates with memory cells in the parallel processor memory (such as...). Figure 22A It is coupled to one of the memory cells 2224A-2224N (e.g., within the parallel processor memory 2222).

[0372] In at least one embodiment, ROP 2226 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2226 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP 2226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2226 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data per tile.

[0373] In at least one embodiment, ROP 2226 is included within each processing cluster (e.g., Figure 22A The clusters 2214A-2214N are used instead of the partition unit 2220. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted via the memory crossbar switch 2216. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...) Figure 21 Displayed on one or more display devices 2110, routed by processor 2102 for further processing, or by... Figure 22A One of the processing entities within the parallel processor 2200 is routed for further processing.

[0374] Figure 22C This is a block diagram of a processing cluster 2214 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 22A An instance of one of the processing clusters 2214A-2214N. In at least one embodiment, the processing cluster 2214 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of typically synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0375] In at least one embodiment, the operation of the processing cluster 2214 can be controlled via a pipeline manager 2232 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2232... Figure 22AThe scheduler 2210 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2234 and / or texture unit 2236. In at least one embodiment, the graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2214 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2214 may include one or more instances of the graphics multiprocessor 2234. In at least one embodiment, the graphics multiprocessor 2234 can process data, and the data crossover switch 2240 can be used to allocate the processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2232 can facilitate the allocation of processed data by specifying the destination of the processed data to be allocated via the data crossover switch 2240.

[0376] In at least one embodiment, each graphics multiprocessor 2234 within the processing cluster 2214 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0377] In at least one embodiment, instructions sent to the processing cluster 2214 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group can be assigned to a different processing engine within the graphics multiprocessor 2234. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2234, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on the graphics multiprocessor 2234.

[0378] In at least one embodiment, the graphics multiprocessor 2234 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2234 may forgo the internal cache and use a cache memory within the processing cluster 2214 (e.g., L1 cache 2248). In at least one embodiment, each graphics multiprocessor 2234 may also access partition units (e.g., Figure 22A The L2 cache is located within partition units 2220A-2220N, which are shared among all processing clusters 2214 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2234 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2202 can be used as global memory. In at least one embodiment, the processing cluster 2214 includes multiple instances of the graphics multiprocessor 2234, which can share common instructions and data that can be stored in the L1 cache 2248.

[0379] In at least one embodiment, each processing cluster 2214 may include a memory management unit (“MMU”) 2245 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2245 may reside in Figure 22A The memory interface 2218 is located within the MMU 2245. In at least one embodiment, the MMU 2245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2245 may include an address translation lookup buffer (TLB) or a cache that may reside within the graphics multiprocessor 2234, the L1 cache 2248, or the processing cluster 2214. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0380] In at least one embodiment, the processing cluster 2214 can be configured such that each graphics multiprocessor 2234 is coupled to a texture unit 2236 to perform a texture mapping operation that determines texture sample locations, reads texture data, and filters texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2234, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2234 outputs a processed task to a data crossbar switch 2240 to provide the processed task to another processing cluster 2214 for further processing, or stores the processed task in an L2 cache, local parallel processor memory, or in system memory via a memory crossbar switch 2216. In at least one embodiment, a preROP 2242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2234 and direct the data to a ROP unit, which can be associated with a partitioning unit (e.g., [missing information]). Figure 22A The PreROP 2242 unit is located together with the partitioning units 2220A-2220N. In at least one embodiment, the PreROP 2242 unit can perform optimizations for color mixing, organizing pixel color data, and performing address translation.

[0381] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in the graphics processing cluster 2214 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0382] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0383] Figure 22DA graphics multiprocessor 2234 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2234 is coupled to a pipeline manager 2232 of a processing cluster 2214. In at least one embodiment, the graphics multiprocessor 2234 has an execution pipeline including, but not limited to, an instruction cache 2252, an instruction unit 2254, an address mapping unit 2256, a register file 2258, one or more general-purpose graphics processing unit (GPGPU) cores 2262, and one or more load / store units 2266. In at least one embodiment, the GPGPU cores 2262 and the load / store units 2266 are coupled to a cache memory 2272 and a shared memory 2270 via a memory and cache interconnect 2268.

[0384] In at least one embodiment, instruction cache 2252 receives a stream of instructions to be executed from pipeline manager 2232. In at least one embodiment, instructions are cached in instruction cache 2252 and dispatched for execution by instruction unit 2254. In at least one embodiment, instruction unit 2254 may dispatch instructions as thread groups (e.g., thread bundles), wherein each thread in the thread group is assigned to a different execution unit within GPGPU core 2262. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2256 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 2266.

[0385] In at least one embodiment, register file 2258 provides a set of registers for functional units of graphics multiprocessor 2234. In at least one embodiment, register file 2258 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2234 (e.g., GPGPU core 2262, load / store unit 2266). In at least one embodiment, register file 2258 is partitioned among each functional unit, such that a dedicated portion of register file 2258 is allocated to each functional unit. In at least one embodiment, register file 2258 is partitioned among different thread bundles being executed by graphics multiprocessor 2234.

[0386] In at least one embodiment, each GPGPU core 2262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2234. In at least one embodiment, the architectures of the various GPGPU cores 2262 may be similar or different. In at least one embodiment, a first portion of the GPGPU core 2262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2234 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2262 may also include fixed-function or special-function logic.

[0387] In at least one embodiment, the GPGPU core 2262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0388] In at least one embodiment, the memory and cache interconnect 2268 is an interconnect network connecting each functional unit of the graphics multiprocessor 2234 to the register file 2258 and the shared memory 2270. In at least one embodiment, the memory and cache interconnect 2268 is a cross-switch interconnect that allows the load / store unit 2266 to perform load and store operations between the shared memory 2270 and the register file 2258. In at least one embodiment, the register file 2258 can operate at the same frequency as the GPGPU core 2262, resulting in very low latency for data transfer between the GPGPU core 2262 and the register file 2258. In at least one embodiment, the shared memory 2270 can be used to implement communication between threads executing on functional units within the graphics multiprocessor 2234. In at least one embodiment, the cache memory 2272 can be used, for example, as a data cache for caching texture data communicated between functional units and texture units 2236. In at least one embodiment, the shared memory 2270 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2272, the thread executing on GPGPU core 2262 can also programmatically store data in shared memory.

[0389] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0390] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9BDetails are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in the graphics multiprocessor 2234 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0391] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0392] Figure 23 A multi-GPU computing system 2300 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 2300 may include a processor 2302 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2306A-D via a host interface switch 2304. In at least one embodiment, the host interface switch 2304 is a PCI Express switch device that couples the processor 2302 to a PCI Express bus, through which the processor 2302 can communicate with the GPGPUs 2306A-D. In at least one embodiment, the GPGPUs 2306A-D may be interconnected via a set of high-speed P2P (peer-to-peer) GPU-to-GPU links 2316. In at least one embodiment, the GPU-to-GPU links 2316 are connected to each of the GPGPUs 2306A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 2316 enable direct communication between each GPGPU 2306A-D without communication via the host interface bus 2304 to which the processor 2302 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 2316, the host interface bus 2304 remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 2300 via one or more network devices. While in at least one embodiment, the GPGPUs 2306A-D are connected to the processor 2302 via the host interface switch 2304, in at least one embodiment, the processor 2302 includes direct support for the P2P GPU link 2316 and can be directly connected to the GPGPUs 2306A-D.

[0393] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be used in a multi-GPU computing system 2300 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0394] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0395] Figure 24 This is a block diagram of a graphics processor 2400 according to at least one embodiment. In at least one embodiment, the graphics processor 2400 includes a ring interconnect 2402, a pipeline front end 2404, a media engine 2437, and graphics cores 2480A-2480N. In at least one embodiment, the ring interconnect 2402 couples the graphics processor 2400 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2400 is one of many processors integrated within a multi-core processing system.

[0396] In at least one embodiment, the graphics processor 2400 receives multiple batches of commands via a ring interconnect 2402. In at least one embodiment, the input commands are interpreted by a command streamer 2403 in a pipeline front-end 2404. In at least one embodiment, the graphics processor 2400 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2480A-2480N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2403 provides the commands to the geometry pipeline 2436. In at least one embodiment, for at least some media processing commands, the command streamer 2403 provides the commands to a video front-end 2434, which is coupled to a media engine 2437. In at least one embodiment, the media engine 2437 includes a video quality engine (VQE) 2430 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2433 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2436 and the media engine 2437 each generate an execution thread for thread execution resources provided by at least one graphics core 2480.

[0397] In at least one embodiment, the graphics processor 2400 includes scalable thread execution resources featuring graphics cores 2480A-2480N (which may be modular and sometimes referred to as core slices), each graphics core having multiple sub-cores 2450A-2450N, 2460A-2460N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2400 may have any number of graphics cores 2480A. In at least one embodiment, the graphics processor 2400 includes graphics cores 2480A having at least a first sub-core 2450A and a second sub-core 2460A. In at least one embodiment, the graphics processor 2400 is a low-power processor with a single sub-core (e.g., 2450A). In at least one embodiment, the graphics processor 2400 includes multiple graphics cores 2480A-2480N, each graphics core including a set of first sub-cores 2450A-2450N and a set of second sub-cores 2460A-2460N. In at least one embodiment, each of the first sub-cores 2450A-2450N includes at least a first set of execution units 2452A-2452N and media / texture samplers 2454A-2454N. In at least one embodiment, each of the second sub-cores 2460A-2460N includes at least a second set of execution units 2462A-2462N and samplers 2464A-2464N. In at least one embodiment, each sub-core 2450A-2450N and 2460A-2460N shares a set of shared resources 2470A-2470N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.

[0398] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in graphics processor 2400 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0399] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0400] Figure 25 This is a block diagram illustrating a microarchitecture for a processor 2500 according to at least one embodiment, the processor 2500 including logic circuitry for executing instructions. In at least one embodiment, the processor 2500 can execute instructions, including x86 instructions, ARM instructions, special-purpose instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2500 may include registers for storing packed data, such as 64-bit wide MMX data in a microprocessor implemented using Intel's MMX technology from Santa Clara, California. TM Registers. In at least one embodiment, an MMX register available in both integer and floating-point forms can operate with packed data elements accompanying Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (beyond) (commonly referred to as “SSEx”) technology can hold such packed data operands. In at least one embodiment, processor 2500 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0401] In at least one embodiment, processor 2500 includes an ordered front end (“front end”) 2501 for fetching instructions to be executed and preparing instructions for later use in the processor pipeline. In at least one embodiment, front end 2501 may include several units. In at least one embodiment, instruction prefetcher 2526 fetches instructions from memory and feeds the instructions to instruction decoder 2528, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2528 decodes the received instructions into one or more machine-executable so-called “micro-operations” or “micro-instructions” (also referred to as “micro ops” or “uops”). In at least one embodiment, instruction decoder 2528 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2530 may assemble the decoded micro-operations into an ordered sequence or trace of programs in micro-operation queue 2534 for execution. In at least one embodiment, when the trace cache 2530 encounters a complex instruction, the microcode ROM 2532 provides the micro-operations required to complete the operation.

[0402] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 2528 may access the microcode ROM 2532 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-operations for processing at the instruction decoder 2528. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction may be stored in the microcode ROM 2532. In at least one embodiment, the tracking cache 2530 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2532 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2532 has completed the serialization of the micro-operations of the instruction, the machine front end 2501 may resume fetching micro-operations from the tracking cache 2530.

[0403] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2503 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance as the instruction stream moves down the pipeline and is scheduled for execution. In at least one embodiment, the out-of-order execution engine 2503 includes, but is not limited to, an allocator / register renamer 2540, a memory micro-operation queue 2542, an integer / floating-point micro-operation queue 2544, a memory scheduler 2546, a fast scheduler 2502, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2504, and a simple floating-point scheduler (“simple FP scheduler”) 2506. In at least one embodiment, the fast scheduler 2502, the slow / general-purpose floating-point scheduler 2504, and the simple floating-point scheduler 2506 are also collectively referred to herein as “micro-operation schedulers 2502, 2504, 2506”. In at least one embodiment, the allocator / register renamer 2540 allocates the machine buffers and resources required for each micro-operation to execute. In at least one embodiment, the allocator / register renamer 2540 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2540 also allocates entries for each micro-operation in one of two micro-operation queues, preceding the memory scheduler 2546 and micro-operation schedulers 2502, 2504, 2506, with memory micro-operation queue 2542 for memory operations and integer / floating-point micro-operation queue 2544 for non-memory operations. In at least one embodiment, the micro-operation schedulers 2502, 2504, 2506 determine when a micro-operation is ready to be executed based on the readiness of their dependent input register operand sources and the availability of execution resources required for the micro-operation to complete its operation. In at least one embodiment, the fast scheduler 2502 may schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2504 and the simple floating-point scheduler 2506 may schedule once per master processor clock cycle. In at least one embodiment, micro-operation schedulers 2502, 2504, and 2506 arbitrate dispatch ports to schedule micro-operations for execution.

[0404] In at least one embodiment, execution block 2511 includes, but is not limited to, integer register file / bypass network 2508, floating-point register file / bypass network (“FP register file / bypass network”) 2510, address generation units (“AGU”) 2512 and 2514, fast arithmetic logic units (ALU) (“fast ALU”) 2516 and 2518, slow arithmetic logic unit (“slow ALU”) 2520, floating-point ALU (“FP”) 2522, and floating-point move unit (“FP move”) 2524. In at least one embodiment, integer register file / bypass network 2508 and floating-point register file / bypass network 2510 are also referred to herein as “register files 2508, 2510”. In at least one embodiment, AGUs 2512 and 2514, fast ALUs 2516 and 2518, slow ALU 2520, floating-point ALU 2522, and floating-point movement unit 2524 are also referred to herein as "execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524". In at least one embodiment, execution block 2511 may include, but is not limited to, any number (including zero) and type of register files, bypass networks, address generation units, and execution units in any combination.

[0405] In at least one embodiment, register networks 2508, 2510 may be arranged between micro-operation schedulers 2502, 2504, 2506 and execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524. In at least one embodiment, integer register file / bypass network 2508 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2510 performs floating-point operations. In at least one embodiment, each of register networks 2508, 2510 may include, but is not limited to, a bypass network that can bypass a recently completed result that has not yet been written to a register file or forward it to a new relevant micro-operation. In at least one embodiment, register networks 2508, 2510 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2508 may include, but is not limited to, two separate register files, one for low-order 32-bit data and the other for high-order 32-bit data. In at least one embodiment, the floating-point register file / bypass network 2510 may include, but is not limited to, 128-bit wide entries, since floating-point instructions typically have operands with widths ranging from 64 to 128 bits.

[0406] In at least one embodiment, execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524 can execute instructions. In at least one embodiment, register networks 2508 and 2510 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2500 can include, but is not limited to, any number of execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524, and combinations thereof. In at least one embodiment, floating-point ALU 2522 and floating-point movement unit 2524 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2522 can include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider for performing division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2516 and 2518. In at least one embodiment, fast ALUs 2516 and 2518 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to slow ALU 2520, because slow ALU 2520 can include, but is not limited to, integer execution hardware for long-delay type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by ALUs 2512 and 2514. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2522 and the floating-point moving unit 2524 can be implemented to support a range of operands with various bit widths, such as supporting 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0407] In at least one embodiment, micro-operation schedulers 2502, 2504, and 2506 dispatch dependent operations before the parent load has completed execution. In at least one embodiment, since micro-operations can be speculatively scheduled and executed within processor 2500, processor 2500 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily prevents the scheduler from accessing the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, replaying dependent operations may be necessary and may allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0408] In at least one embodiment, "register" can refer to an onboard processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register can be one that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuitry. Rather, in at least one embodiment, a register can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0409] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into execution block 2511 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 2511. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2511 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0410] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0411] Figure 26 A deep learning application processor 2600 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2600 uses instructions that, if executed by the deep learning application processor 2600, cause the deep learning application processor 2600 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2600 is an application-specific integrated circuit (ASIC). In at least one embodiment, as a result of executing one or more instructions or both, the application processor 2600 performs matrix multiplication operations or is "hardwired" into hardware. In at least one embodiment, the deep learning application processor 2600 includes, but is not limited to, a processing cluster 2610(1)-2610(12), an inter-chip link (“ICL”) 2620(1)-2620(12), an inter-chip controller (“ICC”) 2630(1)-2630(2), a second-generation high-bandwidth memory (“HBM2”) 2640(1)-2640(4), a memory controller (“Mem Ctrlr”) 2642(1)-2642(4), a high-bandwidth memory physical layer (“HBM PHY”) 2644(1)-2644(4), a management controller central processing unit (“management controller CPU”) 2650, a serial peripheral interface, internal integrated circuits, and a general purpose input / output block (“SPI, I…”). 2 C, GPIO”)2660, Peripheral Component Interconnect Fast Controller and Direct Memory Access Block (“PCIe Controller and DMA”)2670, and Sixteen-Channel Peripheral Component Interconnect Fast Port (“PCI Express x 16”)2680.

[0412] In at least one embodiment, processing cluster 2610 can perform deep learning operations, including inference or prediction operations based on weight parameters computed using one or more training techniques (including those described herein). In at least one embodiment, each processing cluster 2610 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2600 can include any number and type of processing cluster 2600. In at least one embodiment, inter-chip link 2620 is bidirectional. In at least one embodiment, inter-chip link 2620 and inter-chip controller 2630 enable multiple deep learning application processors 2600 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2600 can include any number (including zero) and type of ICL 2620 and ICC 2630.

[0413] In at least one embodiment, the HBM2 2640 provides a total of 32GB of memory. In at least one embodiment, the HBM2 2640(i) is associated with both the memory controller 2642(i) and the HBM PHY 2644(i), where “i” is any integer. In at least one embodiment, any number of HBM2 2640s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controller 2642 and HBM PHY 2644. In at least one embodiment, any number and type of blocks implementing any number and type of communication standards can replace SPI, I... 2 C. GPIO 2660, PCIe controller and DMA 2670 and / or PCIe 2680.

[0414] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the deep learning application processor 2600. In at least one embodiment, the deep learning application processor 2600 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2600. In at least one embodiment, the processor 2600 may be used to perform one or more neural network use cases described herein.

[0415] In at least one embodiment, inference and / or training logic 915 is used to select a neural network for data points in a joint learning (FL) setting. In at least one embodiment, inference and / or training logic 915 provides results from different parts of training the supernet on different computing systems to train the supernet. Once the supernet is trained, an optimal neural network is determined for data points on each different computing system. In at least one embodiment, inference and / or training logic 915 determines the optimal neural network under the guidance of a local validation set and / or loss function at the computing system.

[0416] Figure 27 This is a block diagram of a neuromorphic processor 2700 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2700 may receive one or more inputs from a source external to the neuromorphic processor 2700. In at least one embodiment, these inputs may be transmitted to one or more neurons 2702 within the neuromorphic processor 2700. In at least one embodiment, the neurons 2702 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2700 may include, but is not limited to, thousands or millions of instances of neurons 2702, but any suitable number of neurons 2702 may be used. In at least one embodiment, each instance of a neuron 2702 may include a neuron input 2704 and a neuron output 2706. In at least one embodiment, a neuron 2702 may generate an output that can be transmitted to inputs of other instances of the neuron 2702. For example, in at least one embodiment, neuron inputs 2704 and neuron outputs 2706 may be interconnected via synapses 2708.

[0417] In at least one embodiment, neuron 2702 and synapse 2708 may be interconnected, causing neuromorphic processor 2700 to operate to process or analyze information received by neuromorphic processor 2700. In at least one embodiment, neuron 2702 may send an output pulse (or "fire" or "spike") when the input received through neuron input 2704 exceeds a threshold. In at least one embodiment, neuron 2702 may sum or integrate the signal received at neuron input 2704. For example, in at least one embodiment, neuron 2702 may be implemented as a leaky integrate-and-fire neuron, wherein if the summation (referred to as "membrane potential") exceeds a threshold, neuron 2702 may use a transfer function such as a sigmoid or threshold function to generate an output (or "fire"). In at least one embodiment, the leaky integrate-and-fire neuron may sum the signal received at neuron input 2704 to a membrane potential and may also apply an attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky, integrated firing neuron may fire if multiple input signals are received at neuron input 2704 quickly enough to exceed a thresho...

Claims

1. A processor, comprising: One or more circuits are used for: - Select two or more different parts of a second neural network from a plurality of neural networks, the selection being based at least in part on training data used to train the selected different parts, the training data including at least one image; - Using the selected different parts, train the corresponding different parts of the first neural network among the plurality of neural networks in the following manner: --Data points obtained from the at least one image are passed to the first neural network; --Use a generator network to reconstruct the data points to generate reconstructed data points; --Compare the reconstructed data points with the original data points; as well as --Update one or more weights of the first neural network; as well as - In response to receiving an input image by one or more second neural networks, the input image is processed using the trained first neural network.

2. The processor of claim 1, wherein the selected different portions of the two or more second neural networks are selected at least in part based on information to be used for inference with the first neural network.

3. The processor of claim 2, wherein the one or more circuits are further configured to: Receive training results, including model parameters, from each of the two or more second neural networks; and The model parameters are used to train the first neural network.

4. The processor according to claim 2, wherein the first neural network is a supernetwork comprising multiple neural networks.

5. The processor of claim 4, wherein the one or more circuits are further configured to: The results of the comparison are used to indicate which operation to select from each layer of the first neural network to determine the second neural network for the data points.

6. The processor of claim 5, wherein the operations performed on the data point at each layer are averaged before the data point is fed into a subsequent layer to perform additional operations on the data point.

7. The processor of claim 5, wherein the comparison is performed using a local verification set.

8. The processor of claim 7, wherein the loss is determined based on the local verification set.

9. The processor of claim 5, wherein the one or more circuits are further configured to: The second data point is passed to the first neural network for inference using at least one computer system; The generator network is used to reconstruct the second data point to generate the reconstructed second data point; The second data point to be reconstructed is compared with the second data point; as well as The result of the comparison is used to indicate which operation to select from each layer of the first neural network to select another second neural network among the two or more second neural networks for the second data point, wherein the other second neural network is the same second neural network or a different second neural network.

10. The processor of claim 9, wherein the second data point has the same input type as the data point.

11. A system comprising: One or more computers having one or more processors for: - Select two or more different parts of a second neural network from a plurality of neural networks, the selection being based at least in part on training data used to train the selected different parts, the training data including at least one image; - Using the selected different parts, train the corresponding different parts of the first neural network among the plurality of neural networks in the following manner: --Data points obtained from the at least one image are passed to the first neural network; --Use a generator network to reconstruct the data points to generate reconstructed data points; --Compare the reconstructed data points with the original data points; as well as --Update one or more weights of the first neural network; as well as - In response to receiving an input image by one or more second neural networks, the input image is processed using the trained first neural network.

12. The system according to claim 11, wherein, Training corresponding different parts of the first neural network further includes: the one or more computers being configured with one or more processors to select a second neural network from the two or more second neural networks for training.

13. The system according to claim 11, wherein, The second neural network of the two or more second neural networks includes an optimal path, which is determined at least in part based on information to be used for reasoning by at least one of the two or more second neural networks.

14. The system of claim 11, wherein the one or more processors are further configured to: Receive model weights from multiple different computer systems; and The model weights are aggregated and the information from the aggregated model weights is used to train the corresponding different parts of the first neural network.

15. The system of claim 14, wherein the one or more processors are further configured to: The result of the comparison is used to indicate which operation to select from each layer of the first neural network to select the second neural network for the data points.

16. The system of claim 15, further comprising the one or more computers having one or more processors, for generating a weighted average from operations to be performed on the data points at each layer before feeding the data points into subsequent layers to perform additional operations on the data points.

17. The system of claim 15, wherein the comparison is performed using a local verification set.

18. The system of claim 17, wherein the loss is determined based on the local validation set.

19. The system of claim 11, wherein the one or more computers having one or more processors further select the two or more second neural networks as different second neural networks for different data points of the same type.

20. A machine-readable medium having a set of instructions stored thereon, said set of instructions, when executed by one or more processors, causing said one or more processors to: Selecting different parts of two or more second neural networks from a plurality of neural networks, the selection being based at least in part on training data used to train the selected different parts, the training data including at least one image; Using the selected different parts, the corresponding different parts of the first neural network among the plurality of neural networks are trained in the following manner: - Data points obtained from the at least one image are passed to the first neural network; - Use a generator network to reconstruct the data points to generate reconstructed data points; - Compare the reconstructed data points with the data points; as well as - Update one or more weights of the first neural network; as well as In response to one or more second neural networks receiving an input image, the input image is processed using the trained first neural network.

21. The machine-readable medium of claim 20, wherein if said set of instructions is executed by said one or more processors, the one or more processors further cause said one or more processors to: Training a portion of the first neural network at least partially based on local data from each of the two or more second neural networks; receiving model parameters from each of the two or more second neural networks; and The model parameters are aggregated and the information from the aggregated model parameters is used to generate the first neural network.

22. The machine-readable medium of claim 21, wherein if said set of instructions is executed by said one or more processors, the one or more processors further cause said one or more processors to: The result of the comparison is used to indicate which operation to select from each layer of the first neural network to select the second neural network for the data points.

23. The machine-readable medium of claim 22, wherein each corresponding different portion of the first neural network includes a selected second neural network.

24. The machine-readable medium of claim 23, wherein the second neural network includes an optimal path, the optimal path being determined at least in part based on information to be used for reasoning with the first neural network.

25. The machine-readable medium of claim 24, wherein the information to be inferred includes local data accessible to each of the different computer systems but inaccessible to the other computer systems.

26. The machine-readable medium of claim 20, wherein the set of instructions, if executed by the one or more processors, further causes the one or more processors to train the first neural network to perform medical image segmentation.

27. The machine-readable medium of claim 20, wherein the first neural network is a convolutional neural network.

28. A processor, comprising: One or more circuits are used for: - In response to one or more second neural networks receiving an input image, a first neural network is used to infer information from the input image, wherein different portions of the first neural network are trained using different portions of two or more second neural networks selected from a plurality of neural networks, the selected different portions of the two or more second neural networks being selected based at least on training data used to train the selected different portions, the training data comprising at least one image, and the training of the different portions of the first neural network is performed in the following manner: --Data points obtained from the at least one image are passed to the first neural network; --Use a generator network to reconstruct the data points to generate reconstructed data points; --Compare the reconstructed data points with the original data points; as well as --Update one or more weights of the first neural network.

29. The processor of claim 28, wherein the first neural network is a supernetwork.

30. The processor according to claim 29, wherein, By selecting one of the two or more second neural networks from the supernetwork for training, different parts of the supernetwork are trained on different systems, wherein the second neural network is selected by each of the different computer systems at least in part based on information that is inaccessible to other computer systems and is intended for inference using the first neural network.

31. The processor of claim 30, wherein the one or more circuits are further configured to: Receive training results, including model parameters, from each of the different computer systems, wherein each of the different computer systems trains a portion of the first neural network using data not shared with other computer systems; and The supernetwork is trained using the model parameters.

32. The processor of claim 31, wherein the one or more circuits are further configured to: The result of the comparison is used to indicate which operation to select from each layer of the first neural network to select the second neural network for the data points.

33. The processor of claim 32, wherein the one or more circuits are further configured to generate the results of the comparison between the reconstructed data points and the data points by using cross-entropy in the reconstruction loss function.

34. The processor of claim 33, wherein the first neural network is trained to perform image segmentation.

35. The processor of claim 28, wherein the first neural network comprises a convolutional neural network.

36. A system comprising: One or more computers having one or more processors for: - In response to one or more second neural networks receiving an input image, a first neural network is used to infer information from the input image, wherein different portions of the first neural network are trained using different portions of two or more second neural networks selected from a plurality of neural networks, the selected different portions of the two or more second neural networks being selected based at least on training data used to train the selected different portions, the training data comprising at least one image, and the training of the different portions of the first neural network is performed in the following manner: --Data points obtained from the at least one image are passed to the first neural network; --Use a generator network to reconstruct the data points to generate reconstructed data points; --Compare the reconstructed data points with the data points; and --Update one or more weights of the first neural network.

37. The system of claim 36, wherein training the corresponding different portions of the first neural network at each of the different computer systems further comprises: The one or more computers, each having one or more processors, select a path from the two or more second neural networks to be trained, wherein the path is selected at least in part based on information to be used for inference with the first neural network.

38. The system of claim 37, wherein the one or more processors are further configured to: Receive model weights from each of the different computer systems; and The model weights are aggregated and the information from the aggregated model weights is used to train the first neural network.

39. The system of claim 38, wherein the one or more processors are further configured to: The result of the comparison is used to indicate which operation to select from each layer of the first neural network to construct the path for the data point.

40. The system of claim 39, wherein the data points used by the different computer systems are inaccessible to other computer systems.

41. The system of claim 36, wherein the different portions of the neural network are trained to adapt to the domains of each of different computer systems.

42. A machine-readable medium having a set of instructions stored thereon, said set of instructions, when executed by one or more processors, causing said one or more processors to: - In response to one or more second neural networks receiving an input image, a first neural network is used to infer information from the input image, wherein different portions of the first neural network are trained using different portions of two or more second neural networks selected from a plurality of neural networks, the selected different portions of the two or more second neural networks being selected based at least on training data used to train the selected different portions, the training data comprising at least one image, the training of the different portions of the first neural network being performed in the following manner: --Data points obtained from the at least one image are passed to the first neural network; --Use a generator network to reconstruct the data points to generate reconstructed data points; --Compare the reconstructed data points with the original data points; as well as --Update one or more weights of the first neural network.

43. The machine-readable medium according to claim 42, wherein, Training the corresponding different parts of the first neural network further includes: selecting one of the two or more second neural networks from the first neural network for training, wherein the second neural network is selected at least in part based on information to be used for inference by the first neural network.

44. The machine-readable medium of claim 43, wherein if the set of instructions is executed by the one or more processors, the one or more processors further cause the one or more processors to: Receive model parameters from each of the two or more neural networks; and The model parameters are aggregated and the information from the aggregated model parameters is used to generate the first neural network.

45. The machine-readable medium of claim 44, wherein if said set of instructions is executed by said one or more processors, the one or more processors further cause said one or more processors to: The result of the comparison is used to indicate which operation to select from each layer of the first neural network to select the second neural network for the data points.

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