Accessing multi-level memory cells

Abstract

This application relates to accessing multi-level memory cells. A memory device can perform a read operation including a pre-read portion and a read portion to access the multi-level memory cells. During the pre-read portion, the memory device can apply a plurality of voltages to a plurality of memory cells to identify a possible distribution of memory cells storing a first logic state. During the read portion, the memory device can apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device can apply a second read voltage to the memory cell during the read portion based on the first read voltage. The memory device can determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

Description

[0001] Cross-reference

[0002] This patent application is the national phase application of International Patent Application No. PCT / US2021 / 039534, entitled "Accessing a Multi-Level Memory Cell," filed June 29, 2021, by Sarpatwari et al., which claims priority to U.S. Patent Application No. 16 / 926,556, entitled "Accessing a Multi-Level Memory Cell," filed July 10, 2020, by Sarpatwari et al., each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to access multilevel memory cells. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than one state, storing any of those states. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write or program states into the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), and so on. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for extended periods, even in the absence of an external power supply. Volatile memory devices (e.g., DRAM) can lose their stored state when disconnected from an external power supply. FeRAM can achieve densities similar to volatile memory, but its non-volatile nature is attributed to the use of ferroelectric capacitors as storage devices.

[0006] Improving memory devices typically involves increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. It is desirable to store multiple bits of information in memory cells to increase data storage density without increasing the physical memory cell density. Summary of the Invention

[0007] Describe a method. The method may include: applying a plurality of voltages to a plurality of memory cells as a pre-fetch portion of a read operation; applying a first read voltage to memory cells of the plurality of memory cells at least in part based on the application of the plurality of voltages to identify a logical state stored in the memory cells as a read portion of the read operation; applying a second read voltage to the memory cells of the plurality of memory cells at least in part based on the application of the first read voltage as a read portion of the read operation; and determining the logical state stored in the memory cells at least in part based on the application of the first read voltage and the application of the second read voltage.

[0008] Describe a method. The method may include: applying a plurality of voltages to a plurality of memory cells as a pre-fetch portion of a read operation; applying a first read voltage having a first magnitude and a first polarity to memory cells of the plurality of memory cells, at least in part based on the application of the plurality of voltages, to identify a logic state stored in the memory cells as a read portion of the read operation; applying a second read voltage having a second magnitude and the first polarity to the memory cells, at least in part based on the application of the first read voltage, as the read portion of the read operation; and determining the logic state stored in the memory cells, at least in part based on the application of the first read voltage and the application of the second read voltage.

[0009] Describe a method. The method may include: applying a plurality of voltages to a plurality of memory cells as a pre-read portion of a read operation; applying a first read voltage of a first polarity to memory cells of the plurality of memory cells at least in part based on the application of the plurality of voltages to identify a logical state stored in the memory cells as a read portion of the read operation; applying a second read voltage of a second polarity to the memory cells at least in part based on the application of the first read voltage as the read portion of the read operation; and determining the logical state stored in the memory cells at least in part based on the application of the first read voltage and the application of the second read voltage.

[0010] Describe an apparatus. The apparatus may include: a memory array including a plurality of memory cells; and a control component coupled to the memory array, the control component being configured such that the apparatus: applies a plurality of voltages to the plurality of memory cells as a pre-fetch portion of a read operation; applies a first read voltage to memory cells of the plurality of memory cells at least in part based on the application of the plurality of voltages to identify a logical state stored in the memory cells as a read portion of the read operation; applies a second read voltage to memory cells of the plurality of memory cells at least in part based on the application of the first read voltage as a read portion of the read operation; and determines the logical state stored in the memory cells at least in part based on the application of the first read voltage and the application of the second read voltage.

[0011] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code containing instructions that, when executed by a processor of an electronic device, cause the electronic device to: apply a plurality of voltages to a plurality of memory cells as a pre-fetch portion of a read operation; apply a first read voltage to memory cells of the plurality of memory cells at least in part based on the application of the plurality of voltages to identify a logical state stored in the memory cells as a read portion of the read operation; apply a second read voltage to memory cells of the plurality of memory cells at least in part based on the application of the first read voltage as a read portion of the read operation; and determine the logical state stored in the memory cells at least in part based on the application of the first read voltage and the application of the second read voltage. Attached Figure Description

[0012] Figure 1 This describes an example memory device that supports access to multilevel memory cells, based on examples disclosed herein.

[0013] Figure 2 This describes an example of a memory array that supports access to multilevel memory cells, as illustrated in the examples disclosed herein.

[0014] Figure 3A The illustration shows an example of a diagram illustrating the distribution of threshold voltages in a self-selected memory cell that supports access to multilevel memory cells, based on examples disclosed herein.

[0015] Figure 3B This describes an example of a timing diagram supporting access to a multilevel memory cell, based on examples disclosed herein.

[0016] Figure 4AThe illustration shows an example of a diagram illustrating the distribution of threshold voltages in a self-selected memory cell that supports access to multilevel memory cells, based on examples disclosed herein.

[0017] Figure 4B This describes an example of a timing diagram supporting access to a multilevel memory cell, based on examples disclosed herein.

[0018] Figure 5 A block diagram illustrating a memory device that supports access to multilevel memory cells, based on examples disclosed herein.

[0019] Figures 6 to 8 The flowchart illustrates one or more methods for supporting access to multilevel memory cells, based on examples disclosed herein. Detailed Implementation

[0020] Self-select memory cells containing chalcogenide materials can be instances of multilevel cells configured to store three or more unique states. Thus, a single multilevel self-select memory cell can be configured to store more than one data bit. In some cases, the self-select memory cell can be selected by applying a bias voltage between the word line and the digital line. The logic state stored in the self-select memory cell can be based on the polarity of the programming pulse applied to the self-select memory cell and the polarity of the read pulse used to detect the state stored by the self-select memory cell. For some multilevel self-select memory cells, a programming pulse sequence consisting of two pulses can be used to program one or more intermediate memory states into the self-select memory cell. In some cases, one or more pulses with the same or different polarities or the same or different values ​​can be used.

[0021] This invention describes apparatus, systems, and techniques for accessing multilevel self-selective memory cells storing three or more states. A read operation for a multilevel self-selective memory cell may include two or more portions, including a pre-fetch portion and a read portion. During the pre-fetch portion, multiple different voltages may be applied to multiple partitions of the memory device. The memory device may identify possible distributions associated with memory cells storing a first logic state. Based on said distribution, the memory device may select a first read voltage to distinguish between storing a first logic state and a second logic state based on performing the pre-fetch portion. The memory device may also select a second read voltage to distinguish between storing a second logic state and a third logic state based on the first read voltage. The memory device may determine the logic state based on the applied first and second read voltages.

[0022] Accessing multilevel memory cells by applying multiple voltages during the prefetch phase and applying first and second read voltages during the read phase can improve read margins of read operations by selecting the read voltage based on current conditions in the memory device. In some instances, these techniques can save current and power by selecting the first read voltage based on the voltage applied during the prefetch phase. In such cases, multilevel reads that store three or more logic states per memory cell can increase the number of bits accessed per memory cell, thereby improving the performance of self-selecting memory cells.

[0023] Originally in reference Figures 1 to 2 Features of this disclosure are described within the context of the memory array described. Features of this disclosure are described in contextual diagrams and timing diagrams illustrating the distribution of threshold voltages, as described with reference to Figures 3 and 4. These and other features of this disclosure are further illustrated and described with reference to device diagrams and flowcharts relating to accessing multilevel memory cells, as described with reference to… Figures 5 to 8 describe.

[0024] Figure 1 This describes an example memory device 100 that supports access to multilevel memory cells, as disclosed herein. The memory device 100 may also be referred to as an electronic memory device. Components and features of the memory device 100 are shown to illustrate functional interrelationships, without specifying their actual physical location within the memory device 100. The memory device 100 includes a three-dimensional (3D) memory array. The memory array includes memory cells 105 programmable to store different states. In some instances, each memory cell 105 is programmable to store two states represented as logic 0 and logic 1. In some instances, the memory cell 105 may be configured to store more than two logic states. In some instances, the memory cell 105 may include self-selecting memory cells. Although the numbers are marked with numeric indicators... Figure 1 Some elements are shown, but other corresponding elements are not labeled, but they are the same or will be understood as similar, in an effort to increase the visibility and clarity of the features depicted.

[0025] A 3D memory array can comprise two or more two-dimensional (2D) memory arrays formed on top of each other. Compared to 2D arrays, this increases the number of memory cells that can be placed or generated on a single die or substrate, which in turn can reduce manufacturing costs or increase the performance of the memory device, or both. Figure 1The example depicted shows a memory array comprising two levels of memory cells 105 and thus considered a 3D memory array; however, the number of levels is not limited to two. Each level can be aligned or positioned such that memory cells 105 can be aligned with each other across each level (completely, overlapping, or approximately), thereby forming a memory cell stack 145. In some cases, the memory cell stack 145 may comprise multiple self-selecting memory cells laid on top of each other while sharing an access line, as explained below. In some cases, the self-selecting memory cells may be multi-level self-selecting memory cells configured to use multi-level storage techniques to store more than one data bit.

[0026] In some instances, each row of memory cells 105 is connected to access lines 110, and each column of memory cells 105 is connected to bit lines 115. Access lines 110 and bit lines 115 may be substantially perpendicular to each other and may form an array of memory cells. Two memory cells 105 in a stack of memory cells 145 may share a common conductive line (e.g., bit line 115). That is, bit line 115 may be in electronic communication with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. Other configurations are possible; for example, a third material may share access lines 110 with the lower material. Generally, a memory cell 105 may be located at the intersection of two conductive lines (e.g., access lines 110 and bit lines 115). This intersection may be referred to as the address of the memory cell. The target memory cell 105 may be a memory cell 105 located at the intersection of the energized access line 110 and the bit line 115; that is, the access line 110 and the bit line 115 may be energized to read or write to the memory cell 105 at its intersection. Other memory cells 105 that are electronically communicated with the same access line 110 or bit line 115 (e.g., connected to the same access line 110 or bit line 115) may be referred to as non-target memory cells 105.

[0027] As discussed above, electrodes may be coupled to memory cell 105 and access line 110 or bit line 115. The term electrode may refer to an electrical conductor and, in some cases, may serve as an electrical contact to memory cell 105. Electrodes may include traces, wires, conductive lines, conductive materials, or the like that providing a conductive path between elements or components of memory device 100. In some instances, memory cell 105 may include a chalcogenide material positioned between a first electrode and a second electrode. One side of the first electrode may be coupled to access line 110 and the other side of the first electrode may be coupled to the chalcogenide material. Additionally, one side of the second electrode may be coupled to bit line 115 and the other side of the second electrode may be coupled to the chalcogenide material. The first electrode and the second electrode may be made of the same material (e.g., carbon) or different materials.

[0028] Operations (e.g., read and write) can be performed on memory cell 105 by activating or selecting access line 110 and bit line 115. In some instances, access line 110 may also be referred to as word line 110, and bit line 115 may also be referred to as bit line 115. References to word line and bit line or the like are interchangeable without loss of understanding or operation. Activating or selecting word line 110 or bit line 115 may involve applying a voltage to the respective line. Word line 110 and bit line 115 may be made of conductive materials, such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductive doped semiconductors, or other conductive materials, alloys, compounds, or the like.

[0029] Access to memory cell 105 can be controlled via row decoder 120 and column decoder 130. For example, row decoder 120 can receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, column decoder 130 can receive a column address from memory controller 140 and activate the appropriate digital line 115. Therefore, by activating word line 110 and digital line 115, memory cell 105 at their intersection can be accessed.

[0030] After access, the memory cell 105 can be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, a voltage can be applied to the memory cell 105 (using the corresponding word line 110 and bit line 115), and the presence of the resulting current may depend on the applied voltage and threshold voltage of the memory cell 105. In some cases, more than one voltage may be applied. Furthermore, if the applied voltage does not result in current flow, other voltages may be applied until current is detected by the sensing component 125. By evaluating the voltage that results in current flow, the stored logic state of the memory cell 105 can be determined. In some cases, the voltage may be ramped up in magnitude until current flow is detected. In other cases, determined voltages may be applied sequentially until current is detected. Similarly, current may be applied to the memory cell 105, and the magnitude of the voltage that produces the current may depend on the resistance or threshold voltage of the memory cell 105.

[0031] Sensing component 125 may include various transistors or amplifiers to detect and amplify differences in signals (this may be referred to as latching). The detected logic state of memory unit 105 can then be output as input / output 135 via column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 may be connected to or in electronic communication with column decoder 130 or row decoder 120. Sensing component can be associated with column decoder or row decoder without losing its functional purpose.

[0032] Memory cell 105 can be set or written by similarly activating the associated word line 110 and digital line 115, and at least three logic values ​​can be stored in memory cell 105. In some cases, more than three logic values ​​can be stored in memory cell 105. Column decoder 130 or row decoder 120 can accept data to be written to memory cell 105 (for example, input / output 135). In the case of a self-selective memory cell containing chalcogenide material, data can be stored by applying multiple pre-read voltages during a pre-read portion and then applying a first read voltage and a second read voltage during a read portion. The magnitude and polarity of the first read voltage and the second read voltage can vary. See below for reference. Figure 3A , 3B This process is discussed in more detail in sections 4A and 4B.

[0033] The memory controller 140 can control the operation (e.g., read, write, rewrite, refresh, discharge) of the memory cell 105 via various components (e.g., row decoder 120, column decoder 130, and sensing component 125). In some cases, one or more of the row decoder 120, column decoder 130, and sensing component 125 may be co-located with the memory controller 140. The memory controller 140 can generate row and column address signals to activate the desired word line 110 and digital line 115. The memory controller 140 can also generate and control various voltages or currents used during the operation of the memory device 100.

[0034] The memory controller 140 can be configured to access multilevel memory cells. For example, the memory controller 140 can be configured to perform a prefetch portion and a fetch portion to access the multilevel memory cells. During the prefetch portion, the memory controller 140 can apply multiple different voltages to multiple partitions of the memory device (e.g., each partition contains a certain number of memory cells). The memory controller 140 can identify the distribution associated with the memory cells storing a first logic state.

[0035] Based on the identified distribution, the memory controller 140 can select a first read voltage to distinguish between storing a first logic state and a second logic state, and apply the first read voltage as part of the read portion. Next, the memory controller 140 can select a second read voltage to distinguish between storing a second logic state and a third logic state, and apply the second read voltage as part of the read portion. The selected second read voltage can be based on the selected first read voltage. The memory device can determine the logic state (e.g., first, second, or third logic state) based on the applied first and second read voltages. Accessing multilevel memory cells via a pre-fetch portion and a read portion saves current and improves the performance of the multilevel memory cells.

[0036] Figure 2 This describes an example of a memory array 200 that supports access to multilevel memory cells, as disclosed herein. The memory array 200 may be used as a reference. Figure 1 An example of a portion of the described memory array. Memory array 200 may include a first memory cell array or layer 205 positioned above substrate 204 and a second memory cell array or layer 210 located on top of the first array or layer 205. Memory array 200 may also include word lines 110-a and 110-b, and bit line 115-a, which may be as described in reference... Figure 1 Examples of word line 110 and bit line 115 are described. The memory cells of the first level 205 and the second level 210 may each have one or more self-selectable memory cells. Although the numerical indicators are used to indicate the inclusion of... Figure 2 Some elements are shown, but other corresponding elements are not labeled, but they are the same or will be understood as similar, in an effort to increase the visibility and clarity of the features depicted.

[0037] The self-selection memory cell of the first layer 205 may include a first electrode 215-a, a chalcogenide material 220-a, and a second electrode 225-a. Additionally, the self-selection memory cell of the second layer 210 may include a first electrode 215-b, a chalcogenide material 220-b, and a second electrode 225-b. In some embodiments, the self-selection memory cells of the first layer 205 and the second layer 210 may have a common conductive line, such that corresponding self-selection memory cells of each layer 205 and 210 can share [as referenced]. Figure 1 The bit line 115 or word line 110 is described. For example, the first electrode 215-b of the second layer 210 and the second electrode 225-a of the first layer 205 can be coupled to the bit line 115-a, such that the bit line 115-a is shared by vertically adjacent self-select memory cells.

[0038] The architecture of memory array 200 can be referred to as a cross-point architecture, in which memory cells are formed at the topological cross-points between word lines and bit lines, such as... Figure 2 The explanation is as follows. Compared to other memory architectures, this crosspoint architecture can provide relatively high-density data storage at a lower production cost. For example, the crosspoint architecture can have memory cells with a smaller area and therefore increased memory cell density compared to other architectures. For example, DRAM can use transistors (which are three-terminal devices) as selection components for each memory cell and can have a larger memory cell area compared to the crosspoint architecture.

[0039] In some architectures, multiple word lines may be formed on a parallel plane or layer parallel to the substrate. The multiple word lines may be configured to include multiple vias to allow multiple bit lines to be formed orthogonally to the plane of the word lines, such that each of the multiple bit lines penetrates a set of vertical alignment vias (e.g., the bit lines are positioned perpendicular to the plane of the word lines and the horizontal substrate). Memory cells containing memory elements (e.g., self-selecting memory cells containing chalcogenide material) may be formed at the intersection of the word lines and bit lines (e.g., the space between the word lines and bit lines in the set of vertical alignment vias). (Refer to the above) Figure 1 A similar approach can be described where a memory cell (e.g., a self-selecting memory cell containing chalcogenide material) can be operated (e.g., read and / or programmed) by selecting the appropriate access line (e.g., bit line and word line) and applying a voltage or current pulse.

[0040] Although Figure 2 The example illustrates two memory layers, but other configurations are possible. In some instances, a single memory layer (which may be referred to as a two-dimensional memory) of self-selecting memory cells may be constructed above substrate 204. In some instances, three or four memory layers of memory cells may be configured in a manner similar to that in a three-dimensional intersection architecture. In some instances, one or more of the memory layers may contain self-selecting memory cells comprising chalcogenide material 220. Chalcogenide material 220 may (for example) comprise chalcogenide glasses, such as (for example) alloys of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some instances, a chalcogenide material primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some instances, the SAG alloy may comprise silicon (Si), and this chalcogenide material may be referred to as a SiSAG alloy. In some instances, chalcogenide glasses may contain additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F).

[0041] In some instances, a selectable memory cell containing chalcogenide material 220 can be accessed by applying a prefetch voltage and one or more read voltages to the selectable memory cell using bit line 115 and word line 110. In one instance, a controller associated with the selectable memory cell can apply multiple voltages (e.g., prefetch voltages) to multiple selectable memory cells. Based on the distribution identified from the applied multiple voltages, a first read voltage can be determined and applied to the selectable memory cell. A second read voltage can be determined based on the determined first read voltage and applied to the selectable memory cell. In such cases, the controller associated with the selectable memory cell can determine the logic state stored by the memory cell based on the applied first read voltage and second read voltage.

[0042] Figure 3A The illustration shows an example of diagram 300 illustrating the distribution of threshold voltages for a self-selecting memory cell that supports access to a multilevel memory cell, as disclosed herein. The multilevel self-selecting memory cell can be configured to store logic states representing multiple data bits using multilevel storage technology. The voltage distribution depicts the readable logic states. The threshold voltage distribution can represent a multilevel cell programming scheme for accessing the multilevel memory cell.

[0043] exist Figure 3A In some instances, distribution 305 may represent a set state (e.g., a first logic state), distribution 310 may represent an intermediate state (e.g., a second logic state), and distribution 315 may represent a reset state (e.g., a third logic state). In some cases, distributions 305, 310, and 315 may represent intermediate voltage values ​​(e.g., normal quantiles) corresponding to the voltage distribution for each logic state. In some instances, two distributions may have overlapping portions, and therefore there may not be a clear separation between the two distributions. In some instances, each distribution may not be symmetrical about its midpoint. In some instances, each distribution may represent a different range of voltage values. In some cases, an intermediate state (e.g., distribution 310) may have a voltage programming polarity with the same polarity as a set state (e.g., distribution 305) or a reset state (e.g., distribution 315). In some cases, diagram 300 may include distributions representing more logic states. For example, diagram 300 may include distributions representing a fourth, fifth, or more logic states.

[0044] Figure 3B This describes an example of a timing diagram 360 supporting access to a multilevel memory cell, as disclosed herein. Timing diagram 360 may include a prefetch section 320 and a fetch section 325. Timing diagram 360 may plot the magnitude of one or more pulses (y-axis) of voltage applied to the memory cell relative to time (x-axis).

[0045] The prefetch portion 320 of timing diagram 360 may include multiple voltages 330. The multiple voltages 330 may be examples of prefetch voltages. During the prefetch portion 320, the multiple voltages 330 may be applied to several different groups of memory cells. For example, the memory device may apply multiple voltages 330 to multiple memory cells as part of the prefetch portion 320 of a read operation. The prefetch portion of the read operation can be used to determine the distribution of at least one logic state stored by the memory cells. The voltage threshold associated with the first logic state stored by the memory cells may drift over time based on changing conditions in the memory device. Using the distribution determined during the prefetch portion, read voltages that can reduce or mitigate the possibility of errors during the read operation can be selected.

[0046] The plurality of voltages 330 may include at least a first voltage 335-a, a second voltage 335-b, and a third voltage 335-c. The plurality of voltages 330 may have the same polarity as the first read voltage 340. In some cases, the magnitude of each of the plurality of voltages 330 may differ from the magnitude 345 of the first read voltage 340. For example, the magnitude of each of the first voltage 335-a, the second voltage 335-b, and the third voltage 335-c may be less than the magnitude 345 of the first read voltage 340.

[0047] In some cases, the prefetch portion 320 may include applying different voltages (e.g., multiple voltages 330) to one or more partitions of the memory array. The memory array may include multiple partitions, each of which may contain multiple memory cells (e.g., two or more memory cells). As part of the prefetch portion 320, the memory device may apply a first voltage 335-a to a first partition of the multiple memory cells and identify a first number of memory cells in the first partition where a backlash event has occurred. The memory device may then apply a second voltage 335-b to a second partition of the multiple memory cells and identify a second number of memory cells in the second partition where a backlash event has occurred. The memory device may apply a third voltage 335-c to a third partition of the multiple memory cells and identify a third number of memory cells in the third partition where a backlash event has occurred. Based on the first, second, and third numbers of memory cells, the memory device may identify the magnitude 345 or polarity of the first read voltage 340, or both, as described in further detail below.

[0048] In some instances, the memory device may apply any number of voltages 330 to any number of memory cells or partitions. For example, the memory device may apply different voltages 330 to different partitions of multiple memory cells and identify the number of memory cells in which a backlash event occurs. In such cases, the memory device may identify the magnitude 345 or polarity of the first read voltage 340, or both, based on the number of memory cells. In some cases, the memory device may apply any number of voltages 330 to sub-cells or bits of the memory device.

[0049] In some instances, multiple voltages 330 may be applied to the codewords of a partition. The codewords may be divided into codeword sets, allowing each codeword set to be read under different voltages 330. Based on the application of multiple voltages 330 to the codewords, the memory device may then identify a possible distribution of one of the logic states in the memory cells. For example, the memory device may combine prefetch data (e.g., data associated with the application of a first voltage 335-a, a second voltage 335-b, and a third voltage 335-c) to determine the shape of the distribution. In such cases, the memory device may summarize the data associated with the application of the first voltage 335-a to the first partition, the second voltage 335-b to the second partition, and the third voltage 335-c to the third partition. Summarizing the prefetch data can improve the efficiency of the memory device by reducing read latency and selecting a first read voltage based on the prefetch data. In some cases, the memory device may determine the shape of the distribution by identifying one or more possible distributions (e.g., distribution 305) of the threshold voltage associated with the memory cell storing the first logic state.

[0050] The shape of a distribution can be determined by reading memory cells at different voltages 330 (e.g., a first voltage 335-a, a second voltage 335-b, and a third power supply 335-c) and determining the voltage drift associated with each distribution (e.g., distributions 305, 310, and 315). The memory device can ramp up different partitions to different voltages 330 and determine the amount of bit thresholding at each of the plurality of voltages 330 (e.g., a first voltage 335-a, a second voltage 335-b, and a third power supply 335-c). Increasing the amount of bit thresholding can increase the accuracy of the determined shape of the distribution. In some cases, the determined bit thresholding amount may be higher than a threshold that identifies a reverting event.

[0051] In some cases, distributions experiencing low voltage drift or no voltage drift may be given lower priority compared to distributions experiencing high voltage drift. For example, distribution 305 may experience almost no voltage drift, while distribution 310 may experience higher voltage drift compared to distribution 305. Based on voltage drift, a first read voltage 340 can be selected between distributions experiencing low or no voltage drift and distributions experiencing high voltage drift. The memory device can sort the distributions and select the highest priority as the starting point for the first read voltage 340.

[0052] Timing diagram 360 may include a read portion 325 following a pre-fetch portion 320. Read portion 325 may include a first read voltage 340 and a second read voltage 350. Using the information associated with possible distributions and the shape of those distributions, the memory device may select the first read voltage 340 for the operating read portion 325. In some instances, the memory device may count the number of set bits in a codeword based on a pre-fetch setting state (e.g., distribution 305). The first read voltage 340 may be determined based on summarizing pre-fetch data, identifying one or more possible distributions of a threshold voltage, or both. In some instances, the magnitude 345 or polarity of the first read voltage 340 may be determined based on data associated with the pre-fetch portion 320.

[0053] The memory device may apply a first read voltage 340 to a memory cell of a plurality of memory cells to identify the logical state stored by the memory cell as part of a read portion 325 of a read operation. In some cases, the memory device may identify the magnitude 345 of the first read voltage 340 based on the application of a plurality of voltages 330. The memory device may also determine the polarity of the first read voltage 340. For example, the memory device may determine that the polarity of the first read voltage 340 is positive.

[0054] In some cases, the first read voltage 340 may be between the voltage associated with distribution 305 and the voltage associated with distribution 310. In such cases, the memory device may determine that the first read voltage 340 is between the voltage of a first type of state (e.g., distribution 305) and the voltage of a second type of state (e.g., distribution 310). The first type of state may be stored through memory cells that have been disturbed after a backlash event. The second type of state may be stored through memory cells that have been enhanced after a backlash event. In some instances, the memory device may read the logic state associated with distribution 305 based on the application of the first read voltage 340.

[0055] Read interference may be induced after the first read voltage 340 is applied. In such cases, a write-back operation can be performed on the memory cell to reduce read interference to the intermediate state of the memory cell (e.g., distribution 310). The memory device can detect the intermediate state associated with distribution 310 and determine whether a first surge event has occurred based on the application of the first read voltage 340. The memory device can then perform a reprogramming operation on the memory cell after determining that the logic state stored by the memory cell is an intermediate state and that a first surge event has occurred. In some instances, the memory device can determine that the logic state associated with distribution 315 has not experienced a surge event, thereby avoiding read interference to distribution 315.

[0056] In some instances, the memory device may recognize voltage drift from the applied first read voltage 340. In such cases, the memory device may select a second read voltage 350 to be applied to the memory cell. For example, the memory device may select the second read voltage 350 based on an offset (e.g., a pre-configured or predetermined offset) between the first read voltage 340 and the second read voltage 350. In such cases, the memory device may recognize an offset between a magnitude 345 of the first read voltage 340 and a magnitude 355 of the second read voltage 350. This offset can be used because, in some cases, the variation in the distribution of voltage thresholds for the first logic state may resemble the variation in the distribution of voltage thresholds for other logic states.

[0057] In some cases, the memory device may determine that the voltage drift of distribution 305 is the same as that of distribution 310. In such cases, the memory device may select a second read voltage 350 based on a constant offset (e.g., voltage drift). The voltage drift of distribution 315 may be greater than the voltage drifts of distributions 310 and 305. In such cases, the sensing window of distribution 315 may be increased. The memory device may determine the magnitude 355 of the second read voltage 350 based on determining the magnitude 315 of the first read voltage, determining the offset, or both. For example, the magnitude 355 of the second read voltage 350 may be greater than the magnitude 345 of the first read voltage 340.

[0058] After applying the first read voltage 340, the memory device may apply a second read voltage 350 to a memory cell of a plurality of memory cells as part of a read portion 325 of a read operation. The second read voltage 350 may be between a voltage associated with distribution 310 and a voltage associated with distribution 315. In such cases, the memory device may determine that the second read voltage 350 is between a voltage of a second type of state (e.g., distribution 310) and a voltage of a third type of state (e.g., distribution 315). The second type may be able to be stored by memory cells enhanced after a backlash event. The third type may be able to be stored by memory cells disturbed after a backlash event.

[0059] In some cases, the memory device may determine the polarity of the second read voltage 350. For example, the memory device may determine that the polarity of the second read voltage 350 is positive. In such cases, the polarity of the second read voltage 350 is the same as the polarity of the first read voltage 340. In some cases, applying the second read voltage 350 may be based on determining the second read voltage 350, identifying the polarity of the second read voltage 350, identifying the magnitude 355 of the second read voltage 350, or a combination thereof. In some instances, applying the second read voltage 350 may be based on determining that a first backlash event has not occurred.

[0060] The performance of a memory cell can be improved by applying two read voltages of the same polarity, thereby preventing the memory device from changing the polarity of the read voltage during the read portion 325. Changing the voltage polarity during a read operation can increase the duration of the read operation or increase the power consumed by the read operation, or both. In some cases, a pre-read portion 320 that includes a first read voltage 340 identifying the read portion 325 during a read operation can increase the number of bits accessed per memory cell, reduce the size of the memory die, and reduce the density of the memory array, thereby reducing power consumption and increasing the read, write, and erase operations of the memory device.

[0061] In some instances, apparatus, systems, and techniques for accessing multilevel self-selective memory cells that store more than three states are described. See references... Figure 3B The memory device can select a second read voltage 350 to distinguish between storing a second logic state and a third logic state based on a first read voltage 340. In some cases, the memory device can select a third read voltage to distinguish between storing a third logic state and a fourth logic state based on the second read voltage 350. In other instances, the memory device can select a fourth read voltage to distinguish between storing a fourth logic state and a fifth logic state based on the third read voltage. In such cases, the memory device can determine the fourth or fifth logic state based on the applied third and fourth read voltages.

[0062] Figure 4A This illustration shows an example of Figure 400, illustrating the distribution of threshold voltages for self-selecting memory cells supporting access to multi-level memory cells according to an example disclosed herein. Figure 400 may be used as a reference. Figure 3A An example of diagram 300 is described. In some cases, diagram 400 may contain a distribution representing more than three logical states. For example, diagram 400 may contain a distribution representing a fourth, fifth, or more logical states.

[0063] Figure 4B This describes an example of timing diagram 460 supporting access to multilevel memory cells, as disclosed herein. Timing diagram 460 may include a prefetch section 420 and a fetch section 425. Timing diagram 460 may plot the magnitude of one or more pulses (y-axis) of voltage applied to the memory cell relative to time (x-axis).

[0064] The pre-read section 420 and the multiple voltages 430 including the first voltage 435-a, the second voltage 435-b, and the third voltage 435-c can each be a reference. Figure 3BExamples of the described prefetch section 320, multiple voltages 330, first voltage 335-a, second voltage 335-b, and third voltage 335-c. Operations performed by the memory device and associated with the prefetch section 420 may be performed by the memory device and associated with a reference... Figure 3B The description describes an example of the operation associated with the pre-read section 320. The first read voltage 440, having a magnitude of 445, can be a reference voltage. Figure 3B An example of a first reading voltage of 340 with a described value of 345.

[0065] In some cases, the memory device may determine the polarity of the second read voltage 450. For example, the memory device may determine that the polarity of the second read voltage 450 is negative. In such cases, the polarity of the second read voltage 450 is different from the polarity of the first read voltage 440. The memory device may apply the second read voltage 450, having a second polarity and a second magnitude 455, to a portion of the read portion 425 of a memory cell as a read operation. In some cases, the second read voltage 450 may have a magnitude 455 different from the magnitude 445 relative to a reference voltage magnitude.

[0066] The memory device can determine that a crash event has occurred in a setting state associated with distribution 405. In such a case, the memory device can reverse the polarity of a reset state associated with distribution 415 and determine that a crash event has occurred in the reset state. In such a case, the setting state and the reset state can be strengthened after the crash event occurs (e.g., the memory cell can be refreshed after determining that a crash event has occurred). The polarity of a first read voltage 440 can be selected to strengthen (e.g., associated with distribution 405) the setting state, and the polarity of a second read voltage 450 can be selected to strengthen the reset state (e.g., associated with distribution 415).

[0067] The intermediate states associated with distribution 410 can remain undisturbed, thereby maintaining their connection with the reference. Figure 3B The described write-back operation amount is reduced compared to the write-back operation performed on the intermediate state. The memory device can determine that a rush event did not occur for the intermediate state. In such cases, the memory device can determine the voltage drift associated with the intermediate state based on the lack of a rush event and the lack of a refresh operation. Read operations according to timing diagram 460 can be selected to reduce read interference, while read operations according to timing diagram 360 can be selected to reduce voltage drift.

[0068] The memory device can change the polarity of the second read voltage 450 during the read section 425 by applying two sequential read voltages of opposite polarity (e.g., changing it to be opposite to the polarity of the first read voltage 440). In some instances, the difference in polarity between the first read voltage 440 and the second read voltage 450 can reduce the amount of write-back operations performed on intermediate states (e.g., distribution 410). In some cases, write-back operations on intermediate states may not be performed based on sequential read voltages using opposite polarities. In such cases, the memory device may not interfere with intermediate states of positive or negative polarity, thereby affecting the reference... Figure 3B The described read operation reduces power consumption and improves read efficiency. Since the intermediate state is unaffected by the first or second read voltage, write-back operations in the intermediate state can be eliminated, thereby reducing the duration and power consumption of the read operation.

[0069] In some instances, apparatus, systems, and techniques for accessing multilevel self-selective memory cells that store more than three states are described. See references... Figure 4B The memory device can select a second read voltage 450 to distinguish between storing a second logic state and a third logic state based on a first read voltage 440. In some cases, the memory device can select a third read voltage to distinguish between storing a third logic state and a fourth logic state based on the second read voltage 450. In other instances, the memory device can select a fourth read voltage to distinguish between storing a fourth logic state and a fifth logic state based on the third read voltage. In such cases, the memory device can determine the fourth or fifth logic state based on the applied third and fourth read voltages.

[0070] Figure 5 A block diagram 500 illustrates a memory device 505 supporting access to multilevel memory cells according to an example disclosed herein. The memory device 505 may be as described in the references... Figure 1 Examples of aspects of the memory device described in section 4. The memory device 505 may include a prefetch component 510, a first voltage component 515, a second voltage component 520, a logic state component 525, and a partitioning component 530. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0071] The prefetch component 510 may apply a set of voltages to a set of memory cells as part of the prefetch portion of a read operation. In some instances, the prefetch component 510 may apply a first voltage to a first partition of the set of memory cells. In some instances, the prefetch component 510 may apply a second voltage to a second partition of the set of memory cells.

[0072] In some instances, the prefetch component 510 may identify the magnitude or polarity of the first read voltage, or both, based on a first quantity and a second quantity. In some instances, the prefetch component 510 may summarize data associated with applying a first voltage to a first partition and applying a second voltage to a second partition, wherein identifying the first magnitude of the first read voltage is based on the summarized data.

[0073] In some instances, the prefetch component 510 may identify one or more possible distributions of threshold voltages associated with memory cells storing a first logic state based on a first quantity and a second quantity, wherein the identification of the magnitude or polarity of the first read voltage, or both, is based on identifying one or more possible distributions of threshold voltages. In some instances, the prefetch component 510 may apply different voltages to different partitions of the set of memory cells. In some instances, the prefetch component 510 may identify the magnitude or polarity of the first read voltage, or both, based on the number of memory cells.

[0074] The first voltage component 515 may apply a first read voltage to the memory cells of the group of memory cells based on the application of the set of voltages to identify the logical state stored in the memory cells as a portion of the read operation. In some instances, the first voltage component 515 may apply a first read voltage having a first magnitude and a first polarity to the memory cells of the group of memory cells based on the application of the set of voltages to identify the logical state stored in the memory cells as a portion of the read operation. In some instances, the first voltage component 515 may apply a first read voltage having a first polarity to the memory cells of the group of memory cells based on the application of the set of voltages to identify the logical state stored in the memory cells as a portion of the read operation.

[0075] In some instances, the first voltage component 515 may identify a first magnitude of the first read voltage based on applying the set of voltages, wherein applying the first read voltage is based on identifying the first magnitude of the first read voltage. In some instances, the first voltage component 515 may determine that the first read voltage is between a voltage capable of storing a first type of state through a memory cell that has been disturbed after a backlash event and a voltage capable of storing a second type of state through a memory cell that has been enhanced after a backlash event, wherein applying the first read voltage is based on the determination.

[0076] In some instances, the first voltage component 515 can identify the polarity of the first read voltage, wherein applying the first read voltage is based on identifying the polarity of the first read voltage. In some instances, the first voltage component 515 can identify a first polarity of both the first read voltage and the second read voltage, wherein applying the first read voltage and applying the second read voltage are based on identifying the first polarity, wherein the first polarity is positive. In some instances, the first voltage component 515 can identify a first polarity of the first read voltage, wherein applying the first read voltage is based on identifying the first polarity of the first read voltage.

[0077] The second voltage component 520 may apply a second read voltage to the memory cells of the group of memory cells as a read portion of a read operation based on the application of a first read voltage. In some instances, the second voltage component 520 may apply a second read voltage having a second magnitude and a first polarity to the memory cells as a read portion of a read operation based on the application of a first read voltage. In some instances, the second voltage component 520 may apply a second read voltage having a second polarity to the memory cells as a read portion of a read operation based on the application of a first read voltage.

[0078] In some instances, the second voltage component 520 may identify a second value of the second read voltage based on identifying a first value of the first read voltage, wherein the second read voltage is applied based on the identified second value of the second read voltage. In some instances, the second voltage component 520 may identify a second value of the second read voltage based on identifying a first value of the first read voltage, wherein the second read voltage is applied based on the identified second value of the second read voltage, wherein the first value is less than the second value. In some instances, the second voltage component 520 may identify a second value of the second read voltage based on identifying a first value of the first read voltage, wherein the second read voltage is applied based on the identified second value of the second read voltage, wherein the first value is equal to the second value.

[0079] In some instances, the second voltage component 520 may identify an offset between a first magnitude of the first read voltage and a second magnitude of the second read voltage, wherein the identification of the second magnitude of the second read voltage is based on the offset and the first magnitude. In some instances, the second voltage component 520 may determine that the second read voltage is between a voltage capable of storing a second type of state through a memory cell enhanced after a backlash event and a voltage capable of storing a third type of state through a memory cell disturbed after a backlash event, wherein the second read voltage is applied based on the determination.

[0080] In some instances, the second voltage component 520 can identify the polarity of the second read voltage, wherein applying the second read voltage is based on identifying the polarity of the second read voltage. In some instances, the second voltage component 520 can identify a second polarity of the second read voltage, wherein applying the second read voltage is based on identifying a second polarity of the second read voltage, wherein the first polarity is positive and the second polarity is negative.

[0081] The logic state component 525 can determine the logic state stored in the memory cell based on the application of a first read voltage and the application of a second read voltage. In some instances, the logic state component 525 can determine whether a first surge event has occurred based on the application of the first read voltage, wherein the application of the second read voltage is based on the determination that the first surge event did not occur. In some instances, the logic state component 525 can perform a reprogramming operation on the memory cell after determining the logic state stored in the memory cell based on the determination that a first surge event has occurred.

[0082] The partitioning component 530 can identify a first number of memory cells in a first partition where a rush event has occurred based on the application of a first voltage. In some instances, the partitioning component 530 can identify a second number of memory cells in a second partition where a rush event has occurred based on the application of a second voltage. In some instances, the partitioning component 530 can identify the number of memory cells in a flash event based on the application of a different voltage.

[0083] Figure 6 The flowchart illustrates one or more methods 600 for supporting access to multilevel memory cells according to examples disclosed herein. The operation of method 600 can be implemented by a memory device or its components as described herein. For example, it can be implemented by... (refer to...) Figure 5 The described memory device performs the operation of method 600. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described function. Alternatively or additionally, the memory device may use dedicated hardware to perform aspects of the described function.

[0084] In 605, the memory device may apply a set of voltages to a set of memory cells as part of a pre-fetch portion of a read operation. The operation of 605 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The described aspect of the prefetch component performing the 605 operation.

[0085] In 610, the memory device may apply a first read voltage to a memory cell of the set of memory cells based on applying the set of voltages to identify the logical state stored by the memory cell as a portion of the read portion of a read operation. The operation of 610 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 5 The first voltage component described performs the operation of 610.

[0086] In 615, the memory device may apply a second read voltage to a memory cell of the set of memory cells as part of a read operation based on the application of a first read voltage. The operation of 615 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 5 The second voltage component described performs the operation of 615.

[0087] In 620, the memory device can determine the logical state stored in the memory cell based on the application of a first read voltage and the application of a second read voltage. Operation of 620 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 5 The described logical state component performs the 620 operation aspect.

[0088] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: applying a set of voltages to a set of memory cells as a pre-fetch portion of a read operation; applying a first read voltage to memory cells of the set of memory cells based on the applied set of voltages to identify a logical state stored in the memory cells as a read portion of the read operation; applying a second read voltage to the memory cells of the set of memory cells based on the applied first read voltage as a read portion of the read operation; and determining the logical state stored in the memory cells based on the applied first read voltage and the applied second read voltage.

[0089] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for identifying a first magnitude of a first read voltage based on the application of the set of voltages, wherein the application of the first read voltage may be based on the identification of a first magnitude of the first read voltage.

[0090] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for identifying a second value of a second read voltage based on a first value of a first read voltage, wherein applying the second read voltage may be based on the second value of the second read voltage.

[0091] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for identifying an offset between a first value of a first read voltage and a second value of a second read voltage, wherein the identification of the second value of the second read voltage may be based on the offset and the first value.

[0092] In some instances of the method 600 and apparatus described herein, applying the set of voltages may further include operations, features, components, or instructions for: applying a first voltage to a first partition of the set of memory cells; identifying a first number of memory cells in the first partition where a backlash event has occurred based on the application of the first voltage; applying a second voltage to a second partition of the set of memory cells; identifying a second number of memory cells in the second partition where the backlash event has occurred based on the application of the second voltage; and identifying the magnitude or polarity of the first read voltage, or both, based on the first number and the second number.

[0093] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for summarizing data associated with applying a first voltage to a first partition and applying a second voltage to a second partition, wherein identifying a first magnitude of the first read voltage may be based on the summarized data.

[0094] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for identifying one or more possible distributions of threshold voltages associated with a memory cell storing a first logic state based on a first quantity and a second quantity, wherein the identification of the magnitude or polarity of the first read voltage, or both, may be based on identifying one or more possible distributions of the threshold voltage.

[0095] In some instances of the method 600 and apparatus described herein, the first partition and the second partition each contain two or more memory cells from the set of memory cells.

[0096] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for determining a first read voltage between a voltage of a first type of state that can be stored by a memory cell that can be disturbed after a backlash event and a voltage of a second type of state that can be stored by a memory cell that can be enhanced after a backlash event, wherein the application of the first read voltage may be based on the determination.

[0097] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for determining a second read voltage between a voltage of a second type of state that can be stored by a memory cell that can be enhanced after a backlash event and a voltage of a third type of state that can be stored by a memory cell that can be disturbed after a backlash event, wherein the application of the second read voltage may be based on the determination.

[0098] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for identifying the polarity of a first read voltage, wherein applying the first read voltage may be based on identifying the polarity of the first read voltage and identifying the polarity of a second read voltage, wherein applying the second read voltage may be based on identifying the polarity of the second read voltage.

[0099] In some instances of the method 600 and apparatus described herein, the polarity of the first read voltage may be the same as the polarity of the second read voltage.

[0100] In some instances of the method 600 and apparatus described herein, the polarity of the first read voltage may be different from the polarity of the second read voltage.

[0101] In some instances of the method 600 and apparatus described herein, applying the set of voltages may further include operations, features, components, or instructions for: applying different voltages to different partitions of the set of memory cells; identifying the number of memory cells in which a backlash event occurred based on the application of the different voltages; and identifying the magnitude or polarity of a first read voltage, or both, based on the number of memory cells.

[0102] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for determining whether a first backlash event has occurred based on the application of a first read voltage, wherein the application of a second read voltage may be based on the determination that the first backlash event has not occurred.

[0103] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for performing a reprogramming operation on a memory cell after determining the logical state stored in the memory cell based on the determination that a first recurrence event has occurred.

[0104] Figure 7 The flowchart illustrates one or more methods 700 for supporting access to multilevel memory cells according to examples disclosed herein. The operation of method 700 can be implemented by a memory device or its components as described herein. For example, it can be implemented by... (refer to...) Figure 5 The described memory device performs the operation of method 700. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described function. Alternatively or additionally, the memory device may use dedicated hardware to perform aspects of the described function.

[0105] In 705, the memory device may apply a set of voltages to a set of memory cells as part of a pre-fetch portion of a read operation. The operation of 705 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5The described aspects of the prefetch component performing the 705 operation.

[0106] In 710, the memory device may apply a first read voltage having a first magnitude and a first polarity to the memory cells of the set of memory cells based on applying the set of voltages to identify the logical state stored by the memory cells as a portion of the read portion of a read operation. The operation of 710 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 5 The first voltage component described performs the operation of 710.

[0107] In 715, the memory device can apply a second read voltage having a second magnitude and a first polarity to a portion of the memory cell as a read portion of a read operation, based on the application of a first read voltage. The operation of 715 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The second voltage component described performs the operation of 715.

[0108] In 720, the memory device can determine the logical state stored in the memory cell based on the application of a first read voltage and the application of a second read voltage. Operation of 720 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 5 The described logical state component performs the 720 operation.

[0109] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: applying a set of voltages to a set of memory cells as a pre-fetch portion of a read operation; applying a first read voltage having a first magnitude and a first polarity to memory cells of the set of memory cells based on the applied set of voltages to identify a logical state stored in the memory cells as a read portion of the read operation; applying a second read voltage having a second magnitude and the first polarity to the memory cells based on the applied first read voltage as the read portion of the read operation; and determining the logical state stored in the memory cells based on the applied first read voltage and the applied second read voltage.

[0110] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for identifying a first magnitude of a first read voltage based on the application of the set of voltages, wherein the application of the first read voltage may be based on the identification of a first magnitude of the first read voltage.

[0111] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for identifying a second value of a second read voltage based on a first value of a first read voltage, wherein applying the second read voltage may be based on identifying a second value of the second read voltage, wherein the first value may be less than the second value.

[0112] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for identifying an offset between a first value of a first read voltage and a second value of a second read voltage, wherein the identification of the second value of the second read voltage may be based on the offset and the first value.

[0113] In some examples of the method 700 and apparatus described herein, applying the set of voltages may further include operations, features, components, or instructions for: applying a first voltage to a first partition of the set of memory cells; identifying a first number of memory cells in the first partition where a backlash event has occurred based on the application of the first voltage; applying a second voltage to a second partition of the set of memory cells; identifying a second number of memory cells in the second partition where the backlash event has occurred based on the application of the second voltage; and identifying the magnitude or polarity of the first read voltage, or both, based on the first number and the second number.

[0114] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for identifying a first polarity of a first read voltage and a second read voltage, wherein applying the first read voltage and applying the second read voltage may be based on identifying the first polarity, wherein the first polarity may be positive.

[0115] Figure 8 The flowchart illustrates one or more methods 800 for supporting access to multilevel memory cells according to examples disclosed herein. The operation of method 800 can be implemented by a memory device or its components as described herein. For example, it can be implemented by... (refer to...) Figure 5 The described memory device performs the operation of method 800. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described function. Alternatively or additionally, the memory device may use dedicated hardware to perform aspects of the described function.

[0116] In 805, a memory device may apply a set of voltages to a set of memory cells as part of a pre-fetch portion of a read operation. The operation of 805 can be performed according to the methods described herein. In some instances, it can be performed as described in reference... Figure 5 The described aspects of the prefetch component performing 805 operations.

[0117] In 810, the memory device may apply a first read voltage of a first polarity to a memory cell of the set of memory cells based on the application of the set of voltages to identify the logical state stored by the memory cell as a portion of the read portion of a read operation. The operation of 810 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 5 The first voltage component described performs the operation of 810.

[0118] In 815, the memory device may apply a second read voltage of a second polarity to a portion of the memory cell as a read portion of a read operation, based on the application of a first read voltage. The operation of 815 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 5 The second voltage component described performs the operation of 815.

[0119] In 820, the memory device can determine the logical state stored in the memory cell based on the application of a first read voltage and the application of a second read voltage. Operation of 820 can be performed according to the methods described herein. In some instances, it can be performed by, as referenced... Figure 5 The described logical state component performs the 820 operation.

[0120] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: applying a set of voltages to a set of memory cells as a pre-fetch portion of a read operation; applying a first read voltage of a first polarity to memory cells of the set of memory cells based on the applied set of voltages to identify a logical state stored in the memory cells as a read portion of the read operation; applying a second read voltage of a second polarity to the memory cells based on the applied first read voltage as the read portion of the read operation; and determining the logical state stored in the memory cells based on the applied first read voltage and the applied second read voltage.

[0121] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for identifying a first magnitude of a first read voltage based on the application of the set of voltages, wherein the application of the first read voltage may be based on the identification of a first magnitude of the first read voltage.

[0122] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for identifying a second value of a second read voltage based on identifying a first value of a first read voltage, wherein applying the second read voltage may be based on identifying a second value of the second read voltage, wherein the first value may be equal to the second value.

[0123] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for identifying an offset between a first value of a first read voltage and a second value of a second read voltage, wherein the identification of the second value of the second read voltage may be based on the offset and the first value.

[0124] In some examples of the method 800 and apparatus described herein, applying the set of voltages may further include operations, features, components, or instructions for: applying a first voltage to a first partition of the set of memory cells; identifying a first number of memory cells in the first partition where a backlash event has occurred based on the application of the first voltage; applying a second voltage to a second partition of the set of memory cells; identifying a second number of memory cells in the second partition where the backlash event has occurred based on the application of the second voltage; and identifying the magnitude or polarity of the first read voltage, or both, based on the first number and the second number.

[0125] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for identifying a first polarity of a first read voltage, wherein applying the first read voltage may be based on identifying a first polarity of the first read voltage and identifying a second polarity of a second read voltage, wherein applying the second read voltage may be based on identifying a second polarity of the second read voltage, wherein the first polarity may be positive and the second polarity may be negative.

[0126] It should be noted that the methods described herein are possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods may be combined.

[0127] Describe a device. The device may include: a memory array including a set of memory cells; and a control component coupled to the memory array, the control component being configured such that the device: applies a set of voltages to a portion of the set of memory cells as a pre-fetch portion of a read operation; applies a first read voltage to a memory cell of the set of memory cells based on the applied set of voltages to identify a logical state stored in the memory cell as a read portion of the read operation; applies a second read voltage to a portion of the memory cell of the set of memory cells based on the applied first read voltage as a read portion of the read operation; and determines the logical state stored in the memory cell based on the applied first read voltage and the applied second read voltage.

[0128] Some instances may further include identifying a first magnitude of the first read voltage based on the application of the set of voltages, wherein the application of the first read voltage may be based on the identification of the first magnitude of the first read voltage.

[0129] Some instances may further include identifying a second value of a second read voltage based on a first value of the first read voltage, wherein applying the second read voltage may be based on the second value of the second read voltage.

[0130] Some instances may further include identifying an offset between a first value of the first read voltage and a second value of the second read voltage, wherein identifying the second value of the second read voltage may be based on the offset and the first value.

[0131] Some examples may further include applying a first voltage to a first partition of the set of memory cells, identifying a first number of memory cells in the first partition where a backlash event has occurred based on the applied first voltage, applying a second voltage to a second partition of the set of memory cells, identifying a second number of memory cells in the second partition where the backlash event has occurred based on the applied second voltage, and identifying the magnitude or polarity of the first read voltage or both based on the first number and the second number.

[0132] Some instances may further include data summarizing the application of a first voltage to a first partition and a second voltage to a second partition, wherein a first magnitude of the first read voltage may be identified based on the summarizing data.

[0133] Some instances may further include identifying one or more possible distributions of threshold voltages associated with the memory cell storing the first logic state based on a first quantity and a second quantity, wherein the magnitude or polarity of the first read voltage or both may be identified based on identifying one or more possible distributions of the threshold voltages.

[0134] In some instances, the first partition and the second partition each contain two or more memory cells from the set of memory cells.

[0135] Some examples may further include determining that a first read voltage is between a voltage of a first type of state that can be stored by a memory cell that can be disturbed after a backlash event and a voltage of a second type of state that can be stored by a memory cell that can be enhanced after a backlash event, wherein the first read voltage may be applied based on the determination.

[0136] Some examples may further include determining that the second read voltage is between the voltage of a second type of state that can be stored by a memory cell that can be enhanced after a backlash event and the voltage of a third type of state that can be stored by a memory cell that can be disturbed after a backlash event, wherein the second read voltage is applied based on the determination.

[0137] Some instances may further include identifying the polarity of a first read voltage, wherein applying the first read voltage may be based on identifying the polarity of the first read voltage and identifying the polarity of a second read voltage, wherein applying the second read voltage may be based on identifying the polarity of the second read voltage.

[0138] In some instances, the polarity of the first read voltage may be the same as the polarity of the second read voltage.

[0139] In some instances, the polarity of the first read voltage may be different from that of the second read voltage.

[0140] Some examples may further include applying different voltages to different partitions of the set of memory cells, identifying the number of memory cells in which a backlash event occurs based on the applied different voltages, and identifying the magnitude or polarity of a first read voltage or both based on the number of memory cells.

[0141] Some instances may further include determining whether a first backlash event has occurred based on the application of a first read voltage, wherein the application of a second read voltage may be based on the determination that the first backlash event has not occurred.

[0142] Some instances may further include performing a reprogramming operation on the memory cell after determining the logical state stored in the memory cell based on the determination that the first backlash event has occurred.

[0143] Describe a device. The device may include: a memory array including a set of memory cells; and a control component coupled to the memory array, the control component being configured such that the device: applies a set of voltages to a portion of the set of memory cells as a pre-read portion of a read operation; applies a first read voltage having a first magnitude and a first polarity to the memory cells of the set of memory cells based on the applied set of voltages to identify a logical state stored in the memory cells as a read portion of the read operation; applies a second read voltage having a second magnitude and the first polarity to the memory cells as a read portion of the read operation based on the applied first read voltage; and determines the logical state stored in the memory cells based on the applied first read voltage and the applied second read voltage.

[0144] Some instances may further include identifying a first magnitude of the first read voltage based on the application of the set of voltages, wherein the application of the first read voltage may be based on the identification of the first magnitude of the first read voltage.

[0145] Some instances may further include identifying a second value of a second read voltage based on identifying a first value of a first read voltage, wherein applying the second read voltage may be based on identifying the second value of the second read voltage, wherein the first value may be less than the second value.

[0146] Some instances may further include identifying an offset between a first value of the first read voltage and a second value of the second read voltage, wherein identifying the second value of the second read voltage may be based on the offset and the first value.

[0147] Some examples may further include applying a first voltage to a first partition of the set of memory cells, identifying a first number of memory cells in the first partition where a backlash event has occurred based on the applied first voltage, applying a second voltage to a second partition of the set of memory cells, identifying a second number of memory cells in the second partition where the backlash event has occurred based on the applied second voltage, and identifying the magnitude or polarity of the first read voltage or both based on the first number and the second number.

[0148] Some instances may further include identifying a first polarity of the first read voltage and the second read voltage, wherein applying the first read voltage and applying the second read voltage may be based on identifying the first polarity, wherein the first polarity may be positive.

[0149] Describe a device. The device may include: a memory array including a set of memory cells; and a control component coupled to the memory array, the control component being configured such that the device: applies a set of voltages to a portion of the set of memory cells as a pre-fetch portion of a read operation; applies a first read voltage of a first polarity to the memory cells of the set of memory cells based on the applied set of voltages to identify a logical state stored in the memory cells as a read portion of the read operation; applies a second read voltage of a second polarity to the memory cells as a read portion of the read operation based on the applied first read voltage; and determines the logical state stored in the memory cells based on the applied first read voltage and the applied second read voltage.

[0150] Some instances may further include identifying a first magnitude of the first read voltage based on the application of the set of voltages, wherein the application of the first read voltage may be based on the identification of the first magnitude of the first read voltage.

[0151] Some instances may further include identifying a second value of a second read voltage based on identifying a first value of a first read voltage, wherein applying the second read voltage may be based on identifying the second value of the second read voltage, wherein the first value may be equal to the second value.

[0152] Some instances may further include identifying an offset between a first value of the first read voltage and a second value of the second read voltage, wherein identifying the second value of the second read voltage may be based on the offset and the first value.

[0153] Some examples may further include applying a first voltage to a first partition of the set of memory cells, identifying a first number of memory cells in the first partition where a backlash event has occurred based on the applied first voltage, applying a second voltage to a second partition of the set of memory cells, identifying a second number of memory cells in the second partition where the backlash event has occurred based on the applied second voltage, and identifying the magnitude or polarity of the first read voltage or both based on the first number and the second number.

[0154] Some instances may further include identifying a first polarity of a first read voltage, wherein applying the first read voltage may be based on identifying the first polarity of the first read voltage and identifying a second polarity of a second read voltage, wherein applying the second read voltage may be based on identifying a second polarity of the second read voltage, wherein the first polarity may be positive and the second polarity may be negative.

[0155] The information and signals described herein can be represented using any of a variety of technologies and techniques. For example, they can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof, as well as the data, instructions, commands, information, signals, bits, symbols, and chips referenced above. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0156] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to a relationship between components that supports signal flow between them. Components are considered to be in electronic communication (or conductive contact, connection, or coupling) with each other if any conductive path exists between them that can readily support signal flow between them. At any given time, the conductive path between components that are in electronic communication (or conductive contact, connection, or coupling) can be open or closed, depending on the operation of a device containing connected components. The conductive path between connected components can be a direct conductive path between components or an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, signal flow between connected components can be interrupted for a period of time using one or more intermediate components, such as switches or transistors.

[0157] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can be used as an electrical contact to a memory cell or other component of a memory array. Electrodes can comprise traces, wires, conductive lines, conductive materials, or the like that providing a conductive path between elements or components of the memory array.

[0158] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOS)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0159] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned off" or "deactivated."

[0160] The descriptions set forth herein, and the example configurations described with accompanying drawings, do not represent all instances that can be implemented or are within the scope of the claims. The term "example" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to other examples." Specific details are included to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0161] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash after the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0162] The information and signals described herein can be represented by any of a variety of technologies and techniques. For example, they can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof, as well as the data, instructions, commands, information, signals, bits, symbols, and chips referenced herein.

[0163] The various illustrative blocks and modules described herein can be implemented or executed using general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0164] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or program code. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including portions distributed such that the functions are implemented in different physical locations. Furthermore, as used herein, the word "or" included in the claims, such as in a list of items (for example, a list of items beginning with phrases such as "at least one of..." or "one or more of..."), indicates a list of inclusions such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a conditionally closed set. For example, without departing from the scope of this disclosure, an instance step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0165] Computer-readable media includes both non-transitory computer storage media and communication media containing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is suitably referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. The combination described above is also included within the scope of computer-readable media.

[0166] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for memory operations, comprising: Applying multiple voltages to multiple memory cells is part of the pre-fetch portion of a read operation; At least in part based on the application of the plurality of voltages, a first read voltage having a first magnitude value identified at least in part based on the application of the plurality of voltages is applied to the memory cells of the plurality of memory cells to identify the logic state stored by the memory cells as part of the read portion of the read operation; The memory cells for which the second read voltage is applied, at least in part, is part of the read portion of the read operation, based on the application of the first read voltage; and The logic state stored by the memory cell is determined at least in part based on the application of the first read voltage and the application of the second read voltage.

2. The method according to claim 1, further comprising: The second value of the second read voltage is identified at least in part based on the first value of the first read voltage, wherein the application of the second read voltage is at least in part based on the second value of the second read voltage.

3. The method according to claim 2, further comprising: The offset between the first value of the first read voltage and the second value of the second read voltage is identified, wherein the second value of the second read voltage is identified at least in part based on the offset and the first value.

4. The method of claim 1, wherein applying the plurality of voltages further comprises: A first voltage is applied to the first partition of the plurality of memory cells; The first number of memory cells in the first partition where a sudden return event occurred is identified, at least in part, based on the application of the first voltage; as well as A second voltage is applied to the second partition of the plurality of memory cells; The second number of memory cells in the second partition where the sudden return event occurs is identified, at least in part, based on the application of the second voltage; and The first value or polarity of the first read voltage, or both, is identified at least in part based on the first quantity and the second quantity.

5. The method of claim 4, further comprising: Summarize the data associated with applying the first voltage to the first partition and applying the second voltage to the second partition, wherein the first magnitude of identifying the first read voltage is at least partially based on the summarized data.

6. The method of claim 4, further comprising: The threshold voltage associated with the memory cell storing the first logic state is identified at least in part based on the first quantity and the second quantity, wherein the first quantity or polarity, or both, of the first read voltage is identified at least in part based on the identified threshold voltage.

7. The method of claim 4, wherein the first partition and the second partition each comprise two or more memory cells from the plurality of memory cells.

8. The method of claim 1, further comprising: The first read voltage is determined to be between the voltage of a first type of state that can be stored by the memory cell after a backlash event and the voltage of a second type of state that can be stored by the memory cell after the backlash event, wherein the application of the first read voltage is at least in part based on the determination.

9. The method of claim 1, further comprising: The second read voltage is determined to be between the voltage of a second type of state that can be stored by the memory cell after a backlash event and the voltage of a third type of state that can be stored by the memory cell after a backlash event, wherein the application of the second read voltage is at least in part based on the determination.

10. The method of claim 1, further comprising: The polarity of the first read voltage is identified, wherein applying the first read voltage is based at least in part on the identification of the polarity of the first read voltage; and The polarity of the second read voltage is identified, wherein the application of the second read voltage is based at least in part on the identification of the polarity of the second read voltage.

11. The method of claim 10, wherein the polarity of the first read voltage is the same as the polarity of the second read voltage.

12. The method of claim 10, wherein the polarity of the first read voltage is different from the polarity of the second read voltage.

13. The method of claim 1, wherein applying the plurality of voltages further comprises: Different voltages are applied to different partitions of the plurality of memory cells; The number of memory cells in which a sudden return event occurs is identified, at least in part, based on the different voltages applied. and The first value or polarity of the first read voltage, or both, is identified at least in part based on the number of memory cells.

14. The method of claim 1, further comprising: Whether a first backlash event has occurred is determined at least in part based on the application of the first read voltage, wherein the application of the second read voltage is at least in part based on the determination that the first backlash event has not occurred.

15. The method of claim 14, further comprising: After determining the logical state stored in the memory cell based at least in part on the determination that the first revert event has occurred, a reprogramming operation is performed on the memory cell.

16. A method for memory operations, comprising: Applying multiple voltages to multiple memory cells is part of the pre-fetch portion of a read operation; At least in part, based on applying the plurality of voltages, a first read voltage having a first magnitude and a first polarity is applied to the memory cells of the plurality of memory cells to identify the logic state stored by the memory cells as part of the read portion of the read operation; At least in part, based on applying the first read voltage, a second read voltage having a second magnitude and the first polarity is applied to the memory cell as part of the read portion of the read operation; and The logic state stored by the memory cell is determined at least in part based on the application of the first read voltage and the application of the second read voltage.

17. The method of claim 16, further comprising: The first value of the first read voltage is identified at least in part based on the application of the plurality of voltages, wherein the application of the first read voltage is at least in part based on the identification of the first value of the first read voltage.

18. The method of claim 17, further comprising: The second value of the second read voltage is identified at least in part based on the first value of the first read voltage, wherein applying the second read voltage is at least in part based on the second value of the second read voltage, wherein the first value is less than the second value.

19. The method of claim 17, further comprising: The offset between the first value of the first read voltage and the second value of the second read voltage is identified, wherein the second value of the second read voltage is identified at least in part based on the offset and the first value.

20. The method of claim 16, wherein applying the plurality of voltages further comprises: A first voltage is applied to the first partition of the plurality of memory cells; The first number of memory cells in the first partition where a sudden return event occurred is identified, at least in part, based on the application of the first voltage; A second voltage is applied to the second partition of the plurality of memory cells; The second number of memory cells in the second partition where the sudden return event occurs is identified, at least in part, based on the application of the second voltage; and The magnitude or polarity of the first read voltage, or both, is identified at least in part based on the first quantity and the second quantity.

21. The method of claim 16, further comprising: Identify the first polarity of the first read voltage and the second read voltage, wherein applying the first read voltage and applying the second read voltage are at least partially based on identifying the first polarity, wherein the first polarity is positive.

22. A method for memory operations, comprising: Applying multiple voltages to multiple memory cells is part of the pre-fetch portion of a read operation; At least in part, based on applying the plurality of voltages, a first read voltage of a first polarity is applied to the memory cells of the plurality of memory cells to identify the logical state stored by the memory cells as part of the read portion of the read operation; At least in part, based on applying the first read voltage, a second read voltage of a second polarity is applied to the memory cell as part of the read portion of the read operation; and The logic state stored by the memory cell is determined at least in part based on the application of the first read voltage and the application of the second read voltage.

23. The method of claim 22, further comprising: The first value of the first read voltage is identified at least in part based on the application of the plurality of voltages, wherein the application of the first read voltage is at least in part based on the identification of the first value of the first read voltage.

24. The method of claim 23, further comprising: The second value of the second read voltage is identified at least in part based on the first value of the first read voltage, wherein applying the second read voltage is at least in part based on the second value of the second read voltage, wherein the first value is equal to the second value.

25. The method of claim 24, further comprising: The offset between the first value of the first read voltage and the second value of the second read voltage is identified, wherein the second value of the second read voltage is identified at least in part based on the offset and the first value.

26. The method of claim 22, wherein applying the plurality of voltages further comprises: A first voltage is applied to the first partition of the plurality of memory cells; The first number of memory cells in the first partition where a sudden return event occurred is identified, at least in part, based on the application of the first voltage; A second voltage is applied to the second partition of the plurality of memory cells; The second number of memory cells in the second partition where the sudden return event occurs is identified, at least in part, based on the application of the second voltage; and The magnitude or polarity of the first read voltage, or both, is identified at least in part based on the first quantity and the second quantity.

27. The method of claim 22, further comprising: Identify the first polarity of the first read voltage, wherein applying the first read voltage is at least partially based on identifying the first polarity of the first read voltage; and Identify the second polarity of the second read voltage, wherein applying the second read voltage is at least partially based on identifying the second polarity of the second read voltage, wherein the first polarity is positive and the second polarity is negative.

28. A device for memory operations, comprising: A memory array, which comprises multiple memory cells; and A control component, coupled to the memory array, is configured to cause the device to: Applying multiple voltages to the multiple memory cells is part of the pre-fetch portion of the read operation; At least in part based on the application of the plurality of voltages, a first read voltage having a first magnitude value identified at least in part based on the application of the plurality of voltages is applied to the memory cells of the plurality of memory cells to identify the logic state stored by the memory cells as part of the read portion of the read operation; The memory cells for which the second read voltage is applied, at least in part, is part of the read portion of the read operation, based on the application of the first read voltage; and The logic state stored by the memory cell is determined at least in part based on the application of the first read voltage and the application of the second read voltage.

29. The device of claim 28, wherein the control component is further configured such that the device: The second value of the second read voltage is identified at least in part based on the first value of the first read voltage, wherein the application of the second read voltage is at least in part based on the second value of the second read voltage.

30. The device of claim 28, wherein the control component is further configured such that the device: A first voltage is applied to the first partition of the plurality of memory cells; The first number of memory cells in the first partition where a sudden return event occurred is identified, at least in part, based on the application of the first voltage; A second voltage is applied to the second partition of the plurality of memory cells; The second number of memory cells in the second partition where the sudden return event occurs is identified, at least in part, based on the application of the second voltage; and The first value or polarity of the first read voltage, or both, is identified at least in part based on the first quantity and the second quantity.

31. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Applying multiple voltages to multiple memory cells is part of the pre-fetch portion of a read operation; At least in part based on the application of the plurality of voltages, a first read voltage having a first magnitude value identified at least in part based on the application of the plurality of voltages is applied to the memory cells of the plurality of memory cells to identify the logic state stored by the memory cells as part of the read portion of the read operation; The memory cells for which the second read voltage is applied, at least in part, is part of the read portion of the read operation, based on the application of the first read voltage; and The logic state stored by the memory cell is determined at least in part based on the application of the first read voltage and the application of the second read voltage.

32. The non-transitory computer-readable medium of claim 31, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A first voltage is applied to the first partition of the plurality of memory cells; The first number of memory cells in the first partition where a sudden return event occurred is identified, at least in part, based on the application of the first voltage; A second voltage is applied to the second partition of the plurality of memory cells; The second number of memory cells in the second partition where the sudden return event occurs is identified, at least in part, based on the application of the second voltage; and The first value or polarity of the first read voltage, or both, is identified at least in part based on the first quantity and the second quantity.

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