Micro-opto-electrical device

Abstract

Disclosed are different options for electronic devices, including a doped layer, a functional layer, an ohmic layer, a conductive layer, a planarization layer, and a passivation layer. Also disclosed are configurations for top and bottom side connectors, including isolation structures, associated electrodes for the isolation structures, and height configurations.

Description

Technical Field

[0001] This invention relates to the structure of a micro-optoelectronic device having several layers. This structure helps to reduce the influence of non-ideal factors, such as defects, to improve device performance. Summary of the Invention

[0002] The present invention relates to a vertical optoelectronic device, the device comprising: a doped layer and a blocking layer; a functional layer; the doped layer, the blocking layer and the functional layer etched on an isolation structure; the isolation structure partially comprising an ohmic layer; the isolation structure being located on the top and bottom of the device; a dielectric layer deposited to at least cover the sides of the isolation structure; a conductive layer located on an open region of the isolation structure; and a passivation layer formed to fill the surface of the optoelectronic device. Attached Figure Description

[0003] The foregoing and other advantages of this disclosure will become apparent after reading the following detailed description and referring to the accompanying drawings.

[0004] Figure 1 A photoelectric device with a layered structure is shown, which has an isolation structure.

[0005] Figure 2 The exhibition showcases an optoelectronic device with a layered structure, which includes an isolation structure with VIA (Variable Aqueduct).

[0006] Figure 3 The exhibition showcases an optoelectronic device with a layered structure, which includes an isolation structure with VIA (Variable Aqueduct).

[0007] Figure 4 An optoelectronic device with a layered structure is shown, which has an isolation structure with a conductive layer containing a VIA and a portion of the VIA filled.

[0008] Figure 5 The exhibition showcases an optoelectronic device with a layered structure, which includes a conductive layer with a VIA and a portion filled with the VIA, and an isolation structure with a height difference between the two layers.

[0009] While this disclosure allows for various modifications and alternatives, specific embodiments or implementations have been shown by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that this disclosure is not intended to limit it to the specific forms disclosed. Rather, this disclosure will cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the invention as defined by the appended claims. Detailed Implementation

[0010] This invention relates to the structure of a micro-optoelectronic device having several layers, such as doped layers, barrier layers, and functional layers. The terms "micro-device" and "optoelectronic device" are used interchangeably.

[0011] According to one embodiment of the present invention, as by Figure 1 As shown, a vertical micro-optoelectronic device 100 exists, comprising, for example, a doped layer 102a and a barrier layer 102b and a functional layer 104, wherein the current through the layers is restricted through some isolation layers, and a common electrode on the top of the planarized layer is connected to the isolation layer.

[0012] Some layers can be etched into isolation structures 106a and 106b. Ohmic layers 108a and 108b can be portions of isolation structures 106a and 106b.

[0013] The isolation structure can be located on either the top or bottom side (or only one side).

[0014] Dielectric layers 110a and 110b may be deposited to at least cover the sides of the isolation structures 106a and 106b. Dielectric layers 110a and 110b may cover the sides of the device layer 112.

[0015] Conductive layers 114a and 114b may be deposited after at least a portion of the top of the isolation structures 106a and 106b is opened. Passivation layers 116a and 116b may be formed to fill the surface of the device. Either passivation layer 116a or 116b may cover side 118 of the device.

[0016] In one approach, the isolation layer is formed before the formation of the main structure for the microdevice. In another approach, the isolation layer is formed after the device is formed. Processing techniques may be performed to remove defects on the sidewalls and surfaces (and / or sidewalls of the main structure) between the isolation layers. A dielectric is deposited thereon to cover the areas between the isolation layers or the sidewalls of the isolation structure. A planarization layer is deposited on the surface. The planarization layer is patterned or etched back to expose the top of the isolation layer. If the dielectric layer has not yet been removed from the top, it can be removed from the top. A common electrode is formed on top of the planarization layer.

[0017] In another embodiment, at least one isolation layer is connected to different electrodes. These electrodes are biased to different bias points relative to a common electrode. Under certain operating conditions, the two electrodes may have the same bias point. For example, for lower current densities, one of the electrodes may be biased such that some of the isolation layers prevent current from passing through it.

[0018] According to one embodiment, as by Figure 2As shown, a micro-optoelectronic device 100 comprises, for example, a doped layer 102a, a barrier layer 102b, and a functional layer 104, wherein current through the layers is restricted through some isolation layers, and a common electrode on top of the planarization layer is connected to the isolation layer. Furthermore, one common electrode is coupled to the other side via a VIA formed in the functional layer and the planarization layer.

[0019] Some layers can be etched into the isolation structures 106a and 106b. Ohmic layers 108a and 108b can be portions of the isolation structures 106a and 106b.

[0020] The isolation structure can be located on either the top or bottom side (or only one side).

[0021] Dielectric layers 110a and 110b may be deposited to at least cover the sides of the isolation structures 106a and 106b. Dielectric layers 110a and 110b may cover the sides of the device layer 112.

[0022] Conductive layers / electrodes 114a and 114b may be deposited after at least a portion of the top of the isolation structures 106a and 106b is opened. Passivation layers 116a and 116b may be formed to fill the surface of the device. Either passivation layer 116a or 116b may cover side 118 of the device.

[0023] A VIA 140 is formed to couple the conductive layer 144 to the electrode 114a. A dielectric layer 142 covers the sidewalls of the VIA 140. An opening 146 is formed in the dielectric to provide access to the electrode 114a.

[0024] Pads 130b and 130a may be formed on electrode 114b and conductive layer 144, respectively. The pads may be portions of electrode 114b or conductive layer 144. Electrodes 114a and 114b may be transparent or reflective. VIA 140 may penetrate the passivation of cover side 118.

[0025] In one approach, the isolation layer is formed before the formation of the main structure for the microdevice. In another approach, the isolation layer is formed after the device is formed. Processing techniques may be performed to remove defects on the sidewalls and surfaces (and / or sidewalls of the main structure) between the isolation layers. A dielectric is deposited thereon to cover the areas between the isolation layers or the sidewalls of the isolation structure. A planarization layer is deposited on the surface. The planarization layer is patterned or etched back to expose the top of the isolation layer. If the dielectric layer has not yet been removed from the top, it can be removed from the top. A common electrode is formed on top of the planarization layer.

[0026] In one embodiment, at least one isolation layer is connected to different electrodes. These electrodes are biased to different bias points relative to a common electrode. Under certain operating conditions, the two electrodes may have the same bias point. For example, for lower current densities, one of the electrodes may be biased such that some of the isolation layers prevent current from passing through it.

[0027] A VIA is formed to couple the electrode to the other side of the device. The VIA is covered by a dielectric, and a conductive layer is formed to couple the electrode to the other side. An opening may be present in the dielectric layer. An etch-stop layer of a capping layer may be formed on top of the VIA and the opening (146).

[0028] According to one embodiment, as by Figure 3 As shown, Figure 3 The display can be applied to Figure 2 or Figure 1 Different embodiments of the common electrode are described. Micro-optoelectronic devices 100 exist, comprising, for example, a doped layer 102a, a barrier layer 102b, and a functional layer 104. Here, the planarization is above the ohmic layer. Therefore, any pressure on the common electrode or pad is not directly transmitted to the isolation layer, and damage to the isolation structure is prevented.

[0029] One way to create a height difference is to form a passivation layer that is thicker than the isolation layer height pattern, and to pattern the planarization to create openings in the planarization layer on top of the isolation structure.

[0030] In another case, a sacrificial layer is present on top of the isolation layer, and after the planarization layer is formed, the sacrificial layer is removed, thus creating a depression in the planarization layer on top of the isolation layer.

[0031] Some layers can be etched into isolation structures 106a and 106b. Ohmic layers 108a and 108b can be portions of isolation structures 106a and 106b.

[0032] The isolation structure can be located on either the top or bottom side (or only one side).

[0033] Dielectric layers 110a and 110b may be deposited to at least cover the sides of the isolation structures 106a and 106b. Dielectric layers 110a and 110b may cover the sides of the device layer 112.

[0034] Conductive layers / electrodes 114a and 114b may be deposited after at least a portion of the top of the isolation structures 106a and 106b is opened. Passivation layers 116a and 116b may be formed to fill the surface of the device. Either passivation layer 116a or 116b may cover side 118 of the device.

[0035] A VIA 140 is formed to couple the conductive layer 144 to the electrode 114a. A dielectric layer 142 covers the sidewalls of the VIA 140. An opening 146 is formed in the dielectric to provide access to the electrode 114a.

[0036] Pads 130b and 130a may be formed on electrode 114b and conductive layer 144, respectively. The pads may be portions of electrode 114b or conductive layer 144. Electrodes 114a and 114b may be transparent or reflective.

[0037] In one embodiment, passivation layer 116a or 116b is above isolation structure 106a or 106b. In one case of contouring, a sacrificial layer is formed on top of 108a, 108b. After the passivation layers 116a and 116b are formed, the sacrificial layer is removed. This removes stress from the isolation region during the integration of the micro-optoelectronic device 100 into the substrate.

[0038] VIA 140 can pass through the passivation on the covered side 118.

[0039] According to one embodiment, as by Figure 4 As shown, a micro-optoelectronic device 100 exists, comprising, for example, a doped layer 102a, a barrier layer 102b, and a functional layer 104.

[0040] Some layers can be etched into isolation structures 106a and 106b. Ohmic layers 108a and 108b can be portions of isolation structures 106a and 106b.

[0041] The isolation structure can be located on either the top or bottom side (or only one side).

[0042] Dielectric layers 110a and 110b may be deposited to at least cover the sides of the isolation structures 106a and 106b. Dielectric layers 110a and 110b may cover the sides of the device layer 112.

[0043] Conductive layers 114a and 114b may be deposited after at least a portion of the top of the isolation structures 106a and 106b is opened. Passivation layers 116a and 116b may be formed to fill the surface of the device. Either passivation layer 116a or 116b may cover side 118 of the device.

[0044] A VIA 140 is formed to couple the conductive layer 144 to the electrode 114a. A dielectric layer 142 covers the sidewalls of the VIA 140. An opening 146 is formed in the dielectric to provide access to the electrode 114a. The conductive layer 114c filling a portion of the VIA 140 may be the same as 114a.

[0045] Pads 130b and 130a may be formed on electrode 114b and conductive layer 144, respectively. The pads may be portions of electrode 114b or conductive layer 144. Electrodes 114a and 114b may be transparent or reflective.

[0046] VIA 140 can pass through the passivation on the covered side 118.

[0047] According to one embodiment, as by Figure 5 As shown, a micro-optoelectronic device 100 exists, comprising, for example, a doped layer 102a, a barrier layer 102b, and a functional layer 104.

[0048] Some layers can be etched into isolation structures 106a and 106b. Ohmic layers 108a and 108b can be portions of isolation structures 106a and 106b.

[0049] The isolation structure can be located on either the top or bottom side (or only one side).

[0050] Dielectric layers 110a and 110b may be deposited to at least cover the sides of the isolation structures 106a and 106b. Dielectric layers 110a and 110b may cover the sides of the device layer 112.

[0051] Conductive layers 114a and 114b may be deposited after at least a portion of the top of the isolation structures 106a and 106b is opened. Passivation layers 116a and 116b may be formed to fill the surface of the device. Either passivation layer 116a or 116b may cover side 118 of the device.

[0052] A via 140 is formed to couple the conductive layer 144 to the electrode 114a. A dielectric layer 142 covers the sidewalls of the via 140. An opening 146 is formed in the dielectric to provide access to the electrode 114a. The conductive layer 114c filling a portion of the via 140 may be the same as 114a.

[0053] Pads 130b and 130a may be formed on electrode 114b and conductive layer 144, respectively. The pads may be portions of electrode 114b or conductive layer 144. Electrodes 114a and 114b may be transparent or reflective.

[0054] In one embodiment, passivation layer 116a or 116b is above isolation structure 106a or 106b. In one case, a sacrificial layer is formed on top of 108a, 108b to create a contour. After the passivation layers 116a and 116b are formed, the sacrificial layer is removed. This removes stress from the isolation region during the integration of the micro-optoelectronic device 100 into the substrate.

[0055] VIA 140 can pass through the passivation on the covered side 118.

[0056] Methodological aspects

[0057] The present invention also discloses a method for manufacturing an optoelectronic device comprising a doped layer, a barrier layer, and a functional layer. The doped layer, barrier layer, and functional layer are etched onto an isolation structure. The isolation structure partially comprises an ohmic layer and is located on the top and bottom of the device. A dielectric layer is deposited to cover at least one side of the isolation structure; a conductive layer is located on an open region of the isolation structure; and a passivation layer is formed to fill the surface of the optoelectronic device. A common electrode connected to the isolation structure is formed on top of the planarization layer. Furthermore, the dielectric layer may cover the sides of the doped layer, barrier layer, and functional layer, and the passivation layer covers the dielectric layer. Additionally, the dielectric layer is deposited to cover the region between the isolation structures and the sidewalls of the isolation structure.

[0058] The planarization layer is thus patterned to expose the top of the isolation structure, wherein at least one isolation structure can be connected to the second electrode. The second electrode and the common electrode have the same bias point. The second electrode and the common electrode may also have different bias points. Furthermore, the common electrode on the top of the planarization layer is connected to the isolation structure, and one common electrode is coupled to the other side via a VIA formed in the functional layer and the planarization layer. The VIA is formed such that a conductive layer within the VIA couples to the electrode coupled due to the VIA, and a third dielectric covers the sidewalls of the VIA, wherein openings in the third dielectric provide access to the electrode coupled due to the VIA. A pad is formed on the electrode not coupled due to the VIA. The pad may also be formed on the conductive layer.

[0059] The electrode can be transparent or reflective, and the VIA penetrates the passivation layer. Furthermore, a planarization layer is higher than the ohmic layer. The passivation layer is thicker and higher than the isolation structure, and the planarization layer is a patterned layer with openings on top of the isolation structure. Additionally, the VIA is filled with a second conductive layer identical to the previous conductive layer. Finally, a removable sacrificial layer is formed on top of the ohmic layer.

[0060] For purposes of illustration and description, the foregoing description of one or more embodiments of the invention has been presented. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. In view of the foregoing teachings, many modifications and variations are possible. It is intended that the scope of the invention not be limited by this specific embodiment, but by the appended claims.

Claims

1. A photoelectric device, the device comprising: Doped layers and barrier layers; Functional layer; The doped layer, barrier layer and functional layer are etched onto the isolation structure; The isolation structure partially includes an ohmic layer; The isolation structure is located at the top and bottom of the device; A common electrode, which is connected to the isolation structure and is located on top of a planarization layer that is higher than the ohmic layer and thicker than the isolation structure, such that any pressure applied to the common electrode is not directly transmitted to the isolation structure. A dielectric layer, which is deposited to at least cover the sides of the isolation structure and the area between the isolation structures; A conductive layer, wherein the conductive layer is located on an open area of ​​the isolation structure; as well as A passivation layer is formed to cover the dielectric layer and fill the surface of the optoelectronic device.

2. The apparatus of claim 1, wherein the dielectric layer covers the sides of the doped layer, the barrier layer, and the functional layer.

3. The apparatus of claim 1, wherein the dielectric layer is deposited to cover the sidewalls of the isolation structure.

4. The apparatus of claim 1, wherein the planarization layer is patterned to expose the top of the isolation structure.

5. The apparatus of claim 1, wherein at least one of the isolation structures is connected to the second electrode.

6. The apparatus of claim 5, wherein the second electrode and the common electrode have the same bias point.

7. The apparatus of claim 5, wherein the second electrode and the common electrode have different bias points.

8. The apparatus of claim 1, wherein one of the common electrodes is coupled to the other side via a VIA formed in the functional layer and the planarization layer.

9. The apparatus of claim 8, wherein the VIA is formed such that a conductive layer within the VIA is coupled to the common electrode coupled due to the VIA, and a third dielectric covers the sidewalls of the VIA, wherein an opening in the third dielectric provides electrical contact to the common electrode coupled due to the VIA.

10. The apparatus of claim 9, wherein the pad is formed on the common electrode which is not coupled due to the VIA.

11. The apparatus of claim 9, wherein the pad is formed on the conductive layer within the VIA.

12. The apparatus of claim 8, wherein the common electrode is transparent.

13. The apparatus of claim 8, wherein the common electrode is reflective.

14. The apparatus of claim 9, wherein the VIA passes through the passivation layer.

15. The apparatus of claim 1, wherein the planarization layer is a patterned layer having an opening on top of the isolation structure.

16. The apparatus of claim 15, wherein the passivation layer is higher than the isolation structure.

17. The apparatus of claim 8, wherein the VIA passes through the passivation layer.

18. The apparatus of claim 8, wherein the VIA is filled with a second conductive layer.

19. The apparatus of claim 18, wherein the second conductive layer is the same as the previous conductive layer.

20. The apparatus of claim 18, wherein the passivation layer is higher than the isolation structure.

21. The apparatus of claim 20, wherein a removable sacrificial layer is formed on top of the ohmic layer.

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