Burr detector

Abstract

The present application provides a glitch detector, which comprises a first inverter, a second inverter, a charge sharing component and a warning flag generator. The first inverter is used to receive a first signal at a first node to generate a second signal to a second node. The second inverter is used to receive the second signal at the second node to generate the first signal to the first node. The charge sharing component is coupled between the first node and the second node to selectively connect the first node to the second node. The warning flag generator is coupled to the first node or the second node to determine whether an undervoltage glitch occurs in a power supply voltage of the glitch detector according to a voltage level of the first signal or the second signal and to determine whether to output a warning flag. The present application can effectively detect an undervoltage glitch attack and / or an overvoltage glitch attack and has a smaller chip area.

Description

Technical Field

[0001] This invention relates to glitch detectors, and more specifically, to glitch detectors capable of effectively detecting undervoltage glitch and / or overvoltage glitch. Background Technology

[0002] Electromagnetic fault injection (EMFI) is a well-known technique used to attack the power of a chip to compromise its security. Therefore, power detectors or glitch detectors are designed into the chip to detect power attacks. Traditional glitch detectors can be comparator-based or RC-triggered detectors. However, comparator-based glitch detectors consume a lot of power, and RC-triggered detectors require a large chip area due to their passive components; therefore, these glitch detectors are not suitable for placement within the chip. Summary of the Invention

[0003] Therefore, the purpose of this invention is to provide a glitch detector that has a small chip area and can effectively detect undervoltage glitch attacks and / or overvoltage glitch attacks, so as to solve the above-mentioned problems.

[0004] According to one embodiment of the present invention, a glitch detector is disclosed, comprising a first inverter, a second inverter, a charge-sharing component, and a warning flag generator. The first inverter is configured to receive a first signal at a first node to generate a second signal to a second node. The second inverter is configured to receive the second signal at the second node to generate a first signal to the first node. The charge-sharing component is coupled between the first node and the second node to selectively connect the first node to the second node. The warning flag generator is coupled to either the first node or the second node to determine whether an undervoltage glitch has occurred in the power supply voltage of the glitch detector based on the voltage level of the first signal or the voltage level of the second signal, and to determine whether to output a warning flag.

[0005] According to another embodiment of the present invention, a glitch detector is disclosed, comprising a first inverter, a second inverter, a discharge path, and a warning flag generator. The first inverter is configured to receive a first signal at a first node to generate a second signal to a second node. The second inverter is configured to receive the second signal at the second node to generate the first signal to the first node. The discharge path is configured to selectively provide a current path between the second node and a reference voltage. The warning flag generator is coupled to either the first or second node to determine whether an overvoltage glitch has occurred in the power supply voltage of the glitch detector based on the voltage level of the first signal or the voltage level of the second signal, and to determine whether to output a warning flag.

[0006] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description

[0007] This invention can be more fully understood by taking into account the accompanying drawings and reading the following detailed description and embodiments, wherein:

[0008] Figure 1 This is a schematic diagram of a burr detector according to an embodiment of the present invention.

[0009] Figure 2 An embodiment of the invention is shown when the power supply voltage suffers an undervoltage spike. Figure 1 The operation of the burr detector is shown.

[0010] Figure 3 This is a schematic diagram illustrating a burr detector according to an embodiment of the present invention.

[0011] Figure 4 An embodiment of the invention is shown when the power supply voltage is subjected to an overvoltage spike. Figure 3 The operation of the burr detector is shown.

[0012] Figure 5 A schematic diagram of a burr detector according to an embodiment of the present invention is shown. Detailed Implementation

[0013] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components by differences in name, but rather by differences in function. The term "comprising" throughout the specification and subsequent claims is an open-ended term and should be interpreted as "comprising but not limited to." Furthermore, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if the text describes a first device electrically connected to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means.

[0014] Figure 1 This is a schematic diagram of a burr detector 100 according to an embodiment of the present invention. Figure 1 As shown, the glitch detector 100 includes two latched logic circuits, which are exemplified in this embodiment as inverters 110 and 120. Inverter 110 includes a P-type transistor MP1 and an N-type transistor MN1 connected between a power supply voltage VDD_V and a ground voltage, and is configured to receive a signal X at node N1 and generate a signal Y at node N2. Inverter 120 includes a P-type transistor MP2 and an N-type transistor MN2 connected between a power supply voltage VDD_V and a ground voltage, and is configured to receive a signal Y at node N2 and generate a signal X at node N1. The glitch detector 100 also includes a charge sharing component 130 and a warning flag generator 140, wherein the charge sharing component 130 is connected between nodes N1 and N2, and the warning flag generator 140 is connected to node N1.

[0015] In this embodiment, inverter 110 can easily pull down the voltage level of signal Y at node N2, but it is difficult to pull up the voltage level of signal Y at node N2. To enable inverter 110 to have the above characteristics, the size of N-type transistor MN1 can be larger than the size of P-type transistor MP1. More N-type transistors can be connected in parallel to form N-type transistor MN1, multiple P-type transistors can be connected in series to form P-type transistor MP1, or P-type transistor MP1 and N-type transistor MN1 can be implemented using devices with different threshold voltages. Furthermore, inverter 120 can easily pull up the voltage level of signal X at node N1, but it is difficult to pull down the voltage level of signal X at node N1. To enable inverter 120 to have the above characteristics, the size of P-type transistor MP2 can be larger than the size of N-type transistor MN2. More P-type transistors can be connected in parallel to form P-type transistor MP2, multiple N-type transistors can be connected in series to form N-type transistor MN2, or P-type transistor MP2 and N-type transistor MN2 can be implemented using devices with different threshold voltages.

[0016] Furthermore, the charge-sharing component 130 can be implemented by selectively connecting node N1 to node N2 using a switch. For example, the charge-sharing component 130 can be a switching device controlled to be connected or disconnected by a power supply voltage VDD_V, such as a P-type transistor whose gate is controlled by a power supply voltage VDD_V, with its source and drain connected to nodes N1 and N2, respectively.

[0017] Figure 1 The glitch detector 100 shown is used to detect undervoltage glitch in the power supply voltage VDD_V. Figure 2 An embodiment of the invention is shown when the power supply voltage suffers an undervoltage spike. Figure 1 The operation of the burr detector is shown. In the operation of the burr detector 100, refer to... Figure 1 and Figure 2 In the first stage, signal X is controlled to have a low voltage level (i.e., initial value logic "0"), while signal Y is controlled to have a high voltage level (i.e., initial value logic "1"), and charge sharing component 130 is disabled, causing node N1 to disconnect from the electrical connection with node N2.

[0018] In the second phase following the first phase, due to the undervoltage spike in the power supply voltage VDD_V, the charge sharing component 130 is enabled, causing node N1 to be electrically connected to node N2, and the voltage level of the signal X to be closer to the voltage level of the signal Y.

[0019] In the third stage following the second stage, since inverter 110 can easily pull down the voltage level of signal Y at node N2, and inverter 120 can easily pull up the voltage level of signal X at node N1, inverters 110 and 120 form a positive feedback loop. When the power supply voltage VDD_V returns to its original voltage level, signal X will be pulled high and signal Y will be pulled low. That is, after the undervoltage spike disappears, signal X equals logic value "1", and signal Y equals logic value "0".

[0020] Then, after signal X changes to the logic value "1", warning flag generator 140 is triggered to output a warning signal to the processing circuit to notify that the power supply voltage VDD_V has suffered an undervoltage spike. After the warning flag generator 140 outputs the warning signal, a reset circuit (not shown) will force nodes N1 and N2 to "0" and "1" respectively.

[0021] In another embodiment, the warning flag generator 140 may be connected to node N2, and the warning flag generator 140 is triggered to output a warning signal after the signal Y changes to the logic value "0". This alternative design should fall within the scope of the present invention.

[0022] In summary, the glitch detector 100 can effectively detect undervoltage glitch. Furthermore, since the glitch detector 100 does not contain any passive components, it has a small chip area and is easy to position within the processor.

[0023] Figure 3 This is a schematic diagram illustrating a burr detector 300 according to an embodiment of the present invention. Figure 3 As shown, the glitch detector 300 includes two logic circuits connected in a latching manner. In this embodiment, these two logic circuits are inverters 310 and 320. Inverter 310 includes a P-type transistor MP1 and an N-type transistor MN1 connected between the power supply voltage VDD_V and the ground voltage, and is configured to receive a signal X at node N1 to generate a signal Y at node N2. Inverter 320 includes a P-type transistor MP2 and an N-type transistor MN2 connected between the power supply voltage VDD_V and the ground voltage, and is configured to receive a signal Y at node N2 to generate a signal X at node N1. The glitch detector 300 also includes a bleeding path 330 and a warning flag generator 340, wherein the bleeding path 330 is connected between node N2 and the reference voltage VDD_R, and the warning flag generator 340 is connected to node N1.

[0024] In this embodiment, inverter 110 easily pulls down the voltage level of signal Y at node N2, but has difficulty pulling up the voltage level of signal Y at node N2. To enable inverter 110 to have the above characteristics, the size of N-type transistor MN1 can be larger than the size of P-type transistor MP1. More N-type transistors can be connected in parallel to form N-type transistor MN1, or multiple P-type transistors can be connected in series to form P-type transistor MP1. Alternatively, P-type transistor MP1 and N-type transistor MN1 can be implemented using devices with different threshold voltages. Furthermore, inverter 120 easily pulls up the voltage level of signal X at node N1, but has difficulty pulling down the voltage level of signal X at node N1. To enable inverter 120 to have the above characteristics, the size of P-type transistor MP2 can be larger than the size of N-type transistor MN2. More P-type transistors can be connected in parallel to form P-type transistor MP2, or multiple N-type transistors can be connected in series to form N-type transistor MN2. Alternatively, P-type transistor MP2 and N-type transistor MN2 can be implemented using devices with different threshold voltages.

[0025] Discharge path 330 is configured to selectively provide a current path between node N2 and reference voltage VDD_R. Specifically, discharge path 330 is disabled (i.e., no current path is provided) when signal Y is at a normal voltage level (i.e., close to the supply voltage VDD_V), and enabled when signal Y is greater than a predetermined voltage. In this embodiment, discharge path 330 includes P-type transistors MP3-MP5, wherein P-type transistors MP3 and MP4 are connected in a diode manner and coupled between node N2 and P-type transistor MP5. P-type transistor MP5 is controlled by reference voltage VDD_R. However, these are not limitations of the invention. For example, the predetermined voltage can be determined based on the turn-on threshold voltage of transistor MP5 or the turn-on bias voltage of diode-connected transistors MP3 / MP4. In this embodiment, the reference voltage VDD_R has a high voltage level and is different from the power supply voltage VDD_V. For example, the power supply voltage VDD_V is a power supply signal with overvoltage glitches or undervoltage glitches, while the reference voltage VDD_R is equal to the value of a clean power supply voltage VDD_V without glitches.

[0026] In one embodiment, the bulk of each of the P-type transistors MP3 and MP4 is connected to a reference voltage VDD_R to form a drain-base diode to provide an additional current path.

[0027] Figure 3 The glitch detector 300 shown is used to detect overvoltage glitch in the power supply voltage VDD_V. Figure 4 An embodiment of the invention is shown when the power supply voltage is subjected to an overvoltage spike. Figure 3The operation of the burr detector is shown. In the operation of the burr detector 300, refer to... Figure 3 and Figure 4 In the first stage, signal X is controlled to have a low voltage level (i.e., logic value "0"), while signal Y is controlled to have a high voltage level (i.e., logic value "1"). At this time, the discharge path 330 does not provide a current path between node N2 and the reference voltage VDD_R because the P-type transistor MP5 is disabled.

[0028] In the second stage following the first stage, due to an overvoltage spike in the power supply voltage VDD_V, the power supply voltage VDD_V rapidly charges node N2 through the P-type transistor MP1 of inverter 110, causing the voltage level of signal Y to begin to increase. Furthermore, when the voltage level of signal Y exceeds a predetermined voltage, P-type transistors MP4 and MP5 are activated to provide a current path, and a large current flows from node N2 to the reference voltage VDD_R to prevent the voltage level of signal Y from continuing to rise. At this point, because VDD_V experiences an overvoltage spike, and the voltage of signal Y is difficult to continue rising due to the discharge current in the discharge path, P-type transistor MP2 is activated, causing the power supply voltage VDD_V to begin charging node N1, and the voltage level of signal X begins to rise.

[0029] In the third stage following the second stage, after the overvoltage spike stabilizes, due to the large discharge current provided by the discharge path 330, inverter 310 can easily pull down the voltage level of signal Y at node N2, and inverter 320 can easily pull up the voltage level of signal X at node N1. Inverters 310 and 320 form a positive feedback loop, where signal X will be pulled high and signal Y will be pulled low. That is, after the overvoltage spike disappears, signal X equals logic value "1", and signal Y equals logic value "0".

[0030] Then, after signal X changes to the logic value "1", warning flag generator 340 is triggered to output a warning signal to the processing circuit to notify that the power supply voltage VDD_V has suffered an overvoltage spike. After the warning flag generator 340 outputs the warning signal, a reset circuit (not shown) forces nodes N1 and N2 to "0" and "1" respectively.

[0031] In this embodiment, the P-type transistor MP5 can be used as part of a reset circuit to make signal Y "1". That is, the gate of the P-type transistor MP5 can be controlled by using a reset signal with a low voltage level. The P-type transistor MP3, together with the P-type transistor MP5, pulls signal Y high to reset the glitch detector 300. During non-reset times, the reset signal is high. When the power supply voltage VDD_V experiences an overvoltage glitch, the P-type transistor MP5 forms a current path as a discharge circuit.

[0032] In another embodiment, the warning flag generator 340 may be connected to node N2, and the warning flag generator 340 is triggered to output a warning signal after the signal Y changes to the logic value "0". This alternative design should fall within the scope of the present invention.

[0033] In summary, the glitch detector 300 can effectively detect overvoltage glitch. Furthermore, since the glitch detector 300 does not contain any passive components, it has a small chip area and is easy to position within the processor.

[0034] In an alternative embodiment, Figure 1 The burr detector 100 shown and Figure 3 The glitch detectors 300 shown can be combined to enable them to detect both undervoltage and overvoltage glitches. That is, the glitch detector 100 can be modified to add a discharge path 330, or the glitch detector 300 can be modified to add a charge-sharing component 130. Figure 5 A schematic diagram illustrating a burr detector 500 according to an embodiment of the present invention is shown. Figure 5 As shown, the glitch detector 500 includes two logic circuits connected in a latching manner. In this embodiment, these two logic circuits are inverters 510 and 520. Inverter 510 includes a P-type transistor MP1 and an N-type transistor MN1 connected between the power supply voltage VDD_V and the ground voltage, and inverter 510 is configured to receive a signal X at node N1 to generate a signal Y at node N2. Inverter 520 includes a P-type transistor MP2 and an N-type transistor MN2 connected between the power supply voltage VDD_V and the ground voltage, and inverter 520 is configured to receive a signal Y at node N2 to generate a signal X at node N1. The glitch detector 500 also includes a charge sharing component 530, a discharge path 540, a warning flag generator 550, and a reset circuit 560, wherein the charge sharing component 530 is connected between node N1 and node N2, the discharge path 540 is connected between node N2 and the reference voltage VDD_R, the warning flag generator 550 is connected to node N1, and the reset circuit 560 is connected to node N1.

[0035] In this embodiment, inverter 510 can easily pull down the voltage level of signal Y at node N2, but has difficulty pulling up the voltage level of signal Y at node N2; inverter 520 can easily pull up the voltage level of signal X at node N1, but has difficulty pulling down the voltage level of signal X at node N1. The charge-sharing component 530 can be implemented using a P-type transistor controlled by the power supply voltage VDD_V. The discharge path 540 is configured to selectively provide a current path between node N2 and the reference voltage VDD_R. Specifically, the discharge path 540 is disabled (i.e., no current path is provided) when signal Y is at a normal voltage level (i.e., close to the power supply voltage VDD_V), and enabled when signal Y is greater than a predetermined voltage. In this embodiment, the discharge path 540 includes P-type transistors MP3 to MP5, but the invention is not limited thereto, wherein P-type transistor MP5 is controlled by a reset signal RST. It is worth noting that the operation of the charge-sharing component 530 and the discharge path 540 is similar to... Figure 1 The charge-sharing component 130 shown and Figure 3 The discharge path 330 shown is the same, so details of these components are omitted here.

[0036] The reset circuit 560 includes an inverter 562 and an N-type transistor MN3. In this embodiment, after the warning flag generator 550 outputs a warning signal, a reset signal RST with a low voltage signal is input to the inverter 562, enabling the N-type transistor MN3 to discharge node N1, so that the signal X is again at the logic value "0".

[0037] In this embodiment, the P-type transistor MP5 can be part of a reset circuit, setting signal Y to "1". That is, the gate of P-type transistor MP5 can be controlled using the reset signal RST. P-type transistors MP3 and MP5 together pull signal Y high to reset the glitch detector 500. Furthermore, when the glitch detector 500 does not need to be reset, the reset signal RST can have a high voltage level. During non-reset times, signal RST is high, and P-type transistor MP5 acts as part of the discharge path, providing a current path when an overvoltage glitch occurs. When the glitch detector needs to be reset after an overvoltage glitch and the warning flag generator generates a warning signal, signal RST is low, and transistor MP5 acts as part of the reset circuit.

[0038] In summary, in the glitch detector of this invention, by designing a charge-sharing component, the glitch detector can effectively detect undervoltage glitch; and by designing a discharge path, the glitch detector can effectively detect overvoltage glitch. Furthermore, since the glitch detector can be implemented without using any passive components, the chip area of ​​the glitch detector is smaller and it is easy to position within the processor.

[0039] Those skilled in the art will readily recognize that many modifications and changes can be made to the apparatus and method while retaining the teachings of the invention. Therefore, the above disclosure should be construed as being limited only by the scope and limits of the appended claims.

Claims

1. A burr detector, comprising: The first inverter is used to receive the first signal at the first node and generate a second signal for the second node; A second inverter is used to receive a second signal at the second node and generate the first signal to the first node; A charge-sharing component, coupled between the first node and the second node, is used to selectively connect the first node to the second node; A warning flag generator, coupled to the first node or the second node, is used to determine whether the power supply voltage of the glitch detector is subjected to an undervoltage glitch based on the voltage level of the first signal or the voltage level of the second signal, so as to determine whether to output a warning flag. as well as The discharge path is configured to selectively provide a current path between the second node and the reference voltage.

2. The burr detector as described in claim 1, wherein, The first inverter includes a first P-type transistor and a first N-type transistor, wherein the size of the first N-type transistor is larger than the size of the first P-type transistor, or the first N-type transistor is implemented by a plurality of N-type transistors connected in parallel, or the first P-type transistor is implemented by a plurality of P-type transistors connected in series, or the first P-type transistor and the first N-type transistor are implemented by devices having different threshold voltages.

3. The burr detector as described in claim 1, wherein, The first inverter and the second inverter are powered by the power supply voltage, and the charge-sharing component is enabled when the power supply voltage is subjected to the undervoltage spike.

4. The burr detector as described in claim 3, wherein, The charge-sharing component is a P-type transistor controlled by the power supply voltage.

5. The burr detector as described in claim 3, wherein, Before the power supply voltage experiences an undervoltage spike, the first signal has a first logic value, the second signal has a second logic value different from the first logic value, and the charge sharing component is disabled; when the power supply voltage experiences an undervoltage spike, the charge sharing component is enabled, making the first node and the second node electrically connected; after the undervoltage spike disappears, the first signal has the second logic value, and the second signal has the first logic value.

6. The glitch detector of claim 5, wherein if the first signal has the second logic value or the second signal has the first logic value, the warning flag generator determines that the power supply voltage of the glitch detector is subject to an undervoltage glitch.

7. The burr detector as claimed in claim 1, wherein, When the second signal has a normal voltage level, the discharge path does not provide a current path between the second node and the reference voltage; When the power supply voltage experiences an overvoltage spike and the voltage level of the second signal is greater than a predetermined voltage, the discharge path provides the current path between the second node and the reference voltage.

8. The glitch detector of claim 1, wherein the discharge path includes a P-type transistor to selectively connect the second node to the reference voltage.

9. The glitch detector of claim 1, wherein the first inverter and the second inverter are powered by the power supply voltage; prior to an overvoltage glitch in the power supply voltage, the first signal has a first logic value, the second signal has a second logic value different from the first logic value, and the discharge path is disabled; when the power supply voltage experiences an overvoltage glitch, the discharge path is enabled, providing a current path between the second node and the reference voltage; after the overvoltage glitch stabilizes, the first signal has the second logic value, and the second signal has the first logic value.

10. The glitch detector of claim 9, wherein if the first signal has the second logic value or the second signal has the first logic value, the warning flag generator determines that the power supply voltage of the glitch detector is subject to an undervoltage glitch.

11. The glitch detector of claim 1, further comprising a reset circuit connected to the first node and / or the second node, wherein after the warning flag generator outputs the warning flag, a reset signal of the reset circuit causes the voltage levels of the first node and the second node to return to their initial values.

12. The glitch detector of claim 8, wherein the discharge path is further configured as part of a reset circuit, and the gate of the P-type transistor is coupled to a reset signal.

13. The burr detector as claimed in claim 2, wherein, The first P-type transistor and the first N-type transistor are coupled between the power supply voltage and the ground voltage.

14. The burr detector as claimed in claim 2, wherein, The second inverter includes a second P-type transistor and a second N-type transistor connected between the power supply voltage and the ground voltage, wherein the size of the second P-type transistor is larger than the size of the second N-type transistor, or the second P-type transistor is formed by a plurality of P-type transistors connected in parallel, or the second N-type transistor is formed by a plurality of N-type transistors connected in series, or the second P-type transistor and the second N-type transistor are implemented by devices having different threshold voltages.

15. A burr detector, comprising: The first inverter is used to receive the first signal at the first node and generate the second signal to the second node; A second inverter is used to receive the second signal at the second node and generate the first signal to the first node; A discharge path is provided to selectively provide a current path between the second node and the reference voltage; as well as A warning flag generator, coupled to the first node or the second node, is used to determine whether an overvoltage glitch has occurred in the power supply voltage of the glitch detector based on the voltage level of the first signal or the voltage level of the second signal, so as to determine whether to output a warning flag.

16. The burr detector as claimed in claim 15, wherein, When the second signal has a normal voltage level, the discharge path does not provide a current path between the second node and the reference voltage; When the power supply voltage experiences an overvoltage spike and the voltage level of the second signal is greater than a predetermined voltage, the discharge path provides a current path between the second node and the reference voltage.

17. The glitch detector of claim 15, wherein the discharge path includes a P-type transistor to selectively connect the second node to the reference voltage.

18. The glitch detector of claim 15, wherein the first inverter and the second inverter are powered by the power supply voltage, and before the power supply voltage suffers an overvoltage glitch, the first signal has a first logic value, the second signal has a second logic value different from the first logic value, and the bleed path is disabled; when the power supply voltage experiences an overvoltage glitch, the bleed path is enabled, providing a current path between the second node and the reference voltage; after the overvoltage glitch stabilizes, the first signal has the second logic value, and the second signal has the first logic value.

19. The glitch detector of claim 15, wherein if the first signal has the second logic value or the second signal has the first logic value, the warning flag generator determines that the power supply voltage of the glitch detector has suffered an overvoltage glitch.

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