An electronic system comprising a control unit configured to communicate with a memory

Abstract

Embodiments of the invention relate to an electronic system comprising a control unit configured to communicate with a memory. The system comprises a control unit configured to be electrically connected to an input of the memory via a communication interface. The control unit comprises a first power supply region configured to be powered when the control unit is in an operational mode and a second power supply region configured to be powered when the control unit is in the operational mode and in a low power consumption mode. In the first power supply region, the control unit comprises a first configuration circuitry operated to configure a polarization value of the input of the memory via the communication interface for the operational mode. In the second power supply region, the control unit comprises a second configuration circuitry operated to configure the polarization value of the input of the memory via the communication interface for the low power consumption mode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application No. 2109606, filed on September 14, 2021, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] The embodiments and implementations involve communication between a control unit and peripheral devices, such as using a control unit, such as a microcontroller, to configure the input / output of a memory. Background Technology

[0004] Especially in terms of memory, microcontrollers include both functionality and limited capacity. To increase the functionality and capacity of a microcontroller, at least one input / output interface is typically provided in the microcontroller and configured to be electrically connected to a peripheral device in order to communicate with it. Peripheral devices can increase the functionality or capacity of a microcontroller. For example, a peripheral device can be a memory that can increase the microcontroller's storage space.

[0005] More specifically, the memory includes at least one input / output electrically connected to the input / output ports of the microcontroller. The microcontroller includes configuration circuitry for configuring each input / output of the memory. The configuration of each input / output of the memory includes defining a polarization value to be applied to the input / output of the memory. The polarization value to be applied to the input / output of the memory may correspond to a high logic state or a low logic state.

[0006] Furthermore, different power supply modes can be defined for the microcontroller. Using different power supply modes can avoid unnecessary power consumption during the microcontroller's idle period. Specifically, the microcontroller can be in a so-called operating power supply mode (or active mode) or a low-power mode (or standby mode). When the microcontroller is operating normally, the operating mode is used to power all components of the microcontroller. When the microcontroller's functions are not used, the low-power mode is used, and only the components in the microcontroller that require continuous power can be powered.

[0007] Therefore, a microcontroller can include different power regions, which are powered according to the power supply mode applied to the microcontroller. Each power region includes a set of microcontroller components, which are powered in the same way according to the power supply mode activated for the microcontroller.

[0008] Specifically, two power supply regions can be defined. The first region may include a set of microcontroller components that are powered only when the microcontroller is in operating mode. When the microcontroller is in low-power mode, the components in the first region are therefore not powered. The second region may include a set of microcontroller components that require continuous power. The components in the second region are therefore powered when the microcontroller is in both operating mode and low-power mode.

[0009] The configuration circuitry for configuring each input / output of the microcontroller is located in the first power region. Therefore, when the microcontroller is in its low-power mode, the configuration circuitry is not powered and is thus reset. Consequently, when the microcontroller is in its low-power mode, the configuration circuitry is no longer able to define the configuration of each memory input / output. Specifically, in this case, each memory input / output becomes floating because the microcontroller does not apply a high or low logic state to that input / output. Each input / output is therefore in a high-impedance state. However, when the memory input / output is floating, the polarization applied to it lies between the polarization corresponding to a high logic state and the polarization corresponding to a low logic state. Thus, the polarization applied to the memory input / output can be considered to sometimes correspond to a high logic state and sometimes to a low logic state. This can lead to untimely activation or deactivation of the input / output. Untimely activation of the memory input / output can lead to undesirable configuration of the memory input / output. For example, turning off the power to the configuration circuitry may cause unexpected modification of the data stored in the memory. Inappropriate activation of memory inputs can also lead to leakage current, thereby shortening the battery life of the battery that powers the microcontroller.

[0010] Therefore, a solution is needed that allows memory configuration to be performed at any time, even when the control unit is in low-power mode. Summary of the Invention

[0011] According to one aspect, the system includes a control unit configured to be electrically connected to an input of a memory via a communication interface, wherein the control unit has two power supply regions: a first power supply region configured to be powered when the control unit is in an operating mode and powered off when the control unit is in a low-power mode, and a second power supply region configured to be powered when the control unit is in both the operating mode and the low-power mode, wherein the first power supply region of the control unit includes a first configuration circuit, which operates to configure the polarization value of the memory input via the communication interface when the control unit is in the operating mode, and wherein the second power supply region of the control unit includes a second configuration circuit, which operates to configure the polarization value of the memory input via the communication interface when the control unit is in the low-power mode.

[0012] Specifically, the first power supply region includes a set of control unit elements that are powered only and are therefore activated when the control unit is in the operating mode to ensure the execution of functions that can be performed by the control unit. When the low-power mode is applied to the control unit, the control unit elements in the first power supply region are therefore not powered to reduce the power consumption of the control unit. Therefore, the first configuration circuitry, which is part of the first power supply region, is not powered when the control unit is in the low-power mode. When the control unit is in the low-power mode, the first configuration circuitry cannot therefore be used to configure memory inputs.

[0013] However, when the control unit is in low-power mode, the configuration of the memory input is enabled by the second configuration circuit. In fact, the second configuration circuit is included in the second power supply area and is therefore powered on both when the control unit is in the operating mode and when the control unit is in low-power mode. Therefore, when the control unit is in low-power mode, the second configuration circuit can be used to configure the memory input.

[0014] Therefore, the memory input can be configured via the first configuration circuit when the control unit is in the operating mode, and via the second configuration circuit when the control unit is in the low-power mode.

[0015] In this way, the logic state is continuously applied to the memory inputs. Therefore, the memory inputs are not floating. This reduces the risk of untimely memory activation and deactivation. It also prevents leakage currents that could lead to untimely memory activation. Therefore, system power consumption can be reduced.

[0016] In an advantageous embodiment, the selection circuit is configured to select the first configuration circuit to configure the polarization value of the memory input when the control unit is in an operating mode, or to select the second configuration circuit to configure the polarization value of the memory input when the control unit is in a low-power mode.

[0017] Therefore, the selection circuit allows the configuration circuit for configuring the polarization value of the memory input to be selected based on the power supply mode applied to the control unit.

[0018] In an advantageous embodiment, the first and second configuration circuits are configured to apply a high logic state or a low logic state to the memory input.

[0019] By applying a high or low memory state to the memory input, the first and second configuration circuits maintain control over the memory input state and prevent the latter from being in a high impedance state.

[0020] In an advantageous embodiment, a pull-up resistor is configured to be connected to a communication interface to apply a high logic state to the memory input, a pull-down resistor is configured to be connected to the communication interface to apply a low logic state to the memory input, and a switch can be activated or deactivated based on the logic state to be applied to the memory input defined by the first and second configuration circuits. The pull-up and pull-down resistors and the switch provide a simple way to apply logic states to the memory input.

[0021] In an advantageous embodiment, pull-up resistors and pull-down resistors are provided in the input / output ports of the control unit, which are configured to be connected to a memory input via a communication interface.

[0022] Therefore, such a system has the following advantages: it applies the configuration defined by the first and second configuration circuits using pull-up and pull-down resistors that are typically provided in the input / output ports of a microcontroller. This eliminates the need to add additional pull-up and pull-down resistors to the system to apply the configuration. This helps to facilitate system manufacturing and reduce its cost.

[0023] However, alternatively, pull-up resistors and pull-down resistors can be connected to the communication interface between the microcontroller and the memory.

[0024] In an advantageous embodiment, the first configuration circuitry includes a configuration register that defines the configuration of the polarization value of the memory input when the control unit is in an operating mode. The configuration register is provided in an input / output port of the control unit, which is connected to the memory input via a communication interface.

[0025] In an advantageous embodiment, the second configuration circuitry includes a configuration register that defines the polarization value of the memory input when the control unit is in a low-power mode. The configuration register is provided in an input / output port of the control unit, which is configured to be connected to the memory input via a communication interface.

[0026] In an advantageous embodiment, the polarization value of the memory input to be configured is adapted to activate or deactivate the memory. The second configuration circuit is then adapted to configure the polarization value of the memory input to deactivate the memory when the control unit is in a low-power mode.

[0027] Therefore, the second configuration circuit can deactivate the memory when the control unit is in low-power mode. This reduces the power consumption of the memory.

[0028] By configuring the polarization value of the memory input, especially when the control unit is in low-power mode, the risk of modifying the information stored in this type of peripheral device is reduced.

[0029] Embodiments herein also relate to a method for configuring the polarization of a memory input by a control unit electrically connected to the memory input via a communication interface, the control unit having two power regions: a first power region configured to be powered when the control unit is in an operating mode and powered off when the control unit is in a low-power mode, and a second power region configured to be powered when the control unit is in both the operating mode and the low-power mode, the method comprising: configuring the polarization of the memory input via the communication interface using a first control unit configuration circuit placed in the first power region when the control unit is in the operating mode, and configuring the polarization of the memory input via the communication interface using a second control unit configuration circuit placed in the second power region when the control unit is in the low-power mode, the method comprising: configuring the polarization of the memory input via the communication interface using a first control unit configuration circuit placed in the second power region when the control unit is in the low-power mode.

[0030] In an advantageous implementation, the method further includes: selecting the first control unit configuration circuit via a selection circuit to configure the polarization value of the memory input when the control unit is in an operating mode, and selecting the second configuration circuit to configure the polarization value of the memory input when the control unit is in a low-power mode.

[0031] Advantageously, the method includes applying a high logic state or a low logic state to an input of the memory by first and second configuration circuits. Preferably, the high logic state is applied by a pull-up resistor configured to be connected to the communication interface, and the low logic state is applied by a pull-down resistor configured to be connected to the communication interface. The method further includes using a switch to activate or deactivate the pull-up resistor and the pull-down resistor based on the logic state to be applied to the memory input defined by the first and second configuration circuits.

[0032] In an advantageous implementation, when the control unit is in an operating mode, the configuration of the polarization value of the memory input by the first configuration circuit is defined by a configuration register included in the first configuration circuit, which is provided in the input / output port of the control unit, the input / output port being configured to be connected to the memory input via the communication interface.

[0033] Advantageously, when the control unit is in a low-power mode, the configuration of the polarization value of the memory input by the second configuration circuit is defined by a configuration register included in the second configuration circuit, which is provided in the input / output port of the control unit, the input / output port being configured to be connected to the memory input via the communication interface.

[0034] In an advantageous implementation, the polarization value of the memory input to be configured is configured to activate or deactivate the memory. The method further includes deactivating the memory while the polarization value of the memory input is configured by the second configuration circuit, when the control unit is in a low-power mode. Attached Figure Description

[0035] Other advantages and features of the present invention will become apparent upon examination of the detailed description of the implementations and embodiments, as well as the accompanying drawings, which are not limiting. (See the drawings for details.)

[0036] Figure 1 The diagram illustrates a system with a control unit and a memory;

[0037] Figure 2 and Figure 3 A system illustrating an embodiment of a configuration circuit for a control unit is schematically shown;

[0038] Figure 4 The diagram illustrates the details of the selection circuit;

[0039] Figure 5 The figure illustrates a memory configuration system according to a first embodiment, wherein the control unit in the memory configuration system includes a plurality of input / output ports;

[0040] Figure 6 The illustration shows a memory configuration system according to a second embodiment;

[0041] Figure 7 The diagram illustrates the implementation of a method for configuring the memory. Detailed Implementation

[0042] Figure 1 The diagram illustrates a system SYS according to one embodiment. The system includes a control unit UC and a memory MEM. The control unit UC may be, for example, a microcontroller.

[0043] In order to communicate with the memory MEM, the control unit UC includes an input / output port IOP that is electrically connected to the input / output IN of the memory MEM via a communication interface COM. Specifically, the control unit UC is operated to configure the input / output IN of the memory MEM using the configuration circuit described below.

[0044] Furthermore, the control unit UC is configured to use a power source (particularly a battery) to power itself according to different power supply modes. Using different power supply modes avoids unnecessary power consumption during idle periods. Specifically, the control unit UC can be in a so-called operating power supply mode (operating mode or active mode) or a low-power mode (or standby mode). The operating mode is used to power all components of the control unit UC during normal operation. The low-power mode is used when the functions of the control unit UC are not used. This low-power mode can power only the components in the control unit UC that require continuous power.

[0045] Therefore, the control unit UC includes different power supply regions that are powered according to the power supply mode applied to the control unit UC. Each power supply region includes a set of components in the control unit UC that are powered in the same way according to the power supply mode activated for the control unit UC.

[0046] Specifically, two power regions, VCore and VIO, are defined. The first power region, VCore, includes the set of components in the control unit UC that are powered only when the control unit UC is in its operating mode. Therefore, when the control unit UC is in a low-power mode, the components in the first power region, VCore, are not powered. The second power region, VIO, includes the set of components in the control unit UC that require continuous power. Therefore, when the control unit UC is in its operating mode, and when the control unit UC is in a low-power mode, the components in the second power region, VIO, are powered. The control unit UC may further include another first power region, VCore, and another second power region, VIO, as well as optional additional power regions. The additional power regions include the set of components in the control unit UC that are powered when the control unit UC is in its operating mode and may optionally be powered when the control unit UC is in a low-power mode.

[0047] Figure 2 and Figure 3 The system SYS is schematically illustrated, showing an embodiment of the configuration circuitry for the control unit UC. This configuration circuitry is configured to define the configuration of the input IN to be applied to the memory MEM.

[0048] The configuration of the input IN of the memory MEM includes applying a high logic state or a low logic state to the input IN of the memory MEM.

[0049] To apply the configuration defined by the configuration circuitry to the input IN of the memory MEM, the system SYS includes pull-up resistors PU and pull-down resistors PD connected to a communication interface COM, which is also connected to the input IN of the memory MEM. These pull-up resistors PU and PD can be activated or deactivated via switches MCPU and MCPD according to the configuration defined by the configuration circuitry.

[0050] Specifically, the pull-up resistor PU can apply a high logic state to the input IN of the memory MEM, while the pull-down resistor PD can apply a low logic state to the input IN of the memory MEM.

[0051] Figure 2 The diagram illustrates a configuration circuit that applies a high logic state to the input IN of the memory MEM using a pull-up resistor PU. Figure 3 The diagram illustrates a configuration circuit that uses a pull-down resistor PD to apply a low logic state to the input IN of the memory MEM.

[0052] More specifically, the first terminal of the pull-up resistor PU is connected to the communication interface COM via the switch MCPU, and its second terminal is connected to the power supply VDD. Furthermore, the first terminal of the pull-down resistor PD is connected to the communication interface COM via the switch MCPD, and its second terminal is connected to a cold point (specifically, ground GND). Switches MCPU and MCPD can be MOS transistors.

[0053] Here, the pull-up (PU) and pull-down (PD) resistors are integrated into the input / output (IOP) ports of the control unit (UC). Alternatively, refer to the following section. Figure 6 The pull-up PU and pull-down PD resistors can be placed outside the control unit UC. However, using the pull-up PU and pull-down PD resistors integrated in the input / output port IOP to apply a configuration defined by the configuration circuit has the advantage of being able to use pull-up PU and pull-down PD resistors that are typically already provided in the input / output port IOP of the control unit UC. This helps to facilitate the manufacture of the system SYS and reduce its cost.

[0054] Furthermore, as described above, the configuration circuit allows for defining the configuration of the input IN to be applied to the memory MEM. Specifically, the configuration circuit is adapted to control the switches MCPU and MCPD associated with the pull-up PU and pull-down PD resistors according to the defined configuration.

[0055] Figure 2 The configuration circuit shown is used to apply a high state to the input IN of the memory MEM. Figure 3 The configuration circuit shown is the same as the one used to apply a low state to the input IN of the memory MEM.

[0056] More specifically, the control unit UC includes a first configuration circuit CONF1 and a second configuration circuit CONF2. The first configuration circuit CONF1 is included in the first power supply region VCore, and the second configuration circuit CONF2 is included in the second power supply region VIO.

[0057] Therefore, the first configuration circuit CONF1 is only powered when the control unit UC is in operating mode. The first configuration circuit CONF1 is thus used to define the configuration of the input IN of the memory MEM only when the control unit UC is in operating mode.

[0058] Furthermore, the second configuration circuit CONF2 is powered when the control unit UC is in operating mode, and also when the control unit UC is in low-power mode. The second configuration circuit CONF2 is used to define the configuration of the input IN of the memory MEM when the control unit UC is in low-power mode.

[0059] The input IN of the memory MEM can therefore be configured by the first configuration circuit CONF1 when the control unit UC is in the operating mode, and by the second configuration circuit CONF2 when the control unit UC is in the low power mode.

[0060] In this way, the logic state is continuously applied to the input IN of the memory MEM. Therefore, the input IN of the memory MEM is not floating. This reduces the risk of untimely activation and deactivation of the memory MEM. It also prevents leakage current that could lead to untimely activation of the memory MEM. Therefore, the power consumption of the system SYS can be reduced.

[0061] More specifically, the first configuration circuit CONF1 includes a configuration register VCORE_CR_PU, which defines the polarization configuration of the input IN of the memory MEM when the control unit UC is in operating mode. This configuration register VCORE_CR_PU is provided in the input / output port IOP of the control unit UC, which is configured to be connected to the input IN of the memory MEM via the communication interface COM.

[0062] The configuration register VCORE_CR_PU receives the activation signal at its input and can store the configuration of the polarization value. When the activation signal pulses, the configuration register VCORE_CR_PU stores the new configuration of the polarization value. This polarization value corresponds to the polarization value that was configured at the input IN of the memory MEM when the control unit UC is in operating mode.

[0063] The first configuration circuit CONF1 also includes another configuration register VCORE_CR_PD, which is the same as the configuration register VCORE_CR_PU, and can store the same or different configurations of polarization values.

[0064] By storing the polarization values ​​in the configuration registers VCORE_CR_PU and VCORE_CR_PD, the first configuration circuit CONF1 can save the polarization configuration when the control unit UC is in operating mode. This configuration is used to configure the polarization value of the input IN of the memory MEM when the control unit UC is in operating mode.

[0065] The second configuration circuit CONF2 includes a configuration register VIO_CR_PU, which defines the polarization value of the input IN of the memory MEM when the control unit UC is in low-power mode. This configuration register VIO_CR_PU is provided in the input / output port of the control unit UC, which is configured to be connected to the input IN of the memory MEM via the communication interface COM.

[0066] The configuration register VIO_CR_PU receives the activation signal and can store the configuration of the polarization value. When the activation signal pulses, the configuration register VIO_CR_PU stores the new configuration of the polarization value. This polarization value corresponds to the polarization value configured on the input IN of the memory MEM when the control unit UC is in low-power mode.

[0067] The second configuration circuit CONF2 also includes logic gate ET1, control register APCR1, and flip-flop D1.

[0068] The control register APCR1 receives the same activation signal at its input and can optionally apply a configuration. Then, registers VIO_CR_PU and APCR1 transmit the signal corresponding to the polarization configuration and the input control signal for logic gate ET1, respectively. Logic gate ET1 can send a reset signal to flip-flop D1 based on the received signal.

[0069] Flip-flop D1 has an input "D" that is always set to a high logic state, a reset input that is configured to receive a reset signal, an input that is configured to receive an activation signal ISO_PULSE, and an output "Q" for transmitting the control signal PU_VIO.

[0070] At each pulse of the activation signal ISO_PULSE, the value of the input "D" corresponding to the high logic state is transmitted to the output "Q". This pulse corresponds to the low-power mode of the user-activated control unit UC.

[0071] When flip-flop D1 receives a reset signal, flip-flop D1 automatically resets, causing the low logic state to be transmitted to the output "Q".

[0072] The second configuration circuit CONF2 also includes an additional configuration register VIO_CR_PD, an additional logic gate ET2, an additional control register APCR2, and an additional flip-flop D2.

[0073] The configuration register VIO_CR_PD is the same as the configuration register VIO_CR_PU, and can store the same or different polarization configurations. Logic gate ET2 and control register APCR2 are the same as logic gate ET1 and control register APCR1, respectively. Flip-flop D2 is the same as flip-flop D1, but its output "Q" allows the transmission of the control signal PD_VIO.

[0074] By storing the polarization configuration in configuration registers VIO_CR_PU and VIO_CR_PD, the second configuration circuit CONF2 can save the polarization configuration while the control unit is in operating mode. The user can then optionally apply this configuration to the input / output port IOP of the control unit UC, which is connected to the input IN to be configured. This configuration is used to configure the polarization value of the input IN in the memory MEM when the user activates the low-power mode of the control unit UC after the operating mode has ended.

[0075] The first and second configuration circuits CONF1 and CONF2 are adapted to apply a high logic state to the input IN of the memory MEM and a low logic state to the input IN of the memory MEM. The applied logic states then define the polarization value of the input IN of the memory MEM, and prevent the polarization value from changing randomly and uncontrollably when the control unit UC is in a low-power mode.

[0076] In addition, the system SYS also includes selection circuits MS1 and MS2, which are configured to select either a first configuration circuit CONF1 or a second configuration circuit CONF2 to configure the input IN of the memory MEM. Specifically, selection circuits MS1 and MS2 are configured to select the first configuration circuit CONF1 when the control unit UC is in operating mode, and to select the second configuration circuit CONF2 when the control unit UC is in low-power mode.

[0077] exist Figure 4 The selection circuits MS1 and MS2 are described in detail.

[0078] Specifically, the selection circuit includes a selection circuit MS1 for controlling the pull-up resistor PU and a selection circuit MS2 for controlling the pull-down resistor PD.

[0079] The selection circuit MS1 includes logic gates ET_PU and OU_PU. Gate ET_PU is configured to perform the logic operation ET between the signal PU_VCore and the control signal OK_OUT of the first configuration circuit CONF1.

[0080] The OK_OUT signal is generated by the control unit UC. Specifically, the circuit may include a regulator configured to deliver the power supply voltage to the power region VCore. Therefore, the circuit generates a signal OK_OUT with a value of "1" when the power region VCore is powered, and generates a signal OK_OUT with a value of "0" when the power region VCore is not powered.

[0081] Gate ET_PU transmits a signal corresponding to the result of logic operation ET to gate OU_PU. Gate OU_PU is configured to perform logic operation OU between the signal transmitted by gate ET_PU and the signal PU_VIO of the second configuration circuit CONF2. Gate OU_PU then generates a signal corresponding to the result of logic operation OU. Therefore, based on the value of the signal OK_OUT received by gate ET_PU, gate OU_PU can generate a signal corresponding to either signal PU_VIO or signal PU_VCore. Gate OU_PU then transmits this signal to switch MCPU.

[0082] The selection circuit MS2 includes logic gates ET_PD and OU_PD. Gate ET_PD is configured to perform a logic operation ET between the signal PU_VIO and the control signal OK_OUT of the second configuration circuit CONF2. Gate ET_PD transmits a signal corresponding to the result of the logic operation ET to gate OU_PD. Gate OU_PD is configured to perform a logic operation OU between the signal transmitted by gate ET_PD and the signal PU_VCore of the first configuration circuit CONF1. Gate OU_PD then generates a signal corresponding to the result of the logic operation OU. Therefore, based on the value of the signal OK_OUT received by gate ET_PD, gate OU_PD can generate a signal corresponding to either signal PD_VIO or signal PD_VCore. Gate OU_PD then transmits this signal to the switch MCPD.

[0083] The switch MCPU can activate or deactivate the pull-up resistor PU.

[0084] Figure 5 The illustration depicts a memory configuration system according to a first embodiment, wherein the control unit UC includes a plurality of input / output ports IOP. Each port of the input / output ports IOP is electrically connected to an input IN, which is in turn associated with a memory MEM, thereby forming a communication interface COM. Each communication interface COM enables data exchange between the control unit UC and the memory MEM. Depending on the nature of the input IN of the memory MEM, the user may need to adhere to a specific communication protocol to transmit data to that input IN in order to obtain the desired configuration of the memory MEM.

[0085] For example, the memory MEM can have clock inputs CLK and CLK_N, data inputs DATA, peripheral selection inputs NCS, and data sampling inputs DQS.

[0086] In the same example, the input / output port IOP of the control unit UC is adapted to form a link SPI with the inputs CLK, CLK_N, DATA NCS and DQS to configure the memory MEM.

[0087] The control unit UC includes a control bus CTRL and several selection circuits MS. The selection circuits generate control signals CTRLU1, CTRLU2, CTRLU3, CTRLD1, CTRLD2, CTRLD3, CTRLD4, and CTRLD5 to control switches MCPU1, MCPU2, MCPU3, MCPD1, MCPD2, MCPD3, MCPD4, and MCPD5. The control bus CTRL can connect each selection circuit to its associated switch and then transmit control signals to the switch.

[0088] The user should then use the protocol associated with the link type (such as a link SPI) formed by the input / output port IOP of the control unit UC and the input IN of the memory MEM.

[0089] In communication protocols such as SPI, the input NCS allows the memory MEM to be activated or deactivated based on its polarization value. This input NCS is called the "chip select". The second configuration circuit CONF2 is then adapted to configure this polarization value of the memory MEM's input NCS to deactivate the memory MEM when the control unit UC is in a low-power mode.

[0090] Therefore, the user can select the memory MEM communicating with the control unit UC by activating or deactivating it based on the polarization value of the input NCS. Specifically, when the control unit UC is in a low-power mode, the user can deactivate the memory MEM, which reduces the power dissipation of the memory MEM in this low-power mode. For example, it can be specified that a high logic state of the input NCS applied to the memory MEM will deactivate the memory MEM.

[0091] Pull-up resistors (PU) and pull-down resistors (PD) are provided in the input / output port (IOP) of the control unit (UC), which is configured to be connected to the input (IN) of the memory (MEM).

[0092] Preferably, each input / output port (IOP) of the control unit UC provides a pull-up resistor PU and a pull-down resistor PD. The user can then select the logic state to be applied at the input IN of the memory MEM based on the configuration of the polarization values ​​previously stored in the registers VCORE_CR_PU, VCORE_CR_PD, VIO_CR_PU, or VIO_CR_PD. However, a single pull-up resistor PU can be provided in each input / output port (IOP) of the control unit UC. Similarly, a single pull-down resistor PD can be provided in each input / output port (IOP) of the control unit UC.

[0093] As seen above, by integrating pull-up resistors (PU) and pull-down resistors (PD) into the input / output ports (IOP) of the control unit (UC), the manufacturing process of the control unit (UC) can be simplified.

[0094] However, alternatively, such as Figure 6 As shown, the pull-up PU and pull-down PD resistors can be connected to the communication interface COM between the control unit UC and the memory MEM.

[0095] Specifically, Figure 6 The figure illustrates a memory configuration system according to a second embodiment, wherein system SYS and Figure 5 The system is the same as SYS, except that the pull-up PU and pull-down PD resistors, as well as the switches MCPU and MCPD, are placed outside the control unit UC and connected to the communication interface COM.

[0096] The user can then design a circuit that includes its own pull-up PU and pull-down PD resistors, as well as its own switches MCPU and MCPD. This circuit can then be connected to the communication interface COM and controlled by the control unit UC, which does not have circuitry for applying logic states at the input IN of the memory MEM.

[0097] In the same Figure 6 In this configuration, pull-up resistors PU1, PU2, and PU3 are connected to the power supply VDD and are respectively connected to the sources of MCPU1, MCPU2, and MCPU3. The drains of MCPU1, MCPU2, and MCPU3 are respectively connected to the inputs CLK, CLK_N, and NCS of the memory MEM. Pull-down resistors PD1, PD2, PD3, PD4, and PD5 are connected to the sources of MCPD1, MCPD2, MCPD3, and MCPD4. The drains of MCPD1, MCPD2, MCPD3, MCPD4, and MCPD5 are respectively connected to the inputs DQS, CLK, CLK_N, DATA, and NCS of the memory MEM.

[0098] The control unit UC includes a control bus CTRL connected to one of its input / output ports IOP and several selection circuits MS. The selection circuits generate control signals CTRLU1, CTRLU2, CTRLU3, CTRLD1, CTRLD2, CTRLD3, CTRLD4, and CTRLD5 to control switches MCPU1, MCPU2, MCPU3, MCPD1, MCPD2, MCPD3, MCPD4, and MCPD5. The control bus CTRL can connect each selection circuit to its associated switch and can then transmit control signals to the switch.

[0099] Figure 7 The diagram illustrates an implementation of a method for configuring the memory MEM. More specifically, a control unit UC, electrically connected to the input IN of the memory MEM via a communication interface COM, configures the polarization value of the input IN on the memory MEM. This configuration method can be implemented using the aforementioned system SYS.

[0100] The method includes configuring the polarization value of the input IN of the memory MEM via the communication interface COM by using the first configuration circuit CONF1 of the control unit UC when the control unit UC is in the operating mode or the second configuration circuit CONF2 of the control unit UC when the control unit UC is in the low power mode.

[0101] Specifically, the control unit UC is configured to receive instructions from the user and change modes according to those instructions.

[0102] Figure 7 A more specific example of a method for configuring the memory MEM is illustrated, wherein the control unit is initially in an operating mode, then switches to a low-power mode, and then returns to the operating mode.

[0103] At step 20, the control unit UC is in operating mode, and regions VCore and VIO are powered. The contents of registers APCR1 and APCR2 are set to "0" to prevent the second configuration circuit CONF2 from configuring the input IN of the memory MEM. The first configuration circuit CONF1 uses the values ​​contained in the configuration registers VCORE_CR_PU and VCORE_CR_PD to generate control signals PU_VCore and PD_VCore. As described above, these signals PU_VCore and PD_VCore enable the configuration of the polarization value of the input IN of the memory MEM.

[0104] Furthermore, when the control unit UC is in the aforementioned operating mode, the control unit UC generates a control signal OK_OUT with a value of "1" at the inputs of the selection circuits MS1 and MS2.

[0105] The configuration method also includes a selection step 21 performed by selection circuits MS1 and MS2 of the first configuration circuit CONF1. This step 21 more specifically corresponds to the above-described selection of the control signals PU_VCore and PD_VCore generated by the first configuration circuit CONF1 to configure the polarization value of the input IN of the memory MEM.

[0106] In step 22, the selected control signal PU_VCore is transmitted to the switch MCPU by the selection circuit MS1. The switch MCPU can be turned on or off according to the control signal value corresponding to the configuration applied at the input IN of the memory to be stored (MEM). Similarly, the selected control signal PD_VCore is transmitted to the switch MCPD by the selection circuit MS2. The switch MCPD can be turned on or off according to the control signal value corresponding to the configuration applied at the input IN of the memory to be stored (MEM).

[0107] For example, the switch MCPD is turned on for the configuration value transmitted by the signal PD_VCore. The switch MCPD then activates the pull-down resistor PD to apply a low logic state to the input IN of the memory MEM.

[0108] Similarly, the switch MCPU is turned on in response to the configuration value transmitted by the signal PU_VCore. The switch MCPU then activates the pull-up resistor PU to apply a high logic state to the input IN of the memory MEM.

[0109] In step 23, the contents of configuration registers VIO_CR_PU and VIO_CR_PD, as well as the contents of registers APCR1 and APCR2, are modified to configure the input IN of memory MEM via the second configuration circuit CONF2 when the control unit is in low-power mode. The operation of registers VIO_CR_PU, VIO_CR_PD, APCR1, and APCR2 of the second configuration circuit CONF2 is the same as described above.

[0110] At step 24, the control unit switches to low-power mode. Power region VCore is then turned off, while power region VIO continues to be powered. The control unit UC generates a control signal OK_OUT with a value of "0" at the inputs of selection circuits MS1 and MS2, and generates the signal ISO_PULSE at the inputs of flip-flops D1 and D2. The second configuration circuit CONF2 then uses the values ​​contained in the configuration registers VIO_CR_PU and VIO_CR_PD to generate control signals PU_VIO and PD_VIO. As described above, these signals PU_VIO and PD_VIO enable the configuration of the polarization value of the input IN of memory MEM.

[0111] The configuration method also includes a selection step 25 performed by the selection circuits MS1 and MS2 of the second configuration circuit CONF2. This step 25 more specifically corresponds to the above-described selection of the control signals PU_VIO and PD_VIO generated by the second configuration circuit CONF2 to configure the polarization value of the input IN of the memory MEM.

[0112] At step 26, the selected control signal PU_VIO is transmitted from selection circuit MS1 to switch MCPU. Based on the value of this control signal corresponding to the configuration applied at input IN of the memory to be stored (MEM), switch MCPU can be turned on or off. Similarly, the selected control signal PD_VIO is transmitted from selection circuit MS2 to switch MCPD. Based on the value of this control signal corresponding to the configuration applied at input IN of the memory to be stored (MEM), switch MCPD can be turned on or off.

[0113] For example, the switch MCPD is turned on for the configuration value transmitted by the signal PD_VIO. The switch MCPD then activates the pull-down resistor PD to apply a low logic state to the input IN of the memory MEM.

[0114] Similarly, the switch MCPU is turned on in response to the configuration value transmitted by the signal PU_VIO. The switch MCPU then activates the pull-up resistor PU to apply a high logic state to the input IN of the memory MEM.

[0115] More specifically, when MCPU3 is turned on at step 26, a high logic state can be applied to the input NCS of the memory MEM by pull-up resistor PU3. For example, MCPU3 is turned on when signal CTRLU3 is in a low logic state. In particular, when the control unit UC is in a low-power mode, and therefore when signal CTRLU3 corresponds to the control signal PU_VIO generated by the second configuration circuit CONF2, the memory MEM is then deactivated.

[0116] Finally, in step 27, the control unit UC switches to operating mode, the power supply region VCore is powered on again, and the contents of registers VCORE_CR_PU and VCORE_CR_PD are reset. Then, it is necessary to modify the contents of these registers VCORE_CR_PU and VCORE_CR_PD to enable configuration of the memory MEM via the first configuration circuit CONF1 input IN, and to deactivate the second configuration circuit by setting the contents of registers APCR1 and APCR2 to "0". The method can then continue from step 20.

Claims

1. A system comprising: The control unit can be electrically connected to the memory input via a communication interface; The control unit includes two power supply regions: a first power supply region configured to be powered when the control unit is in an operating mode and to be turned off when the control unit is in a low-power mode; And a second power supply region, configured to be powered when the control unit is in the operating mode and when it is in the low power mode; The control unit includes: In the first power supply region, the first configuration circuit operates when the control unit is in the operating mode to configure the polarization value of the input of the memory via the communication interface; as well as In the second power region, the second configuration circuit operates when the control unit is in the low-power mode to configure the polarization value of the input of the memory via the communication interface.

2. The system of claim 1 further includes a selection circuit configured to select the first configuration circuit to configure the polarization value of the input of the memory when the control unit is in the operating mode, and to select the second configuration circuit to configure the polarization value of the input of the memory when the control unit is in the low-power mode.

3. The system of claim 1, wherein the first configuration circuit and the second configuration circuit are configured to apply a logic state, either a high logic state or a low logic state, to the input of the memory.

4. The system according to claim 3, further comprising: A pull-up resistor is configured to be connected to the communication interface to apply the high logic state to the input of the memory; A pull-down resistor is configured to be connected to the communication interface to apply the low logic state to the input of the memory; The switch is selectively controlled to activate or deactivate the pull-up resistor and the pull-down resistor based on the logic state of the input to the memory defined by the first configuration circuit and the second configuration circuit.

5. The system of claim 4, wherein the pull-up resistor and the pull-down resistor are provided in the input / output port of the control unit, the input / output port being configured to be connected to the input of the memory via the communication interface.

6. The system according to claim 4, further comprising: The memory; as well as The communication interface connects the memory to the control unit; The pull-up resistor and the pull-down resistor are connected to the communication interface between the control unit and the memory.

7. The system of claim 1, wherein the first configuration circuitry includes a configuration register defining a configuration of the polarization value of the memory's input when the control unit is in the operating mode, the configuration register being provided in an input / output port of the control unit configured to be connected to the memory's input via the communication interface.

8. The system of claim 1, wherein the second configuration circuitry includes a configuration register defining a configuration of the polarization value of the memory's input when the control unit is in the low-power mode, the configuration register being provided in an input / output port of the control unit configured to be connected to the memory's input via the communication interface.

9. The system of claim 1, wherein the polarization value of the input of the memory to be configured operates to activate or deactivate the memory, and wherein the second configuration circuit operates to configure the polarization value of the input of the memory to deactivate the memory when the control unit is in the low-power mode.

10. A method for configuring the polarization of the input of a memory via a control unit electrically connected to the input of the memory through a communication interface, wherein the control unit has two power supply regions: a first power supply region configured to be powered when the control unit is in an operating mode and to be turned off when the control unit is in a low-power mode; and a second power supply region configured to be powered when the control unit is in the operating mode and in the low-power mode, the method comprising: When the control unit is in the operating mode, the polarization value of the input of the memory is configured via the communication interface using the first configuration circuit of the control unit located in the first power area; as well as When the control unit is in the low-power mode, the polarization value of the input of the memory is configured via the communication interface using the second configuration circuit of the control unit located in the second power area.

11. The method of claim 10, further comprising: When the control unit is in the operating mode, the polarization value of the input of the memory is selected by the selection circuit of the first configuration circuit; as well as When the control unit is in the low-power mode, the polarization value of the input to the memory is selected by the selection circuit of the second configuration circuit.

12. The method of claim 10, further comprising applying a state of either a high logic state or a low logic state to the input of the memory by the first configuration circuit and the second configuration circuit.

13. The method according to claim 12, wherein: Applying the high logic state includes using a pull-up resistor configured to be connected to the communication interface; Applying the low logic state includes using a pull-down resistor configured to be connected to the communication interface.

14. The method of claim 13, further comprising: Based on the logic state of the input to the memory defined by one or more of the first and second configuration circuits, a switch connected to the pull-up resistor is selectively actuated to apply the high logic state. as well as The low logic state is selectively applied by a switch connected to the pull-down resistor, based on the logic state of the input to the memory defined by one or more of the first and second configuration circuits.

15. The method of claim 14, wherein the pull-up resistor and the pull-down resistor are provided in the input / output port of the control unit, the input / output port being configured to be connected to the input of the memory via the communication interface.

16. The method of claim 14, wherein the pull-up resistor and the pull-down resistor are connected to the communication interface between the control unit and the memory.

17. The method of claim 10, further comprising: When the control unit is in the operating mode, the polarization value of the input of the memory is loaded into a configuration register included in the first configuration circuit. The configuration register is provided in the input / output port of the control unit, which is configured to be connected to the input of the memory via the communication interface.

18. The method of claim 10, wherein when the control unit is in the low-power mode, the polarization value of the input of the memory is loaded into a configuration register included in the second configuration circuit, the configuration register being provided in an input / output port of the control unit, the input / output port being configured to be connected to the input of the memory via the communication interface.

19. The method of claim 10, wherein the polarization value of the input to the memory is applied to selectively activate or deactivate the memory, the method further comprising: When the control unit is in the low-power mode, the memory is deactivated during the configuration of the polarization value of the input of the memory by the second configuration circuit.

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