Chip bus detection method and device, electronic equipment and storage medium

Abstract

The application provides a chip bus detection method and device, electronic equipment and a storage medium. The chip bus detection method comprises the following steps: in response to detecting a bandwidth detection event, obtaining clock information of a bus node in a chip, wherein the clock information comprises the frequency of a clock signal; obtaining the read-write times of the bus node; and generating bandwidth information of the bus node according to the frequency of the clock signal and the read-write times. Thus, the bandwidth information of the chip bus node can be detected, and the transmission performance of the chip bus can be verified.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip bus testing method, apparatus, electronic device, and storage medium. Background Technology

[0002] As the design scale of System on Chip (SOC) increases, the performance of SOC chips gradually improves. However, the number and complexity of the intellectual property cores (IP cores) used in SOC chips have also increased significantly. Various IP cores share memory system resources and bus resources, which places higher demands on the architecture design and verification of SOC chip buses. Summary of the Invention

[0003] The first aspect of this application proposes a chip bus detection method that can detect the bandwidth information of chip bus nodes, thereby verifying the transmission performance of the chip bus.

[0004] The second aspect of this application provides a chip bus detection device.

[0005] A third aspect of this application provides an electronic device.

[0006] The fourth aspect of this application provides a computer-readable storage medium.

[0007] The first aspect of this application proposes a chip bus detection method, comprising: in response to detecting a bandwidth detection event, acquiring clock information of a bus node in the chip, wherein the clock information includes the frequency of a clock signal; acquiring the number of read / write operations of the bus node; and generating bandwidth information of the bus node based on the frequency of the clock signal and the number of read / write operations.

[0008] According to the chip bus detection method of this application embodiment, in response to the detection of a bandwidth detection event, the clock information of the bus node in the chip is first acquired, wherein the clock information includes the frequency of the clock signal. Then, the number of read / write operations of the bus node is acquired, and the bandwidth information of the bus node is generated based on the frequency of the clock signal and the number of read / write operations. Thus, the bandwidth information of the chip bus node can be detected, thereby verifying the transmission performance of the chip bus.

[0009] In addition, the chip bus detection method according to the above embodiments of this application may also have the following additional technical features:

[0010] In one embodiment of this application, obtaining the read / write count of the bus node includes: obtaining a valid window time; performing data read / write operations on the chip to detect the read / write count of the bus node within the valid window time, wherein the read / write count includes valid read / write counts.

[0011] In one embodiment of this application, generating the bandwidth information of the bus node based on the frequency of the clock signal and the number of read / write operations includes: obtaining the data transmission bit width of the bus node; generating the bandwidth information of the bus node based on the data transmission bit width, the effective number of read / write operations, the number of read / write operations, and the frequency of the clock signal, wherein the bandwidth information includes the maximum theoretical load that the chip can carry.

[0012] In one embodiment of this application, the maximum theoretical load is calculated using the following formula:

[0013] P=(valid_cnt / total_cnt)*(aclk_freq*SIZE*1000),

[0014] Wherein, P is the maximum theoretical load, valid_cnt is the number of valid reads and writes, total_cnt is the number of reads and writes, aclk_freq is the frequency of the clock signal, and SIZE is the data transmission width of the bus node.

[0015] In one embodiment of this application, the chip bus detection method further includes: if a bandwidth detection request is received, then determining that the bandwidth detection event has been detected.

[0016] A second aspect of this application provides a chip bus detection device, comprising: a first acquisition module, configured to acquire clock information of a bus node in the chip in response to a detected bandwidth detection event, wherein the clock information includes the frequency of a clock signal; a second acquisition module, configured to acquire the number of read / write operations of the bus node; and a generation module, configured to generate bandwidth information of the bus node based on the frequency of the clock signal and the number of read / write operations.

[0017] The chip bus detection device of this application embodiment first acquires the clock information of the bus node in the chip in response to the detection of a bandwidth detection event by a first acquisition module, wherein the clock information includes the frequency of the clock signal. Then, a second acquisition module acquires the read and write counts of the bus node, and a generation module generates the bandwidth information of the bus node based on the frequency of the clock signal and the read and write counts. Thus, the bandwidth information of the chip bus node can be detected, thereby verifying the transmission performance of the chip bus.

[0018] In addition, the chip bus detection device according to the above embodiments of this application may also have the following additional technical features:

[0019] In one embodiment of this application, the second acquisition module is specifically used for: acquiring a valid window time; performing data read and write operations on the chip to detect the number of read and write operations of the bus node within the valid window time, wherein the number of read and write operations includes the number of valid read and write operations.

[0020] In one embodiment of this application, the generation module is specifically used to: obtain the data transmission bit width of the bus node; and generate the bandwidth information of the bus node based on the data transmission bit width, the effective read / write count, the read / write count, and the frequency of the clock signal, wherein the bandwidth information includes the maximum theoretical load carried by the chip.

[0021] In one embodiment of this application, the generation module calculates the maximum theoretical load using the following formula:

[0022] P=(valid_cnt / total_cnt)*(aclk_freq*SIZE*1000),

[0023] Wherein, P is the maximum theoretical load, valid_cnt is the number of valid reads and writes, total_cnt is the number of reads and writes, aclk_freq is the frequency of the clock signal, and SIZE is the data transmission width of the bus node.

[0024] In one embodiment of this application, the chip bus detection device further includes: a determination module, configured to determine that the bandwidth detection event has been detected if a bandwidth detection request is received.

[0025] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the chip bus detection method described in the first aspect of the application.

[0026] The electronic device of this application embodiment can detect the bandwidth information of the chip bus node by executing a computer program stored in the memory through a processor, thereby verifying the transmission performance of the chip bus.

[0027] The fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the chip bus detection method as described in the first aspect of the present invention.

[0028] The computer-readable storage medium of this application embodiment can detect the bandwidth information of the chip bus node by storing a computer program and having it executed by a processor, thereby verifying the transmission performance of the chip bus.

[0029] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0030] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0031] Figure 1 This is a schematic flowchart of a chip bus detection method according to an embodiment of this application;

[0032] Figure 2 This is a schematic flowchart of a chip bus detection method according to another embodiment of this application;

[0033] Figure 3 This is a schematic flowchart of a chip bus detection method according to another embodiment of this application;

[0034] Figure 4 This is a schematic diagram of the structure of a chip bus detection device according to an embodiment of this application; and

[0035] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0036] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0037] The following describes, with reference to the accompanying drawings, a method, apparatus, electronic device, and storage medium for detecting a chip bus according to embodiments of this application.

[0038] The chip bus detection method provided in this application embodiment can be executed by a monitor, which is composed of synchronous timing logic circuits and is used to detect the performance of the chip bus. The monitor can be configured to be executed in an electronic device.

[0039] In this embodiment, the electronic device may include a processing component, a storage component, and a driver component. Optionally, the driver component and the processing component may be integrated, and the storage component may store an operating system, application programs, or other program modules. The processing component implements the chip bus detection method provided in this embodiment by executing the application programs stored in the storage component.

[0040] Figure 1 This is a flowchart illustrating a chip bus detection method according to an embodiment of this application.

[0041] The chip bus detection method of this application embodiment can also be executed by the chip bus detection device (e.g., the device in the monitor) provided in this application embodiment. The device can be configured in an electronic device to realize the acquisition of the clock information of the bus node in the chip in response to the detection of a bandwidth detection event. The clock information includes the frequency of the clock signal. Then, the number of read and write operations of the bus node is acquired, and the bandwidth information of the bus node is generated according to the frequency of the clock signal and the number of read and write operations. In this way, the bandwidth information of the chip bus node can be detected, thereby verifying the transmission performance of the chip bus.

[0042] like Figure 1 As shown, the detection method for the chip bus may include:

[0043] Step 101: In response to the detection of a bandwidth detection event, obtain the clock information of the bus node in the chip. The clock information may include the frequency of the clock signal. The frequency of the clock signal can be calibrated according to the actual situation and requirements, and no limitation is made here.

[0044] The bus may include AXI (Advanced eXtensible Interface) bus and AHB (Advanced High Performance Bus) bus, etc. The bus node may be the bus interface of the memory system in the chip as well as various subsystems and modules, and there may be one or more bus nodes.

[0045] In this embodiment, the clock signal generation unit in the chip can generate a clock signal, which can be a periodic pulse signal, used to provide a reference for data transmission between multiple synchronously executing circuits in the chip, as well as between different subsystems or modules in the chip. The clock signal generation unit may include a clock oscillator (e.g., a quartz crystal resonator and a resistor-capacitor oscillator) and a clock oscillation circuit, etc., for generating the clock signal.

[0046] As a possible alternative, a clock signal can be generated by an external clock source (such as a clock oscillator or clock circuit) and then input into the chip through the chip's clock signal input pin to provide a clock signal for the chip.

[0047] To clearly illustrate the previous embodiment, in one embodiment of this application, if a bandwidth detection request is received, it is determined that a bandwidth detection event has been detected.

[0048] In this embodiment of the application, relevant personnel can create a bandwidth detection request on a relevant client and send the bandwidth detection request to a monitor, which will receive and respond to it.

[0049] Specifically, when the monitor receives the aforementioned bandwidth detection request, it can determine that a bandwidth detection event has been detected and, in response to the bandwidth detection request, obtain the clock information of the bus node in the chip.

[0050] Step 102: Obtain the number of read and write operations for the bus node.

[0051] To clearly illustrate the previous embodiment, in one embodiment of this application, such as Figure 2 As shown, obtaining the read / write count of a bus node can include:

[0052] Step 201: Obtain the effective window time. The effective window time can be calibrated according to the actual situation and needs, and there are no restrictions here. For example, it can be 5 seconds, 10 seconds, or 20 seconds.

[0053] Step 202: Perform data read and write operations on the chip to detect the number of read and write operations of the bus node within the valid window time. The number of read and write operations may include the number of valid read and write operations, and the data read and write operations may include one or more of the following: data read operations and data write operations.

[0054] In this embodiment, during data read / write operations on the chip, if the read / write operation is successful, it can be determined that the read / write operation is valid. This involves controlling the transmission of multiple signals from bus nodes between the chip's master and slave devices to perform data read / write operations on the chip.

[0055] Specifically, after the monitor obtains the aforementioned effective window time, it can perform data read and write operations on the chip, and during the data read and write process, it obtains the number of read and write operations of the aforementioned bus node within the effective window time.

[0056] As one possible scenario, the monitor can first perform data read and write operations on the chip, and then obtain the aforementioned effective window time to detect the number of read and write operations of the bus node within the effective window time. That is, during the data read and write process, the monitor can obtain the number of read and write operations of the bus node within the effective window time.

[0057] Step 103: Generate the bandwidth information of the bus node based on the frequency of the clock signal and the number of read / write operations.

[0058] To clearly illustrate the previous embodiment, in one embodiment of this application, such as Figure 3 As shown, the bandwidth information of the bus node is generated based on the frequency of the clock signal and the number of read / write operations, and may include:

[0059] Step 301: Obtain the data transmission bit width of the bus node.

[0060] The data transmission bit width can be the number of binary bits transmitted in one data transmission.

[0061] Specifically, when the monitor performs data read and write operations on the chip, the read and write data can be transmitted through the chip bus. During the transmission of read and write data on the chip bus, the monitor can obtain the data transmission bit width of the aforementioned bus node.

[0062] Step 302: Generate the bandwidth information of the bus node based on the data transmission bit width, effective read / write count, read / write count and clock signal frequency. The bandwidth information may include the maximum theoretical load that the chip can carry.

[0063] Furthermore, in one embodiment of this application, the maximum theoretical load can be calculated using the following formula (1):

[0064] P=(valid_cnt / total_cnt)*(aclk_freq*SIZE*1000) (1)

[0065] Where P can be the maximum theoretical load, valid_cnt can be the number of valid reads and writes, total_cnt can be the number of reads and writes, aclk_freq can be the frequency of the clock signal, and SIZE can be the data transmission width of the bus node.

[0066] Specifically, after the monitor obtains the data transmission bit width, effective read / write count, read / write count and clock signal frequency, it can calculate the maximum theoretical load of the bus node using the formula (1). This maximum theoretical load can be used as a performance indicator of the chip bus to characterize the load capacity of the chip bus during data transmission.

[0067] In summary, the chip bus detection method according to the embodiments of this application firstly, in response to the detection of a bandwidth detection event, acquires the clock information of the bus node in the chip, wherein the clock information includes the frequency of the clock signal; then, acquires the number of read / write operations of the bus node; and generates the bandwidth information of the bus node based on the frequency of the clock signal and the number of read / write operations. Thus, the bandwidth information of the chip bus node can be detected, thereby verifying the transmission performance of the chip bus.

[0068] Figure 4 This is a block diagram of a chip bus detection device according to an embodiment of the present application.

[0069] The chip bus detection device of this application embodiment can be configured in an electronic device to realize the acquisition of clock information of bus nodes in the chip in response to the detection of a bandwidth detection event. The clock information includes the frequency of the clock signal. Then, the number of read and write operations of the bus node is acquired, and the bandwidth information of the bus node is generated according to the frequency of the clock signal and the number of read and write operations. In this way, the bandwidth information of the chip bus node can be detected, thereby verifying the transmission performance of the chip bus.

[0070] like Figure 4 As shown, the chip bus detection device 400 may include: a first acquisition module 410, a second acquisition module 420, and a generation module 430.

[0071] The first acquisition module 410 is used to acquire the clock information of the bus node in the chip in response to the detection of a bandwidth detection event, wherein the clock information includes the frequency of the clock signal.

[0072] The second acquisition module 420 is used to acquire the number of read and write operations of the bus node;

[0073] The generation module 430 is used to generate the bandwidth information of the bus node based on the frequency of the clock signal and the number of read / write operations.

[0074] In one embodiment of this application, the second acquisition module 420 is specifically used for: acquiring the effective window time; performing data read and write operations on the chip to detect the number of read and write operations of the bus node within the effective window time, wherein the number of read and write operations includes the effective read and write operations.

[0075] In one embodiment of this application, the generation module 430 is specifically used to: obtain the data transmission bit width of the bus node; and generate the bandwidth information of the bus node based on the data transmission bit width, the effective read / write count, the read / write count, and the frequency of the clock signal, wherein the bandwidth information includes the maximum theoretical load that the chip can carry.

[0076] In one embodiment of this application, the generation module 430 calculates the maximum theoretical load using the following formula:

[0077] P=(valid_cnt / total_cnt)*(aclk_freq*SIZE*1000),

[0078] Where P is the maximum theoretical load, valid_cnt is the number of valid read / write operations, total_cnt is the number of read / write operations, aclk_freq is the frequency of the clock signal, and SIZE is the data transmission width of the bus node.

[0079] In one embodiment of this application, the detection device 400 of the chip bus further includes a determination module, which determines that a bandwidth detection event has been detected if a bandwidth detection request is received.

[0080] It should be noted that for details not disclosed in the chip bus detection device of this application embodiment, please refer to the details disclosed in the chip bus detection method of this application embodiment, which will not be repeated here.

[0081] In summary, the chip bus detection device of this application embodiment first acquires the clock information of the bus node in the chip in response to the detection of a bandwidth detection event by a first acquisition module, wherein the clock information includes the frequency of the clock signal. Then, a second acquisition module acquires the number of read / write operations of the bus node, and a generation module generates the bandwidth information of the bus node based on the frequency of the clock signal and the number of read / write operations. Thus, the bandwidth information of the chip bus node can be detected, thereby verifying the transmission performance of the chip bus.

[0082] To achieve the above embodiments, such as Figure 5 As shown, this application also proposes an electronic device 500, including a memory 510, a processor 520, and a computer program stored in the memory 510 and executable on the processor 520. The processor 520 executes the program to implement the chip bus detection method proposed in the foregoing embodiments of this application.

[0083] The electronic device of this application embodiment can detect the bandwidth information of the chip bus node by executing a computer program stored in the memory through a processor, thereby verifying the transmission performance of the chip bus.

[0084] To implement the above embodiments, this application also proposes a non-transitory computer-readable storage medium storing a computer program thereon, which is executed by a processor to implement the chip bus detection method proposed in the foregoing embodiments of this application.

[0085] The computer-readable storage medium of this application embodiment can detect the bandwidth information of the chip bus node by storing a computer program and having it executed by a processor, thereby verifying the transmission performance of the chip bus.

[0086] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0087] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0088] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A method for detecting a chip bus, characterized in that, include: In response to the detection of a bandwidth detection event, clock information of the bus node in the chip is acquired, wherein the clock information includes the frequency of the clock signal; Obtain the read / write count of the bus node; The bandwidth information of the bus node is generated based on the frequency of the clock signal and the number of read / write operations. The step of obtaining the read / write count of the bus node includes: Obtain the valid window time; Data read and write operations are performed on the chip to detect the number of read and write operations of the bus node within the effective window time, wherein the number of read and write operations includes the effective number of read and write operations; The step of generating the bandwidth information of the bus node based on the frequency of the clock signal and the number of read / write operations includes: Obtain the data transmission bit width of the bus node; The bandwidth information of the bus node is generated based on the data transmission bit width, the effective read / write count, the read / write count, and the frequency of the clock signal, wherein the bandwidth information includes the maximum theoretical load that the chip can carry.

2. The chip bus detection method according to claim 1, characterized in that, The maximum theoretical load is calculated using the following formula: ， Wherein, P is the maximum theoretical load, and the For the effective read / write count, the For the number of read / write operations, the The frequency of the clock signal, the This refers to the data transmission bit width of the bus node.

3. The chip bus detection method according to claim 1, characterized in that, Also includes: If a bandwidth detection request is received, it is determined that the bandwidth detection event has been detected.

4. A chip bus detection device, characterized in that, include: The first acquisition module is used to acquire clock information of the bus node in the chip in response to the detection of a bandwidth detection event, wherein the clock information includes the frequency of the clock signal; The second acquisition module is used to acquire the number of read and write operations of the bus node; The generation module is used to generate the bandwidth information of the bus node based on the frequency of the clock signal and the number of read / write operations. The second acquisition module is specifically used for: Obtain the valid window time; Data read and write operations are performed on the chip to detect the number of read and write operations of the bus node within the effective window time, wherein the number of read and write operations includes the effective number of read and write operations; Specifically, the generation module is used for: Obtain the data transmission bit width of the bus node; The bandwidth information of the bus node is generated based on the data transmission bit width, the effective read / write count, the read / write count, and the frequency of the clock signal, wherein the bandwidth information includes the maximum theoretical load that the chip can carry.

5. The chip bus detection device according to claim 4, characterized in that, The generation module calculates the maximum theoretical load using the following formula: ， Wherein, P is the maximum theoretical load, and the For the effective read / write count, the For the number of read / write operations, the The frequency of the clock signal, the This refers to the data transmission bit width of the bus node.

6. The chip bus detection device according to claim 4, characterized in that, Also includes: The determination module is used to determine that the bandwidth detection event has been detected if a bandwidth detection request is received.

7. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the chip bus detection method as described in any one of claims 1-3.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the chip bus detection method as described in any one of claims 1-3.

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