A method and apparatus for timing analysis of a critical path of a digital circuit

Abstract

The application relates to the technical field of digital circuit fault analysis, in particular to a digital circuit key path timing analysis method and device, which can solve the problems that a traditional algorithm can only process a low-dimensional change space of a small number of independent random variables and only focuses on unit-level fault time while ignoring the correlation between unit levels. The method comprises the following steps: acquiring the number of units in a digital circuit system and the order D of the system-level fault rate; estimating the unit fault rate and the simultaneous fault rate of the same number of units as the number of unit levels; calculating the D-order and D-1-order local failure rates based on the simultaneous fault rate; calculating the upper limit value of the D+1-order local failure rate based on the D-order and D-1-order local failure rates, wherein the upper limit value of the D+1-order local failure rate and the D-order local failure rate are used for calculating the second estimation value of the D-order system fault rate; and selecting the asymptotic probability approximation value from the interval composed of the first estimation value of the D-order system fault rate and the second estimation value of the D-order system fault rate.

Description

Technical Field

[0001] This application relates to the field of digital circuit fault analysis technology, and more specifically, to a method and apparatus for critical path timing analysis of digital circuits. Background Technology

[0002] As circuits become increasingly integrated and circuit designs become more complex, achieving highly reliable large-scale integrated circuit designs is a current research focus.

[0003] Timing analysis is a workflow in electronic engineering that calculates and predicts the timing of digital circuits. The critical path typically refers to the path with the longest combinational logic delay in a synchronous logic circuit; in other words, the critical path is the timing path that has a decisive impact on the design performance. Critical path timing analysis of digital circuits essentially analyzes the probability of system failure in a digital circuit system.

[0004] System-level failure events are often based on the occurrence of unit-level failure events. Existing technologies use significance sampling (BS), boundary search (BS), and subset simulation (SUS) to analyze system-level failure events. When calculating the system failure rate, these technologies often assume that unit-level failure events are independent of each other. Therefore, these existing methods ignore the correlation between units when calculating the system failure rate. Summary of the Invention

[0005] To address the problem that traditional algorithms only focus on unit-level fault events while ignoring the correlation between unit levels, this application provides a method and apparatus for timing analysis of critical paths in digital circuits.

[0006] The embodiments of this application are implemented as follows: One embodiment of this application provides a timing analysis method for critical paths in digital circuits, the method comprising: Obtain the number of cells and the order D of the system-level failure rate in a digital circuit system; Estimate the same number of cell failure rates and simultaneous failure rates as the number of cell levels, where the cell failure rate is used to characterize the probability of a cell-level failure event occurring in the digital circuit, and the simultaneous failure rate is obtained by linearly combining all the cell failure rates. Based on the simultaneous failure rate, calculate the D-order local failure rate and the D-1-order local failure rate. The D-order and D-1-order local failure rates are used to calculate the first estimate of the D-order system failure rate. The local space corresponding to the local failure rate includes multiple of the aforementioned units. The upper limit of the D+1 order local failure rate is calculated based on the D-order local failure rate and the D-1 order local failure rate. The upper limit of the D+1 order local failure rate and the D-order local failure rate are used to calculate the second estimate of the D-order system failure rate. The minimum value is selected from the interval formed by the first estimated failure rate of the D-order system and the second estimated failure rate of the D-order system. The minimum value is the asymptotic probability approximation.

[0007] In some embodiments, the unit failure rate and simultaneous failure rate are determined through the following steps: The digital circuit system is divided into multiple intermediate failure regions composed of multiple units, and samples are extracted from the intermediate failure regions to obtain the first sample set; Based on the subset simulation algorithm, the unit failure rate of all samples in the first sample set is calculated, and a first group of samples is generated based on the unit failure rate of all samples in the first sample set. All samples in the first group fall into the intermediate failure region. Based on the Metropolis algorithm, the first set of samples is used to generate a Markov chain Monte Carlo sample sequence, thus obtaining the Markov chain. Based on the subset simulation algorithm, the unit failure rate of each sample in the Markov chain is calculated; The simultaneous failure rate is obtained by linearly combining the unit failure rates and multiplying the resulting linearly combined unit failure rates.

[0008] In some embodiments, the method further includes calculating the confidence interval of the asymptotic probability approximation at a preset confidence level.

[0009] In some embodiments, calculating the confidence interval of the asymptotic probability approximation at a preset confidence level further includes: The logarithm of the unit failure rate is calculated based on the first estimate of the D-order system failure rate and the second estimate of the D-order system failure rate. Calculate the mean and variance estimates of the logarithm of the unit failure rate; A normal distribution function is established based on the mean estimate and the variance estimate, and the normal distribution function approximates the distribution interval of the mean estimate; The asymptotic probability approximation is calculated within a confidence interval of a preset confidence level based on the distribution interval.

[0010] In some embodiments, the calculation of the logarithm of the unit failure rate, including the mean estimate and variance estimate, further includes: When the first estimated failure rate of the D-order system is less than the second estimated failure rate of the D-order system, the mean estimated failure rate of the D-order system is calculated based on the logarithm. The mean estimated failure rate of the D-order system is numerically equal to the variance estimated failure rate of the D-order system. The variance estimated failure rate is used to evaluate the reliability of the mean estimated failure rate. Alternatively, when D is even, a mean estimate of order D is calculated based on the logarithm of D-1 and the logarithm of the unit failure rate. The mean estimate of order D is numerically equal to the variance estimate of order D, and the variance estimate is used to evaluate the reliability of the mean estimate.

[0011] In some embodiments, calculating the unit failure rate of each sample in the Markov chain based on the subset simulation algorithm further includes: Select samples from the first sample to form a sample subset; The sample failure rate is calculated based on the total number of samples in the sample subset and the total number of samples in the first sample set. Based on the Metropolis algorithm and the sample failure rate, a Markov chain Monte Carlo sample sequence is generated to obtain a Markov chain. The total number of samples in the Markov chain is equal to the number of units in the intermediate failure region. A subsample subset is selected from the samples contained in the Markov chain, and the samples in the subsample subset fall into the intermediate failure region; Based on the total number of samples in the sub-sample set and the total number of samples in the Markov chain, calculate the cell failure rate of the cells contained in the intermediate failure region. The unit failure rate of each sample in the Markov chain is calculated based on the unit failure rate of the units contained in the intermediate failure region.

[0012] Another embodiment of this application provides an apparatus for timing analysis of critical paths in digital circuits, comprising: The acquisition module is used to obtain the number of cells and the order D of the system-level failure rate in a digital circuit system. An estimation module is used to estimate the same number of unit failure rates and simultaneous failure rates as the number of unit levels. The unit failure rate is used to characterize the probability of a unit-level failure event occurring in the digital circuit, and the simultaneous failure rate is obtained by linearly combining all the unit failure rates. The first calculation module is used to calculate the D-order local failure rate and the D-1-order local failure rate based on the simultaneous failure rate. The D-order and D-1-order local failure rates are used to calculate the first estimate of the D-order system failure rate. The local space corresponding to the local failure rate includes multiple units. The second calculation module is used to calculate the upper limit of the D+1 order local failure rate based on the D-order local failure rate and the D-1 order local failure rate. The upper limit of the D+1 order local failure rate and the D-order local failure rate are used to calculate the second estimate of the D-order system failure rate. The selection module is used to select the minimum value from the interval formed by the first estimated value of the failure rate of the D-order system and the second estimated value of the failure rate of the D-order system, wherein the minimum value is an asymptotic probability approximation value.

[0013] In some embodiments, the estimation module includes: An extraction unit is used to divide a digital circuit system into multiple intermediate failure regions composed of multiple units, and extract samples from the intermediate failure regions to obtain a first sample set. The first generation unit is used to calculate the unit failure rate of all samples in the first sample set based on the subset simulation algorithm, and generate a first group of samples based on the unit failure rates of all samples in the first sample set, wherein all samples in the first group fall into the intermediate failure region. The second generation unit is used to generate a Markov chain Monte Carlo sample sequence from the first group of samples based on the Metropolis algorithm, so as to obtain a Markov chain. The first computing unit is used to calculate the unit failure rate of each sample in the Markov chain based on the subset simulation algorithm. The second calculation unit is used to perform a linear combination of the unit failure rates, and the product of the linearly combined unit failure rates is the simultaneous failure rate.

[0014] Another embodiment of this application provides a terminal device, including: At least one processor and memory; The memory is used to store program instructions; The processor is used to call and execute program instructions stored in the memory, so that the terminal device executes the digital circuit critical path timing analysis method as described above.

[0015] Another embodiment of this application provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the critical path timing analysis of a digital circuit as described in any of the preceding claims.

[0016] Another embodiment of this application provides a computer program product containing instructions that, when the computer program product is run on an electronic device, enable the electronic device to perform the digital circuit critical path timing analysis as described above.

[0017] The beneficial effects of this application are as follows: by estimating the unit failure rate and obtaining the simultaneous failure rate by linearly combining the unit failure rates, the purpose of associating unit components can be achieved; furthermore, by constructing a first estimate and a second estimate of the D-order system failure rate based on the simultaneous failure rate and the order, and selecting the minimum value from the first estimate and the second estimate of the D-order system failure rate as an asymptotic probability approximation, the system failure rate can be estimated. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a digital circuit critical path timing analysis method according to one or more embodiments of this application; Figure 2 A comparison of the computational efficiency of the Monte Carlo method and the algorithm of this application is presented. Figure 3 A comparison chart showing the failure rates of the Monte Carlo method, the traditional LF algorithm, and the algorithm proposed in this application. Detailed Implementation

[0020] To make the objectives, implementation methods and advantages of this application clearer, the exemplary implementation methods of this application will be clearly and completely described below with reference to the accompanying drawings of the exemplary embodiments of this application. Obviously, the described exemplary embodiments are only some embodiments of this application, and not all embodiments.

[0021] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0022] The terms "first," "second," "third," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities, and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms are interchangeable where appropriate.

[0023] The terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device that includes a range of components is not necessarily limited to all of the components that are clearly listed, but may include other components that are not clearly listed or that are inherent to such product or device.

[0024] The terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0025] like Figure 1The flowchart shown is a method for timing analysis of critical paths in digital circuits provided in this application. This method for timing analysis of critical paths in digital circuits is implemented through the following steps: In step 110, the number of units N in the digital circuit system and the order D of the preset system-level failure rate are obtained; In step 120, the same number of unit failure rates and simultaneous failure rates as the number of unit levels are estimated. The unit failure rate is used to characterize the probability of a unit-level failure event occurring in the digital circuit, and the simultaneous failure rate is the product of all unit failure rates after linear combination. Where the unit probability is expressed as Meanwhile, the failure rate is expressed as The efficient Hierarchical Subset Simulation (H-SUS) algorithm is based on the Hierarchical Subset Simulation (SUS) algorithm. It divides the whole into different layers, randomly samples each layer according to a specified ratio, and uses this algorithm to estimate... At the same time, it makes the samples more representative. H-SUS is an extension of SUS that approximates the overall failure rate based on a set of carefully defined probability events, thereby realizing the asymptotic probabilistic approximation method (APA).

[0026] In some embodiments, the calculation unit failure rate and simultaneous failure rate are achieved through the following steps: In step 210, the digital circuit system is divided into multiple intermediate failure regions composed of multiple units, and samples are extracted from the intermediate failure regions to obtain the first sample set. The probability of the intermediate failure region is expressed as: ,in , Representing the Units, This is the intermediate failure region; the first sample set includes... There are 1 sample, denoted as _ ... .

[0027] In step 220, based on the subset simulation algorithm, the unit failure rate of all samples in the first sample set is calculated, and a first group of samples is generated based on the unit failure rate of all samples. All samples in the first group fall into the intermediate failure region. The subset simulation algorithm is used to estimate the unit failure rate of all samples in the first sample set, where the first sample in the first sample set is represented as follows: When =1, the unit failure rate of the first sample is The first set of samples is generated based on the unit failure rate of all samples. The first set of samples is represented as follows: ,in , tThis represents the number of subsets. By defining the number of subsets, the failure rate of the sample can be calculated. The first group of samples all fall into the middle failure region. , represented as .

[0028] Due to different defined scenarios Indicates the first When one unit fails, the first The failure probability of each unit; when =1, satisfying It is also equal to the following Usage of .

[0029] Unit failure rate, It is a subset of points defined by the sample, and the performance of the study is located in the middle failure region. It is equivalent to replacing the original larger data sample with a smaller sample value to participate in the calculation, thus reducing the amount of computation.

[0030] In step 230, the first set of samples is used to generate a Markov chain Monte Carlo sample sequence based on the Metropolis algorithm to obtain the Markov chain; All samples in the Markov chain are represented as follows: ,in, .

[0031] In step 240, the unit failure rate of each sample in the Markov chain is calculated based on the subset simulation algorithm; In step 250, the cell failure rate for each sample in the Markov chain is calculated. The simultaneous failure rate is obtained by performing linear combinations and multiplying the failure rates of the units after the linear combinations. This can be expressed as a formula: in, Indicates the first Unit failure rate of each unit.

[0032] In some embodiments, the cell failure rate of each sample in the Markov chain is calculated based on a subset simulation algorithm, which is achieved through the following steps: In step 310, from the first sample set... , Indicates the total number of samples in the first sample set; In step 320, samples are selected from the first sample through transistor-level simulation to form a sample subset, which is represented as follows: The samples in the sample subset fall into the intermediate failure region. This represents the total number of samples in the sample subset; In step 330, the sample failure rate is calculated based on the total number of samples in the sample subset and the total number of samples in the first sample set; the first sample set includes There are 1 sample, denoted as _ ... Represents the total number of samples in the first sample set, when When =1, the sample failure rate Represented as: ; In step 340, samples are extracted from the intermediate failure region to obtain second and third sample sets, and sample subsets are selected from the second and third sample sets respectively. Calculations are then performed based on the sample sets and sample subsets. The sample failure rate at given time is used to generate a Markov chain Monte Carlo sample sequence based on the Metropolis algorithm and the sample failure rate, thus obtaining the Markov chain. The total number of samples in the Markov chain is [not specified in the original text]. It equals the number of samples in all sample sets; In step 350, a subsample subset is selected from the samples contained in the Markov chain. Samples in the subsample subset fall into the intermediate failure region; the subsample subset is represented as... , This represents the total number of samples in the sub-sample subset; using Markov chain rules for unit probability sampling can greatly reduce the amount of sampling data and improve computation speed.

[0033] In step 360, based on the total number of samples in the subsample subset and the total number of samples in the Markov chain, the cell failure rate of the cells contained in the intermediate failure region is calculated. , represented as:

[0034] In step 370, the cell failure rate of each sample in the Markov chain is calculated based on the cell failure rate of the cells contained in the intermediate failure region.

[0035] ; in, This indicates that you are interested in a specific performance characteristic of the cell, such as lifetime or performance. This indicates the properties of the performance, such as the failure rate corresponding to the lifetime. , Multiple independent variables can be considered.

[0036] when Substituting this into equation (7) yields the unit failure rate for all samples in the first sample set. .

[0037] In step 130, the D-order local failure rate and the D-1 order local failure rate are calculated based on the simultaneous failure rate. The D-order and D-1 order local failure rates are used to calculate the first estimate of the D-order system failure rate. The local space corresponding to the local failure rate includes multiple elements. D The local failure rate is expressed as , D- The first-order local failure rate is expressed as as well as D The first estimate of the failure rate of a first-order system is expressed as: .

[0038] Among them, based on simultaneous failure rate calculate Then based on First estimate of failure rate for D-order system N This represents the number of repeating units. The failure rate here is approximated by two linear functions, with coefficients ( N-D+1 ), ( ND )and D It is related to the number of repeating units in the order.

[0039] in, , , ..., , Indicates the first d Unit failure rate of each unit.

[0040] In step 140, the upper limit of the local failure rate of order D+1 is calculated based on the local failure rate of order D and the local failure rate of order D-1. The upper limit of the local failure rate of order D+1 and the local failure rate of order D are used to calculate the second estimate of the failure rate of order D system.

[0041] Wherein, the upper limit of the local failure rate of order D+1 is expressed as The second estimate of the failure rate of a D-order system is expressed as follows: The asymptotic probability approximation is expressed as: .

[0042] when D When it is an odd number,

[0043] when D When it is even, ; in, and It is P D+1 , respectively, are the upper limits when D is odd and even.

[0044] Then based on and calculate , .

[0045] In step 150, the first estimate of the failure rate of the D-order system is obtained. Second estimate of the failure rate of D-order system The minimum value is selected from the intervals formed; the minimum value is the asymptotic probability approximation. , represented as: .

[0046] In some embodiments, after determining the asymptotic probability approximation, the method further includes: calculating the confidence interval of the asymptotic probability approximation at a preset confidence level.

[0047] A confidence interval is an estimated interval for a population parameter constructed from a sample statistic. In statistics, a confidence interval for a probability sample is an interval estimate of a population parameter for that sample. A confidence interval shows the degree to which the true value of this parameter has a certain probability of falling around the measurement result; it gives the confidence level of the measured value of the measured parameter, i.e., the "probability" mentioned earlier.

[0048] In some embodiments, the confidence interval of the asymptotic probability approximation at a preset confidence level is calculated through the following steps: In step 410, the first estimate of the failure rate of the D-order system is calculated. Second estimate of the failure rate of D-order system Calculate the unit failure rate (expressed as) The logarithm of ) (represented as ).

[0049] In step 420, the mean estimate of the logarithm is calculated, expressed by the formula: ; express The normal distribution function has two values ​​that represent the logarithmic mean and variance mean calculated by H-SUS, respectively, reflecting the distribution of the data and verifying the reliability of the distribution.

[0050] By studying the logarithmic distribution of the unit failure rate, it can be approximated as a normal distribution. This represents the cell failure rate calculated using the H-SUS method.

[0051] ; in, ; Represents variance. It represents the number of Markov chains created, and also the number of samples that fall into the intermediate failure region. This represents the failure probability of the Markov chain;

[0052]

[0053] ; Where Q represents the number of samples, For indicator functions; This means that when a sample falls into the failure region, it is in a failure state with a failure probability of 1; otherwise, it is in a non-failure state.

[0054] In some embodiments, calculating the mean estimate of the logarithm further includes: When the first estimated failure rate of a D-order system is less than the second estimated failure rate of a D-order system, the mean estimate based on logarithm is expressed by the formula: if Calculated using formula (13) The mean estimate is expressed by the formula: ; Under the premise of satisfying formula (8), And log( )= At this time, the formula (13) is satisfied. The left side of the formula (13) represents the mean (subscript D, D) of the partial sampling of the D-order system, which is numerically equal to the variance of the D-order system (subscript D).

[0055] L and M represent the variables introduced in calculating the confidence interval, used to characterize the relationship between the failure rate and the mean. This is the mean estimate, where ν represents the variance estimate. The asterisk (*) represents the cell failure rate calculated using the H-SUS (Hierarchical Subset Simulation) method, and the variance estimate corresponding to this method is expressed as... In the formulas below, variables marked with an asterisk (*) also indicate that the variable was calculated using the H-SUS algorithm.

[0056] When D is even, calculate based on the logarithm and logarithm of D-1. The D-order mean estimate is calculated using formula (14); ; When D is odd ; In all cases except where the first estimated failure rate of a D-order system is less than the second estimated failure rate of a D-order system, and D is an even number, the variance estimate is approximately equal to the highest-order variance value, expressed by the formula: ≈ ; in, ; The variance, representing the sample failure rate, reflects the reliability of the data within a certain range. represent The upper limit.

[0057] A normal distribution function is established based on mean estimation and variance estimation, and the distribution interval of the approximate mean estimation is based on the normal distribution function; for Using normal distribution approximate distributed, Expressed using formula (16): ; By approximating the function using a normal distribution, prediction and analysis can be performed more conveniently.

[0058] Through normal distribution approximate distributed, S Representative system, Expressed using formulas (17)-(19): ; ; ; Through normal distribution approximate distributed, Expressed using formula (20): ； Through the normal distribution interval approximate distributed, Expressed using formulas (21) and (22): ;

[0059] 。

[0060] Based on distribution interval Calculating the confidence interval of the asymptotic probability approximation at a pre-set confidence level includes: if The pre-set reliability of 95% is calculated using formulas (23) and (24). Confidence intervals are determined by formulas (25) and (26), otherwise the confidence intervals with a pre-set confidence level of 95% are calculated. Confidence interval.

[0061] ; ; ; .

[0062] in, Approximation The two parameter values ​​after normal distribution Near is similar The two parameter values ​​after normal distribution.

[0063] The system failure rate represents the overall performance of the research object. Since a system is composed of multiple units and parts, there is a certain relationship between the system failure rate and the failure rate of each unit. The APA method approximates the overall failure rate by defining multiple failure events, greatly reducing the sampling and computational costs while maintaining a relatively high level of accuracy. The relaxed APA method is a derivation based on APA, which relaxes the partial failure rate of units to an upper bound. By estimating the unit failure rate and obtaining the simultaneous failure rate by linearly combining the unit failure rates, the purpose of associating unit components can be achieved. Furthermore, by constructing a first estimate and a second estimate of the D-order system failure rate based on the simultaneous failure rate and the order, and selecting the minimum value between the first estimate and the second estimate as an asymptotic probability approximation, the system failure rate can be estimated.

[0064] Figure 2 A comparison of the computational efficiency of the Monte Carlo method and the algorithm of this application is presented. Figure 3 A comparison chart showing the failure rates of the Monte Carlo method, the traditional LF algorithm, and the algorithm proposed in this application.

[0065] The Monte Carlo method is widely recognized as the most accurate simulation method in computational methods, such as... Figure 2 The diagram shows the change in computational cost between the Monte Carlo method and the method described in this application when calculating the same number of units. The Monte Carlo algorithm requires a particularly large amount of computation, which increases exponentially with the number of units, especially when calculating low-probability events. The computational cost increases exponentially with the number of samples. In contrast, the algorithm described in this paper uses a simple linear relationship between computational cost and the number of samples. Therefore, compared to the Monte Carlo method, the method described in this application significantly reduces the cost of simulation computation.

[0066] As shown in Figure 6, the algorithm in this application not only has a significantly lower computational cost than the Monte Carlo algorithm, but also achieves a computational accuracy very close to that of the Monte Carlo method, demonstrating excellent computational efficiency and accuracy. Compared with the traditional LF algorithm, both computational efficiency and accuracy have been greatly improved.

[0067] The LF algorithm (loop flattening method) ignores the correlation between units. Therefore, comparing the LF algorithm with the method in this application, it can be seen that the computational efficiency and accuracy of this application are greatly improved when calculating the system-level failure rate based on the correlation between units.

[0068] The Monte Carlo algorithm is essentially a completely random sampling algorithm, which has a very large computational load. However, its results are generally used as the sole standard for verifying the accuracy of other algorithms. Therefore, comparing the computational accuracy of the algorithm in this application with that of the Monte Carlo algorithm, as shown in Figure 6, the computational accuracy of the algorithm in this application is closer to that of the Monte Carlo method than that of the LF algorithm.

[0069] By selecting samples from all units in a digital circuit system using hierarchical subset simulation algorithm, subset simulation algorithm, and Metropolis algorithm, and then calculating asymptotic probability approximations based on the samples, the workload is reduced compared to calculating based on all samples. Therefore, the method in this application can independently simulate system faults with a large number of random variables, reduce computational costs, and improve operating efficiency.

[0070] In some embodiments, this application also provides an apparatus for timing analysis of critical paths in digital circuits, comprising: The acquisition module is used to obtain the number of cells and the order D of the system-level failure rate in a digital circuit system. An estimation module is used to estimate the same number of unit failure rates and simultaneous failure rates as the number of unit levels. The unit failure rate is used to characterize the probability of a unit-level failure event occurring in the digital circuit, and the simultaneous failure rate is obtained by linearly combining all the unit failure rates. The first calculation module is used to calculate the D-order local failure rate and the D-1-order local failure rate based on the simultaneous failure rate. The D-order and D-1-order local failure rates are used to calculate the first estimate of the D-order system failure rate. The local space corresponding to the local failure rate includes multiple units. The second calculation module is used to calculate the upper limit of the D+1 order local failure rate based on the D-order local failure rate and the D-1 order local failure rate. The upper limit of the D+1 order local failure rate and the D-order local failure rate are used to calculate the second estimate of the D-order system failure rate. The selection module is used to select the minimum value from the interval formed by the first estimated value of the failure rate of the D-order system and the second estimated value of the failure rate of the D-order system, wherein the minimum value is an asymptotic probability approximation value.

[0071] In some embodiments, the estimation module includes: An extraction unit is used to divide a digital circuit system into multiple intermediate failure regions composed of multiple units, and extract samples from the intermediate failure regions to obtain a first sample set. The first generation unit is used to calculate the unit failure rate of all samples in the first sample set based on the subset simulation algorithm, and generate a first group of samples based on the unit failure rates of all samples in the first sample set, wherein all samples in the first group fall into the intermediate failure region. The second generation unit is used to generate a Markov chain Monte Carlo sample sequence from the first group of samples based on the Metropolis algorithm, so as to obtain a Markov chain. The first computing unit is used to calculate the unit failure rate of each sample in the Markov chain based on the subset simulation algorithm. The second calculation unit is used to perform a linear combination of the unit failure rates, and the product of the linearly combined unit failure rates is the simultaneous failure rate.

[0072] In some embodiments, this application also provides a terminal device, including: At least one processor and memory; The memory is used to store program instructions; The processor is used to call and execute program instructions stored in the memory, so that the terminal device executes the above-described digital circuit critical path timing analysis method.

[0073] In some embodiments, this application also provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the above-described digital circuit critical path timing analysis.

[0074] In some embodiments, this application also provides a computer program product containing instructions that, when run on an electronic device, enable the electronic device to perform the above-described digital circuit critical path timing analysis.

[0075] For ease of explanation, the above description has been provided in conjunction with specific embodiments. However, the discussion in some embodiments above is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. Various modifications and variations can be obtained based on the above teachings. The selection and description of the above embodiments are for the purpose of better explaining the principles and practical applications, thereby enabling those skilled in the art to better utilize the embodiments and various different variations of the embodiments suitable for specific application considerations.

Claims

1. A timing analysis method for critical paths in digital circuits, characterized in that, The method includes: Obtain the number of cells and the order D of the system-level failure rate in a digital circuit system; Estimate the same number of cell failure rates and simultaneous failure rates as the number of cell levels, wherein the cell failure rate is used to characterize the probability of a cell-level failure event occurring in the digital circuit, and the simultaneous failure rate is obtained by linearly combining all the cell failure rates. Based on the simultaneous failure rate, calculate the D-order local failure rate and the D-1-order local failure rate. The D-order and D-1-order local failure rates are used to calculate the first estimate of the D-order system failure rate. The local space corresponding to the local failure rate includes multiple units. The upper limit of the D+1 order local failure rate is calculated based on the D-order local failure rate and the D-1 order local failure rate. The upper limit of the D+1 order local failure rate and the D-order local failure rate are used to calculate the second estimate of the D-order system failure rate. The minimum value is selected from the interval formed by the first estimated failure rate of the D-order system and the second estimated failure rate of the D-order system, and the minimum value is the asymptotic probability approximation value. The unit failure rate and simultaneous failure rate are determined through the following steps: The digital circuit system is divided into multiple intermediate failure regions composed of multiple units, and samples are extracted from the intermediate failure regions to obtain the first sample set; Based on the subset simulation algorithm, the unit failure rate of all samples in the first sample set is calculated, and a first group of samples is generated based on the unit failure rate of all samples in the first sample set. All samples in the first group fall into the intermediate failure region. Based on the Metropolis algorithm, the first set of samples is used to generate a Markov chain Monte Carlo sample sequence, thus obtaining the Markov chain. Based on the subset simulation algorithm, the unit failure rate of each sample in the Markov chain is calculated; The simultaneous failure rate is obtained by linearly combining the unit failure rates and multiplying the resulting linearly combined unit failure rates.

2. The timing analysis method for critical paths in digital circuits as described in claim 1, characterized in that, The method further includes calculating the confidence interval of the asymptotic probability approximation at a preset confidence level.

3. The timing analysis method for critical paths in digital circuits as described in claim 2, characterized in that, The calculation of the confidence interval of the asymptotic probability approximation at a preset confidence level further includes: The logarithm of the unit failure rate is calculated based on the first estimate of the D-order system failure rate and the second estimate of the D-order system failure rate. Calculate the mean and variance estimates of the logarithm of the unit failure rate; A normal distribution function is established based on the mean estimate and the variance estimate, and the normal distribution function approximates the distribution interval of the mean estimate; The asymptotic probability approximation is calculated within a confidence interval of a preset confidence level based on the distribution interval.

4. The timing analysis method for critical paths in digital circuits as described in claim 3, characterized in that, The calculation of the logarithm of the unit failure rate, including the mean estimate and variance estimate, further includes: When the first estimated failure rate of the D-order system is less than the second estimated failure rate of the D-order system, the mean estimated failure rate of the D-order system is calculated based on the logarithm. The mean estimated failure rate of the D-order system is numerically equal to the variance estimated failure rate of the D-order system. The variance estimated failure rate is used to evaluate the reliability of the mean estimated failure rate. Alternatively, when D is even, a mean estimate of order D is calculated based on the logarithm of D-1 and the logarithm of the unit failure rate. The mean estimate of order D is numerically equal to the variance estimate of order D, and the variance estimate is used to evaluate the reliability of the mean estimate.

5. The timing analysis method for critical paths in digital circuits as described in claim 1, characterized in that, Based on the subset simulation algorithm, the unit failure rate of each sample in the Markov chain is calculated, further including: Select samples from the first sample to form a sample subset; The sample failure rate is calculated based on the total number of samples in the sample subset and the total number of samples in the first sample set. Based on the Metropolis algorithm and the sample failure rate, a Markov chain Monte Carlo sample sequence is generated to obtain a Markov chain. The total number of samples in the Markov chain is equal to the number of units in the intermediate failure region. A subsample subset is selected from the samples contained in the Markov chain, and the samples in the subsample subset fall into the intermediate failure region; Based on the total number of samples in the sub-sample set and the total number of samples in the Markov chain, calculate the cell failure rate of the cells contained in the intermediate failure region. The unit failure rate of each sample in the Markov chain is calculated based on the unit failure rate of the units contained in the intermediate failure region.

6. An apparatus for timing analysis of critical paths in digital circuits, characterized in that, include: The acquisition module is used to obtain the number of cells and the order D of the system-level failure rate in a digital circuit system. An estimation module is used to estimate the same number of cell failure rates and simultaneous failure rates as the number of cell levels. The cell failure rate is used to characterize the probability of a cell-level failure event occurring in a digital circuit, and the simultaneous failure rate is obtained by linearly combining all the cell failure rates. The first calculation module is used to calculate the D-order local failure rate and the D-1-order local failure rate based on the simultaneous failure rate. The D-order and D-1-order local failure rates are used to calculate the first estimate of the D-order system failure rate. The local space corresponding to the local failure rate includes multiple units. The second calculation module is used to calculate the upper limit of the D+1 order local failure rate based on the D-order local failure rate and the D-1 order local failure rate. The upper limit of the D+1 order local failure rate and the D-order local failure rate are used to calculate the second estimate of the D-order system failure rate. The selection module is used to select the minimum value from the interval formed by the first estimated value of the failure rate of the D-order system and the second estimated value of the failure rate of the D-order system, wherein the minimum value is an asymptotic probability approximation. The estimation module includes: An extraction unit is used to divide a digital circuit system into multiple intermediate failure regions composed of multiple units, and extract samples from the intermediate failure regions to obtain a first sample set. The first generation unit is used to calculate the unit failure rate of all samples in the first sample set based on the subset simulation algorithm, and generate a first group of samples based on the unit failure rates of all samples in the first sample set, wherein all samples in the first group fall into the intermediate failure region. The second generation unit is used to generate a Markov chain Monte Carlo sample sequence from the first group of samples based on the Metropolis algorithm, so as to obtain a Markov chain. The first computing unit is used to calculate the unit failure rate of each sample in the Markov chain based on the subset simulation algorithm. The second calculation unit is used to perform a linear combination of the unit failure rates, and the product of the linearly combined unit failure rates is the simultaneous failure rate.

7. A terminal device, characterized in that, include: At least one processor and memory; The memory is used to store program instructions; The processor is configured to call and execute program instructions stored in the memory to cause the terminal device to perform the digital circuit critical path timing analysis method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a computer, cause the computer to perform the digital circuit critical path timing analysis as described in any one of claims 1-5.

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