Memory device and method of operating a memory device

Abstract

Embodiments of the present disclosure relate to a memory device and a method of operating a memory device. The present technology relates to an electronic device. According to the present technology, a memory device can include memory cells connected to a plurality of word lines, respectively; a peripheral circuit configured to perform a read operation of reading data stored in a selected memory cell connected to a selected word line among the memory cells; and a read operation controller configured to control the peripheral circuit to: apply a pass voltage to an adjacent word line adjacent to the selected word line during the read operation; discharge the pass voltage to a target pass voltage lower than the pass voltage after a predetermined time elapses; and obtain the data stored in the selected memory cell through a bit line connected to the selected memory cell after a target read time elapses after the voltage applied to the adjacent word line is discharged to the target pass voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0123530, filed on September 15, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to electronic devices, and more particularly to memory devices and methods of operating memory devices. Background Technology

[0004] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device that stores the data therein and a memory controller that controls the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are devices that store data only while powered on and lose the stored data when power is off. Volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] Non-volatile memory devices are devices that do not lose data even when power is off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0007] According to one embodiment of this disclosure, a memory device may include a plurality of memory cells, peripheral circuitry, and a read operation controller. The plurality of memory cells are respectively connected to a plurality of word lines. The peripheral circuitry is configured to perform a read operation to read data stored in a selected memory cell among the plurality of memory cells. The selected memory cell is connected to a selected word line among the plurality of word lines. The read operation controller is configured to control the peripheral circuitry to: apply a voltage to an adjacent word line among the plurality of word lines adjacent to the selected word line during a read operation; discharge the voltage to a target voltage below the voltage after a predetermined time; and after the voltage applied to the adjacent word line is discharged to the target voltage, obtain the data stored in the selected memory cell through a bit line connected to the selected memory cell after a target read time.

[0008] According to one embodiment of this disclosure, the storage device may include a memory controller and a memory device. The memory controller is configured to output a read command for a selected memory cell and an address for a selected word line connected to the selected memory cell. The memory device is configured to: apply a pass voltage to an adjacent word line adjacent to the selected word line by receiving the read command and the address corresponding to the read command; discharge the pass voltage to a target pass voltage with a step voltage smaller than the pass voltage after a predetermined time; and after the voltage applied to the adjacent word line is discharged to the target pass voltage, perform a disconnect read operation to obtain data stored in the selected memory cell through a bit line connected to the selected memory cell after a target read time.

[0009] According to one embodiment of this disclosure, a method for an electronic device to repeatedly perform read operations to read data stored in a selected memory cell connected to a selected word line among a plurality of word lines in a target memory block among a plurality of memory blocks may include: applying a voltage to a word line adjacent to the selected word line; decreasing the voltage by a step voltage at predetermined intervals until the voltage reaches a target voltage; after the voltage reaches the target voltage and a predetermined target read time has elapsed, sensing the potential of a bit line connected to the selected memory cell connected to the selected word line; and determining whether the read operation has succeeded or failed by comparing the number of erroneous bits of data read from the selected memory cell with the number of correctable erroneous bits.

[0010] According to one embodiment of this disclosure, a method for an electronic device to perform a read operation to read data stored in a selected memory cell connected to a selected word line among a plurality of word lines in a target memory block among a plurality of memory blocks may include: applying a voltage to a word line adjacent to the selected word line; discharging the voltage to a target voltage that is a step voltage smaller than the voltage; after a predetermined target read time, sensing the potential of a bit line connected to the selected memory cell connected to the selected word line; and determining whether the read operation has succeeded or failed by comparing the number of erroneous bits of data read from the selected memory cell with the number of correctable erroneous bits. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a memory system according to one embodiment.

[0012] Figure 2 It's a diagram. Figure 1 A diagram illustrating the structure of a memory device.

[0013] Figure 3 It's a diagram. Figure 2 A diagram illustrating one embodiment of a memory cell array.

[0014] Figure 4 It's a diagram. Figure 2 The circuit diagram of any memory block BLKa among memory blocks BLK1 to BLKz.

[0015] Figure 5 It's a diagram. Figure 2 A circuit diagram of another embodiment of any memory block BLKb among memory blocks BLK1 to BLKz.

[0016] Figure 6 This is a block diagram illustrating a read operation for describing the configuration and operation of a memory controller and a memory device according to one embodiment.

[0017] Figure 7 It is illustrated in the diagram. Figure 4 A diagram showing the state of a specific character line being broken.

[0018] Figure 8 The diagram illustrates the reference point. Figure 7 A diagram illustrating a scenario where a read operation fails when a specific word line is disconnected.

[0019] Figure 9 It is a diagram illustrating the voltage applied over time to the selected word line and the word lines adjacent to the selected word line during a read operation.

[0020] Figure 10 This diagram illustrates a scenario where a read failure occurs when the selected word line is disconnected during a read operation.

[0021] Figure 11 This is a diagram illustrating a read operation for retrieving data stored in a memory cell connected to a selected word line, according to one embodiment.

[0022] Figure 12 This is a diagram illustrating the voltage applied to adjacent word lines over time during a read operation according to one embodiment.

[0023] Figure 13 This is a diagram illustrating the change in potential over time in a selected word line during a read operation according to one embodiment.

[0024] Figure 14 The diagram illustrates a disconnected read information storage device according to one embodiment.

[0025] Figure 15 This is a diagram illustrating a bad block information storage device according to one embodiment.

[0026] Figure 16 This is a flowchart illustrating the operation of a storage device according to one embodiment.

[0027] Figure 17 This is a flowchart illustrating a read operation according to one embodiment.

[0028] Figure 18 It's a diagram. Figure 1 A diagram illustrating another embodiment of the memory controller.

[0029] Figure 19 This is a block diagram illustrating a memory card system for applying a storage device according to an embodiment of the present disclosure.

[0030] Figure 20 This is a block diagram illustrating a solid-state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0031] Figure 21 This is a block diagram illustrating a user system that applies a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0032] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are for illustrative purposes only. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0033] The present disclosure will be described in detail below with reference to the accompanying drawings.

[0034] One embodiment of this disclosure provides a memory device that, when a read failure occurs during a read operation on the memory device, recovers data stored in the memory cell where the read failure occurred.

[0035] According to this technology, in one embodiment, when a read failure occurs during a read operation on the memory device, the memory device can perform an operation to recover the data stored in the memory cell where the read failure occurred.

[0036] Figure 1 This is a block diagram illustrating a memory system according to one embodiment.

[0037] refer to Figure 1Storage device 50 may include memory device 100 and memory controller 200 for controlling the operation of memory device. Storage device 50 is a device that stores data under the control of host 300, such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0038] Storage device 50 can be manufactured as one of various types of storage devices depending on the host interface used as a communication method with host 300. For example, storage device 50 can be configured as any of various types of storage devices, such as SSDs, multimedia cards in the form of MMC, eMMC, RS-MMC, or micro-MMC, secure digital cards in the form of SD, mini-SD, or micro-SD, Universal Serial Bus (USB) storage devices, Universal Flash Memory (UFS) devices, PCMCIA card storage devices, Peripheral Component Interconnect (PCI) card storage devices, PCI express (PCI-E) card storage devices; Compact Flash Memory (CF) cards; smart media cards; and memory sticks.

[0039] The storage device 50 can be manufactured in any of a variety of packages. For example, the storage device 50 can be manufactured in any of the following package types: POP (Package-on-Package), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-on-Package (WFP), and Wafer-on-Stack (WSP).

[0040] Memory device 100 can store data. Memory device 100 operates under the control of memory controller 200. Memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A memory block may include a plurality of pages. In one embodiment, a page may be a unit for storing data in memory device 100 or retrieving data stored in memory device 100. A memory block may be a unit for erasing data. In one embodiment, the memory device 100 may be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), a Low Power Double Data Rate 4 (LPDDR4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, a Low Power DDR (LPDDR) SDRAM, a Rambus Dynamic Random Access Memory (RDRAM), a NAND flash memory, a Vertical NAND flash memory, a NOR flash memory, a Resistive Random Access Memory (ReRAM), a Phase Change Random Access Memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), a Spin-Transfer Torque Random Access Memory (STT-RAM), etc. For ease of description in this specification, it is assumed that the memory device 100 is a NAND flash memory.

[0041] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access address-selected regions of the memory cell array. That is, memory device 100 can perform operations instructed by commands on address-selected regions. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, memory device 100 can program data into the address-selected region. During a read operation, memory device 100 can read data from the address-selected region. During an erase operation, memory device 100 can erase data stored in the address-selected region.

[0042] The memory controller 200 controls the overall operation of the storage device 50.

[0043] When power is supplied to storage device 50, memory controller 200 can execute firmware (FW). When storage device 100 is a flash memory device, memory controller 200 can operate firmware such as flash translation layer (FTL) for controlling communication between host 300 and storage device 100.

[0044] In one embodiment, the memory controller 200 may receive data and logical block addresses (LBAs) from the host 300 and translate the LBAs into physical block addresses (PBAs), which indicate the addresses of memory cells included in the memory device 100 in which data will be stored.

[0045] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations in response to requests from the host 300. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, a PBA, and data. During a reading operation, the memory controller 200 can provide the memory device 100 with read commands and a PBA. During an erasing operation, the memory controller 200 can provide the memory device 100 with erase commands and a PBA.

[0046] In one embodiment, the memory controller 200 can generate and transmit programming commands, addresses, and data to the memory device 100 without a request from the host 300. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 to perform background operations, such as programming operations for wear leveling and programming operations for garbage collection.

[0047] In one embodiment, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving method to improve operational performance.

[0048] The host 300 can communicate with the storage device 50 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Away DIMM (LRDIMM).

[0049] Figure 2 It's a diagram. Figure 1 A diagram illustrating the structure of a memory device.

[0050] refer to Figure 2The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130. The control logic 130 may be implemented in hardware, software, or a combination of both. For example, the control logic 130 may be control logic circuitry that operates according to an algorithm and / or executes control logic code.

[0051] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to read and write circuitry 123 via bit lines BL1 to BLm. Each memory block in the multiple memory blocks BLK1 to BLKz includes multiple memory cells. As an embodiment, the multiple memory cells are non-volatile memory cells. Memory cells connected to the same word line among the multiple memory cells can be defined as a physical page. That is, the memory cell array 110 consists of multiple pages.

[0052] Each memory cell in the memory cell of the memory device 100 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0053] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124, and a sensing circuit 126.

[0054] Peripheral circuitry 120 drives memory cell array 110. For example, peripheral circuitry 120 can drive memory cell array 110 to perform programming operations, read operations, and erase operations.

[0055] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to one embodiment of this disclosure, word lines may include normal word lines and dummy word lines. According to one embodiment of this disclosure, row lines RL may also include pipe select lines.

[0056] Address decoder 121 is configured to operate in response to control by control logic 130. Address decoder 121 receives address ADDR from control logic 130.

[0057] Address decoder 121 is configured to decode the block address of the received address ADDR. Address decoder 121 selects at least one memory block among memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 is configured to decode the row address of the received address ADDR. Address decoder 121 can select at least one word line of the selected memory block by applying an operating voltage Vop provided from voltage generator 122 to at least one word line.

[0058] During programming operations, address decoder 121 can apply a programming voltage to the selected word lines and a programming pass voltage with a level lower than the programming voltage to the unselected word lines. During programming verification operations, address decoder 121 can apply a verification voltage to the selected word lines and a verification pass voltage with a level higher than the verification voltage to the unselected word lines.

[0059] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and apply a read pass voltage greater than the read voltage to the unselected word line.

[0060] According to one embodiment of this disclosure, the erase operation of the memory device 100 is performed on a block-by-block basis. The address ADDR input to the memory device 100 during the erase operation includes the block address. The address decoder 121 can decode the block address and select a memory block based on the decoded block address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0061] According to one embodiment of this disclosure, address decoder 121 can be configured to decode the column address of the transmitted address ADDR. The decoded column address can be transmitted to read and write circuitry 123. As an example, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0062] Voltage generator 122 is configured to generate multiple operating voltages Vop using an external power supply voltage provided to memory device 100. Voltage generator 122 operates in response to control of control logic 130.

[0063] As one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 is used as the operating voltage of memory device 100.

[0064] As one embodiment, voltage generator 122 can generate multiple voltages using an external power supply voltage or an internal power supply voltage. Voltage generator 122 can be configured to generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple non-select read voltages.

[0065] In order to generate multiple voltages with different voltage levels, voltage generator 122 may include multiple pump capacitors that receive internal voltages and selectively activate the multiple pump capacitors in response to control logic 130 to generate multiple voltages.

[0066] The generated voltages can be provided to the memory cell array 110 by the address decoder 121.

[0067] The read and write circuit 123 includes first to m-th page buffers PB1 to PBm. The first to m-th page buffers PB1 to PBm are respectively connected to the memory cell array 110 via first to m-th bit lines BL1 to BLm. The first to m-th page buffers PB1 to PBm operate in response to the control of the control logic 130.

[0068] The buffers PB1 to PBm, which are the first to m pages, communicate with the data input / output circuit 124 to receive the data DATA to be stored. During programming, the buffers PB1 to PBm, which are the first to m pages, receive the data DATA to be stored through the data input / output circuit 124 and the data line DL.

[0069] During programming operations, when a programming voltage is applied to the selected word line, the first to m-th page buffers PB1 to PBm can transfer the data DATA to be stored (i.e., the data DATA received via the data input / output circuit 124) to the selected memory cell via bit lines BL1 to BLm. The memory cell of the selected page is programmed according to the transferred data DATA. Memory cells connected to the bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to the bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, the first to m-th page buffers PB1 to PBm read the data DATA stored in the memory cell from the selected memory cell via bit lines BL1 to BLm.

[0070] During a read operation, the read and write circuit 123 can read data DATA from the memory cell of the selected page via bit lines BL1 to BLm and store the read data DATA in the first to m-th page buffers PB1 to PBm.

[0071] During the erase operation, the read and write circuitry 123 can float bit lines BL1 to BLm. As one embodiment, the read and write circuitry 123 may include column select circuitry.

[0072] The data input / output circuit 124 is connected to the first to m-th page buffers PB1 to PBm via data lines DL. The data input / output circuit 124 operates in response to the control logic 130.

[0073] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 receives the data DATA to be stored from an external controller (not shown). During read operations, the data input / output circuit 124 outputs the data DATA transferred from the first to the m-th page buffers PB1 to PBm included in the read and write circuit 123 to the external controller.

[0074] During a read or verification operation, the sensing circuit 126 may generate a reference current in response to the signal of the enable bit VRYBIT generated by the control logic 130, and may compare the sensed voltage VPB received from the read and write circuit 123 with the reference voltage generated by the reference current to output a pass signal PASS or a failure signal FAIL to the control logic 130.

[0075] In one embodiment, the sensing circuit 126 may include a current sensing circuit that counts the number of failure bits, which is the number of programming failure units in the target unit.

[0076] Control logic 130 can be connected to address decoder 121, voltage generator 122, read and write circuitry 123, data input / output circuitry 124, and sensing circuitry 126. Control logic 130 can be configured to control all operations of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0077] Control logic 130 can generate various signals to control peripheral circuitry 120 in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, address ADDR, read and write circuit control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, address ADDR to address decoder 121, read and write control signal PBSIGNALS to read and write circuitry 123, and enable bit VRYBIT to sensing circuitry 126. Additionally, control logic 130 can determine whether the verification operation passed or failed in response to pass signal PASS or failure signal FAIL output by sensing circuitry 126.

[0078] Figure 3 It's a diagram. Figure 2 A diagram illustrating one embodiment of a memory cell array.

[0079] refer to Figure 3 The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged along the +X, +Y, and +Z directions. (Reference) Figure 4 The structure of each memory block is described in more detail.

[0080] Figure 4 It's a diagram. Figure 2 The circuit diagram of any memory block BLKa among memory blocks BLK1 to BLKz.

[0081] refer to Figure 4 The memory block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. As an example, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m can be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged along the row direction (i.e., the +X direction). Figure 4 In this diagram, two unit strings are arranged along the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged along the column direction.

[0082] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0083] The selection transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. As one embodiment, each of the selection transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. As one embodiment, pillars for providing the channel layer may be provided in each cell string. As one embodiment, pillars for providing at least one of the channel layer, tunneling insulating film, charge storage film, and barrier insulating film may be provided in each cell string.

[0084] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0085] As one embodiment, the source selection transistors of cell strings arranged in the same row are connected to source selection lines extending along the row direction, and the source selection transistors of cell strings arranged in different rows are connected to different source selection lines. Figure 4 In the first row, the source selection transistors CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0086] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0087] The first to nth memory cells MC1 to MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0088] The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp are arranged sequentially in the direction opposite to the +Z direction and are connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th to nth memory cells MCp+1 to MCn are arranged sequentially in the +Z direction and are connected in series between the channel transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn are connected to each other through the channel transistor PT. The gates of the first to nth memory cells MC1 to MCn in each cell string are respectively connected to the first to nth word lines WL1 to WLn.

[0089] The gate of the pipe transistor PT in each cell string is connected to the pipe line PL.

[0090] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0091] The cell strings arranged in the column direction are connected to bit lines extending in the column direction. Figure 4 In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0092] In a row-oriented cell string, memory cells connected to the same word line constitute a page. For example, in the cell strings CS11 to CS1m of the first row, memory cells connected to the first word line WL1 constitute one page. In the cell strings CS21 to CS2m of the second row, memory cells connected to the first word line WL1 constitute another page. A cell string arranged in a row direction can be selected by selecting either the drain select line DSL1 or DSL2. A page of the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0093] Figure 5 It's a diagram. Figure 2 A circuit diagram of another embodiment of any memory block BLKb among memory blocks BLK1 to BLKz.

[0094] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. Additionally, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the even-numbered bit lines, and odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the odd-numbered bit lines accordingly.

[0095] As one embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. With more dummy memory cells provided, the reliability of operation on the memory block BLKb is improved; however, the size of the memory block BLKb increases. With fewer memory cells provided, the size of the memory block BLKb can be reduced; however, the reliability of operation on the memory block BLKb decreases.

[0096] To efficiently control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cells can have the desired threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0097] Figure 6 This is a block diagram illustrating a read operation for describing the configuration and operation of a memory controller and a memory device according to one embodiment.

[0098] Storage device 50 may include memory device 100 and memory controller 200 for controlling memory device 100.

[0099] The memory controller 200 may include an operation controller 210, an error correction circuit 220, and a bad block information storage device 230.

[0100] The operation controller 210 can control the operation of the memory device 100. The operation controller 210 can control the memory device 100 to perform read operations to read data stored in memory cells included in the memory device 100. In one embodiment, the read operation may include a normal read operation and a disconnect read operation.

[0101] A normal read operation can be an operation that uses a preset default read voltage to read data stored in a memory cell.

[0102] A disconnect read operation is a read operation performed when a normal read operation fails. A disconnect read operation can be an operation that reads data stored in a memory cell connected to the selected word line when the selected word line corresponding to the address to be read is in a disconnected state.

[0103] Operation controller 210 may provide a Normal Read command (CMD) to memory device 100 during a normal read operation. Operation controller 210 may also provide an Open Read command (CMD) to memory device 100 during a disconnect read operation. In one embodiment, when a normal read operation fails, operation controller 210 may control memory device 100 to perform a disconnect read operation. When a normal read operation fails, operation controller 210 may provide an Open Read command (CMD) to memory device 100.

[0104] The operation controller 210 can provide the memory device 100 with a Read Time Change command (CMD). The Read Time Change command (CMD) can be a command that increments the target read time by a step read time during a disconnected read operation.

[0105] In response to the Normal Read CMD command, memory device 100 can read data stored in a memory cell connected to the selected word line. Memory device 100 can then provide the read data to memory controller 200.

[0106] In response to the Open Read CMD command, memory device 100 can read data stored in a memory cell connected to the selected word line. Memory device 100 can then provide the read data to memory controller 200.

[0107] Error correction circuit 220 can determine the number of error bits included in the data received from memory device 100. Error correction circuit 220 can decode page data according to error correction codes.

[0108] Specifically, when the data received from the memory device 100 includes a preset number or more error bits, the error correction circuit 220 can determine that the read operation on the selected memory cell has failed. When the data received from the memory device 100 includes fewer than the preset number of error bits, the error correction circuit 220 can determine that the read operation on the selected memory cell has succeeded.

[0109] In one embodiment, error correction circuit 220 may provide operation controller 210 with information regarding whether a read operation on a selected memory cell has succeeded or failed.

[0110] The bad block information storage device 230 can store information related to bad blocks among the memory blocks included in the memory device 100. A bad block can refer to a memory block in which read or program operations on the corresponding memory block are restricted.

[0111] In one embodiment, the bad block information storage device 230 can receive information from the operation controller 210 relating to a target memory block including the selected memory cell, and set the target memory block as a bad block.

[0112] The memory device 100 may include a read operation controller 140. The read operation controller 140 may include a read voltage controller 140a, a disconnect read information storage device 140b, and a page buffer controller 140c.

[0113] The read operation controller 140 can respond to the Open Read CMD command from the memory controller 200 to control the peripheral circuitry to read data stored in the memory cell connected to the selected word line.

[0114] Specifically, the read operation controller 140 can control the peripheral circuitry to apply a voltage to a word line adjacent to the selected word line. After a predetermined time has elapsed since the voltage was applied, the read operation controller 140 can control the peripheral circuitry to discharge the voltage to a target voltage. After the voltage applied to the adjacent word line has discharged to the target voltage, the read operation controller 140 can control the peripheral circuitry to retrieve the data stored in the selected memory cell via a bit line connected to the selected memory cell after a target read time has elapsed. As used herein, the term "predetermined" (such as "predetermined time") refers to a parameter whose value is determined before it is used in a process or algorithm. In some embodiments, the parameter value is determined before the process or algorithm begins. In other embodiments, the parameter value is determined during the process or algorithm but before it is used in the process or algorithm.

[0115] When a read disconnect operation fails, the read operation controller 140 can receive a Read Time Change command (CMD) from the memory controller 200. In response to the Read Time Change command (CMD), the read operation controller 140 can increment the target read time by a step read time. The read operation controller 140 can also control the peripheral circuitry to increment the target read time by the step read time and execute the read disconnect operation.

[0116] In response to the Open Read CMD command from the memory controller 200, the read operation controller 140 can control the peripheral circuitry to repeatedly execute the open read operation until the read operation on the selected memory cell is successful.

[0117] The read voltage controller 140a can control the voltage applied to multiple word lines included in the memory device.

[0118] Specifically, the read voltage controller 140a can determine the magnitude of the pass voltage applied to the adjacent word line adjacent to the selected word line based on the pass voltage magnitude information stored in the disconnect read information storage device 140b. The read voltage controller 140a can determine the magnitude of the target pass voltage based on the pass voltage magnitude information stored in the disconnect read information storage device 140b.

[0119] The read voltage controller 140a can determine the time when the pass voltage is applied to the adjacent word line based on the pass voltage timing information stored in the disconnect read information storage device 140b.

[0120] The disconnect read information storage device 140b can store information related to the amplitude of the voltage applied to the word line adjacent to the selected word line. The disconnect read information storage device 140b can also store information related to the duration of the voltage applied to the word line adjacent to the selected word line.

[0121] Disconnecting the read information storage device 140b can store read time information, which is information related to the time during which the page buffer controller 140c senses the potential of the bit line connected to the selected memory cell. Specifically, the read time information may include target read time information and step read time information. The target read time information and step read time information will be referred to later. Figures 12 to 13 Describe it.

[0122] Page buffer controller 140c can control peripheral circuitry to sense the potential of bit lines connected to multiple memory cells during a read operation. In one embodiment, page buffer controller 140c can sense the potential of a bit line connected to a selected memory cell after a target read time has elapsed following the discharge of the pass voltage applied to an adjacent word line to a target pass voltage.

[0123] Figure 7 It is illustrated in the diagram. Figure 4 A diagram showing the state of a specific character line being broken.

[0124] A memory device can perform a read operation on a selected memory cell in response to a read command provided by the memory controller. The read operation can be performed on a page-by-page basis. Multiple memory cells included in a page can be connected to the same word line. During the read operation, a read voltage can be applied to the word line connected to the selected memory cell. A voltage can also be applied to the word line connected to the unselected memory cell.

[0125] The read voltage and pass voltage can be determined by a reference. Figure 2The voltage generated by the voltage generator 122 is described. Under the control of the address decoder, the generated read voltage and pass voltage can be provided to the word line of the selected memory block. At this time, due to various reasons, an open state may occur in which the connection between the address decoder and the word line of the selected memory block is severed. The voltage to be applied may not be provided to the word line in the open state. Therefore, even if the selected memory cell is in the erase state E, the selected memory cell may be read as the programmable state P, or even if the selected memory cell is in the programmable state P, the selected memory cell may be read as the erase state E. As a result, a read operation on a page including the selected memory cell may be determined to fail. In one embodiment, the severing of the word line between the address decoder and the selected memory block may result in an open circuit. In one embodiment, the open state in the word line between the address decoder and the selected memory block may be referred to as an open circuit.

[0126] Figure 8 The diagram illustrates the reference point. Figure 7 A diagram illustrating a scenario where a read operation fails when a specific word line is disconnected or in a disconnected state.

[0127] The read voltage can be a voltage used to read data stored in a selected memory cell. For example, in the case of SLC, the read voltage can be a voltage used to determine whether a threshold voltage Vth for the selected memory cell is included in the erase state E or the programming state P. The memory device can use the read voltage between the erase state E and the programming state P to read the data stored in the selected memory cell.

[0128] When the threshold voltage of the selected memory cell is included in the erase state E, the data stored in the selected memory cell can be read as "0". When the threshold voltage of the selected memory cell is included in the programming state P, the data stored in the selected memory cell can be read as "1".

[0129] In one embodiment, when the selected word line connected to the selected memory cell is disconnected, the read voltage may not be delivered to the gate when a read voltage is applied to the gate of the selected memory cell. Instead, the potential of the selected word line may increase due to coupling through voltage applied to an adjacent word line adjacent to the selected word line. In this case, the potential of the selected word line may be Vread' when the selected memory cell is sensed. Vread' may be greater than Vread, where Vread is the read voltage used to read the data stored in the selected memory cell.

[0130] When the threshold voltage of the selected memory cell is less than Vread', the selected memory cell can be read as an on-cell. When the threshold voltage of the selected memory cell is greater than Vread', the selected memory cell can be read as an off-cell.

[0131] When the threshold voltage of the selected memory cell is included in region A, the selected memory cell may be determined to be in erase state E even if it is in programming state P. Therefore, a read operation on a page including the selected memory cell may fail, and the read operation may be considered as failed.

[0132] Figure 9 It is a diagram illustrating the voltage applied over time to the selected word line and the word lines adjacent to the selected word line during a read operation.

[0133] refer to Figure 9 VWLn indicates the potential based on the voltage applied to the selected word line WLn connected to the selected memory cell during a read operation. VWLn-1 and VWLn+1 indicate the potential based on the voltage applied to adjacent word lines WLn-1 and WLn+1, which are the two word lines that are physically closest to the selected word line WLn.

[0134] At ta1, a voltage Vpass can be applied to the selected word line WLn, and the voltage Vpass can also be applied to the adjacent word lines WLn-1 and WLn+1.

[0135] At ta2, the potential VWLn of the selected word line and the potentials VWLn-1 and VWLn+1 of the adjacent word lines can reach the pass voltage Vpass.

[0136] At ta3, the read voltage Vread can be applied to the selected word line WLn. The potential of the selected word line WLn can be discharged from the voltage Vpass and can reach the read voltage Vread.

[0137] At ta4, the memory device can read the data stored in the selected memory cell by sensing the potential of the bit line connected to the selected memory cell.

[0138] At ta5, voltage can be applied to the selected word line WLn.

[0139] At ta6, the potential VWLn of the selected word line can reach Vpass.

[0140] At ta7, the potential VWLn of the selected word line and the potentials VWLn+1 and VWLn-1 of the adjacent word lines can be discharged.

[0141] For reference Figure 9 As stated above, when the word line is not disconnected, after the potential of the selected word line reaches the read voltage Vread, the memory device can sense the potential of the bit line connected to the selected memory cell. In this case, the read operation may not be considered a failure or may not be regarded as a failure.

[0142] Figure 10 This diagram illustrates a scenario where a read failure occurs when the selected word line is disconnected during a read operation.

[0143] At tb1, a voltage Vpass can be applied to the selected word line WLn and the two adjacent word lines WLn-1 and WLn+1. However, since the selected word line WLn is disconnected, the voltage Vpass applied from the address decoder to the selected word line WLn may not be transmitted to the selected word line WLn.

[0144] At tb2, the potentials VWLn-1 and VWLn+1 of two adjacent word lines can reach Vpass. The potential VWLn of the selected word line can be increased to the coupling voltage Vcoupling by coupling with the through voltage Vpass applied to the two adjacent word lines WLn-1 and WLn+1. Since the selected word line WLn is disconnected and no voltage is transmitted to the selected word line WLn, the potential VWLn of the selected word line can gradually discharge over time.

[0145] At tb3, the memory device can sense the potential of the bit line connected to the selected memory cell to obtain the data stored in the selected memory cell. In this case, the potential of the selected word line WLn can be Vread'. Vread' can be greater than Vread, where Vread is the read voltage used to read the data stored in the selected memory cell.

[0146] From tb4 to tb5, the potential VWLn of the selected word line and the potentials VWLn+1 and VWLn-1 of the adjacent word lines can be discharged.

[0147] For reference Figure 10 As described above, when a word line is disconnected, the memory device can sense the potential of the bit line connected to the selected memory cell before the potential of the selected word line WLn reaches the read voltage Vread. In this case, the read operation may fail and may be considered as having failed.

[0148] Figure 11This is a diagram illustrating a read operation for retrieving data stored in a memory cell connected to a selected word line, according to one embodiment.

[0149] At tc1, the voltage Vpass can be applied to the adjacent word lines WLn-1 and WLn+1.

[0150] From tc1 to tc2, the potential VWLn of the selected word line can be increased to the coupling voltage Vcoupling by coupling based on the through voltage Vpass applied to the two adjacent word lines WLn-1 and WLn+1.

[0151] From tc2 to tc5, the potentials VWLn-1 and VWLn+1 of two adjacent word lines can be discharged to the target pass voltage Vpass_t. The discharge period can be the time during which the potentials VWLn-1 and VWLn+1 of the two adjacent word lines are discharged to the target pass voltage Vpass_t from tc2 to tc5. The target pass voltage Vpass_t can be the minimum voltage required to form a channel in the channel region of the memory cell connected to the adjacent word lines WLn-1 and WLn+1, through which current can flow. The discharge period can include multiple step periods. The potential VWLn of the selected word line can be reduced by coupling with the discharge of the pass voltage Vpass applied to the two adjacent word lines WLn-1 and WLn+1.

[0152] Subsequently, the potential VWLn of the selected word line can gradually discharge over time and reach the read voltage Vread at tc6. At tc6, the memory device can sense the potential of the bit line connected to the selected memory cell to obtain the data stored in the selected memory cell.

[0153] At tc6, since the potential VWLn of the selected word line is Vread when the memory device senses the voltage applied to the bit line connected to the selected memory cell, in this case, a read operation on the page including the selected memory cell can be performed or can be determined to be performed.

[0154] Figure 12 This is a diagram illustrating the voltage applied to adjacent word lines over time during a read operation according to one embodiment.

[0155] In one embodiment, when the memory device receives an Open ReadCMD command from the memory controller, the memory device's read operation controller can control peripheral circuitry to perform a read operation to recover data stored in a selected memory cell. A read voltage controller included in the read operation controller can determine the magnitude of the voltage applied to adjacent word lines or the duration for which the voltage is applied to adjacent word lines.

[0156] At td1, a voltage Vpass can be applied to the two word lines adjacent to the selected word line.

[0157] At td2, the potential of the adjacent word line can be increased from V1 to the pass voltage Vpass.

[0158] The period from td2 to td6 can be the discharge period. The discharge period can include multiple step periods.

[0159] From td2 to td3, the potential of adjacent word lines can be maintained through voltage Vpass during the first sustaining time Tstep1.

[0160] From td3 to td4, the potential of adjacent word lines can be discharged to the discharge voltage Vpass_d. A step voltage ΔVstep can be discharged through the voltage Vpass.

[0161] From td4 to td5, the potential of adjacent word lines can maintain the discharge voltage Vpass_d during the second sustaining time Tstep2.

[0162] From td5 to td6, the potential of adjacent word lines can be discharged to the target pass voltage Vpass_t. The discharge voltage Vpass_d can be discharged by a step voltage ΔVstep. The target pass voltage Vpass_t can be the minimum voltage required to form a current-carrying channel in the channel region of the memory cell connected to the adjacent word line.

[0163] At td7, after the potential of the adjacent word line is discharged to the target pass voltage Vpass_t, the data stored in the selected memory cell can be obtained by sensing the potential of the bit line connected to the selected memory cell after the target read time Ttarget.

[0164] The number of step periods included in the discharge period, the amplitude of the step voltage ΔVstep, and the lengths of the first sustaining time Tstep1 and the second sustaining time Tstep2 are not limited by the embodiments of this disclosure and can be configured in various ways.

[0165] Figure 13 This is a diagram illustrating the change in potential over time in a selected word line during a read operation according to one embodiment.

[0166] refer to Figure 12 and Figure 13 At te1, voltage can be applied to the adjacent word line.

[0167] At te2, the potential of the selected word line can be increased from V2 to the coupling voltage Vcoupling by coupling with the adjacent word line. V2 can be the ground voltage.

[0168] At te3, when the potential of an adjacent word line discharges from the through voltage Vpass to the discharge voltage Vpass_d, the potential of the selected word line can be reduced by coupling with the adjacent word line.

[0169] At te4, when the potential of an adjacent word line discharges from the discharge voltage Vpass_d to the target pass voltage Vpass_t, the potential of the selected word line can be reduced by coupling with the adjacent word line.

[0170] At te6, the memory device can sense the potential of the bit line connected to the selected word line. te6 can occur after the first target read time Ttarget_1 elapsed from te5. te5 can be the same time as td6, where td6 is the time when the voltage applied to the adjacent word line is discharged. Figure 12 The target in the equation is the time it takes for the voltage Vpass_t to pass through.

[0171] At te6, the potential of the selected word line can be greater than the read voltage Vread used to read data stored in the selected memory cell. Therefore, a read-out operation on a page including the selected memory cell may fail, and the read-out operation may be considered as having failed.

[0172] When a read-break operation fails, the memory controller can repeatedly provide the Open Read CMD command to the memory device until a read operation on the page including the selected memory cell is successful. In this case, each time a read-break operation is repeated, the target read time Ttarget can be sequentially increased by a step read time Δt.

[0173] Specifically, after a read-out operation has failed, the memory device can re-perform the read-out operation in response to the Open Read CMD command provided by the memory controller.

[0174] At this point, the memory device can sense the potential of the bit line connected to the selected word line at te7. The potential of the selected word line at te7 can be greater than Vread. Therefore, a break-read operation on a page including the selected memory cell may fail again.

[0175] At tread, the memory device can sense the potential of the bit line connected to the selected word line. The potential of the selected word line can be the same as the read voltage Vread at tread. Therefore, a break-read operation on a page including the selected memory cell can be determined to be successful.

[0176] Figure 14 The diagram illustrates a disconnected read information storage device according to one embodiment.

[0177] During a read-off operation, the memory device can perform the read-off operation based on information stored in a read-off information storage device included in the read operation controller. Specifically, the read-off information storage device can store voltage information and read time information.

[0178] Through voltage information can include information related to the initial through voltage, target through voltage, step voltage, first sustaining time, second sustaining time, target read time, and step read time.

[0179] The initial pass voltage can refer to the pass voltage initially applied to the adjacent word line adjacent to the selected word line during a disconnect read operation.

[0180] A step voltage can refer to the magnitude of the voltage discharged from the initial voltage during a read-off operation to lower the potential of the selected word line. For example, refer to... Figure 12 The initial pass voltage can be applied to the adjacent word line at td1, and the initial pass voltage can be discharged by the step voltage at td3.

[0181] The target pass voltage can be the minimum voltage required to form a current flow path in the channel region of a memory cell connected to an adjacent word line. For example, the read operation controller of a memory device can, based on information stored in the disconnected read information storage device, sequentially reduce the voltage applied to adjacent word lines by a step voltage until the potential of the adjacent word lines reaches the target pass voltage from the initial pass voltage.

[0182] The first sustaining time can refer to the time between the potential of the adjacent word line reaching the initial pass voltage and the potential of the adjacent word line being discharged by the step voltage.

[0183] The second sustaining time can refer to the time between the discharge step voltage from the initial through voltage and the discharge voltage of the adjacent word line's potential to the target through voltage.

[0184] Based on the above description, an example has been given where the discharge period includes two step periods; however, the number of step periods is not limited to the embodiments of this disclosure. For example, refer to... Figure 12 When the discharge period includes three step periods, the disconnect read information storage device can store information related to the first maintenance time, the second maintenance time, and the third maintenance time.

[0185] Read time information may include information related to the target read time and step read time.

[0186] Target read time can refer to the time from when the potential of the adjacent word line is discharged to the target pass voltage until the memory device senses the potential of the bit line connected to the selected memory cell.

[0187] Step read time can refer to the time increase from the target read time when the memory device executes the break read command again after a break read operation has failed.

[0188] Figure 15 This is a diagram illustrating a bad block information storage device according to one embodiment.

[0189] When a read operation on a specific page included in a memory device fails, the operation controller inside the memory controller can set the memory block containing the corresponding page as a bad block.

[0190] Specifically, the operation controller 210 can receive information from the error correction circuit regarding whether a page read operation corresponding to a read command has succeeded or failed. When a read operation on a selected memory cell fails, the operation controller can provide information related to the block containing the selected memory cell to the bad block storage device. The bad block storage device can store bad block information provided by the operation controller. The bad block information may include information related to a list of bad blocks and their addresses.

[0191] Memory operations on memory blocks corresponding to bad block information stored in the bad block storage device can be restricted. For example, when a memory controller provides programming commands to a memory device, the memory controller can control the memory device to store data in memory blocks other than those registered as bad blocks by referring to the bad block information stored in the bad block information storage device.

[0192] Figure 16 This is a flowchart illustrating the operation of a storage device according to one embodiment.

[0193] In step S1601, the storage device may perform a normal read operation to read data stored in selected pages of the memory device, based on a request from the host. This normal read operation may be referred to as a regular memory operation, rather than a disconnected read operation according to embodiments of this disclosure. A normal read operation may be an operation that reads data stored in a memory cell using a preset default read voltage. As used herein, the term "preset" (such as a preset default read voltage) refers to a parameter whose value is determined before it is used in a process or algorithm. In some embodiments, the parameter value is determined before the process or algorithm begins. In other embodiments, the parameter value is determined during the process or algorithm but before it is used in the process or algorithm.

[0194] In step S1603, the storage device can determine whether a normal read operation on the selected page has been successful. Once the normal read operation has been successful, the read data can be transmitted to the host, and the storage device's read operation can end.

[0195] In step S1605, when a normal read operation fails, the storage device can update the bad block information by setting the block containing the corresponding page as a bad block. Specifically, the storage device can store information related to the block containing the corresponding page in a bad block information storage device inside the memory controller.

[0196] In step S1607, the storage device may perform a disconnect read operation on the selected page. The disconnect read operation may be a read operation performed when a normal read operation has failed. The disconnect read operation may also be a read operation used to recover data stored in the selected page.

[0197] In step S1609, the storage device can determine whether the disconnect read operation has succeeded. If the disconnect read operation has failed, the storage device can perform the disconnect read operation by adding a step read time to the target read time, where the target read time is the time used to sense the potential of the bit line connected to the selected memory cell.

[0198] In step S1611, when the disconnect read operation has been completed, the data stored in the target memory block including the selected page can be stored in another memory block.

[0199] After reading the first data stored in the selected page, the storage device can read the second data stored in pages other than the selected page included in the target memory block. The storage device can store the first and second data in another memory block different from the target memory block. In this case, the storage device can refer to bad block information stored in the bad block information storage device.

[0200] Figure 17 This is a flowchart illustrating a disconnect read operation according to one embodiment.

[0201] In step S1701, the storage device may apply a voltage to the word line adjacent to the selected word line.

[0202] In step S1703, the storage device may reduce the voltage by a step voltage at predetermined intervals until the voltage amplitude reaches the target voltage.

[0203] In step S1705, after the amplitude of the through voltage reaches the target through voltage and the target read time has elapsed, the storage device can sense the potential of the bit line connected to the memory cell connected to the selected word line.

[0204] In step S1707, the number of error bits and the number of correctable error bits of data read from the memory cell connected to the selected word line can be compared.

[0205] In step S1709, the storage device can determine whether the read operation has succeeded. If the read operation has succeeded, the operation of the storage device can end. If the read operation has failed, the storage device can increase the target read time by a step read time and then perform the read operation again.

[0206] Figure 18 It's a diagram. Figure 1 A diagram illustrating another embodiment of the memory controller.

[0207] refer to Figure 18 The memory controller 1000 is connected to the host and the memory device. The memory controller 1000 is configured to access the memory device in response to requests from the host. For example, the memory controller 1000 is configured to control write, read, erase, and background operations of the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

[0208] The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction circuit (ECC) 1030, a host interface 1040, a buffer controller 1050, a memory interface 1060, and a bus 1070.

[0209] Bus 1070 can be configured to provide a channel between components of memory controller 1000.

[0210] Processor 1010 can control the overall operation of memory controller 1000 and can execute logical operations. Processor 1010 can communicate with an external host through host interface 1040 and with memory devices through memory interface 1060. Additionally, processor 1010 can communicate with memory buffer 1020 through buffer controller 1050. Processor 1010 can control the operation of memory devices using memory buffer 1020 as operational memory, cache memory, or buffer memory.

[0211] Processor 1010 can perform FTL functions. Processor 1010 can use FTL to translate LBAs provided by the host into PBAs. FTL can use a mapping table to receive LBAs and translate them into PBAs. The address mapping method of the flash translation layer can include various methods based on the mapping unit. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0212] Processor 1010 is configured to randomize data received from the host. For example, processor 1010 may use a randomization seed to randomize data received from the host. The randomized data is provided to the memory device as data to be stored and is programmed into the memory cell array.

[0213] Processor 1010 is configured to derandomize data received from the memory device during a read operation. For example, processor 1010 may use a derandomization seed to derandomize data received from the memory device. The derandomized data may then be output to the host.

[0214] As an example, the processor 1010 can perform randomization and derandomization via driver software or firmware.

[0215] The memory buffer 1020 can be used as the operating memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store code and commands executed by the processor 1010. The memory buffer 1020 can store data processed by the processor 1010. The memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0216] ECC 1030 can perform error correction. ECC 1030 can perform error correction encoding (ECC encoding) based on data to be written to the memory device via memory interface 1060. Error-corrected encoded data can be transferred to the memory device via memory interface 1060. ECC 1030 can perform error correction decoding (ECC decoding) on ​​data received from the memory device via memory interface 1060. For example, ECC 1030 can be included as a component of memory interface 1060 within memory interface 1060.

[0217] The host interface 1040 is configured to communicate with an external host under the control of the processor 1010. The host interface 1040 can be configured to perform communication using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Memory (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Depleted DIMM (LRDIMM).

[0218] The buffer controller 1050 is configured to control the memory buffer 1020 under the control of the processor 1010.

[0219] The memory interface 1060 is configured to communicate with a memory device under the control of the processor 1010. The memory interface 1060 can communicate commands, addresses, and data with the memory device via channels.

[0220] For example, the memory controller 1000 may not include the memory buffer 1020 and the buffer controller 1050.

[0221] For example, processor 1010 can use code to control the operation of memory controller 1000. Processor 1010 can load code from a non-volatile memory device (e.g., read-only memory) provided within memory controller 1000. As another example, processor 1010 can load code from a memory device via memory interface 1060.

[0222] For example, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data within the memory controller 1000, and the control bus can be configured to transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus can be separate from each other and do not interfere with or affect each other. The data bus can be connected to the host interface 1040, the buffer controller 1050, the ECC 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1020, and the memory interface 1060.

[0223] Figure 19 This is a block diagram illustrating a memory card system for applying a storage device according to an embodiment of the present disclosure.

[0224] refer to Figure 19 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0225] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 is configured to access memory device 2200. For example, memory controller 2100 can be configured to control read, write, erase, and background operations of memory device 2200. Memory controller 2100 is configured to provide an interface between memory device 2200 and a host. Memory controller 2100 is configured to drive firmware for controlling memory device 2200. Memory controller 2100 can be used with reference to... Figure 1 The memory controller 200 described is implemented in the same way.

[0226] For example, memory controller 2100 may include components such as random access memory (RAM), processor, host interface, memory interface, and ECC.

[0227] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to specific communication standards. For example, the memory controller 2100 is configured to communicate with external devices via at least one of the following communication standards: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 2300 can be defined by at least one of the aforementioned communication standards.

[0228] For example, the memory device 2200 can be composed of various non-volatile memory elements, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0229] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, or eMMC), SD cards (SD, miniSD, microSD, or SDHC), and universal flash memory (UFS).

[0230] Figure 20 This is a block diagram illustrating a solid-state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0231] refer to Figure 20 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory units 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0232] According to one embodiment of this disclosure, the SSD controller 3210 can perform reference... Figure 1 The functions of the memory controller 200 are described.

[0233] SSD controller 3210 can control multiple flash memory devices 3221 to 322n in response to signals received from host 3100. For example, the signals can be based on the interface between host 3100 and SSD 3200. For example, the signals can be defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0234] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can receive power PWR from host 3100 and can be charged using the power PWR. When power supply from host 3100 is insufficient, auxiliary power supply 3230 can power SSD 3200. For example, auxiliary power supply 3230 can be located inside SSD 3200 or externally to SSD 3200. For example, auxiliary power supply 3230 can be located on the motherboard and can provide auxiliary power to SSD 3200.

[0235] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or it may temporarily store metadata (e.g., mapping tables) of flash memories 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0236] Figure 21 This is a block diagram illustrating a user system that applies a storage device according to an embodiment of the present disclosure.

[0237] refer to Figure 21 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0238] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., that control components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0239] The memory module 4200 can operate as the main memory, operating memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged in a stacked package (POP) and provided as a single semiconductor package.

[0240] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), LTE, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 can be included in application processor 4100.

[0241] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented as a non-volatile semiconductor memory element, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), NAND flash memory, NOR flash memory, and 3D NAND flash memory. For example, storage module 4400 can be provided as a removable storage device (removable drive) such as a memory card and an external drive for user system 4000.

[0242] For example, storage module 4400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be connected to a reference. Figure 1 The memory device 100 described operates in the same manner. The memory module 4400 can be compared with the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0243] User interface 4500 may include interfaces for inputting data or instructions to application processor 4100 or for outputting data to external devices. For example, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touchscreen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

Claims

1. A memory device, comprising: Multiple memory cells are connected to multiple word lines respectively; The peripheral circuitry is configured to perform a read operation to read data stored in a selected memory cell among the plurality of memory cells, the selected memory cell being connected to a selected word line among the plurality of word lines; as well as A read operation controller is configured to control the peripheral circuitry to: during the read operation, apply a voltage to an adjacent word line among the plurality of word lines that is adjacent to the selected word line; After a predetermined time has elapsed, the through voltage is discharged to a target through voltage lower than the through voltage; and after a target read time has elapsed since the through voltage was discharged to the target through voltage, the data stored in the selected memory cell is obtained via a bit line connected to the selected memory cell.

2. The memory device according to claim 1, wherein the read operation controller comprises: The read information storage device is disconnected and configured to store through voltage amplitude information, which is information related to the amplitude of the through voltage and the amplitude of the target through voltage; as well as The voltage controller is read and configured to determine the amplitude of the through voltage and the amplitude of the target through voltage based on the through voltage amplitude information.

3. The memory device of claim 2, wherein the disconnect read information storage device further stores voltage-time information, the voltage-time information being information related to the predetermined time, and The read voltage controller determines the time when the through voltage is applied to the adjacent word line based on the through voltage time information.

4. The memory device of claim 1, wherein the read operation controller includes a page buffer controller that controls a page buffer connected to the bit line to sense the potential of the bit line after the target read time has elapsed.

5. The memory device of claim 2, wherein when a read failure occurs during the read operation, the read operation controller controls the peripheral circuitry to: further increase the target read time by a step read time in response to a read time change command from the memory controller; and perform the read operation by applying a read time changed according to the read time change command in response to a read command provided from the memory controller.

6. The memory device of claim 5, wherein the disconnect read information storage device further stores read time information, the read time information including information related to the target read time and the step read time.

7. The memory device of claim 1, wherein each of the selected memory cells includes a memory cell configured to store one bit of data.

8. The memory device of claim 1, wherein the target through voltage is a minimum voltage for forming a current flow path in the channel region of the memory cell connected to the adjacent word line.

9. The memory device according to claim 1, The selected word line is in a disconnected state.

10. A storage device, comprising: A memory device comprising a memory block, the memory block comprising memory cells; as well as A memory controller including an operation controller configured to: output a read command and an address for the memory cell; and provide a disconnect read command and the address to the memory device when a read operation performed by the memory device in response to the read command fails. In response to the disconnect read command, the memory device applies a voltage to an adjacent word line adjacent to the selected word line connected to the memory cell, discharges the voltage to a target voltage that is a step voltage smaller than the current voltage after a predetermined time, and performs a disconnect read operation to obtain the data stored in the memory cell via the bit line connected to the memory cell after a target read time has elapsed from the current voltage to the target voltage.

11. The storage device of claim 10, wherein when the disconnect read operation fails, the operation controller provides the storage device with a read time change command for further increasing the target read time by a step read time, and then provides the disconnect read command to cause the storage device to perform the disconnect read operation by applying the target read time changed according to the read time change command to the storage device.

12. The storage device of claim 11, wherein the operation controller repeatedly provides the read time change command and the disconnect read command to the storage device until the disconnect read operation for the storage cell has been completed.

13. The storage device of claim 10, wherein the memory controller further comprises an error correction circuit that corrects error bits in data read during the read operation or the disconnect read operation, determines whether the read operation or the disconnect read operation has passed or failed by comparing the number of error bits in the read data with the number of correctable error bits, and provides the operation controller with information relating to whether the read operation or the disconnect read operation has passed or failed.

14. The storage device of claim 13, wherein the storage device comprises a plurality of memory blocks, and The memory controller also includes a bad block information storage device for storing bad block information, which is information related to bad blocks among the plurality of memory blocks, and memory operations on the bad blocks are restricted.

15. The storage device of claim 14, wherein when the disconnect read operation has passed, the operation controller provides a programming command to the memory device such that the memory device stores the data stored in a first memory block including the memory cells in a second memory block among the plurality of memory blocks, excluding bad blocks, and In response to the programming command, the memory device programs the data stored in the first memory block into the second memory block.

16. The storage device of claim 10, wherein the storage device further comprises a read-out information storage means, the read-out information storage means storing through voltage information, the through voltage information including through voltage amplitude information, information related to the predetermined time, and information related to the step voltage, the through voltage amplitude information being information related to the amplitude of the through voltage and the amplitude of the target through voltage, and The operation controller provides the memory device with a command to change at least one of the following: the voltage amplitude information, the information related to the predetermined time, and the information related to the step voltage.

17. A method for operating a storage device to perform a read operation to read data, the data being stored in selected memory cells included in a target memory block among a plurality of memory blocks, the selected memory cells being connected to selected word lines among a plurality of word lines, the method comprising: A voltage will be applied to the word line adjacent to the selected word line; Discharge the voltage to a target voltage lower than the voltage passed; After the through voltage is discharged to the target through voltage and the target read time has elapsed, the potential of the bit line connected to the selected memory cell connected to the selected word line is sensed; as well as The success or failure of the read operation is determined by comparing the number of error bits in the read data with the number of correctable error bits for the selected memory cell.

18. The method of claim 17, wherein discharging the through voltage to the target through voltage comprises: The through voltage is reduced by a step voltage at predetermined intervals until the amplitude of the through voltage reaches the target through voltage.

19. The method of claim 17, further comprising: When the read operation fails, the read operation is repeated by increasing the target read time by a step read time until the read operation on the selected memory cell passes.

20. The method of claim 17, further comprising: When the read operation is successful, the data stored in the selected memory cell is stored in a memory block other than the target memory block.

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