Etching method

Abstract

Embodiments of the present invention relate to an etching method. The present invention provides an etching method capable of reducing processing problems in etching using a catalyst. According to an embodiment, there is provided an etching method of etching a surface formed of a semiconductor by bringing an etchant into contact with a surface formed of a semiconductor on which a catalyst layer containing a noble metal is formed. The etchant contains an oxidizing agent, a corrosive agent, and a N-containing polymer additive.

Description

Technical Field

[0001] Embodiments of the present invention relate to etching methods. Background Technology

[0002] Etching is a known method for forming holes or trenches on semiconductor wafers. Among the etching methods, MacEtch (Metal-Assisted Chemical Etching) is known. MacEtch is a method of etching a semiconductor substrate, for example, using a noble metal as a catalyst. Because high aspect ratio trenches are formed on the semiconductor wafer, when the semiconductor wafer is immersed in a MacEtch solution for an extended period, micro-cavitation problems occur on the upper walls of the trenches. As a result, problems such as trench collapse due to reduced strength or difficulty in forming a dielectric film on the trenches may occur. Summary of the Invention

[0003] According to the embodiments, an etching method can be provided that can reduce processing problems in etching using catalysts.

[0004] According to embodiments, an etching method can be provided that involves contacting an etchant with a surface formed of a semiconductor and containing a catalyst layer comprising a noble metal, thereby etching the surface formed of the semiconductor. The etchant comprises an oxidant, an etchant, and a nitrogen-containing polymeric additive.

[0005] According to the etching method described in the embodiments, an etching method can be provided that can reduce processing problems in etching using catalysts. Attached Figure Description

[0006] Figure 1 This is a schematic diagram illustrating one step of the method for implementing the method.

[0007] Figure 2 To enlarge Figure 1 A schematic diagram of part A.

[0008] Figure 3 This is a graph showing the relationship between pH and the Zeta potential of Si oxide.

[0009] Figure 4 A scanning electron microscope image showing a cross-section of a trench formed by the method of the embodiment.

[0010] Figure 5 This is a scanning electron microscope image showing a cross-section near the upper end of the trench formed by the method of the embodiment.

[0011] Figure 6 A scanning electron microscope image showing the cross-section of the groove formed by the comparative example method.

[0012] Figure 7 This is a scanning electron microscope image showing a cross-section near the upper end of the groove formed by the comparative example method. Detailed Implementation

[0013] The following is a reference to the appendix. Figure 1 The embodiments are described in detail below. Furthermore, components that perform the same or similar functions are represented by the same reference numerals in all the drawings, and repeated descriptions are omitted.

[0014] (First Implementation)

[0015] According to a first embodiment, an etching method is provided. The etching method is an etching method that etches an etchant onto a surface formed of a semiconductor, wherein a catalyst layer containing a noble metal is formed. The etchant comprises an oxidant, an etchant, and a nitrogen-containing polymeric additive.

[0016] When an etchant comes into contact with a surface formed of a semiconductor containing a catalyst layer containing noble metal, an oxidant oxidizes the portion of the surface near the noble metal, and the etchant dissolves and removes the oxide. Therefore, through the action of the catalyst layer, the etchant can etch the surface formed of the semiconductor in a vertical direction relative to the surface. This allows the formation of recesses, such as trenches, on the surface formed of the semiconductor.

[0017] The reason for the cavity-like processing problem occurring on the wall surface near the upper end of the recess, such as a groove, is speculated as follows: the oxide of the semiconductor material at this location dissolves in the etchant through the etchant's corrosive action. This oxide tends to have a positive zeta potential in the etchant. On the other hand, nitrogen-containing polymeric additives have lone pairs of electrons generated by nitrogen atoms. Therefore, nitrogen-containing polymeric additives tend to readily adsorb onto the oxide of the semiconductor material in the etchant, while having a low zeta potential and being difficult to adsorb onto the negative catalyst surface. Thus, nitrogen-containing polymeric additives can selectively adsorb near the upper end of the recess, protecting it from etching by the etchant. As a result, due to the formation of a recess with a high aspect ratio, processing problems near the upper end of the recess can be suppressed even when the surface is immersed in the etchant for a long time.

[0018] The method of implementation will be described in detail below.

[0019] Semiconductors are selected from, for example, semiconductors formed from compounds of group III and group V elements such as silicon (Si); germanium (Ge); gallium arsenide (GaAs) and gallium nitride (GaN); and silicon carbide (SiC). According to one example, the semiconductor substrate contains silicon. Furthermore, the term "group" as used herein refers to the "group" of a short-period periodic table.

[0020] The surface formed from a semiconductor can be, for example, the main surface of a semiconductor substrate. The semiconductor substrate is, for example, a semiconductor wafer. Impurities can be doped into the semiconductor wafer, and semiconductor devices such as transistors or diodes can be formed therein. Furthermore, the main surface of the semiconductor wafer can be parallel to any crystal plane of the semiconductor. For example, a silicon wafer with a (100) main surface or a silicon wafer with a (110) main surface can be used as the semiconductor wafer.

[0021] When a pattern with recesses such as trenches is formed on the surface of a semiconductor, a mask layer with openings can also be formed on the surface of the semiconductor. Etching is then performed on the surface exposed from the openings. The mask layer can be formed, for example, from an inorganic material such as a silicon nitride compound. Alternatively, the mask layer can be prepared, for example, by a method comprising the following steps: First, a mask layer is formed on the surface of the semiconductor. A resist layer is formed on the mask layer. The resist layer can be formed, for example, from a photoresist. The resist layer is processed into the desired pattern shape, forming openings. Pattern formation is performed, for example, by photolithography. The mask layer is processed into the desired pattern shape using, for example, etching, and openings are formed on the mask layer. Next, the resist layer is removed.

[0022] A catalyst layer containing noble metal is formed on the surface of the semiconductor. The formation of the catalyst layer can be performed after a mask layer is formed on the surface of the semiconductor.

[0023] In the catalyst layer, noble metals may exist as noble metal particles. Noble metals are, for example, one or more metals selected from Au, Ag, Pt, Pd, Ru, and Rh.

[0024] The thickness of the catalyst layer is preferably in the range of 0.01 μm to 0.3 μm, more preferably in the range of 0.05 μm to 0.2 μm. If the catalyst layer is too thick, etching is difficult because the etchant cannot reach the semiconductor. If the catalyst layer is too thin, etching is difficult because the ratio of the total surface area of ​​the noble metal ions to the area that should be etched is too small.

[0025] Furthermore, the thickness of the catalyst layer is the distance from one principal surface of the catalyst layer to the opposite principal surface in an image obtained by observing a cross section parallel to its thickness direction using a scanning electron microscope (SEM).

[0026] The catalyst layer may also have discontinuities.

[0027] The noble metal particles are preferably spherical. Other shapes, such as rods or plates, are also possible. The noble metal particles act as catalysts for the oxidation reaction on the semiconductor surface they contact.

[0028] The particle size of the noble metal particles is preferably in the range of 0.001 μm to 1 μm, and more preferably in the range of 0.01 μm to 0.5 μm.

[0029] Furthermore, the "particle size" here is obtained as follows: First, the main surface of the catalyst layer is photographed using a scanning electron microscope. The magnification range is 10,000x to 100,000x. Next, the area of ​​each noble metal particle is calculated from the image. Then, assuming that each noble metal particle is spherical, the diameter of the noble metal particle is calculated from the previous area. This diameter is taken as the "particle size" of the noble metal particle.

[0030] The catalyst layer can be a porous catalyst layer.

[0031] The catalyst layer can be formed, for example, by electroplating, reduction plating, or displacement plating. The catalyst layer can also be formed using coating of a dispersion containing noble metal particles, or by vapor deposition methods such as evaporation and sputtering. Among these methods, displacement plating is particularly preferred because it allows the noble metal to be deposited directly and uniformly on the surface of the semiconductor. Hereinafter, as an example, the formation of a porous catalyst layer using displacement plating will be described.

[0032] For example, aqueous solutions of tetrachloroaluminate (III) or silver nitrate solution can be used for the precipitation of noble metals by displacement plating. An example of this process is described below.

[0033] Displacement plating solutions are, for example, a mixture of an aqueous solution of tetrachloroauro(III) acid tetrahydrate and hydrofluoric acid. Hydrofluoric acid has the function of removing the natural oxide film on the surface of the semiconductor.

[0034] When a semiconductor substrate is immersed in a displacement plating solution, in addition to removing the natural oxide film on the surface of the semiconductor substrate, noble metals, specifically gold, are deposited on the surface of the semiconductor substrate. This results in a porous catalyst layer.

[0035] The concentration of tetrachloroauro(III) acid tetrahydrate in the displacement plating solution is preferably in the range of 0.0001 mol / L to 0.01 mol / L. Furthermore, the concentration of hydrogen fluoride in the displacement plating solution is preferably in the range of 0.1 mol / L to 6.5 mol / L.

[0036] In addition, the displacement plating solution may further contain sulfur-based complexing agents. Alternatively, the displacement plating solution may further contain glycine and citric acid.

[0037] The etching agent is described below. The etching agent contains etchants, oxidants, and nitrogen-containing polymeric additives.

[0038] Etching agents can dissolve the oxides of semiconductor materials. These oxides may be, for example, SiO2. Examples of etchants include hydrofluoric acid and ammonium fluoride. One or more types of etchants may be used. Considering the etching rate and the ease of adsorption of nitrogen-containing polymeric additives, etchants containing hydrofluoric acid are preferred.

[0039] The concentration of hydrogen fluoride in the etchant is preferably in the range of 0.4 mol / L to 20 mol / L, more preferably in the range of 0.8 mol / L to 16 mol / L, and even more preferably in the range of 2 mol / L to 10 mol / L. If the hydrogen fluoride concentration is too low, it is difficult to achieve a high etching rate. If the hydrogen fluoride concentration is too high, there is a possibility that the controllability of etching in the processing direction (e.g., the thickness direction of the semiconductor substrate) may decrease.

[0040] The oxidant in the etching agent can be, for example, at least one selected from hydrogen peroxide, nitric acid, AgNO3, KAuCl4, HAuCl4, K2PtCl6, H2PtCl6, Fe(NO3)3, Ni(NO3)2, Mg(NO3)2, Na2S2O8, K2S2O8, KMnO4, and K2Cr2O7. Hydrogen peroxide is preferred as the oxidant because it does not produce harmful byproducts or contaminate semiconductor devices.

[0041] The concentration of the oxidant, such as hydrogen peroxide, in the etching agent is preferably in the range of 0.2 mol / L to 8 mol / L, more preferably in the range of 0.5 mol / L to 5 mol / L, and even more preferably in the range of 0.5 mol / L to 4 mol / L. If the concentration of the oxidant is too low, it is difficult to achieve a high etching rate. If the concentration of the oxidant is too high, there is a possibility of excessive side etching.

[0042] There are no particular limitations on nitrogen-containing polymer additives, as long as they are polymers containing nitrogen atoms; for example, nitrogen-containing surfactants can be cited. Nitrogen-containing surfactants are expected to be nonionic surfactants and / or cationic surfactants containing nitrogen.

[0043] Examples of N-containing cationic surfactants include polyethyleneimine, ethylenediamine, diethylenetriamine, triethylenetetramine, tetraethylenepentamine, pentaethylenehexamine, and polyoxyethylene alkylamine.

[0044] Examples of nitrogen-containing nonionic surfactants include poly(oxyethylene) octylphenyl ether and ethylenediamine tetra(propoxide-block-ethoxide) tetraol.

[0045] The nitrogen-containing polymeric additives used can be one or more types. Preferred nitrogen-containing polymeric additives include polyethyleneimine.

[0046] The content of nitrogen-containing polymeric additives in the etching solution can be, for example, 0.0001 vol% to 0.01 vol%. By setting the content to 0.0001 vol% or more, it is expected to suppress machining problems on the wall surface of the specified recess. Furthermore, by setting the content to 0.01 vol% or less, it is possible to avoid the etching rate becoming extremely slow. A preferred range is 0.005 vol% to 0.01 vol% or less.

[0047] Etching agents can contain water as a solvent. Etching agents can also be aqueous solutions.

[0048] The etchant can be an aqueous solution with a pH range of, for example, 1 to 2. By maintaining the pH within this range, it is possible to maintain a practical etching rate while promoting the adsorption of nitrogen-containing polymeric additives onto the oxide of the semiconductor material.

[0049] Reference Figures 1-3 This describes one example of an etching method for implementing an embodiment.

[0050] Figure 1 This is a schematic diagram illustrating the etching process of trenches on the main surface of a semiconductor substrate 1 along the xy plane. The semiconductor substrate 1 is, for example, a silicon wafer. Trenches are formed on the main surface of the semiconductor substrate 1 along the xy plane. The trenches extend along the y-axis. For example, a catalyst layer 3 containing Au particles is formed on the bottom surface of the trenches defined on the main surface of the semiconductor substrate 1 along the xy plane. The surface near the upper end of the partition portion 2 that defines the trenches is covered with a protective layer 4 containing a nitrogen-containing polymer additive. The nitrogen-containing polymer additive may be, for example, polyethyleneimine. The entire main surface of the semiconductor substrate 1 along the xy plane and the partition portion 2 are immersed in an etching solution 5, which is an etchant.

[0051] Etching is performed, for example, after a mask layer with a desired pattern is formed on the main surface of the semiconductor substrate 1. As etching proceeds, a portion of the mask layer dissolves in the etchant 5, resulting in stripping. Consequently, a portion of the upper surface of the partition 2 becomes directly in contact with the etchant 5. Therefore, as... Figure 2 As shown in the example, the upper part of the partition 2 is partially oxidized, and a portion of it forms Si oxide 6 such as SiO2. The Si oxide 6 such as SiO2 can have a positive Zeta potential in the etching solution. Figure 3 This represents the relationship between the zeta potential on the surface of SiO2 particles and pH. Figure 3 The horizontal axis represents pH, and the vertical axis represents zeta potential (mV). For example... Figure 3 As shown, the Zeta potential of the SiO2 particle surface is positive at pH below 4. Furthermore, the Zeta potential of the Si surface is negative at pH below 4.

[0052] On the other hand, nitrogen-containing polymeric additives such as polyethyleneimine, due to their multiple lone pairs of electrons, readily adsorb onto the positively charged Si oxide 6 in etching solution 5. Conversely, nitrogen-containing polymeric additives such as polyethyleneimine cannot adsorb onto either the catalyst surface (where the zeta potential can be negative) or the semiconductor surface in etching solution 5, thus not hindering processing. For example, Au has a zeta potential of -20.4 mV at pH 1–2.

[0053] As described above, the protective layer 4, containing nitrogen-containing polymeric additives, can selectively adsorb onto the Si oxide 6 present near the upper end of the partition 2. Therefore, etching can be performed while protecting the upper end of the partition 2 from etching by the etching solution 5. Thus, even when forming trenches with high aspect ratios, the partition 2 can be prevented from becoming a processing problem. This effect cannot be obtained if polyethyleneimine is not used as the etchant but is contained in the catalyst layer 3. For example, when a dispersion containing Au particles and polyethyleneimine is coated onto the main surface of the semiconductor substrate 1 and dried to form the catalyst layer 3, even with extended immersion time in the etching solution, etching in the vertical direction relative to the semiconductor main surface will not occur, and trenches with high aspect ratios cannot be obtained. The maximum depth of vertically processable trenches is approximately tens of μm.

[0054] The method of this embodiment may include a step of removing nitrogen-containing polymeric additives from the surface (semiconductor surface) of the semiconductor after the etching step. Examples of removal methods include washing the semiconductor surface with an alkaline aqueous solution or an organic solvent. Additionally, the method of this embodiment may, as needed, include a step of removing a catalyst layer from the semiconductor surface after the etching step. When there is residue with a mask layer, the method of this embodiment may include a step of removing the mask layer from the semiconductor surface. When the method of this embodiment includes a step of removing the catalyst layer from the semiconductor surface, or a step of removing the mask layer from the semiconductor surface, the nitrogen-containing polymeric additives can be removed in these steps. For example, aqua regia can be used to remove the catalyst layer. On the other hand, hot phosphoric acid can be used to remove the mask layer.

[0055] The method described in this embodiment can be applied, for example, to a pattern forming method for forming recesses or through-holes such as trenches on a semiconductor substrate. Furthermore, according to the method described in this embodiment, a semiconductor device can be manufactured by forming a conductive layer in the recesses or through-holes formed in the semiconductor substrate using plating, or by forming a dielectric thin film using chemical vapor deposition (CVD), followed by a process of forming a wiring layer or the like on top of the semiconductor substrate.

[0056] Example

[0057] The following describes the embodiments and comparative examples.

[0058] (Example)

[0059] The following method is used to form trenches on a semiconductor substrate using etching. Then, after etching, it is confirmed whether micropore-like damage has occurred on the trench walls.

[0060] The semiconductor substrate uses a silicon wafer. First, a mask layer made of silicon nitride compound is formed on the first main surface of the semiconductor substrate. The mask layer has openings at regular intervals.

[0061] A 50 mL plating solution containing an aqueous solution of tetrachloroauro(III) acid tetrahydrate and hydrofluoric acid was prepared. A semiconductor substrate with a mask layer formed thereon was immersed in the plating solution for 60 seconds at room temperature, and a catalyst layer was formed on the first main surface exposed from the opening of the mask layer.

[0062] An etching solution was prepared using an aqueous solution containing 5 mol / L hydrogen fluoride, 4 mol / L hydrogen peroxide, and 0.0001 vol% polyethyleneimine. A semiconductor substrate with a mask layer and a catalyst layer formed thereon was immersed in this etching solution at 25°C for 50 minutes to etch it. The pH of the etching solution was below 1. Figure 4 This is a scanning electron microscope image showing a semiconductor substrate after etching. Additionally, Figure 5 Indicates agreement with regulations Figure 4 A magnified scanning electron microscope image of the upper end of the partition wall of the trench in the semiconductor substrate shown.

[0063] like Figure 4 As shown, no processing problems were observed on the surface of the partition portion where the trenches of the semiconductor substrate were defined. Furthermore, as... Figure 5 As shown, even when magnified and observed near the upper part of the partition, no processing problems were found on the surface of the partition.

[0064] (Comparative Example)

[0065] An etching solution with the same composition and pH as in the examples was prepared, except that it did not contain polyethyleneimine. Etching was performed in the same manner as in the examples, except that the etching solution was used. Figure 6 This is a scanning electron microscope image showing a semiconductor substrate after etching. Additionally, Figure 7 Indicates to Figure 6 A magnified scanning electron microscope image of the upper part of the specified partition portion of the trench in the semiconductor substrate shown.

[0066] like Figure 6 As shown, no processing problems were identified on the surface of the partition portion of the trench in the semiconductor substrate. Additionally, as... Figure 7As shown, when magnified and observed near the upper part of the partition wall, the entire area near the upper part of the partition wall becomes a processing problem.

[0067] According to the method of at least one of the above embodiments or examples, in the method of contacting an etchant with a surface formed of a semiconductor containing a catalyst layer of noble metal and etching the surface formed of the semiconductor, since an etchant containing an oxidant, an etchant and a polymeric additive containing nitrogen is used, an etching method that can reduce processing problems can be provided.

[0068] The invention described in the embodiments is noted below.

[0069] [1] According to an embodiment, an etching method is provided, which is an etching method for etching a surface formed of a semiconductor by contacting an etchant with a catalyst layer containing a noble metal, wherein the etchant comprises an oxidant, an etchant and a nitrogen-containing polymer additive.

[0070] [2] In the etching method described in [1] above, the N-containing polymer additive is an N-containing surfactant.

[0071] [3] The etching method described in [1] above, wherein the N-containing polymeric additive is an N-containing nonionic surfactant and / or an N-containing cationic surfactant.

[0072] [4] In the etching method described above [1], the N-containing polymeric additive is selected from at least one of polyethyleneimine, ethylenediamine, diethylenetriamine, triethylenetetramine, tetraethylenepentamine, pentaethylenehexamine, polyoxyethylene alkylamine, poly(oxyethylene) octylphenyl ether, and ethylenediamine tetra(propoxide-block-ethoxide) tetraol.

[0073] [5] The etching method described in any one of [1] to [4] above, wherein the semiconductor contains silicon.

[0074] [6] The etching method described in any one of [1] to [5] above, wherein the precious metal contains gold.

[0075] [7] The etching method described in any one of [1] to [6] above, wherein the catalyst layer containing noble metal is porous.

[0076] [8] The etching method described in any one of [1] to [7] above, wherein the catalyst layer containing noble metal is formed by displacement plating.

[0077] [9] The etching method described in any one of [1] to [8] above, wherein the oxidant is hydrogen peroxide and the etchant is hydrogen fluoride.

[0078] According to an embodiment, a pattern forming method is provided, which is a pattern forming method in which an etchant is brought into contact with a surface formed of a semiconductor containing a catalyst layer of noble metal, and a recess is formed on the surface formed of the semiconductor, wherein the etchant comprises an oxidant, an etchant and a nitrogen-containing polymer additive.

[0079] Additionally, according to an embodiment, a method for manufacturing a semiconductor device is provided, comprising: contacting an etchant comprising an oxidant, an etchant and a nitrogen-containing polymeric additive to a semiconductor substrate having a catalyst layer comprising a noble metal formed thereon, forming a recess on the semiconductor substrate; and forming a wiring layer above the semiconductor substrate.

[0080] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and their equivalents.

Claims

1. An etching method comprising the steps of contacting an etchant with a surface formed of a silicon-containing semiconductor and comprising forming a catalyst layer containing a noble metal, and etching the surface formed of the semiconductor to form a recess, wherein, The etching agent comprises an oxidizing agent, a corrosive agent, and a nitrogen-containing surfactant. The nitrogen-containing surfactant is selected from at least one of polyethyleneimine, ethylenediamine, diethylenetriamine, triethylenetetramine, tetraethylenepentamine, pentaethylenehexamine, polyoxyethylene alkylamine, and ethylenediamine tetra(propoxide-block-ethoxide)tetraol. The process is performed with a protective layer containing the N-containing surfactant at the upper end of the recess.

2. The etching method according to claim 1, wherein, The precious metal contains gold.

3. The etching method according to claim 1 or 2, wherein, The catalyst layer containing noble metals is porous.

4. The etching method according to claim 1 or 2, wherein, The catalyst layer containing precious metals is formed by displacement plating.

5. The etching method according to claim 1 or 2, wherein, The oxidant is hydrogen peroxide and the corrosive agent is hydrogen fluoride.

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