Electronic device, circuit board, and semiconductor device

Abstract

This disclosure relates to electronic devices, circuit boards, and semiconductor devices. An electronic device includes a semiconductor device and a mounting substrate. The semiconductor device includes a semiconductor chip and a wiring circuit board. The chip includes circuit blocks and first electrode pads. The wiring circuit board includes a first surface and a second surface. The first surface includes second electrode pad wiring. The second surface includes ball electrodes. The first wiring supplies a ground potential to the first circuit block. The second wiring supplies a ground potential to the second circuit block. The second surface includes a first extended pad and a second extended pad. The first extended pad and the second extended pad are positioned at locations where they are connected to each other on the second surface side via a single ball electrode.

Description

Technical Field

[0001] This disclosure relates to electronic devices, circuit boards, and semiconductor devices. Background Technology

[0002] It is important to reduce electromagnetic interference (EMI) in semiconductor devices while improving electromagnetic susceptibility (EMS). EMI reduction can be achieved by reducing the unwanted distribution of electromagnetic noise. EMS improvement is achieved by increasing resistance to electromagnetic noise. Japanese Patent Publication No. 2005-340741 proposes providing multiple terminals for individually supplying ground potential to multiple circuit blocks mounted in a semiconductor device. This achieves a shared ground potential among multiple circuit blocks while preventing multiple circuit blocks from sharing a common impedance. Therefore, electromagnetic noise occurring in one particular circuit block is less likely to infiltrate into another circuit block. That is, EMI is reduced.

[0003] Japanese Patent Publication No. 2021-044458 proposes providing separate grounding wiring for multiple circuit blocks, connecting bonding pads to the corresponding grounding wiring, and connecting extension pads to the bonding pads via bonding wires. Furthermore, the impedance of the grounding wiring is adjusted by connecting multiple extension pads with wires. Therefore, EMI is reduced and EMS is improved.

[0004] Incidentally, semiconductor devices are mounted on various mounting substrates with different designs, thus requiring EMI reduction and EMS improvement for each substrate on which the semiconductor devices are mounted. According to Japanese Patent Publication No. 2021-044458, impedance reduction and EMS improvement are achieved by adjusting the impedance using multiple extended pads connected or not connected via wire bonding. However, adjusting impedance via wire bonding is not easy. Since the wire bonding used for impedance adjustment may interfere with other wiring, the freedom of wire bonding arrangement is limited. Summary of the Invention

[0005] This disclosure provides an electronic device comprising: a semiconductor device including a semiconductor chip having a plurality of circuit blocks and a plurality of first electrode pads connected to any of the circuit blocks, a wiring circuit board on which the semiconductor chip is mounted, and a seal sealing the semiconductor chip on the wiring circuit board; and a mounting substrate on which the semiconductor device is mounted, wherein the wiring circuit board includes a first surface on which the semiconductor chip is mounted and a second surface facing the mounting substrate, the first surface including: a plurality of second electrode pads connected by wires to the plurality of first electrode pads disposed on the semiconductor chip and a plurality of wirings connected to any of the plurality of second electrode pads, the second surface including wirings connected to... Any of the plurality of wirings and a plurality of ball electrodes configured to contact a plurality of opposing pads disposed on a mounting substrate, the first wiring of the plurality of wirings being a ground wiring for supplying ground potential to a first circuit block of the plurality of circuit blocks, the second wiring of the plurality of wirings being a ground wiring for supplying ground potential to a second circuit block of the plurality of circuit blocks, the second surface further including a first extended pad connected to the first ball electrode connected to the first wiring and a second extended pad connected to the second ball electrode connected to the second wiring, and the first extended pad and the second extended pad being disposed at a location where the first extended pad and the second extended pad are connected to each other on the second surface side by a single ball electrode.

[0006] This disclosure may provide a circuit board comprising: a semiconductor chip having a plurality of circuit blocks and a plurality of first electrode pads connected to any of the circuit blocks; a first surface on which the semiconductor chip is mounted; and a second surface facing a mounting substrate on which a wiring circuit board is mounted, wherein the first surface includes: a plurality of second electrode pads connected by wires to the plurality of first electrode pads disposed on the semiconductor chip, and a plurality of wirings connected to the plurality of second electrode pads; the second surface includes a plurality of ball electrodes connected to any of the wirings and deployed to contact any of the plurality of opposing pads disposed on the mounting substrate; a first wiring of the plurality of wirings is a ground wiring for supplying a ground potential to a first circuit block of the plurality of circuit blocks, and a second wiring of the plurality of wirings is a ground wiring for supplying a ground potential to a second circuit block of the plurality of circuit blocks; the second surface further includes a first extended pad connected to a first ball electrode connected to a first wiring and a second extended pad connected to a second ball electrode connected to a second wiring, and the first extended pad and the second extended pad are deployed at a location where the first extended pad and the second extended pad are connected to each other on the second surface side by a single ball electrode.

[0007] This disclosure may also provide a semiconductor device, comprising: a semiconductor chip having a plurality of circuit blocks and a plurality of first electrode pads connected to any of the circuit blocks; a wiring circuit board having the semiconductor chip mounted thereon; and a sealant sealing the semiconductor chip on the wiring circuit board, wherein the wiring circuit board includes: a first surface on which the semiconductor chip is mounted and a second surface facing a mounting substrate on which the semiconductor device is mounted, the first surface including: a plurality of second electrode pads connected by wires to the plurality of first electrode pads disposed on the semiconductor chip and a plurality of wirings connected to any of the plurality of second electrode pads, and the second surface including any of the wirings connected to the plurality of wirings. The second surface further includes a first extension pad connected to the first ball electrode connected to the first ball electrode connected to the first wiring and a second extension pad connected to the second ball electrode connected to the second wiring. The first extension pad and the second extension pad are deployed at a location where the first extension pad and the second extension pad are connected to each other on the second surface side via a single ball electrode.

[0008] Further features of the invention will become clear from the following description of exemplary embodiments (with reference to the accompanying drawings). Attached Figure Description

[0009] Figure 1 This is a perspective view of the illustrated electronic device.

[0010] Figure 2 This is a plan view of the semiconductor device.

[0011] Figure 3 This is a plan view of a semiconductor chip.

[0012] Figure 4 This is a plan view of the wiring pattern on the front surface of the circuit board.

[0013] Figure 5 This is a plan view of the wiring pattern on the rear surface side of the circuit board.

[0014] Figure 6A and Figure 6B This is a side view of the layers of the circuit board shown in the diagram.

[0015] Figure 7 This is a plan view illustrating the wiring pattern on the front surface of the mounting substrate.

[0016] Figure 8A and Figure 8BThis is a plan view of the wiring pattern on the rear surface side of the circuit board.

[0017] Figure 9 This is a plan view of the wiring pattern on the rear surface side of the circuit board.

[0018] Figure 10 This is a plan view illustrating the wiring pattern on the front surface of the mounting substrate.

[0019] Figure 11 This is a side view of the layers of the circuit board shown in the diagram. Detailed Implementation

[0020] In the following, embodiments will be described in detail with reference to the accompanying drawings. It should be noted that the following embodiments are not intended to limit the scope of the claimed invention. Several features are described in the embodiments, but this is not a limitation to an invention claiming all such features, and multiple such features may be appropriately combined. Furthermore, in the drawings, the same or similar structures are given the same reference numerals, and redundant descriptions thereof are omitted.

[0021] First Embodiment

[0022] Structure of semiconductor devices

[0023] like Figure 1 As shown, in the electronic device 100, a semiconductor device 1 is mounted on a mounting substrate 10. The semiconductor device 1 includes a semiconductor chip 2, a wiring circuit board 4, bonding wires 6, a seal 7, and ball electrodes 9. The semiconductor chip 2 is mounted on a first surface 31 of the wiring circuit board 4. The bonding wires 6 are conductive and electrically connect the semiconductor chip 2 and the wiring circuit board 4. The seal 7, made of resin, seals the semiconductor chip 2 and the multiple bonding wires 6 to the wiring circuit board 4. Multiple ball electrodes 9 are deployed on a second surface 32 of the wiring circuit board 4. The second surface 32 is the surface opposite to the first surface 31; therefore, the first surface 31 can also be referred to as the "front surface" or "top surface," and the second surface 32 can also be referred to as the "rear surface" or "bottom surface." Each ball electrode 9 is a type of external terminal. In this way, the semiconductor device 1 is a ball grid array (BGA) semiconductor package.

[0024] Wiring circuit boards and semiconductor chips

[0025] like Figure 2As shown, the semiconductor chip 2 is mounted at the center of the wiring circuit board 4. The semiconductor chip 2 includes multiple circuit blocks formed on a semiconductor wafer made of silicon or the like. Multiple electrode pads 3 are deployed near each of the four sides of the semiconductor chip 2. Each electrode pad 3 can be a power terminal for supplying power voltage and ground potential to the circuit blocks disposed on the semiconductor chip 2, a signal terminal for inputting signals to the circuit blocks, or a signal terminal for outputting signals from the circuit blocks.

[0026] The wiring circuit board 4 is, for example, an electronic circuit board in which a wiring pattern is formed using copper foil on a resin board. The wiring circuit board 4 includes bonding pad areas 51, 52, 53, and 54. The bonding pad areas 51, 52, 53, and 54 are arranged to face a plurality of electrode pads 3 disposed near the side of the semiconductor chip 2. A plurality of bonding pads 5 are disposed in the bonding pad areas 51, 52, 53, and 54. The plurality of bonding pads 5 are electrically connected to the electrode pads 3 via bonding lines 6. The plurality of bonding pads 5 are electrically connected to ball electrodes 9 disposed on the second surface 32 of the wiring circuit board 4 via vias, etc. Typically, vias are non-through-hole holes that electrically connect multiple layers. The semiconductor chip 2 outputs / receives signals to / from the outside via the ball electrodes 9 and receives / supplyes power supply voltage and ground potential.

[0027] Structure of semiconductor chips

[0028] like Figure 3 As shown, semiconductor chip 2 includes multiple circuit blocks. For example, these multiple circuit blocks include OSC 21, PLL 22, REG 23, ROM 24, CPU 25, RAM 26, logic 27, and ADC 28. When describing common aspects of multiple components, lowercase letters added to the end of the reference numerals assigned to the multiple components may be omitted.

[0029] OSC 21 is an oscillation circuit used to generate a reference clock signal based on an input signal from a crystal oscillator external to semiconductor chip 2. OSC 21 is connected to electrode pads 3g and 3h. Electrode pad 3g is used to receive the power supply voltage VCC_OSC. Electrode pad 3h is used to receive the ground potential (hereinafter also referred to as "GND potential") GND_OSC.

[0030] PLL 22 is a phase synchronization circuit that multiplies the frequency of the reference clock signal generated by OSC 21. PLL 22 is connected to electrode pads 3e and 3f. Electrode pad 3e is used to receive the power supply voltage VDD_PLL. Electrode pad 3f is used to receive the GND potential GND_PLL. OSC 21 and PLL 22 are circuits used to generate various clock signals based on the reference clock signal. The voltage level of the clock signal changes repeatedly. Therefore, oscillation noise may occur due to the clock signal. Oscillation noise can seep from one circuit block to another through the common impedance between multiple circuit blocks. Therefore, oscillation noise may increase the level of radiated noise, which is a major cause of EMI. In the first embodiment, in order to reduce EMI within the semiconductor chip 2, multiple power supply lines for supplying the power supply voltage are separated between multiple circuit blocks, and multiple ground lines for supplying the GND potential (hereinafter referred to as "GND lines") are also separated between multiple circuit blocks. Therefore, the multiple circuit blocks do not have a common impedance.

[0031] REG 23 is a linear regulator circuit used to generate a power supply voltage to be used inside the semiconductor chip 2 based on the power supply voltage supplied from an external power supply device 1. REG 23 is connected to electrode pads 3a, 3b, and 3c. Electrode pad 3a is used to receive the power supply voltage VDD supplied from the external power supply device. Electrode pad 3b is used to receive the GND potential GND_REG. Electrode pad 3c is used to output the power supply voltage VCC_REG generated by REG 23.

[0032] ROM 24 is a non-volatile memory that stores the control program to be executed by CPU 25. ROM 24 is connected to electrode pads 3i and 3j. Electrode pad 3i is used to receive the power supply voltage VCC_ROM. Electrode pad 3j is used to receive the GND potential GND_ROM. CPU 25 reads the control program stored in ROM 24 and performs various types of calculations according to the control program.

[0033] RAM 26 is volatile memory. RAM 26 temporarily stores data that will undergo computational processing by CPU 25.

[0034] Logic 27 includes hardware circuitry, such as communication circuitry or timer circuitry. Logic 27 performs operations corresponding to instructions output from CPU 25.

[0035] ADC 28 is an analog-to-digital converter circuit that converts analog signals input from external terminals into digital signals. ADC 28 is connected to electrode pads 3n and 3m. Electrode pad 3n is used to receive the power supply voltage VCC_ADC. Electrode pad 3m is used to receive the GND potential GND_ADC.

[0036] like Figure 3 As shown, CPU 25, RAM 26, and logic 27 are connected to electrode pads 3c, 3d, 3k, 3l, and 3o. Electrode pad 3c supplies a common power supply voltage VDD to CPU 25, RAM 26, and logic 27. Electrode pads 3d, 3k, 3l, and 3o supply a common GND potential CGND to CPU 25, RAM 26, and logic 27. In this first embodiment, each circuit block requires a different power supply voltage. Therefore, there are power supply voltages VDD and VCC.

[0037] Wiring pattern of a wiring circuit board

[0038] Figure 4 An example of a wiring pattern 11 disposed on a first surface 31 of a wiring circuit board 4 is shown. A semiconductor chip 2 is mounted on the first surface 31 in an area surrounded by dotted lines. Seventeen bonding pads 5 are arranged in two rows in each of bonding pad areas 51, 52, 53, and 54. Figure 4 In the wiring pattern 11 connecting to the bonding pads 5 located in bonding pad areas 51, 52, 53, and 54, the GND wiring used to supply ground potential (e.g., GND_PLL and CGND) is shaded. The bonding pads 5 other than those with GND wiring are not shaded. That is, the remaining bonding pads 5 are indicated by hollow patterns. The bonding pads 5 indicated by hollow patterns are connected to electrode pads 3, each electrode pad 3 serving as one of the signal input terminal, signal output terminal, and power supply terminal of the semiconductor chip 2. One end of the wiring pattern 11 connected to the bonding pads 5 indicated by hollow patterns is connected to a via 8. The via 8 is electrically connected to a ball electrode 9 deployed on the second surface 32 of the wiring board 4. Figure 4 As shown, the other end of all wiring patterns 11 extends to the side (end) of the wiring circuit board 4. In this way, through holes 8 are provided at one end of the wiring pattern 11, and the other end of the wiring pattern 11 extends to the side of the wiring circuit board 4, and bonding pads 5 are provided at approximately the center of the wiring pattern 11.

[0039] A circle indicating a via 8 is added to one end of the wiring pattern 11 connected to the bonding pads 5 for power supply voltages VDD_PLL, VDD, VCC_REG, VCC_ADC, VCC_OSC, and VCC_ROM. A circle also indicating a via 8 is added to the wiring pattern 11 connected to the bonding pads 5 for GND potentials GND_PLL, GND, GND_REG, GND_ADC, GND_OSC, and GND_ROM. Figure 4 As shown, wiring patterns 11 for the GND potential CGND are respectively disposed on the four sides of the wiring circuit board 4. The four wiring patterns 11 for the GND potential CGND are connected to each other via GND wiring 41 disposed in the central portion of the wiring circuit board 4. Wiring pattern 11 for the GND potential GND_PLL is connected to GND wiring 42. Wiring pattern 11 for the GND potential GND_REG is connected to GND wiring 43.

[0040] exist Figure 4 In the above configuration, bonding pad 5d is connected to GND wiring 41 for GND potential CGND via wiring pattern 11. Bonding pad 5f is connected to GND wiring 42 for GND potential GND_PLL via wiring pattern 11. Bonding pad 5b is connected to GND wiring 43 for GND potential GND_REG via wiring pattern 11.

[0041] Bond pad 5o is connected to GND wiring 41 for GND potential CGND via wiring pattern 11. Bond pad 5m is connected to GND wiring 44 for GND potential GND_ADC via wiring pattern 11. Bond pad 5k is connected to GND wiring 41 for GND potential CGND via wiring pattern 11. Bond pad 5j is connected to GND wiring 45 for GND potential GND_ROM via wiring pattern 11. Bond pad 5h is connected to GND wiring 46 for GND potential GND_OSC via wiring pattern 11.

[0042] The wiring patterns 11 for power supply voltages VDD_PLL, VDD, VCC_REG, VCC_ADC, VCC_OSC, and VCC_ROM are separate from each other. The bonding pads 5 of the wiring patterns 11 for these power supply voltages are connected to the corresponding electrode pads 3. The wiring patterns 11 for GND potentials GND_PLL, GND, GND_REG, GND_ADC, GND_OSC, and GND_ROM are also separate from each other. The bonding pads 5 of the wiring patterns 11 for these GND potentials are also connected to the corresponding electrode pads 3.

[0043] The greater the number of power lines and GND lines, the greater the reduction in wiring efficiency on the mounting substrate 10. If the number of substrate layers constituting the mounting substrate 10 is small (e.g., two layers), the wiring efficiency may be further reduced. As a result, the individual impedance of a power line or a GND line may be too high to be ignored.

[0044] Figure 5 An example of a wiring pattern disposed on the second surface 32 of the wiring circuit board 4 is shown. It should be noted that... Figure 5 The viewpoint is located on the second surface 32 side of the wiring circuit board 4, and Figure 5 It shows Figure 4 The horizontally flipped image of the first surface 31 shown. Figure 5 The area near the rear surface of the bonding pad region 51 is shown. GND wiring 61 is connected to GND wiring 41 disposed on the first surface 31 via a plurality of vias 8a. Furthermore, GND wiring 61 is connected to bonding pad 5d via GND wiring 41. GND wiring 62 is connected to GND wiring 42 on the first surface 31 via vias 8b. GND wiring 62 is also connected to bonding pad 5f via GND wiring 42. GND wiring 63 is connected to GND wiring 43 on the first surface 31 via vias 8c. GND wiring 63 is also connected to bonding pad 5b via GND wiring 43. Wiring patterns (indicated by hollow patterns) of wiring other than GND wiring are connected to the corresponding bonding pads 5 via vias 8.

[0045] Ball electrodes 9 can be provided for multiple bonding pads located in bonding pad region 51. For example, ball electrode 9d is provided for bonding pad 5d via GND wiring 41, via 8a, and GND wiring 61. That is, they are electrically connected. Similarly, ball electrode 9f is connected to bonding pad 5f via GND wiring 42, via 8b, and GND wiring 62. Ball electrode 9b is connected to bonding pad 5b via GND wiring 43, via 8c, and GND wiring 63. Thus, multiple bonding pads 5 located in bonding pad region 51 can be electrically connected to mounting substrate 10 via ball electrodes 9. When ball electrode 9 is mounted on extension pad 101, GND wiring 61 and GND wiring 62 are connected via ball electrode 9. When ball electrode 9 is provided on extension pad 102, GND wiring 61 and GND wiring 63 are connected via ball electrode 9.

[0046] Figure 6AThis is a side view of the wiring circuit board 4 without ball electrodes 9 on the extended pads 101 and 102. Various traces (power traces, signal traces, GND traces, etc.) are formed on the front and back layers of the substrate 71 using copper foil. The surface of the copper foil is covered with resist 73. In this example, GND traces 61 and 62 are provided on the back layer of the substrate 71. Traces 72 are provided on the front layer of the substrate 71. Traces 72 are composed of various traces including GND traces 61, 62, and 63. GND traces 61, 62, and 63 can be provided on two layers.

[0047] Extended pads 101 are provided for connecting GND wiring 61 and GND wiring 62. Similarly, extended pads 102 are provided for connecting GND wiring 61 and GND wiring 63. Extended pads 101 are formed by exposed copper foil 103a of GND wiring 61 and exposed copper foil 103b of GND wiring 62. Extended pads 102 are formed by exposed copper foil 103c of GND wiring 61 and exposed copper foil 103d of GND wiring 63. The exposed copper foils 103a to 103d are formed by not providing resist 73 or by removing a portion of them after providing resist 73. It should be noted that the exposed copper foils 103a to 103d serve as electrodes, and therefore each of the exposed copper foils 103a to 103d may sometimes be referred to as an "extended pad".

[0048] exist Figure 6B In this configuration, ball electrodes 9r and 9s are respectively disposed on extension pads 101 and 102. Therefore, GND wiring 61 and GND wiring 62 are connected, and GND wiring 63 is also connected.

[0049] Connection between semiconductor device and mounting substrate

[0050] Figure 7This diagram illustrates an example of a wiring pattern on a mounting substrate 10. A ball electrode 9 of the semiconductor device 1 is placed on a circular connecting pad 90 located in regions 60a and 60b on the front surface side of the mounting substrate 10. Thus, the connecting pad 90 and the ball electrode 9 are electrically connected. A GND wiring 91, disposed on the front surface side of the mounting substrate 10, forms a GND wiring pattern on the mounting substrate 10. The GND wiring 91 is connected to a GND wiring 61 on the second surface 32 of the wiring circuit board 4 via the connecting pad 90d and the ball electrode 9d, and is also connected to a GND wiring 41 on the first surface 31 of the wiring circuit board 4. A GND wiring 92 is also a GND wiring pattern on the mounting substrate 10. A GND wiring 93 is connected to a GND wiring 63 on the second surface 32 of the wiring circuit board 4 via the connecting pad 90b and the ball electrode 9b, and is also connected to a GND wiring 43 on the first surface 31 of the wiring circuit board 4. The GND wiring 92 also forms a GND wiring pattern on the mounting substrate 10. GND wiring 92 is connected to GND wiring 62 on the second surface 32 of wiring circuit board 4 via connecting pad 90f and ball electrode 9f, and is also connected to GND wiring 42 on the first surface 31 of wiring circuit board 4.

[0051] Each wiring pattern 96, indicated as an open pattern, is a signal or power wiring. A circular pad 90 is provided at one end of the wiring pattern 96, and a through-hole 94 is provided at the other end. Typically, a through-hole 94 refers to a hole extending through the substrate into which leads of an electronic device are inserted, but in this embodiment, it can also be an interstitial via into which no leads are inserted. GND wirings 91, 92, and 93 are electrically connected at position 95. Position 95 is separated from the pad 90 of any wiring pattern 96 that contacts the ball electrode 9 of the semiconductor device 1. In the first embodiment, the pad 90 is not provided around the through-hole and can therefore also be referred to as a "pad".

[0052] For example, when the individual impedance of GND wiring 42 on wiring board 4 is higher than that of GND wiring 41, semiconductor chip 2 may fail due to EMS. EMS causes a change in the ground potential of each GND wiring. Therefore, GND wiring 42 with its high individual impedance causes clock distortion generated by PLL 22. CPU 25 operates based on the clock signal supplied from PLL 22. Therefore, the timing of CPU 25's operation becomes inconsistent, and, for example, CPU 25 enters an error state such as a bus failure.

[0053] There is also a situation where the individual impedance of GND wiring 43 on the wiring board 4 is higher than that of GND wiring 41. In this case, semiconductor chip 2 may fail due to EMS. That is, EMS changes the ground potential of each GND wiring. Therefore, the high individual impedance of GND wiring 43 causes distortion of the reference voltage generated by REG 23. CPU 25 operates based on the voltage supplied from REG 23. Therefore, CPU 25 may fail.

[0054] In the first embodiment, an extension pad 101 for connecting GND wiring 61 and GND wiring 62 is provided on the second surface 32 of the wiring circuit board 4 to avoid this erroneous state. The extension pad 101 is deployed between the ball electrode 9 provided on the second surface 32 side and GND wiring 61. GND wiring 61 is connected to GND wiring 41. GND wiring 62 is connected to GND wiring 42. When the individual impedance of GND wiring 42 is higher than that of GND wiring 41, GND wiring 61 and GND wiring 62 are electrically connected by mounting the ball electrode 9 on the extension pad 101. Therefore, the individual impedance of GND wiring 42 of PLL 22 becomes lower, and PLL 22 is less likely to fail. That is, EMS is improved.

[0055] like Figure 5 As shown, an extension pad 102 for connecting GND wiring 61 and GND wiring 63 is deployed between GND wiring 63 and GND wiring 61, which are connected to ball electrode 9b. GND wiring 61 is connected to GND wiring 41 via via 8a. GND wiring 63 is connected to GND wiring 43 via via 8c. When the individual impedance of GND wiring 43 is higher than that of GND wiring 41, GND wiring 61 and GND wiring 63 are electrically connected by mounting ball electrode 9 on extension pad 102. Therefore, the individual impedance of GND wiring 43 of REG 23 becomes lower, and REG 23 is less likely to fail. That is, EMS is improved.

[0056] exist Figure 5 In the example, extension pads 101 and 102 are provided; this is merely an example. Extension pads can be added to connect GND wiring 61 to GND wiring for one of the GND potentials GND_ADC, GND_OSC, and GND_ROM.

[0057] Figure 8AAn extended pad 104 is shown connecting the GND wiring 61 disposed on the second surface 32 side to the GND wiring 111 for the GND_ADC. The GND wiring 111 includes a ball electrode 9 and a via 8. The ball electrode 9 is positioned to make electrical contact with the pad on the mounting substrate 10. The via 8 electrically connects the GND wiring 111 to the GND wiring 44 for the GND_ADC disposed on the first surface 31 side. Therefore, the GND wiring 61, GND wiring 111, and GND wiring 41 can be electrically connected via the ball electrode 9 disposed on the extended pad 104. Consequently, individual impedances can be adjusted.

[0058] Figure 8B The connection pad 105 between the GND wiring 61 disposed on the second surface 32 side and the GND wiring 121 for GND_OSC is shown. Figure 8B An extended pad 106 connecting the GND wiring 61 disposed on the second surface 32 side to the GND wiring 122 for GND_ROM is also shown. The GND wiring 121 includes a ball electrode 9 and a via 8. The ball electrode 9 is deployed to make electrical contact with the pad on the mounting substrate 10. The via 8 electrically connects the GND wiring 121 to the GND wiring 46 disposed on the first surface 31 side for GND potential GND_OSC. Therefore, the GND wiring 61, GND wiring 121, and GND wiring 41 can be electrically connected via the ball electrode 9 disposed on the extended pad 105. Thus, individual impedances can be adjusted. The GND wiring 122 includes a ball electrode 9 and a via 8. The ball electrode 9 is deployed to make electrical contact with the pad on the mounting substrate 10. The via 8 electrically connects the GND wiring 122 to the GND wiring 45 disposed on the first surface 31 side for GND potential GND_ROM. Therefore, GND wiring 61, GND wiring 122, and GND wiring 41 can be electrically connected via ball electrodes 9 disposed on the extension pad 106. Thus, individual impedances can be adjusted.

[0059] According to the first embodiment, extended pads 101 to 106 are deployed on the second surface 32 of the wiring circuit board 4. Depending on whether ball electrodes 9 are provided on the extended pads 101 to 106, the connection and separation of the wiring pattern on the first surface 31 side and the wiring pattern on the second surface 32 side can be switched. Therefore, individual impedance and common impedance can be adjusted. Furthermore, the designer can choose whether to reduce EMI or prioritize improving EMS by using the extended pads 101 to 106. That is, the freedom of routing on the mounting substrate 10 is increased.

[0060] According to the first embodiment, impedance adjustment is achieved based on whether the ball electrode 9 is connected to the extension pads 101 to 106. If the mounting substrate 10 is changed to reduce manufacturing costs, the impedance conditions change, and therefore a version of the wiring board 4 may need to be revised. However, in the first embodiment, the impedance can be adjusted based on the presence or absence of the ball electrode 9, so there is no need to revise the version of the wiring board 4, thereby reducing manufacturing costs. Even after the semiconductor device 1 is packaged, the combination of the presence or absence of the ball electrode 9 can be changed, thus increasing the design freedom of the electronic device 100 including the semiconductor device 1 and the mounting substrate 10.

[0061] Second Embodiment

[0062] According to the first embodiment, the extended pads 101 to 106 and the ball electrode 9 connect two traces. Therefore, in the second embodiment, it is proposed to use one extended pad and one ball electrode 9 to connect three GND traces. In the second embodiment, descriptions of matters identical or similar to those in the first embodiment are omitted, and the descriptions in the first embodiment apply.

[0063] Wiring pattern of a wiring circuit board

[0064] Figure 9 An example of the wiring pattern on the second surface 32 side of the wiring circuit board 4 is shown. Figure 9 In, with Figure 5 Compared to the previous version, GND wiring 61, GND wiring 62, and GND wiring 63 extend longer in the y-direction. Furthermore, an extension pad 107 is provided at the closest points of GND wiring 61, GND wiring 62, and GND wiring 63 to each other. The extension pad 107 includes exposed copper foils 103a, 103b, and 103d. Exposed copper foil 103a is part of GND wiring 61. Exposed copper foil 103b is part of GND wiring 62. Exposed copper foil 103d is part of GND wiring 63. GND wiring 61, GND wiring 62, and GND wiring 63 are electrically connected together by a ball electrode 9 disposed on the extension pad 107.

[0065] Connection between semiconductor device and mounting substrate

[0066] Figure 10 It is the same as in the first embodiment. Figure 7 The corresponding figure shows the front surface side of the mounting substrate 10. Figure 10 In the middle, a portion of the GND wiring 91 is larger in the y-direction than Figure 7The ball electrode 9 extends further and connects to a circular connecting pad 90t disposed in region 60c on the front surface side of the mounting substrate 10. The position of the connecting pad 90t in the xy coordinates matches the position of the extended pad 107 in the xy coordinates. Once the ball electrode 9 is placed on the connecting pad 90t, the connecting pad 90t is electrically connected to the ball electrode 9. Moreover, in the extended pad 107, the ball electrode 9 is electrically connected to GND wiring 61, GND wiring 62, and GND wiring 63. In addition, GND wiring 91 is connected to GND wiring 61 and GND wiring 41 of the wiring board 4. GND wiring 93 is also connected to GND wiring 63 and GND wiring 43 via the connecting pad 90 and the ball electrode 9. GND wiring 92 is also connected to GND wiring 62 and GND wiring 42 via the connecting pad 90 and the ball electrode 9.

[0067] As described in the first embodiment, the semiconductor chip 2 may malfunction when the individual impedances of GND wiring 42 and GND wiring 43 are higher than the individual impedance of GND wiring 41. That is, when the ground potential of each GND wiring changes, the higher individual impedances of GND wiring 42 and GND wiring 43 cause distortion in the clock generated by PLL 22. Alternatively, distortion may occur in the reference voltage generated by REG 23. These can cause malfunctions in the CPU 25, etc.

[0068] In the second embodiment, an extension pad 107 connecting GND wirings 61, 62, and 63 is provided on the second surface 32 side of the wiring circuit board 4. When the individual impedance of GND wirings 42 and 43 is higher than that of GND wiring 41, GND wirings 61, 62, and 63 are electrically connected by mounting a ball electrode 9 on the extension pad 107. Therefore, the individual impedance of GND wiring 42 of PLL 22 becomes lower, EMS is improved, and PLL 22 is less likely to fail. Furthermore, the individual impedance of GND wiring 43 of REG 23 also decreases, thus improving EMS and making REG 23 less likely to fail.

[0069] In the second embodiment, three GND traces are connected via a ball electrode and an extension pad, but this is merely exemplary. Four or more GND traces can be connected via a ball electrode and an extension pad. Other advantages of the second embodiment are the same as those of the first embodiment, and therefore their description is omitted.

[0070] Third Embodiment

[0071] In the first and second embodiments, the wiring circuit board 4 has two layers. In the third embodiment, a wiring circuit board 4 comprising three or more layers will be described. In the third embodiment, descriptions of matters identical or similar to those in the first and second embodiments are omitted, and the descriptions in the first and second embodiments apply.

[0072] Wiring pattern of a wiring circuit board

[0073] Figure 11 The wiring circuit board 4 shown has four wiring layers. That is, the wiring circuit board 4 includes layers L1 to L4. Substrate 71 is disposed between adjacent layers. GND wiring 61 is disposed in layer L4. GND wiring 62 is disposed in layer L3. GND wiring 63 is disposed on layer L2. GND wiring 62 disposed in layer L3 extends to layer L4 due to via 151. Extended pad 108 is composed of exposed copper foil 103e of GND wiring 62 and exposed copper foil 103f of GND wiring 61, the foils being exposed from layer L4. GND wiring 61 and GND wiring 62 are electrically connected by ball electrode 9 disposed on extended pad 108. GND wiring 63 disposed on layer L2 extends to layer L4 due to via 152. Extended pad 109 is composed of exposed copper foil 103h of GND wiring 63 and exposed copper foil 103g of GND wiring 61, the foils being exposed from layer L4. GND wiring 61 and GND wiring 63 are electrically connected via ball electrodes 9 disposed on extension pad 109.

[0074] Furthermore, in the third embodiment, similar to the first embodiment, when the individual impedance of GND wiring 42 is higher than that of GND wiring 41, a ball electrode 9 is mounted on the extension pad 108. Therefore, GND wiring 61 and GND wiring 62 are electrically connected. As a result, the individual impedance of GND wiring 42 of PLL 22 becomes lower, EMS is improved, and PLL 22 is less likely to fail. When the individual impedance of GND wiring 43 is higher than that of GND wiring 41, a ball electrode 9 is provided on the extension pad 109. Therefore, GND wiring 61 and GND wiring 63 are electrically connected, and the individual impedance of GND wiring 43 of REG 23 becomes lower. Therefore, EMS of REG 23 is improved, and REG 23 is less likely to fail.

[0075] As a result of the wiring circuit board 4 having multiple layers, the GND wiring can be distributed across multiple layers. Therefore, the GND wiring connected to the extension pads 108 and 109 can be thicker in the wiring circuit board 4, and the individual impedance can be lower. Other advantages of the third embodiment are the same as those of the first embodiment, and therefore their description is omitted.

[0076] Technical concepts derived from the embodiments

[0077] Viewpoints 1, 13, and 14

[0078] like Figure 1 As shown, the semiconductor device 1 may include a semiconductor chip 2, a wiring circuit board 4 on which the semiconductor chip 2 is mounted, and a seal 7 sealing the semiconductor chip 2 on the wiring circuit board. The semiconductor chip 2 includes multiple circuit blocks and multiple first electrode pads (e.g., electrode pads 3) connected to the multiple circuit blocks. The electronic device 100 includes the semiconductor device 1 and a mounting substrate 10 on which the semiconductor device 1 is mounted. The wiring circuit board 4 may include a first surface 31 on which the semiconductor chip 2 is mounted and a second surface 32 opposite to the mounting substrate 10. The first surface 31 includes multiple second electrode pads (e.g., multiple bonding pads 5) connected to the multiple first electrode pads disposed on the semiconductor chip 2 by wires. The first surface 31 may also include multiple wirings (GND wirings 41 to 46) connected to the multiple bonding pads. The second surface 32 may include multiple ball electrodes 9 deployed to contact multiple opposing pads (e.g., connection pads 90) disposed on the mounting substrate 10. The first wiring (e.g., GND wiring 41) among the multiple wirings is a grounding wiring used to supply ground potential to a first circuit block (e.g., CPU 25, RAM 26) among the multiple circuit blocks. The second wiring (e.g., GND wiring 42) among the multiple wirings is a grounding wiring used to supply ground potential to a second circuit block (e.g., PLL 22) among the multiple circuit blocks. The second surface 32 may also include a first extended pad (e.g., exposed copper foil 103a) and a second extended pad (e.g., exposed copper foil 103b). The first extended pad is a pad connected to a first ball electrode (e.g., ball electrode 9d) connected to the first wiring. The second extended pad is a pad connected to a second ball electrode (e.g., ball electrode 9f) connected to the second wiring. Figure 6A and Figure 6B As shown, the first and second extension pads are deployed at locations where these extension pads can be connected to each other on the second surface 32 using a single ball electrode 9r. Conventionally, multiple GND traces are connected using bonding wires, which presents various difficulties. However, according to the first to third embodiments, multiple GND traces can be connected using extension pads and ball electrodes. Therefore, compared to the past, it is easier to achieve EMI reduction and EMS improvement.

[0079] Viewpoint 2

[0080] Before connecting the first and second extension pads using a single ball electrode 9r, the individual impedance of the second trace is higher than that of the first trace. In this case, after connecting the first and second extension pads using a single ball electrode 9r, the individual impedance of the second trace becomes lower. By performing this impedance adjustment, EMI reduction and EMS improvement are achieved more easily than before.

[0081] Viewpoint 3

[0082] For reference Figure 5 As described, via 8a is an example of a first via for connecting a first wiring and a first extended pad. Via 8b is an example of a second via for connecting a second wiring and a second extended pad. By using vias 8 in this manner, electrical continuity can be more easily established between the wiring on the first surface 31 side of the wiring board 4 and the extended pad on the second surface 32 side.

[0083] Viewpoint 4

[0084] GND wiring 61 is disposed on the second surface 32 or inside the wiring board 4, and is an example of a first ground pattern connecting the first ball electrode (e.g., ball electrode 9d) and the first extended pad. GND wiring 62 is disposed on the second surface 32 or inside the wiring board 4, and is an example of a second ground pattern connecting the second ball electrode (e.g., ball electrode 9f) and the second extended pad. In this way, by further distributing GND wiring on the second surface 32 or inside the wiring board 4, EMI reduction and EMS improvement are achieved more easily than before.

[0085] Viewpoint 5

[0086] like Figure 6A and Figure 6B As shown, the first ground pattern and the second ground pattern can be deployed in the same layer inside the wiring circuit board 4. In this case, the first extended pad is a portion of the first ground pattern exposed on the second surface side (e.g., exposed copper foil 103a). The second extended pad is a portion of the second ground pattern exposed on the second surface side (e.g., exposed copper foil 103b).

[0087] Viewpoint 6

[0088] like Figure 11As shown, the first ground pattern can also be deployed in a first layer (e.g., layer L4) inside the wiring board. The second ground pattern can also be deployed in a second layer (e.g., layer L3) inside the wiring board. In this case, the first extended pad is a portion of the first ground pattern exposed on the second surface side (e.g., exposed copper foil 103f). The second extended pad is a portion of the second ground pattern disposed in the second layer, extending to the first layer and exposed on the second surface side (e.g., exposed copper foil 103e). By employing this multilayer structure, the ground pattern can be thicker, and the individual impedance can be reduced. Therefore, compared to the past, it is easier to achieve EMI reduction and EMS improvement.

[0089] Viewpoint 7

[0090] like Figure 7 As shown, the mounting substrate 10 may further include wiring groups (e.g., GND wirings 91 and 92) connecting a first opposing pad (e.g., connection pad 90d) that contacts the first ball electrode and a second opposing pad (e.g., connection pad 90f) that contacts the second ball electrode.

[0091] Viewpoint 8

[0092] The third trace (e.g., GND trace 43) among the multiple traces disposed on the wiring board 4 is a ground trace used to supply ground potential to the third circuit block (e.g., REG 23) among the multiple circuit blocks. Ball electrode 9b is an example of a third ball electrode connected to the third trace. Exposed copper foil 103d is an example of a third extended pad connected to ball electrode 9b. Exposed copper foil 103c is an example of a fourth extended pad connected to the first ball electrode among the multiple ball electrodes disposed on the second surface, which is connected to the first trace. Figure 6A and Figure 6B As shown, the third and fourth extension pads are deployed at locations where these extension pads can be connected to each other on the second surface side using a single ball electrode (e.g., ball electrode 9s).

[0093] Viewpoint 9

[0094] Before connecting the third and fourth extension pads via a single ball electrode, the individual impedance of the third trace can be higher than that of the first trace. In this case, after connecting the third and fourth extension pads using a single ball electrode, the individual impedance of the third trace becomes lower. Therefore, EMI reduction and EMS improvement are more easily achieved compared to the past.

[0095] Viewpoint 10

[0096] like Figure 9As shown, the first, second, and third extension pads can also be deployed at locations where these extension pads can be connected to each other using a single ball electrode on the second surface side. In this way, by connecting the three extension pads to each other using a single ball electrode, it is easier to achieve EMI reduction and EMS improvement compared to the past.

[0097] Viewpoint 11

[0098] Before connecting the first, second, and third extension pads using a single ball electrode, the individual impedance of the second trace can be higher than that of the first trace. Similarly, the individual impedance of the third trace can be higher than that of the first trace. In this case, after connecting the first, second, and third extension pads using a single ball electrode, the individual impedances of both the second and third traces become lower. In this way, because the impedance of multiple traces can be adjusted using a single ball electrode, EMI reduction and EMS improvement are more easily achieved compared to conventional methods.

[0099] Viewpoint 12

[0100] Through-hole 8c is an example of a third through-hole used to connect the third wiring and the third extended pad. By using through-hole 8 in this way, it is easier to establish electrical continuity between the GND wiring 43 on the first surface 31 side of the wiring board 4 and the extended pad (e.g., exposed copper foil 103d) on the second surface 32 side.

[0101] Other embodiments

[0102] One or more embodiments of the present invention can also be implemented by a computer of a system or device that reads and executes computer-executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be more fully referred to as a "non-transitory computer-readable storage medium") to perform the functions of one or more of the above embodiments and / or includes one or more circuits (e.g., application-specific integrated circuits (ASICs)) for performing the functions of one or more of the above embodiments, and by a method performed by a computer of a system or device, for example, by reading and executing computer-executable instructions from the storage medium to perform the functions of one or more of the above embodiments and / or controlling one or more circuits to perform the functions of one or more of the above embodiments. The computer may include one or more processors (e.g., a central processing unit (CPU), a microprocessor unit (MPU)) and may include a network of separate computers or separate processors to read and execute the computer-executable instructions. The computer-executable instructions may be provided to the computer, for example, from a network or a storage medium. The storage medium may include, for example, a hard disk, random access memory (RAM), read-only memory (ROM), storage devices for distributed computing systems, optical discs (such as CDs, DVDs, or Blu-ray discs). TM One or more of the following: flash memory devices, memory cards, etc.

[0103] Other embodiments

[0104] The embodiments of the present invention can also be implemented by providing software (programs) that perform the functions of the above embodiments to a system or device via a network or various storage media, and the computer or central processing unit (CPU) or microprocessor unit (MPU) of the system or device reads out and executes the program.

[0105] While the invention has been described with reference to exemplary embodiments, it should be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation to cover all such modifications and equivalent structures and functions.

Claims

1. An electronic device, characterized in that, The electronic device includes: A semiconductor device includes a semiconductor chip having a plurality of circuit blocks and a plurality of first electrode pads connected to any of the plurality of circuit blocks, a wiring circuit board on which the semiconductor chip is mounted, and a seal sealing the semiconductor chip on the wiring circuit board; and A mounting substrate is on which the semiconductor device is mounted. The wiring circuit board includes a first surface on which the semiconductor chip is mounted and a second surface facing the mounting substrate. The first surface includes: Multiple second electrode pads are connected to the multiple first electrode pads disposed on the semiconductor chip using wires, and Multiple wirings are connected to any of the plurality of second electrode pads. The second surface includes a plurality of ball electrodes connected to any of the plurality of wirings and deployed to contact a plurality of opposing pads disposed on the mounting substrate. The first of the plurality of wirings is a grounding wiring used to supply ground potential to the first circuit block of the plurality of circuit blocks. The second wiring among the plurality of wirings is a grounding wiring used to supply ground potential to the second circuit block among the plurality of circuit blocks. The second surface further includes a first extended pad connected to a first ball electrode connected to the first wiring and a second extended pad connected to a second ball electrode connected to the second wiring, and The first extended pad and the second extended pad are deployed at a location where the first extended pad and the second extended pad are connected to each other on the second surface side by a single ball electrode.

2. The electronic device according to claim 1, wherein Before the first and second extended pads are connected via the single ball electrode, the individual impedance of the second wiring is higher than that of the first wiring. After the first and second extended pads are connected via the single ball electrode, the individual impedance of the second wiring becomes lower.

3. The electronic device according to claim 1, further comprising: The first via is configured to connect the first wiring and the first extended pad; as well as The second via is configured to connect the second wiring and the second extended pad.

4. The electronic device according to claim 1, wherein The wiring circuit board further includes: A first grounding pattern is disposed on the second surface or inside the wiring circuit board, and connects the first ball electrode and the first extended pad. A second grounding pattern is disposed on the second surface or inside the wiring circuit board and connects the second ball electrode and the second extended pad.

5. The electronic device according to claim 4, wherein The first grounding pattern and the second grounding pattern are deployed in the same layer inside the wiring circuit board. The first extended pad is a portion of the first ground pattern exposed on the second surface side, and The second extended pad is a portion of the second ground pattern exposed on the second surface side.

6. The electronic device according to claim 4, wherein The first grounding pattern is deployed in a first layer inside the wiring circuit board, and the second grounding pattern is deployed in a second layer inside the wiring circuit board. The first extended pad is a portion of the first ground pattern exposed on the second surface side, and The second extended pad is a portion of the second ground pattern disposed in the second layer, which extends into the first layer and is exposed on the second surface side.

7. The electronic device according to claim 1, wherein The plurality of relative pads includes a first relative pad and a second relative pad. The first opposing pad is in contact with the first ball electrode. The second opposing pad contacts the second ball electrode, and The mounting substrate includes a wiring group connecting the first opposing pad and the second opposing pad.

8. The electronic device according to claim 1, wherein The plurality of wirings includes a third wiring disposed on the wiring circuit board. The third wiring is a grounding wiring that supplies ground potential to the third circuit block among the plurality of circuit blocks. The second surface further includes a third extended pad and a fourth extended pad. The third extended pad is connected to the third ball electrode, which is connected to the third wiring. The fourth extended pad is connected to the first ball electrode that is connected to the first wiring. The first ball electrode is one of the plurality of ball electrodes disposed on the second surface, and The third and fourth extended pads are deployed at locations where the third and fourth extended pads are connected to each other on the second surface side by a single ball electrode.

9. The electronic device according to claim 8, wherein Before the third and fourth extended pads are connected via the single ball electrode, the individual impedance of the third wiring is higher than that of the first wiring. After the third and fourth extended pads are connected via the single ball electrode, the individual impedance of the third wiring becomes lower.

10. The electronic device according to claim 1, wherein The plurality of wirings disposed on the wiring circuit board include a third wiring. The third wiring is a grounding wiring that supplies ground potential to the third circuit block among the plurality of circuit blocks. The plurality of ball electrodes disposed on the second surface include a third ball electrode connected to the third wiring. The second surface further includes a third extended pad connected to the third ball electrode, and The first extended pad, the second extended pad, and the third extended pad are deployed at a location where the first extended pad, the second extended pad, and the third extended pad are connected to each other on the second surface side by a single ball electrode.

11. The electronic device of claim 10, wherein Before the first, second, and third extended pads are connected by a single ball electrode, the individual impedance of the second and third traces is higher than the individual impedance of the first trace. After the first extended pad, the second extended pad, and the third extended pad are connected by a single ball electrode, the individual impedance of the second wiring and the third wiring becomes lower.

12. The electronic device of claim 8, further comprising: The third via is configured to connect the third wiring and the third extended pad.

13. A circuit board, characterized in that, The circuit board includes: A semiconductor chip having multiple circuit blocks and multiple first electrode pads connected to any of the multiple circuit blocks; A first surface, on which the semiconductor chip is mounted; and The second surface is the mounting substrate on which the wiring circuit board is mounted. The first surface includes: Multiple second electrode pads are connected via wires to the multiple first electrode pads disposed on the semiconductor chip, and Multiple wirings are connected to the multiple second electrode pads. The second surface includes a plurality of ball electrodes connected to any of the plurality of wirings and deployed to contact any of the plurality of opposing pads disposed on the mounting substrate. The first of the plurality of wirings is a grounding wiring used to supply ground potential to the first circuit block of the plurality of circuit blocks. The second wiring among the plurality of wirings is a grounding wiring used to supply ground potential to the second circuit block among the plurality of circuit blocks. The second surface further includes a first extended pad connected to a first ball electrode connected to the first wiring and a second extended pad connected to a second ball electrode connected to the second wiring. The first extended pad and the second extended pad are deployed at a location where the first extended pad and the second extended pad are connected to each other on the second surface side by a single ball electrode.

14. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor chip having multiple circuit blocks and multiple first electrode pads connected to any of the multiple circuit blocks; A wiring circuit board on which the semiconductor chip is mounted; and A sealing element that seals the semiconductor chip on the wiring circuit board. The wiring circuit board includes: A first surface, on which the semiconductor chip is mounted, and The second surface faces the mounting substrate on which the semiconductor device is mounted. The first surface includes: Multiple second electrode pads are connected to the multiple first electrode pads disposed on the semiconductor chip using wires, and Multiple wirings are connected to any of the plurality of second electrode pads. The second surface includes a plurality of ball electrodes connected to any of the plurality of wirings and deployed to contact any of the plurality of opposing pads disposed on the mounting substrate. The first of the plurality of wirings is a grounding wiring used to supply ground potential to the first circuit block of the plurality of circuit blocks. The second wiring among the plurality of wirings is a grounding wiring used to supply ground potential to the second circuit block among the plurality of circuit blocks. The second surface further includes a first extended pad connected to a first ball electrode connected to the first wiring and a second extended pad connected to a second ball electrode connected to the second wiring, and The first extended pad and the second extended pad are deployed at a location where the first extended pad and the second extended pad are connected to each other on the second surface side by a single ball electrode.

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