High electron mobility transistor and its fabrication method

Abstract

This invention discloses a high electron mobility transistor and its fabrication method. The high electron mobility transistor includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer buried in the first III-V compound layer, a P-type gallium nitride gate buried in the second III-V compound layer, a gate electrode disposed on the second III-V compound layer and in contact with the P-type gallium nitride gate, a source electrode disposed on one side of the gate electrode, and a drain electrode disposed on the other side of the gate electrode.

Description

Technical Field

[0001] This invention relates to a high electron mobility transistor and a method for manufacturing the same, and more particularly to a high electron mobility transistor and a method for manufacturing the same, which increases the breakdown voltage and reduces the on-resistance of the high electron mobility transistor. Background Technology

[0002] III-V semiconductor compounds, due to their semiconductor properties, can be used to form many types of integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, or high electron mobility transistors (HEMTs). In HEMTs, two semiconductor materials with different band gaps are combined to form a heterojunction, providing a channel for charge carriers. In recent years, gallium nitride (GaN) series materials have become suitable for high-power and high-frequency products due to their wide band gap and high saturation velocity. GaN series HEMTs generate a two-dimensional electron gas (2DEG) through the piezoelectric effect of the material itself. Compared to traditional transistors, HEMTs have higher electron velocity and density, thus increasing switching speed.

[0003] However, in order to cope with the increased density of semiconductor devices, it is necessary to further increase the breakdown voltage of high electron mobility transistors and reduce the on-resistance of high electron mobility transistors. Summary of the Invention

[0004] In view of this, the present invention provides a high electron mobility transistor that achieves the above-mentioned requirements without increasing the overall thickness of the high electron mobility transistor.

[0005] According to a preferred embodiment of the present invention, a high electron mobility transistor includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer buried in the first III-V compound layer, wherein the composition of the second III-V compound layer is different from that of the first III-V compound layer, a P-type gallium nitride gate is buried in the second III-V compound layer, a gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate, a source electrode is disposed on one side of the gate electrode, located on the second III-V compound layer and in contact with both the second III-V and first III-V compound layers, and a drain electrode is disposed on the other side of the gate electrode, located on the second III-V compound layer and in contact with both the second III-V and first III-V compound layers.

[0006] According to another preferred embodiment of the present invention, a method for fabricating a high electron mobility transistor includes forming a normally-off transistor. The steps of forming the normally-off transistor include: firstly, providing a substrate and a first III-V compound layer disposed on the substrate; then, etching the first III-V compound layer to form a first trench; then performing a first epitaxial process to form a second III-V compound layer to fill the first trench; then, etching the second III-V compound layer to form a second trench; then performing a second epitaxial process to form a P-type gallium nitride gate to fill the second trench; subsequently forming a first gate electrode, wherein the first gate electrode is located on the second III-V compound layer and contacts the P-type gallium nitride gate; and finally forming a first source electrode and a first drain electrode, wherein the first source electrode and the first drain electrode are respectively disposed on both sides of the first gate electrode, and both the first source electrode and the first drain electrode are located on the second III-V compound layer and contact the second III-V compound layer and the first III-V compound layer.

[0007] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0008] Figure 1 , Figure 2A , Figures 3 to 8 This is a schematic diagram illustrating a method for fabricating a high electron mobility transistor according to a preferred embodiment of the present invention, wherein... Figure 5 for Figure 4 The top view shown;

[0009] Figure 2B A schematic diagram illustrating a method for fabricating a high electron mobility transistor according to another preferred embodiment of the present invention;

[0010] Figure 9 This is a schematic diagram illustrating a high electron mobility transistor structure according to another preferred embodiment of the present invention.

[0011] Explanation of main component symbols

[0012] 10: Base

[0013] 12: First III-V compound layer

[0014] 14: First trench

[0015] 15: Aluminum nitride layer

[0016] 16: Third trench

[0017] 18: First epitaxial manufacturing process

[0018] 20: Second III-V compound layer

[0019] 22: Mask

[0020] 24: Second trench

[0021] 26: Second epitaxial fabrication process

[0022] 28: P-type gallium nitride gate

[0023] 30a: First source electrode

[0024] 30b: Second source electrode

[0025] 32a: First drain electrode

[0026] 32b: Second drain electrode

[0027] 34a: Protective layer

[0028] 34b: Protective layer

[0029] 36a: First gate electrode

[0030] 36b: Second gate electrode

[0031] 38: Interlayer dielectric layer

[0032] 40: Conductive plug

[0033] 42: Trapezoid

[0034] 42a: Top bottom

[0035] 42b: Bottom

[0036] 42c: Side

[0037] 44: Two-dimensional electronic gas

[0038] 100: Normally Off High Electron Mobility Transistor

[0039] 200: Normally Open High Electron Mobility Transistor

[0040] 300: Normally Off High Electron Mobility Transistor

[0041] A: Normally off transistor region

[0042] B: Normally Open Transistor Region

[0043] C: First obtuse angle

[0044] D: Second obtuse angle

[0045] L: Distance

[0046] X: Distance

[0047] Y: Distance Detailed Implementation

[0048] Figure 1 , Figure 2A , Figures 3 to 8 A method for fabricating a high electron mobility transistor according to a preferred embodiment of the present invention is illustrated, wherein... Figure 5 According to Figure 4 The top view shown.

[0049] like Figure 1 As shown, a substrate 10 is first provided, which is divided into a normally-off transistor region A and a normally-on transistor region B. A first III-V compound layer 12 is disposed on the substrate 10 and simultaneously covers the normally-off transistor region A and the normally-on transistor region B. Next, the first III-V compound layer 12 is etched to form a first trench 14 and a third trench 16. The first trench 14 is located in the normally-off transistor region A, and the third trench 16 is located in the normally-on transistor region B. Dry etching is preferred. It is worth noting that a first obtuse angle C is formed between the bottom of the first trench 14 and the sidewall of the first trench 14, and a second obtuse angle D is formed between the bottom of the third trench 16 and the sidewall of the third trench 16. The first obtuse angle C is preferably between 120 and 150 degrees. The second obtuse angle D is also preferably between 120 and 150 degrees.

[0050] like Figure 2A As shown, a first epitaxial fabrication process 18 is performed to form a second III-V compound layer 20 that fills the first trench 14 and the third trench 16. The first epitaxial fabrication process 18 includes metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The upper surface of the second III-V compound layer 20 is flush with the upper surface of the first III-V compound layer 12.

[0051] According to another preferred embodiment of the present invention, such as Figure 2B As shown, prior to the first epitaxial fabrication process 18, an aluminum nitride layer 15 can be selectively formed to conformally cover the first trench 14 and the third trench 16, followed by subsequent... Figure 2A The steps are as follows: to form the aforementioned second III-V compound layer 20, the thickness of the aluminum nitride layer 15 is preferably between 1 and 2 nanometers.

[0052] Figure 3 To continue Figure 2A The steps, such as Figure 3 As shown, after forming a mask 22 to cover the normally-on transistor region B, a second III-V compound layer 20 is etched onto the normally-off transistor region B to form a second trench 24. The depth of the second trench 24 is preferably between 40 and 90 nanometers. Figure 4 As shown, a second epitaxial fabrication process 26 is performed to form a P-type gallium nitride gate 28 filling the second trench 24. The second epitaxial fabrication process 26 includes metal-organic chemical vapor deposition or molecular beam epitaxy. After completing the P-type gallium nitride gate 28, the mask 22 is removed. Please also refer to... Figure 4 and Figure 5 Viewed from the direction shown in the top view, in normally off transistor region A, the first III-V compound layer 12 surrounds the second III-V compound layer 20, and the second III-V compound layer 20 surrounds the P-type gallium nitride gate 28. In normally on transistor region B, the first III-V compound layer 12 surrounds the second III-V compound layer 20. Furthermore, as... Figure 4 As shown, in normally off transistor region A, the upper surface of the second III-V compound layer 20, the upper surface of the first III-V compound layer 12, and the upper surface of the P-type gallium nitride gate 28 are aligned; in normally on transistor region B, the upper surface of the second III-V compound layer 20 and the upper surface of the first III-V compound layer 12 are aligned.

[0053] like Figure 6 As shown, a first source electrode 30a, a first drain electrode 32a, a second source electrode 30b, and a second drain electrode 32b are simultaneously formed on the second III-V compound layer 20 and all simultaneously contact the second III-V compound layer 20 and the first III-V compound layer 12. According to a preferred embodiment of the present invention, the formation of the first source electrode 30a, the first drain electrode 32a, the second source electrode 30b, and the second drain electrode 32b can include the formation of the first source electrode 30a, the first drain electrode 32a, the second source electrode 30b, and the second drain electrode 32b. Before electrode 32b, a protective layer 34a is first formed to cover the second III-V compound layer 20 and the first III-V compound layer 12. Then, the protective layer 34a is etched to form several openings on it, exposing the interface between the first III-V compound layer 12 and the second III-V compound layer 20. Next, a metal layer (not shown) is formed using a deposition process to fill the openings and cover the protective layer 34a. Then, the metal layer is patterned to form the first source electrode 30a, the first drain electrode 32a, the second source electrode 30b, and the second drain electrode 32b. For example... Figure 7As shown, a first gate electrode 36a and a second gate electrode 36b are formed simultaneously. The first gate electrode 36a is located on the second III-V compound layer 20 of the normally off transistor region A and contacts the P-type gallium nitride gate 28. The second gate electrode 36b is located on the second III-V compound layer 20 of the normally on transistor region B. Specifically, before forming the first gate electrode 36a and the second gate electrode 36b, a protective layer 34b is first formed to cover the protective layer 34a, the first source electrode 30a, the first drain electrode 32a, the second source electrode 30b, and the second drain electrode 32b. Then, the protective layer 34b is etched to form two openings on the protective layer 34b. One opening exposes the P-type gallium nitride gate 28, and the other opening exposes the second III-V compound layer 20 of the normally on transistor region B. Afterward, a metal layer (not shown) is formed using a deposition process to fill the openings and cover the protective layer 34b. Then, the metal layer is patterned to form the first gate electrode 36a and the second gate electrode 36b.

[0054] like Figure 8 As shown, an interlayer dielectric layer 38 is then formed to cover the normally-off transistor region A and the normally-on transistor region B. Then, several conductive plugs 40 are formed, penetrating the interlayer dielectric layer 38 and contacting the first gate electrode 36a, the first source electrode 30a, the first drain electrode 32a, the second gate electrode 36b, the second source electrode 30b, and the second drain electrode 32b, respectively. Thus, the normally-off high electron mobility transistor 100 and the normally-on high electron mobility transistor 200 of the present invention have been completed.

[0055] In addition, according to another preferred embodiment of the present invention, the first gate electrode 36a and the second gate electrode 36b can be fabricated first, and then the first source electrode 30a, the first drain electrode 32a, the second source electrode 30b and the second drain electrode 32b can be fabricated.

[0056] Figure 8 This is a high electron mobility transistor structure illustrated according to a preferred embodiment of the present invention. For example... Figure 8As shown, a high electron mobility transistor structure includes a substrate 10, which is divided into a normally-off transistor region A and a normally-on transistor region B. A normally-off high electron mobility transistor 100 is disposed in the normally-off transistor region A, and a normally-on transistor region 200 is disposed in the normally-on transistor region B. The high electron mobility transistor structure includes a first III-V compound layer 12 disposed on the substrate 10 in the normally-off transistor region A and the normally-on transistor region B. Two second III-V compound layers 20 are respectively embedded in the first III-V compound layer 12 in the normally-off transistor region A and the first III-V compound layer 12 in the normally-on transistor region B. The composition of the V-compound layer 20 differs from that of the first III-V compound layer 12. Notably, the side views of both second III-V compound layers 20 include a trapezoid 42, comprising an upper base 42a, a lower base 42b, and two side edges 42c. The upper base 42a is flush with the upper surface of the first III-V compound layer 12, and the length of the upper base 42a is greater than the length of the lower base 42c. An obtuse angle C is formed between one side edge 42c and the lower base 42b in normally off transistor region A, and an obtuse angle D is formed between one side edge 42c and the lower base 42b in normally off transistor region B. According to a preferred embodiment of the present invention, the obtuse angles C and D are each between 120 and 150 degrees. If the angle between the side edge 42c and the lower base 42b is less than 90 degrees, i.e., a non-obtuse angle, a two-dimensional electron gas 44 cannot be formed. This is because when the angle is less than 90 degrees, the second III-V compound layer 20 cannot form a crystal plane capable of generating a two-dimensional electron gas 44. A P-type gallium nitride gate 28 is buried in the second III-V compound layer 20 within the normally off transistor region A, but there is no P-type gallium nitride gate 28 in the normally on transistor region B. Furthermore, the P-type gallium nitride gate 28 does not contact the first III-V compound layer 12. Please also refer to... Figure 5 Viewed from the direction of the top view, in normally off transistor region A, the first III-V compound layer 12 surrounds the second III-V compound layer 20, and the second III-V compound layer 20 surrounds the P-type gallium nitride gate 28. In normally on transistor region B, the first III-V compound layer 12 surrounds the second III-V compound layer 20.

[0057] A first gate electrode 36a is located on the second III-V compound layer 20 of the normally off transistor region A and contacts the P-type gallium nitride gate 28, and a second gate electrode 36b is located on the second III-V compound layer 20 of the normally on transistor region B. A first gate electrode 36a is located on the second III-V compound layer 20 and contacts the P-type gallium nitride gate 28. A first source electrode 30a and a first drain electrode 32a are respectively disposed on opposite sides of the first gate electrode 36a, on the second III-V compound layer 20 located in the normally off transistor region A, and simultaneously contact the second III-V compound layer 20 and the first III-V compound layer 12. A second gate electrode 36b is located on the second III-V compound layer 20 in the normally open transistor region B. A second source electrode 30b and a second drain electrode 32b are respectively disposed on opposite sides of the second gate electrode 36b, on the second III-V compound layer 20 located in the normally open transistor region B, and contact the second III-V compound layer 20 and the first III-V compound layer 12. The first source electrode 30a, the first drain electrode 32a, the second source electrode 30b, and the second drain electrode 32b each contact the interface between the first III-V compound layer 12 and the second III-V compound layer 20. A two-dimensional electron gas 44 is located between the second III-V compound layer 20 and the first III-V compound layer 12, and the two-dimensional electron gas 44 has a trench profile. Because the two-dimensional electron gas 44 forms at the interface between the first III-V compound layer 12 and the second III-V compound layer 20, the first source electrode 30a, the first drain electrode 32a, the second source electrode 30b, and the second drain electrode 32b must all contact the interface between the first III-V compound layer 12 and the second III-V compound layer 20 to communicate with the two-dimensional electron gas 44. A protective layer 34a covers the first III-V compound layer 12 and the second III-V compound layer, and a protective layer 34b covers the protective layer 34a.

[0058] As described above, the first III-V compound layer 12, the second III-V compound layer 20, the P-type gallium nitride gate 28, the first gate electrode 36a, the first source electrode 30a, and the first drain electrode 32a in normally-off transistor region A constitute a normally-off high electron mobility transistor 100; and the first III-V compound layer 12, the second III-V compound layer 20, the second gate electrode 36b, the second source electrode 30b, and the second drain electrode 32b in normally-on transistor region B constitute a normally-on high electron mobility transistor 200.

[0059] An interlayer dielectric layer 38 covers the normally-off high electron mobility transistor 100 and the normally-on high electron mobility transistor 200. Several conductive plugs 40 penetrate the interlayer dielectric layer 38 and respectively contact the first gate electrode 36a, the first source electrode 30a, the first drain electrode 32a, the second gate electrode 36b, the second source electrode 30b, and the second drain electrode 32b.

[0060] A distance X is provided between the bottom of the p-type gallium nitride gate 28 and the first III-V compound layer 12, perpendicular to the upper surface of the substrate 10, and preferably between 10 and 20 nanometers. Furthermore, the thickness of each of the two second III-V compound layers 20 is preferably between 50 and 100 nanometers. The thickness of the p-type gallium nitride gate 28 is preferably between 40 and 90 nanometers, and the distance Y from the bottom of the second III-V compound layer 20 to the upper surface of the substrate 10 is preferably between 2 and 6 micrometers. The first III-V compound layer 12 comprises gallium nitride (GaN) and indium gallium nitride (In). x Ga 1-x N), aluminum gallium nitride (Al) x Ga 1-x N), aluminum indium nitride (Al) x In 1-x N), aluminum indium gallium nitride (Al) 1-x-y In x Ga y In this embodiment, the first III-V compound layer 12 is preferably gallium nitride, and the second III-V compound layer 20 comprises aluminum gallium nitride (AlN) or aluminum nitride (AlN). x Ga 1-x N), aluminum indium nitride (Al) x In 1-x N), aluminum indium gallium nitride (Al) 1-x-y In x Ga y In this embodiment, the second III-V compound layer 20 is preferably aluminum gallium nitride (AlN) or aluminum nitride (AlN), and the thickness of the second III-V compound layer 20 is about 100 nanometers.

[0061] The substrate 10 is preferably a silicon substrate with a (1,1,1) crystal plane. The p-type gallium nitride gate 28 can be formed by implanting gallium nitride with magnesium as a dopant. The protective layers 34a / 34b comprise silicon nitride or aluminum nitride. The first gate electrode 36a, the first source electrode 30a, the first drain electrode 32a, the second gate electrode 36b, the second source electrode 30b, and the second drain electrode 32b each comprise titanium, aluminum, nickel, platinum, or gold.

[0062] Figure 9 The illustration depicts a high electron mobility transistor structure according to another preferred embodiment of the present invention, wherein elements having the same position and function will use Figure 8 The component symbols in the text. Figure 8 and Figure 9 The difference lies in Figure 9 The normally-off high electron mobility transistor 300 achieves its normally-off effect using a recessed gate electrode. That is, the normally-off high electron mobility transistor 300 does not have a P-type gallium nitride gate, and the first gate electrode 36 extends into the second III-V compound layer 20. A gate insulating layer 44 is disposed around the first gate electrode 36a. A distance L exists between the bottom of the first gate electrode 36a and the first III-V compound layer 12, and the distance L is perpendicular to the upper surface of the substrate 10, preferably between 1 and 2 nanometers. In another preferred embodiment, the first gate electrode 36a can truncate the second III-V compound layer 20 and extend into the first III-V compound layer 12.

[0063] This invention intentionally increases the thickness of the second III-V compound layer to improve the breakdown voltage of the high electron mobility transistor (HMT), increase the concentration of the two-dimensional electron gas, and reduce the on-resistance. However, for normally-off HMTs, increasing the thickness of the second III-V compound layer necessitates increasing the thickness of the P-type gallium nitride gate to maintain the normally-off effect. To avoid increasing the overall thickness of the HMT, this invention embeds the second III-V compound layer within the first III-V compound layer and the P-type gallium nitride gate within the second III-V compound layer. Furthermore, because embedding the second III-V compound layer within the first III-V compound layer creates a trench contour for the two-dimensional electron gas, the fabrication of the first source electrode, first drain electrode, second source electrode, and second drain electrode does not require etching the second and first III-V compound layers to allow the two-dimensional electron gas to contact the first source electrode, first drain electrode, second source electrode, and second drain electrode.

[0064] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A high electron mobility transistor, comprising: Base; A first III-V compound layer is disposed on the substrate; A second III-V compound layer is embedded in the first III-V compound layer, wherein the composition of the second III-V compound layer is different from that of the first III-V compound layer; A P-type gallium nitride gate is buried in the second III-V compound layer; A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate; The source electrode is disposed on one side of the gate electrode, located on the second III-V compound layer, and in contact with the second III-V compound layer and the first III-V compound layer; as well as The drain electrode is disposed on the other side of the gate electrode, on the second III-V compound layer, and in contact with both the second III-V compound layer and the first III-V compound layer. The upper surfaces of the second III-V compound layer, the first III-V compound layer, and the P-type gallium nitride gate are aligned.

2. The high electron mobility transistor of claim 1, wherein the side view of the second III-V compound layer comprises a trapezoid, the trapezoid comprising an upper base, a lower base and two side edges, the upper base being flush with the upper surface of the first III-V compound layer, and the length of the upper base being greater than the length of the lower base.

3. The high electron mobility transistor of claim 2, wherein one of the two sides forms an obtuse angle with the bottom.

4. The high electron mobility transistor of claim 3, wherein the obtuse angle is between 120 and 150 degrees.

5. The high electron mobility transistor of claim 1, wherein the first III-V compound layer surrounds the second III-V compound layer, and the second III-V compound layer surrounds the P-type gallium nitride gate.

6. The high electron mobility transistor of claim 1, wherein the P-type gallium nitride gate does not contact the first III-V compound layer.

7. The high electron mobility transistor of claim 1, wherein there is a distance between the bottom of the P-type gallium nitride gate and the first III-V compound layer, the distance being perpendicular to the upper surface of the substrate, the distance being between 10 and 20 nanometers.

8. The high electron mobility transistor of claim 1, wherein the thickness of the second III-V compound layer is between 50 and 100 nanometers.

9. The high electron mobility transistor of claim 1, wherein the distance from the bottom of the second III-V compound layer to the upper surface of the substrate is 2 to 6 micrometers.

10. The high electron mobility transistor of claim 1, wherein a two-dimensional electron gas is formed between the second III-V compound layer and the first III-V compound layer, the two-dimensional electron gas having a trench profile.

11. The high electron mobility transistor of claim 1, wherein the first III-V compound layer is gallium nitride, and the second III-V compound layer comprises aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, or aluminum nitride.

12. The high electron mobility transistor of claim 1, further comprising an aluminum nitride layer disposed between the second III-V compound layer and the first III-V compound layer.

13. A method for fabricating a high electron mobility transistor, comprising: Forming a normally-off transistor, wherein the step of forming the normally-off transistor includes: A substrate and a first III-V compound layer are disposed on the substrate; The first III-V compound layer is etched to form the first trench; A first epitaxial fabrication process is performed to form a second III-V compound layer to fill the first trench; The second III-V compound layer is etched to form the second trench; A second epitaxial fabrication process is performed to form a P-type gallium nitride gate to fill the second trench; A first gate electrode is formed, wherein the first gate electrode is located on the second III-V compound layer and contacts the P-type gallium nitride gate; as well as A first source electrode and a first drain electrode are formed, wherein the first source electrode and the first drain electrode are respectively disposed on both sides of the first gate electrode, and the first source electrode and the first drain electrode are both located on the second III-V compound layer and in contact with the second III-V compound layer and the first III-V compound layer.

14. The method of fabricating a high electron mobility transistor as claimed in claim 13, wherein an obtuse angle is formed between the bottom of the first trench and the sidewall of the first trench.

15. The method for fabricating a high electron mobility transistor as claimed in claim 13, wherein the P-type gallium nitride gate does not contact the first III-V compound layer.

16. The method of fabricating a high electron mobility transistor as claimed in claim 13, wherein there is a distance between the bottom of the P-type gallium nitride gate and the first III-V compound layer, the distance being perpendicular to the upper surface of the substrate, and the distance being between 10 nanometers and 20 nanometers.

17. The method of fabricating a high electron mobility transistor as claimed in claim 13, wherein the first III-V compound layer surrounds the second III-V compound layer, and the second III-V compound layer surrounds the P-type gallium nitride gate.

18. The method for fabricating a high electron mobility transistor as claimed in claim 13, wherein the upper surface of the second III-V compound layer, the upper surface of the first III-V compound layer, and the upper surface of the P-type gallium nitride gate are aligned.

19. The method for fabricating a high electron mobility transistor as claimed in claim 13, further comprising forming an aluminum nitride layer covering the first trench prior to performing the first epitaxial fabrication process.

20. The method for fabricating a high electron mobility transistor as claimed in claim 13, wherein the substrate is divided into a normally-off transistor region and a normally-on transistor region, and the normally-off transistor is located in the normally-off transistor region.

21. The method for fabricating a high electron mobility transistor as claimed in claim 20, further comprising forming a normally-on transistor in the normally-on transistor region of the substrate, wherein the fabrication step of the normally-on transistor includes: While etching the first III-V compound layer to form the first trench, the first III-V compound layer is etched to form a third trench located in the normally open transistor region; During the first epitaxial fabrication process, two second III-V compound layers are simultaneously formed to fill the first trench and the third trench respectively. After forming a mask to cover the normally open transistor region, the second III-V compound layer is etched to form the second trench; After completing the P-type gallium nitride gate, remove the mask; After removing the mask, a second gate electrode is formed simultaneously with the formation of the first gate electrode on the second III-V compound layer of the normally open transistor region; and After removing the mask, while forming the first source electrode and the first drain electrode, a second source electrode and a second drain electrode are formed in the normally open transistor region. The second source electrode and the second drain electrode are respectively disposed on both sides of the second gate electrode. The second source electrode and the second drain electrode are both located on the second III-V compound layer and contact the second III-V compound layer and the first III-V compound layer.

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