A solar cell and a photovoltaic module

Abstract

The application relates to a solar cell and a photovoltaic module. The solar cell comprises a substrate, a tunneling oxide layer, a doped conductive layer, an intrinsic polysilicon layer and a first electrode. The substrate has a first surface; the tunneling oxide layer covers the first surface; the doped conductive layer covers a side surface of the tunneling oxide layer away from the substrate; the intrinsic polysilicon layer is arranged on a side of the doped conductive layer away from the tunneling oxide layer; a plurality of first electrodes are arranged on a side of the intrinsic polysilicon layer away from the doped conductive layer, and the plurality of first electrodes are electrically connected with the doped conductive layer; at least part of the first electrodes is located in the intrinsic polysilicon layer, and a gap exists between the top end of the first electrode and the substrate. The tunneling oxide layer can be prevented from being damaged, the first surface can maintain a good interface passivation effect, the increase of carrier recombination is avoided, the photoelectric conversion efficiency of the solar cell is improved, and the front cell efficiency, the back cell efficiency and the double-sided cell rate of the solar cell are all increased.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and more particularly to a solar cell and a photovoltaic module. Background Technology

[0002] Solar cells can directly convert solar radiation energy into electrical energy. In order to suppress carrier recombination on the surface of solar cell substrate, a tunneling oxide layer and a doped conductive layer are usually prepared on the substrate surface to enhance the passivation effect on the substrate.

[0003] In the prior art, the electrodes of solar cells can easily penetrate the tunnel oxide layer and come into contact with the substrate, which destroys the passivation effect of the substrate surface, increases carrier recombination, and affects the photoelectric conversion efficiency of the solar cell. Summary of the Invention

[0004] This application provides a solar cell and a photovoltaic module that can improve the photoelectric conversion efficiency of solar cells.

[0005] A first aspect of this application provides a solar cell, the solar cell comprising:

[0006] A substrate having a first surface;

[0007] A tunneling oxide layer, which covers the first surface;

[0008] A doped conductive layer covers the surface of the tunneling oxide layer away from the substrate;

[0009] An intrinsic polysilicon layer is disposed on the side of the doped conductive layer away from the tunneling oxide layer.

[0010] First electrode, a plurality of first electrodes are disposed on the side of the intrinsic polysilicon layer away from the doped conductive layer, and the plurality of first electrodes are electrically connected to the doped conductive layer;

[0011] At least a portion of the first electrode is located within the intrinsic polysilicon layer, and there is a gap between the top of the first electrode and the substrate.

[0012] In one possible design, the intrinsic polysilicon layer covers the entire surface of the doped conductive layer on the side away from the tunneling oxide layer.

[0013] In one possible design, the solar cell further includes a first passivation layer covering the intrinsic polycrystalline silicon layer on the side of the surface away from the doped conductive layer.

[0014] In one possible design, the intrinsic polysilicon layer includes a plurality of covering portions for covering the side surface of the doped conductive layer away from the tunneling oxide layer; the plurality of covering portions respectively cover the portions on the doped conductive layer corresponding to the plurality of first electrodes.

[0015] In one possible design, the solar cell further includes a first passivation layer, a portion of which covers the portion of the doped conductive layer where the cover is not provided, and another portion of which covers the surface of the cover portion away from the doped conductive layer.

[0016] In one possible design, the thickness D1 of the intrinsic polycrystalline silicon layer satisfies: 10nm ≤ D1 ≤ 80nm.

[0017] In one possible design, the solar cell further includes a locally doped region connected to the first electrode, the intrinsic polycrystalline silicon layer, and the doped conductive layer, respectively, so that the first electrode is electrically connected to the doped conductive layer.

[0018] In one possible design, the first electrode is a metal electrode, and the first electrode and the doped conductive layer have doping elements of the same conductivity type, and the doping concentration of the first electrode is greater than the doping concentration of the doped conductive layer; the doping elements in the first electrode penetrate toward the doped conductive layer to form the localized doped region.

[0019] In one possible design, the concentration of the dopant element in the doped conductive layer is 1 × 10⁻⁶. 20 atoms / cm 3 ~1×10 21 atoms / cm 3 .

[0020] In one possible design, the concentration of the dopant element in the localized doped region is 1 × 10⁻⁶. 19 atoms / cm 3 ~1×10 20 atoms / cm 3 .

[0021] In one possible design, the first electrode has the same type of dopant as the substrate.

[0022] In one possible design, the first electrode has a doping element with a different conductivity type than the substrate.

[0023] In one possible design, the cross-sectional area of ​​the locally doped region is 1 × 10⁻⁶. -8 mm2 ~1×10 -6 mm 2 .

[0024] In one possible design, the first electrode includes a body and an extension extending along the body toward the doped conductive layer; the extension is located within the intrinsic polysilicon layer and / or the doped conductive layer, and there is a gap between the top end of the extension and the substrate, and the locally doped region covers the extension.

[0025] In one possible design, the extension includes a first portion and a second portion, the first portion being connected to the body, and the second portion being spaced apart from both the body and the first portion; a portion of the locally doped region covers the first portion, and another portion of the locally doped region covers the second portion.

[0026] In one possible design, the thickness D2 of the doped conductive layer satisfies: 10nm ≤ D2 ≤ 80nm.

[0027] In one possible design, the substrate also has a second surface disposed opposite to the first surface;

[0028] The solar cell also includes:

[0029] An emitter, wherein the emitter is disposed on the second surface;

[0030] Second electrodes, a plurality of second electrodes are disposed on the side of the emitter away from the substrate, and the plurality of second electrodes are electrically connected to the emitter;

[0031] A second passivation layer is applied to the surface of the emitter away from the substrate.

[0032] A second aspect of this application provides a photovoltaic module, the photovoltaic module comprising:

[0033] A battery string, wherein the battery string is composed of multiple solar cells connected together, and the solar cells are the solar cells described above;

[0034] Encapsulation layer, the encapsulation layer being used to cover the surface of the battery string;

[0035] A cover plate for covering the surface of the encapsulation layer away from the battery string.

[0036] In this application, by setting an intrinsic polycrystalline silicon layer, the first electrode can be prevented from penetrating the tunneling oxide layer and making contact with the substrate, thus avoiding damage to the tunneling oxide layer. This allows the first surface to maintain a good interface passivation effect, preventing an increase in carrier recombination, and thereby improving the photoelectric conversion efficiency of the solar cell. This results in increased efficiency on the front side, back side, and bifaciality of the solar cell. Furthermore, the intrinsic polycrystalline silicon layer is undoped, and its light absorption coefficient is much lower than that of a doped conductive layer. Therefore, setting an intrinsic polycrystalline silicon layer can also reduce optical losses in the solar cell and improve the utilization rate of light energy.

[0037] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0038] Figure 1 A cross-sectional structural schematic diagram of the solar cell provided in this application in a first specific embodiment;

[0039] Figure 2 A cross-sectional structural schematic diagram of the solar cell provided in this application in a second specific embodiment;

[0040] Figure 3 for Figure 1 Enlarged view of section A;

[0041] Figure 4 This is a schematic diagram of the structure of the photovoltaic module provided in this application.

[0042] Figure label:

[0043] 1-Base;

[0044] 1a - First surface;

[0045] 1b - Second surface;

[0046] 2-Tunneling oxide layer;

[0047] 3-Doped conductive layer;

[0048] 4-Intrinsic polycrystalline silicon layer;

[0049] 41-Covering section;

[0050] 5 - First electrode;

[0051] 51-Ontology;

[0052] 52-Extension;

[0053] 521 - Part One;

[0054] 522 - Part Two;

[0055] 6-Locally doped regions;

[0056] 7-First passivation layer;

[0057] 8-Emitter;

[0058] 9 - Second electrode;

[0059] 10 - Second passivation layer;

[0060] 110-battery string;

[0061] 120 - Encapsulation layer;

[0062] 130 - Cover plate;

[0063] 140 - Conductive strip.

[0064] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Detailed Implementation

[0065] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0066] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0067] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0068] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0069] It should be noted that the directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this application are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this application. Furthermore, in the context, it should be understood that when it is mentioned that an element is connected "upper" or "lower" to another element, it can be directly connected to the other element "upper" or "lower," or indirectly connected to the other element "upper" or "lower" through an intermediate element.

[0070] In existing technologies, when fabricating solar cells, a tunneling oxide layer and a doped conductive layer are deposited on one side of the substrate. The tunneling oxide layer acts as a tunneling layer for majority carriers and simultaneously chemically passivates the substrate surface, reducing interface states. The doped conductive layer can form band bends, enabling selective carrier transport, reducing recombination losses, and ensuring carrier transport efficiency. Furthermore, a metal electrode is fabricated on the substrate surface. The metal electrode is electrically connected to the doped conductive layer and does not penetrate the tunneling oxide layer, thus maintaining good interface passivation.

[0071] However, the doped conductive layer has light absorption capabilities, which causes optical losses and reduces the efficiency of both the front and back cells of the solar cell, thus decreasing the bifaciality and consequently the bifacial power generation efficiency when the solar cell is used for bifacial power generation. To improve this situation, the thickness of the doped conductive layer can be reduced, thereby reducing its light absorption capacity, reducing optical losses, and improving the cell efficiency. However, when the doped conductive layer is thinned, the metal electrode can easily penetrate the tunneling oxide layer and come into contact with the substrate, disrupting the passivation effect of the substrate surface. This leads to increased carrier recombination on the substrate surface, resulting in a decrease in the cell's photoelectric conversion efficiency. Furthermore, existing metal electrode fabrication processes struggle to control the contact between the metal electrode and the doped conductive layer without penetrating the tunneling oxide layer.

[0072] Based on the above, embodiments of this application provide a solar cell that can reduce recombination losses on the substrate surface and improve the photoelectric conversion efficiency of the solar cell. For example... Figure 1 As shown, the solar cell includes a substrate 1, a tunneling oxide layer 2, a doped conductive layer 3, an intrinsic polycrystalline silicon layer 4, and a first electrode 5. The substrate 1 has a first surface 1a, the tunneling oxide layer 2 covers the first surface 1a, the doped conductive layer 3 covers the side of the tunneling oxide layer away from the substrate 1, the intrinsic polycrystalline silicon layer 4 is disposed on the side of the doped conductive layer 3 away from the tunneling oxide layer 2, and a plurality of first electrodes 5 are disposed on the side of the intrinsic polycrystalline silicon layer 4 away from the doped conductive layer 3. The plurality of first electrodes 5 are electrically connected to the doped conductive layer 3, at least a portion of the first electrode 5 is located within the intrinsic polycrystalline silicon layer 4, and there is a gap between the top of the first electrode 5 and the substrate 1.

[0073] like Figure 1 As shown, substrate 1 is used to receive incident light and generate photogenerated carriers. Tunneling oxide layer 2 can chemically passivate the first surface 1a, reducing the interface defect density of the first surface 1a, thereby reducing the recombination centers of the first surface 1a and lowering the carrier recombination rate. Doped conductive layer 3 is used to form a field passivation layer, which can reduce the minority carrier concentration, thereby lowering the carrier recombination rate. Intrinsic polysilicon layer 4 is disposed on the side of doped conductive layer 3 away from tunneling oxide layer 2, which can increase the distance between the first electrode 5 and tunneling oxide layer 2. At least a portion of the first electrode 5 can contact the doped conductive layer 3 through intrinsic polysilicon layer 4 and achieve electrical connection with the doped conductive layer 3. At the same time, there is a gap between the top of the first electrode 5 and substrate 1, ensuring that the first electrode 5 will not penetrate the tunneling oxide layer 2 and contact the substrate 1, thereby enabling the first surface 1a to maintain a good interface passivation effect.

[0074] In this embodiment, by providing an intrinsic polycrystalline silicon layer 4, the first electrode 5 can be prevented from penetrating the tunneling oxide layer 2 and making contact with the substrate 1, thus avoiding damage to the tunneling oxide layer 2. This allows the first surface 1a to maintain a good interface passivation effect, preventing an increase in carrier recombination and thereby improving the photoelectric conversion efficiency of the solar cell. Consequently, the efficiency of the front cell, the efficiency of the back cell, and the bifaciality of the solar cell are all increased. Furthermore, the intrinsic polycrystalline silicon layer 4 is undoped, and its light absorption coefficient is much lower than that of the doped conductive layer 3. Therefore, providing an intrinsic polycrystalline silicon layer 4 can also reduce the optical loss of the solar cell and improve the utilization rate of light energy by the solar cell.

[0075] It should be noted that the first electrode 5 not penetrating the tunneling oxide layer 2 includes two situations: the first electrode 5 not contacting the tunneling oxide layer 2, and the first electrode 5 partially extending into the tunneling oxide layer 2, but not completely penetrating the tunneling oxide layer 2.

[0076] In this embodiment, substrate 1 can be a silicon substrate, including but not limited to monocrystalline silicon substrate, polycrystalline silicon substrate, microcrystalline silicon substrate, nanocrystalline silicon substrate, etc.

[0077] In one specific embodiment, such as Figure 1 As shown, the intrinsic polycrystalline silicon layer 4 covers the entire surface of the doped conductive layer 3 on the side away from the tunneling oxide layer 2.

[0078] The intrinsic polysilicon layer 4 completely covers the surface of the doped conductive layer 3 away from the tunneling oxide layer 2, which can increase the distance between the first electrode 5 and the tunneling oxide layer 2. During the sintering of the electrode paste to form the first electrode 5, the top of the first electrode 5 will first contact the intrinsic polysilicon layer 4 and then contact the doped conductive layer 3, reducing the possibility that the first electrode 5 will penetrate the tunneling oxide layer 2 and contact the substrate 1.

[0079] Specifically, such as Figure 1 As shown, the solar cell also includes a first passivation layer 7, which covers the intrinsic polycrystalline silicon layer 4 on the side away from the doped conductive layer 3.

[0080] The first passivation layer 7 serves to passivate the surfaces it contacts, enhancing the passivation effect of the solar cell. This reduces carrier recombination at the interface, improves carrier transport efficiency, and thus increases the photoelectric conversion efficiency of the solar cell. The first passivation layer 7 also reduces or eliminates reflected light from the solar cell surface and increases light transmittance, further improving the photoelectric conversion efficiency of the solar cell.

[0081] Specifically, the first passivation layer 7 may include components such as silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride. In addition, the first passivation layer 7 may be a single-layer structure or a multi-layer structure, and the refractive index and thickness of each layer may be designed accordingly.

[0082] Furthermore, in another specific embodiment, such as Figure 2 As shown, the intrinsic polysilicon layer 4 includes a plurality of covering portions 41, which are used to cover the side surface of the doped conductive layer 3 away from the tunneling oxide layer 2. The plurality of covering portions 41 respectively cover the portions of the doped conductive layer 3 corresponding to the plurality of first electrodes 5.

[0083] In this embodiment, the intrinsic polycrystalline silicon layer 4 is composed of a plurality of spaced-apart covering portions 41. Each covering portion 41 covers a portion of the surface of the doped conductive layer 3 and corresponds to the positions of the plurality of first electrodes 5. This ensures that the first electrodes 5 can contact the covering portion 41 first and then the doped conductive layer 3, reducing the possibility that the first electrodes 5 can penetrate the tunnel oxide layer 2 and contact the substrate 1. Furthermore, the spaced-apart covering portions 41 help reduce the optical loss of the solar cell, allowing more light to be absorbed by the substrate 1, generating more charge carriers, and thus improving the photoelectric conversion efficiency of the solar cell. It also reduces the cost of setting the intrinsic polycrystalline silicon layer 4, thereby lowering the manufacturing cost of the solar cell.

[0084] Specifically, such as Figure 2 As shown, the solar cell also includes a first passivation layer 7. A portion of the first passivation layer 7 covers the portion of the doped conductive layer 3 where the cover portion 41 is not provided, and another portion of the first passivation layer 7 covers the surface of the cover portion 41 away from the doped conductive layer 3.

[0085] like Figure 2As shown, the first passivation layer 7 can completely cover all exposed parts on the surface of the doped conductive layer 3 away from the tunneling oxide layer 2, and can also completely cover the surface and side of the covered part 41 away from the doped conductive layer 3, thus playing a good passivation role, thereby reducing the recombination of charge carriers on the above-mentioned surface, improving the charge carrier transport efficiency, and thus improving the photoelectric conversion efficiency of the solar cell.

[0086] In one specific embodiment, such as Figure 3 As shown, the thickness D1 of the intrinsic polysilicon layer 4 satisfies: 10nm ≤ D1 ≤ 80nm. Specifically, the thickness D1 of the intrinsic polysilicon layer 4 can be 10nm, 30nm, 50nm, 70nm or 80nm, or other values ​​within the above range, which are not limited here.

[0087] When D1 is too small (e.g., less than 10 nm), the intrinsic polycrystalline silicon layer 4 is too thin, resulting in a small distance between the first electrode 5 and the tunneling oxide layer 2. The first electrode 5 can easily penetrate the tunneling oxide layer 2 and contact the substrate 1, leading to increased carrier recombination and affecting the photoelectric conversion efficiency of the solar cell. When D1 is too large (e.g., greater than 80 nm), the cost of the intrinsic polycrystalline silicon layer 4 increases, but the photoelectric conversion efficiency of the solar cell does not significantly improve. Therefore, when the thickness D1 of the intrinsic polycrystalline silicon layer 4 is between 10 nm and 80 nm, it is possible to ensure an improvement in the photoelectric conversion efficiency of the solar cell while appropriately reducing the manufacturing cost.

[0088] In one specific embodiment, such as Figure 3 As shown, the solar cell also includes a locally doped region 6, which is connected to the first electrode 5, the intrinsic polycrystalline silicon layer 4 and the doped conductive layer 3, respectively, so that the first electrode 5 is electrically connected to the doped conductive layer 3.

[0089] The intrinsic polysilicon layer 4 contains no doped elements. Compared to the doped conductive layer 3, the intrinsic polysilicon layer 4 has weaker conductivity. When the first electrode 5 does not penetrate the intrinsic polysilicon layer 4, that is, when the first electrode 5 only contacts the intrinsic polysilicon layer 4 and not the doped conductive layer 3, an electrical connection cannot be established between the first electrode 5 and the doped conductive layer 3, resulting in a decrease in the carrier transport rate. Therefore, a locally doped region 6 with stronger conductivity is needed to achieve the electrical connection between the first electrode 5 and the doped conductive layer 3.

[0090] Specifically, such as Figure 3As shown, the locally doped region 6 is located within the region of the intrinsic polysilicon layer 4 and the doped conductive layer 3. When the first electrode 5 does not penetrate the intrinsic polysilicon layer 4, the locally doped region 6 can connect with the first electrode 5, the intrinsic polysilicon layer 4, and the doped conductive layer 3 respectively, thereby achieving an electrical connection between the first electrode 5 and the doped conductive layer 3 and accelerating the carrier transport rate. When the first electrode 5 penetrates the intrinsic polysilicon layer 4 and forms an electrical connection with the doped conductive layer 3, the locally doped region 6 can further improve the conductivity between the first electrode 5 and the doped conductive layer 3, thereby accelerating the carrier transport rate.

[0091] Specifically, the first electrode 5 is a metal electrode, and the first electrode 5 and the doped conductive layer 3 have doping elements of the same conductivity type. The doping concentration of the first electrode 5 is greater than that of the doped conductive layer 3. The doping elements in the first electrode 5 penetrate toward the doped conductive layer 3 to form a local doped region 6.

[0092] When the first electrode 5 and the doped conductive layer 3 have doped elements of the same conductivity type, and the doping concentration of the first electrode 5 is greater than that of the doped conductive layer 3, during the high-temperature sintering process of the electrode paste, the doped elements can penetrate along the direction from high to low concentration to form local doped regions 6 extending from the first electrode 5 toward the doped conductive layer 3 at the intrinsic polycrystalline silicon layer 4 and the doped conductive layer 3. After local doped regions 6 are formed in a part of the intrinsic polycrystalline silicon layer 4, the conductivity of the region can be improved, which is beneficial to realize the electrical connection between the first electrode 5 and the doped conductive layer 3, thereby improving the performance of the solar cell.

[0093] Specifically, the doping element can be an N-type dopant of group V elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb), or a P-type dopant of group III elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In).

[0094] In addition, the first electrode 5 is sintered from a metal electrode paste. The proportion of doped elements in the metal electrode paste to the total composition of the paste is 0.01% to 5%, specifically 0.01%, 0.05%, 1%, 3% or 5%, or other values ​​within the above range, which are not limited here.

[0095] After forming the local doped region 6, the ratio of the doping concentration of the doped element in the local doped region 6 to the doping concentration of the doped element in the doped conductive layer 3 is 1:100 to 1:1. Specifically, it can be 1:100, 1:80, 1:50, 1:30 or 1:1, or other values ​​within the above range, which are not limited here.

[0096] Specifically, the concentration of dopant elements in the doped conductive layer 3 is 1×10⁻⁶.20 atoms / cm 3 ~1×10 21 atoms / cm 3 The concentration of doped elements in local doped region 6 is 1×10⁶. 19 atoms / cm 3 ~1×10 20 atoms / cm 3 .

[0097] Optionally, the concentration of dopant elements in the doped conductive layer 3 can be 1×10⁻⁶. 20 atoms / cm 3 0.3×10 21 atoms / cm 3 0.5×10 21 atoms / cm 3 0.8×10 21 atoms / cm 3 Or 1×10 21 atoms / cm 3 It can also be any other value within the above range, and is not limited here.

[0098] Optionally, the concentration of the dopant element in the locally doped region 6 can be 1×10⁻⁶. 19 atoms / cm 3 0.3×10 20 atoms / cm 3 0.5×10 20 atoms / cm 3 0.8×10 20 atoms / cm 3 Or 1×10 20 atoms / cm 3 It can be any other value within the above range, and is not limited here.

[0099] When the concentrations of doped elements in the doped conductive layer 3 and the local doped region 6 meet the above-mentioned ranges, it can be ensured that a stable electrical connection can be formed between the first electrode 5 and the doped conductive layer 3, thereby improving the carrier transport rate and thus improving the performance of the solar cell.

[0100] In one specific embodiment, the first electrode 5 and the substrate 1 have doped elements of the same conductivity type.

[0101] In this embodiment, the first electrode 5 has the same doping element as the substrate 1, which can be an N-type dopant including group V elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb), or a P-type dopant including group III elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In).

[0102] In another specific embodiment, the first electrode 5 and the substrate 1 are doped with dopants of different conductivity types.

[0103] In this embodiment, the doping elements in the first electrode 5 are different from those in the substrate 1. When the doping elements in the substrate 1 are N-type dopants including group V elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb), the doping elements in the first electrode 5 are P-type dopants including group III elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In). Alternatively, when the doping elements in the substrate 1 are P-type dopants including group III elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In), the doping elements in the first electrode 5 are N-type dopants including group V elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb).

[0104] In one specific embodiment, the cross-sectional area of ​​the locally doped region 6 is 1×10⁻⁶. -8 mm 2 ~1×10 -6 mm 2 Optionally, the cross-sectional area of ​​the locally doped region 6 can be 1×10⁻⁶. -8 mm 2 0.5×10 -7 mm 2 1×10 -7 mm 2 0.5×10 -6 mm 2 Or 1×10 -6 mm 2 It can also be any other value within the above range, and is not limited here.

[0105] When the cross-sectional area of ​​the local doped region 6 is too small (e.g., less than 1×10), -8 mm 2 When the area of ​​the first electrode 5 and the doped conductive layer 3 is too small, it will result in an insufficient contact area, which is not conducive to the transport of charge carriers; when the cross-sectional area of ​​the local doped region 6 is too large (e.g., greater than 1×10), it will result in an insufficient contact area between the first electrode 5 and the doped conductive layer 3, which will hinder the transport of charge carriers. -6 mm 2When this is done, the concentration of doping elements in the first electrode 5 needs to be increased, meaning more doping elements need to be incorporated into the electrode paste. This significantly increases the manufacturing difficulty and cost of the first electrode 5, but the carrier transport rate does not improve significantly. Therefore, when the cross-sectional area of ​​the locally doped region 6 is 1×10⁻⁶, -8 mm 2 ~1×10 -6 mm 2 This approach can increase the contact area between the first electrode 5 and the doped conductive layer 3, thereby improving the carrier transport efficiency, and can also appropriately reduce the manufacturing cost of solar cells.

[0106] In one specific embodiment, such as Figure 3 As shown, the first electrode 5 includes a body 51 and an extension 52 extending along the body 51 toward the doped conductive layer 3. The extension 52 is located within the intrinsic polysilicon layer 4 and / or the doped conductive layer 3, and there is a gap between the top end of the extension 52 and the substrate 1. A locally doped region 6 covers the extension 52.

[0107] like Figure 3 As shown, the body 51 is disposed on the side of the intrinsic polysilicon layer 4 away from the doped conductive layer 3. The body 51 does not directly contact the doped conductive layer 3, which can reduce the damage to the field passivation layer and ensure that the first surface 1a has a good passivation effect. The extension 52 is electrically connected to the first body 51, and both can play the role of transporting charge carriers. The extension 52 extends along the direction of the body 51 toward the doped conductive layer 3. The extension 52 is formed by the electrode paste penetrating toward the doped conductive layer 3 during the sintering process of the electrode paste. The intrinsic polysilicon layer 4 can prevent the extension 52 from penetrating the tunnel oxide layer 2, so that there is a gap between the top of the extension 52 and the substrate 1. The locally doped region 6 covers the surface of the extension 52 that is in contact with the body 51 and can be connected to the intrinsic polysilicon layer 4 and the doped conductive layer 3 to realize the electrical connection between the extension 52 and the doped conductive layer 3.

[0108] Specifically, such as Figure 3 As shown, the extension 52 includes a first part 521 and a second part 522. The first part 521 is connected to the body 51. The second part 522 is spaced apart from both the body 51 and the first part 521. A portion of the locally doped region 6 covers the first part 521, and another portion of the locally doped region 6 covers the second part 522.

[0109] The extension 52 has two forms: one is a first part 521 that is directly connected to the body 51, and the other is a second part 522 that is spaced apart from the body 51. The second part 522 is a free-state grain. The surfaces of the first part 521 and the second part 522 are covered with local doped regions 6 to ensure a stable electrical connection between the extension 52 and the doped conductive layer 3.

[0110] In one specific embodiment, such as Figure 3 As shown, the thickness D2 of the doped conductive layer 3 satisfies: 10nm ≤ D2 ≤ 80nm. Specifically, the thickness D2 of the doped conductive layer 3 can be 10nm, 30nm, 50nm, 70nm or 80nm, or other values ​​within the above range, which are not limited here.

[0111] In this embodiment, when the thickness D2 of the doped conductive layer 3 is 10nm≤D2≤80nm, it can ensure the reliability of the electrical connection between the first electrode 5 and the doped conductive layer 3, improve the carrier transport rate, reduce the light absorption capacity of the doped conductive layer 3, thereby reducing the optical loss of the solar cell, improving the cell efficiency of the solar cell, and also reduce the overall thickness and weight of the solar cell, making it easier to install and transport.

[0112] In one specific embodiment, such as Figure 1 As shown, the substrate 1 also has a second surface 1b disposed opposite to the first surface 1a. The solar cell also includes an emitter 8, a second electrode 9, and a second passivation layer 10. The emitter 8 is disposed on the second surface 1b, and a plurality of second electrodes 9 are disposed on the side of the emitter 8 away from the substrate 1. The plurality of second electrodes 9 are electrically connected to the emitter 8, and the second passivation layer 10 covers the side of the emitter 8 away from the substrate 1.

[0113] Both the first surface 1a and the second surface 1b of the substrate 1 can be used to receive incident light or reflect light, such as Figure 1 As shown, an emitter 8, a second electrode 9, and a second passivation layer 10 are sequentially disposed on the second surface 1b opposite to the first surface 1a. When the substrate 1 is a P-type silicon substrate, the emitter 8 can be an N-type emitter, and the two can together form a PN junction structure. Alternatively, when the substrate 1 is an N-type silicon substrate, the emitter 8 can be a P-type emitter. The second passivation layer 10 has a similar function and effect to the first passivation layer 7, namely, it passivates the surfaces in contact with it, thereby reducing carrier recombination at the interface, improving carrier transport efficiency, and thus improving the photoelectric conversion efficiency of the solar cell.

[0114] In addition, such as Figure 1As shown, the second surface 1b of the substrate 1 can be configured as a pyramidal textured surface to reduce the reflectivity of the second surface 1b to incident light and increase the light absorption and utilization rate, thereby improving the light transmittance of the second surface 1b and thus improving the photoelectric conversion efficiency of the solar cell. The first surface 1a of the substrate 1 can be configured as a non-pyramidal textured surface, such as a layered stepped morphology, to give the tunneling oxide layer 2 on the first surface 1a high density and uniformity, so that the tunneling oxide layer 2 has a good passivation effect on the substrate 1. Specifically, the first surface 1a can be the back side of the substrate 1, that is, the side of the substrate 1 facing away from the sun, and correspondingly, the second surface 1b can be the front side of the substrate 1, that is, the side of the substrate 1 facing the sun and used to receive sunlight; or, the first surface 1a can also be the front side of the substrate 1, and correspondingly, the second surface 1b can also be the back side of the substrate 1.

[0115] This application also provides a photovoltaic module, such as... Figure 4 As shown, the photovoltaic module includes a battery string 110, an encapsulation layer 120, and a cover plate 130. The battery string 110 is composed of multiple solar cells connected together. The solar cells are the solar cells described in the above embodiments. The encapsulation layer 120 is used to cover the surface of the battery string 110, and the cover plate 130 is used to cover the surface of the encapsulation layer 120 away from the battery string 110.

[0116] like Figure 4 As shown, solar cells are electrically connected in a single unit or in multiple segments to form multiple cell strings 110, which are electrically connected in series and / or parallel. Specifically, the multiple cell strings 110 can be electrically connected to each other via conductive strips 140. An encapsulation layer 120 covers the front and back of the solar cell. Specifically, the encapsulation layer 120 can be an organic encapsulation film such as ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene copolymer elastomer (POE) film, polyethylene terephthalate (PET) film, or polyvinyl butyral (PVB). A cover plate 130 can be a light-transmitting cover plate such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate 130 facing the encapsulation layer 120 can be an uneven surface to increase the utilization rate of incident light.

[0117] The solar cell is provided with an intrinsic polycrystalline silicon layer 4, which can prevent the tunnel oxide layer 2 from being damaged by the first electrode 5, thereby improving the photoelectric conversion efficiency of the solar cell. Thus, the photoelectric conversion efficiency of the photovoltaic module containing the solar cell can also be improved.

[0118] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A solar cell, characterized in that, The solar cell includes: A substrate (1) having a first surface (1a); A tunneling oxide layer (2) is formed on the first surface (1a). A doped conductive layer (3) is provided, which covers the surface of the tunneling oxide layer (2) away from the substrate (1) and is used to form a field passivation layer. The intrinsic polysilicon layer (4) includes a plurality of cover portions (41) for covering the side surface of the doped conductive layer (3) away from the tunneling oxide layer (2). First electrode (5), a plurality of first electrodes (5) are disposed on the side of the intrinsic polysilicon layer (4) away from the doped conductive layer (3), and the plurality of first electrodes (5) are electrically connected to the doped conductive layer (3); The plurality of covering portions (41) respectively cover the portion of the doped conductive layer (3) corresponding to the plurality of first electrodes (5), at least a portion of the first electrodes (5) is located within the covering portion (41), and there is a gap between the end of the first electrode (5) near the substrate (1) and the substrate (1). The solar cell further includes a first passivation layer (7), a portion of which covers the part of the doped conductive layer (3) where the covering portion (41) is not provided, and another portion of which covers the surface of the covering portion (41) away from the doped conductive layer (3).

2. The solar cell according to claim 1, characterized in that, The thickness D1 of the intrinsic polycrystalline silicon layer (4) satisfies: 10nm≤D1≤80nm.

3. The solar cell according to claim 1, characterized in that, The solar cell further includes a locally doped region (6), which is connected to the first electrode (5), the intrinsic polycrystalline silicon layer (4) and the doped conductive layer (3) respectively, so that the first electrode (5) is electrically connected to the doped conductive layer (3).

4. The solar cell according to claim 3, characterized in that, The first electrode (5) is a metal electrode. The first electrode (5) and the doped conductive layer (3) have doping elements of the same conductivity type, and the doping concentration of the first electrode (5) is greater than the doping concentration of the doped conductive layer (3). The doping element in the first electrode (5) penetrates toward the doped conductive layer (3) to form the local doped region (6).

5. The solar cell according to claim 4, characterized in that, The concentration of the doped element in the doped conductive layer (3) is 1×10⁻⁶. 20 atoms / cm 3 ~1×10 21 atoms / cm 3 .

6. The solar cell according to claim 4, characterized in that, The concentration of the dopant element in the local doped region (6) is 1×10⁻⁶. 19 atoms / cm 3 ~1×10 20 atoms / cm 3 .

7. The solar cell according to claim 4, characterized in that, The first electrode (5) has the same type of dopant as the substrate (1).

8. The solar cell according to claim 4, characterized in that, The first electrode (5) and the substrate (1) have doped elements with different conductivity types.

9. The solar cell according to claim 3, characterized in that, The cross-sectional area of ​​the locally doped region (6) is 1×10 -8 mm 2 ~1×10 -6 mm 2 .

10. The solar cell according to claim 3, characterized in that, The first electrode (5) includes a body (51) and an extension (52) extending along the body (51) toward the doped conductive layer (3). The extension (52) is located within the intrinsic polysilicon layer (4) and / or the doped conductive layer (3), and there is a gap between the end of the extension (52) near the substrate (1) and the substrate (1), and the local doped region (6) covers the extension (52).

11. The solar cell according to claim 10, characterized in that, The extension (52) includes a first part (521) and a second part (522), the first part (521) being connected to the body (51), and the second part (522) being spaced apart from both the body (51) and the first part (521); A portion of the local doped region (6) covers the first portion (521), and another portion of the local doped region (6) covers the second portion (522).

12. The solar cell according to claim 1, characterized in that, The thickness D2 of the doped conductive layer (3) satisfies: 10nm≤D2≤80nm.

13. The solar cell according to any one of claims 1-12, characterized in that, The substrate (1) also has a second surface (1b) disposed opposite to the first surface (1a); The solar cell also includes: Emitter (8), the emitter (8) is disposed on the second surface (1b); Second electrode (9), a plurality of second electrodes (9) are disposed on the side of the emitter (8) away from the substrate (1), and the plurality of second electrodes (9) are electrically connected to the emitter (8); A second passivation layer (10) is applied to the surface of the emitter (8) away from the substrate (1).

14. A photovoltaic module, characterized in that, The photovoltaic module includes: A battery string (110), wherein the battery string (110) is composed of multiple solar cells connected together, wherein the solar cells are any one of claims 1-13; An encapsulation layer (120) is used to cover the surface of the battery string (110); A cover plate (130) is used to cover the surface of the encapsulation layer (120) away from the battery string (110).

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