Current limiting method and device of three-leg topology circuit, storage medium and processor

Abstract

This application discloses a current limiting method, apparatus, storage medium, and processor for a three-arm bridge topology circuit. The method includes: acquiring the current value flowing through the inverter inductor; comparing the current value with a first preset current value; and if the current value is greater than the first preset current value, performing a blocking process on the target switch on the third arm. This application solves the problem in related technologies where, when current limiting is applied to the inverter output side of a three-arm bridge topology circuit, simultaneously shutting down the switches of the second and third arms can lead to high bus voltage and shutdown of the inverter output module.

Description

Technical Field

[0001] This application relates to the field of power supply technology, and more specifically, to a current limiting method and apparatus, storage medium and processor for a three-bridge-arm topology circuit. Background Technology

[0002] In recent years, the three-arm topology has become increasingly popular because it requires fewer switching transistors to achieve the same PFC and INV functions. The three-arm topology is a highly efficient PFC and INV topology. Its characteristics include a single-bus, bridgeless PFC input and a single-bus, full-bridge INV output; the PFC and INV share the second arm, and the currents in the second arm almost cancel each other out when the input and output operate at the same frequency, resulting in high overall efficiency.

[0003] like Figure 1 As shown, during the positive half-cycle of the input voltage, the body diodes of VT2 and VT1 form a boost circuit to control the bus voltage. During the negative half-cycle of the input voltage, the body diodes of VT1 and VT2 form a boost circuit to control the bus voltage. VT4 and VT5 are turned on during the positive half-cycle of the inverter voltage, and VT6 and VT3 are turned on during the negative half-cycle of the inverter voltage.

[0004] Depending on the performance of different manufacturers and models of switching transistors, the current flowing through the transistor when it is turned on is limited; otherwise, the transistor will be thermally damaged. For example, in a three-arm bridge topology, when the input and output voltages are strictly in phase, the input and output sides can achieve decoupling control, independent of the middle arm. When the input and output voltages are out of phase, the inverter output requires the middle arm to generate a waveform, causing uncontrolled rectification at the input, leading to bus voltage runaway and damage to the switching transistor. Due to the parallel phase-locked loop (PLL) mechanism, this inevitably results in input and output phase mismatch. If there is a phase deviation, such as during the negative half-cycle of the input voltage while the inverter voltage is in the positive half-cycle, VT1 and VT4 will conduct simultaneously, creating a loop where the DC bus voltage is superimposed on the input voltage. This inductor saturation and large current can damage the switching transistor on the PFC side. Similarly, when a load short circuit occurs on the output side, or when operating with a nonlinear load, a large current will flow through the inverter transistors. If this current is not limited, it will damage the inverter switching transistors. Therefore, when current-limiting conditions occur, it is necessary to appropriately close the corresponding switching transistors to prevent large currents from flowing through them, thereby protecting the switching transistors.

[0005] To address the above situation, current technology involves simultaneously applying CBC blocking to four switches (VT1-VT4) when current limiting is triggered on the PFC side, and simultaneously applying CBC blocking to four switches (VT3-VT6) when current limiting is triggered on the INV side. However, this approach has drawbacks. While it's feasible to shut down four switches (VT1-VT4) when current limiting is triggered on the PFC side, simultaneously shutting down four switches (VT3-VT6) on the INV side can lead to high voltage on the bus, potentially causing the inverter output to shut down.

[0006] When the three-arm bridge topology is operating normally, and input / output phase misalignment, heavy output load, rectifier load, or short circuit occurs, large currents will appear. To protect the switching transistors from overcurrent damage, current limiting is necessary for overcurrent protection. For example, during the positive half-cycle of the inverter voltage, when VT5 and VT4 are conducting, if a load short circuit occurs, the inverter inductor current i... L3 When the voltage increases beyond the threshold that the switching transistors can withstand, pre-set in the DSP, VT5 and VT4 are immediately shut down, effectively blocking the waveform. Figure 2 When a short circuit occurs in the inverter, if CBC current limiting is applied to both the middle and third bridge arms simultaneously, as analyzed above, the following situation will occur: Figure 2 In the circuit shown, the bus voltage is boosted. Figure 2 In the middle, after VT5 and VT4 are blocked, due to the inverter inductor current i L3 Abrupt changes are not allowed. A circuit exists consisting of the inverter inductor L3, output filter capacitor C2, intermediate bridge arm energy storage inductor L2, anti-parallel diode D3 of the upper switch VT3 in the intermediate bridge arm, bus capacitor C1, and anti-parallel diode D6 of the lower switch VT6 in the third bridge arm. This circuit will inevitably cause the bus voltage to spike. Theoretically, after the bus voltage is spiked, it can be reverse-fed back to the input source via the three-arm PFC control, such as... Figure 3 The circuit shown. However, because the middle and third bridge arms are CBC current-limited with a high current-limiting frequency, the bus voltage almost continuously surges to the threshold that the bus capacitor can withstand. At this point, the high voltage on the bus will be triggered, causing the inverter module's output to be shut down.

[0007] In summary, when certain extreme operating conditions occur on the inverter side, resulting in large currents, appropriate blocking measures should be applied to the corresponding switches in the circuit topology. Based on the above analysis, simply blocking all four switches in the middle and third bridge arms would immediately cause the bus high-voltage to shut down.

[0008] There is currently no effective solution to the problem that when current limiting is applied to the inverter output side of a three-arm bridge circuit, the switching transistors of the second and third arms need to be turned off simultaneously, which can lead to high bus voltage and shutdown of the inverter output module. Summary of the Invention

[0009] The main objective of this application is to provide a current limiting method, device, storage medium, and processor for a three-arm bridge topology circuit, in order to solve the problem in related technologies where, when current limiting is applied to the inverter output side of a three-arm bridge topology circuit, the switching transistors of the second and third arms need to be turned off simultaneously, which would result in high bus voltage and shutdown of the inverter output module.

[0010] To achieve the above objectives, according to one aspect of this application, a current limiting method for a three-bridge-arm topology circuit is provided. The method includes: acquiring the current value flowing through the inverter inductor; comparing the current value with the first preset current value; and if the current value is greater than the first preset current value, performing wave blocking processing on the target switch transistor on the third bridge arm.

[0011] Furthermore, after the target switch on the third bridge arm is subjected to wave blocking processing, the method further includes: comparing the current value with a second preset current value, wherein the second preset current value is greater than the first preset current value; if the current value is greater than the second preset current value, then the target switch on the second bridge arm is subjected to wave blocking processing.

[0012] Furthermore, after the target switch on the third bridge arm is blocked, the method further includes: if the current value is detected to be no greater than the first preset current value, then the target switch on the third bridge arm is unblocked.

[0013] Furthermore, after the target switch on the second bridge arm is blocked, the method further includes: if the current value is detected to be no greater than the second preset current value, then the target switch on the second bridge arm is unblocked.

[0014] Furthermore, before comparing the current value with the first preset current value, the method further includes: determining the model and performance of the switching transistors on the second bridge arm and the third bridge arm; configuring the first preset current value and the second preset current value according to the model and performance of the switching transistors on the second bridge arm and the third bridge arm, wherein the first preset current value is the second maximum current threshold that the switching transistors on the second bridge arm and the third bridge arm can withstand, and the second preset current value is the maximum current threshold that the switching transistors on the second bridge arm and the third bridge arm can withstand.

[0015] To achieve the above objectives, according to another aspect of this application, a current limiting device for a three-bridge-arm topology circuit is provided. The device includes: a first acquisition unit for acquiring the current value flowing through the inverter inductor; a first comparison unit for comparing the current value with a first preset current value; and a first processing unit for performing wave blocking processing on a target switch on the third bridge arm if the current value is greater than the first preset current value.

[0016] Furthermore, the device further includes: a second comparison unit, configured to compare the current value with a second preset current value after the target switch on the third bridge arm has undergone wave blocking processing, wherein the second preset current value is greater than the first preset current value; and a second processing unit, configured to perform wave blocking processing on the target switch on the second bridge arm if the current value is greater than the second preset current value.

[0017] Furthermore, the device also includes a third processing unit, which, after the target switch on the third bridge arm is subjected to wave blocking processing, if the current value is detected to be no greater than the first preset current value, then performs unblocking processing on the target switch on the third bridge arm.

[0018] Furthermore, the device also includes a fourth processing unit, which, after the target switch on the second bridge arm is subjected to wave blocking processing, if the current value is detected to be no greater than the second preset current value, then performs unblocking processing on the target switch on the second bridge arm.

[0019] Furthermore, the device further includes: a first determining unit, configured to determine the model and performance of the switching transistors on the second bridge arm and the third bridge arm before comparing the current value with a first preset current value; and a first configuring unit, configured to configure the first preset current value and the second preset current value according to the model and performance of the switching transistors on the second bridge arm and the third bridge arm, wherein the first preset current value is the second maximum current threshold that the switching transistors on the second bridge arm and the third bridge arm can withstand, and the second preset current value is the maximum current threshold that the switching transistors on the second bridge arm and the third bridge arm can withstand.

[0020] This application employs the following steps: obtaining the current value flowing through the inverter inductor; comparing the current value with a first preset current value; if the current value is greater than the first preset current value, then performing a voltage blocking process on the target switch on the third bridge arm. This solves the problem in related technologies where, when current limiting is applied to the inverter output side of a three-bridge-arm topology, the switches of both the second and third bridge arms need to be turned off simultaneously, which can lead to high bus voltage and shutdown of the inverter output module. By comparing the current value with the first preset current value, and performing a voltage blocking process on the target switch on the third bridge arm when the current value is greater than the first preset current value, the target switch can be protected from overcurrent damage. This avoids the problem of high bus voltage and shutdown of the inverter output module when current limiting is applied to the inverter output side of a three-bridge-arm topology, thereby improving the stability of the three-bridge-arm topology. Attached Figure Description

[0021] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0022] Figure 1 This is a schematic diagram of a three-bridge-arm topology circuit based on existing technology;

[0023] Figure 2 This is a schematic diagram of the current flow direction in a three-bridge-arm topology circuit when a short circuit occurs in the inverter, based on existing technology.

[0024] Figure 3 This is a schematic diagram of the current flow direction in a three-bridge arm topology circuit when the bus voltage rises and the reverse feedback to the input source is controlled by PFC, based on existing technology.

[0025] Figure 4 This is a flowchart of a current limiting method for a three-arm bridge topology circuit according to an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of the current flow direction in a three-arm bridge topology circuit when a short circuit occurs in the inverter, according to an embodiment of this application.

[0027] Figure 6 This is a flowchart of the first-stage current limiting method for a three-arm topology circuit according to an embodiment of this application;

[0028] Figure 7 This is a flowchart of the second-stage current limiting method for a three-arm topology circuit according to an embodiment of this application;

[0029] Figure 8 This is a schematic diagram of a current limiting device for a three-arm bridge topology circuit provided in an embodiment of this application. Detailed Implementation

[0030] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] According to an embodiment of this application, a current limiting method for a three-bridge-arm topology circuit is provided.

[0034] Figure 4 This is a flowchart of a current limiting method for a three-arm bridge topology circuit according to an embodiment of this application, such as... Figure 4 As shown, the method includes the following steps:

[0035] Step S101: Obtain the current value flowing through the inverter inductor.

[0036] like Figure 1 The three-arm topology circuit shown includes a first arm, a second arm, and a third arm, which are connected in parallel. The third arm is connected to the inverter inductor L3. Therefore, it is necessary to obtain the current flowing through the inverter inductor L3, i.e., the inverter inductor current i. L3 .

[0037] Step S102: Compare the current value with the first preset current value.

[0038] The inverter inductor current i L3 Compare with the first preset current value.

[0039] Step S103: If the current value is greater than the first preset current value, then the target switch on the third bridge arm is subjected to wave blocking processing.

[0040] If the inverter inductor current i L3 If the current is greater than the first preset current value, then... Figure 1 In a three-arm bridge topology, the VT5 or VT6 switch on the third arm is blocked. Even if the VT5 or VT6 switch is not conducting, a large current will not flow through it, thus preventing overcurrent damage. For example, when the positive half-cycle of the inverter output voltage is short-circuited, VT5 immediately performs CBC blocking, while VT4 is not blocked. The current flow in the three-arm bridge topology is as follows: Figure 5 As shown, the path is: inverter filter inductor L3 → filter capacitor C2 → intermediate bridge arm energy storage inductor L2 → switching transistor VT4 → anti-parallel diode D6 of VT6 → back to filter inductor L3. Since this path does not pass through the bus, the bus voltage will not be boosted, so there will be no high bus voltage phenomenon.

[0041] Through the above steps S101 to S103, by comparing the current value with the first preset current value, when the current value is greater than the first preset current value, the target switch on the third bridge arm is subjected to a blocking process, which can protect the target switch from overcurrent damage. This avoids the problem of high bus voltage and shutdown of the inverter output module when current is limited on the inverter output side of the three-bridge-arm topology circuit, thereby improving the stability of the three-bridge-arm topology circuit.

[0042] Optionally, in the current limiting method for the three-arm topology circuit provided in the embodiments of this application, after the target switch on the third arm is subjected to wave blocking processing, the method further includes: comparing the current value with a second preset current value, wherein the second preset current value is greater than the first preset current value; if the current value is greater than the second preset current value, then the target switch on the second arm is subjected to wave blocking processing.

[0043] like Figure 1 The three-bridge topology circuit shown, after blocking the VT5 or VT6 switch on the third bridge arm, will reduce the inverter inductor current i L3 The current is compared with a second preset current value, where the second preset current value is greater than the first preset current value. If the inverter inductor current i L3 If the current exceeds the second preset value, the VT3 or VT4 switch on the second bridge arm will be blocked, so that even if the VT3 or VT4 switch on the second bridge arm is in a non-conducting state, a large current will not flow through the VT3 or VT4 switch.

[0044] In summary, by applying a waveform blocking treatment to the switching transistors on the second bridge arm, the transistors on the second bridge arm can be effectively protected from overcurrent damage. Furthermore, by applying the waveform blocking treatment to the target switching transistors on the third bridge arm before treating the target switching transistors on the second bridge arm, the possibility of high voltage on the bus causing the inverter output module to shut down is avoided, thereby improving the stability of the three-bridge arm topology circuit.

[0045] Optionally, in the current limiting method for the three-arm topology circuit provided in the embodiments of this application, after the target switch on the third arm is blocked, the method further includes: if the current value is detected to be no greater than the first preset current value, then the target switch on the third arm is unblocked.

[0046] like Figure 1 In the three-bridge topology circuit shown, after blocking the VT5 or VT6 switch on the third bridge arm, if the inverter inductor current i is detected... L3 If the current does not exceed the first preset current value, the VT5 or VT6 switch on the third bridge arm is unblocked, even if the VT5 or VT6 switch on the third bridge arm is in a conducting state. This is because the inverter inductor current i at this time... L3 This is not considered excessive current, therefore current can flow through switching transistors VT5 or VT6. The flowchart is as follows: Figure 6 As shown.

[0047] In summary, by unsealing the switching transistors on the third bridge arm, the switching transistors on the third bridge arm can be effectively protected from overcurrent damage.

[0048] Optionally, in the current limiting method for the three-arm topology circuit provided in the embodiments of this application, after the target switch on the second arm is blocked, the method further includes: if the current value is detected to be no greater than a second preset current value, then the target switch on the second arm is unblocked.

[0049] like Figure 1 In the three-bridge topology circuit shown, after blocking the VT3 or VT4 switch on the second bridge arm, if the inverter inductor current i is detected... L3 If the current does not exceed the first preset current value, the VT3 or VT4 switch on the second bridge arm is de-encoded, even if the VT3 or VT4 switch on the second bridge arm is in a conducting state. This is because the inverter inductor current i at this time... L3 This is not considered excessive current, therefore current can flow through switching transistors VT3 or VT4. (Flowchart shown below) Figure 7 As shown.

[0050] In summary, by unsealing the switching transistors on the second bridge arm, the switching transistors on the second bridge arm can be effectively protected from overcurrent damage.

[0051] Optionally, in the current limiting method for the three-arm topology circuit provided in this application embodiment, before comparing the current value with the first preset current value, the method further includes: determining the model and performance of the switching transistors on the second and third arms; configuring the first preset current value and the second preset current value according to the model and performance of the switching transistors on the second and third arms, wherein the first preset current value is the second maximum current threshold that the switching transistors on the second and third arms can withstand, and the second preset current value is the maximum current threshold that the switching transistors on the second and third arms can withstand.

[0052] In the inverter inductor current i L3 Before comparing with the first preset current value, the inverter inductor current i of the inverter output module is first... L3 Connect to a pin of the DSP, such as pin C1, and connect it to a CMPSS comparator module in the chip, such as CMP2, through the DSP's underlying configuration file; then estimate the submaximum withstand current threshold i based on the type and performance of the switching transistors on the second and third arms of the inverter output module. max1 And set it in the DSP's comparison submodule CMPSS (CMP2); then set the inverter inductor current i of the inverter output module. L3 Connect to another pin of the DSP, such as pin C6, and connect to another comparator module CMPSS in the chip, such as CMP3, through the DSP's low-level configuration; based on the estimated submaximum withstand current threshold i max1 Determine the maximum current threshold i that the switching transistors of the inverter output module can withstand. max2 And set it in another comparison submodule of the DSP, CMPSS (CMP3), where i max2 >i max1 The difference can be determined based on the specific project, such as 5A.

[0053] The above solution allows for the accurate configuration of the current threshold that the switching transistor can withstand in the DSP by considering the model and performance of the switching transistor in the inverter output module, thereby providing better protection for the switching transistor.

[0054] In summary, the current limiting method for the three-arm topology circuit provided in this application obtains the current value flowing through the inverter inductor; compares the current value with a first preset current value; and if the current value is greater than the first preset current value, performs a blocking process on the target switch on the third arm. This solves the problem in related technologies where, when current limiting is applied to the inverter output side of a three-arm topology circuit, the switches of the second and third arms need to be turned off simultaneously, which can lead to high bus voltage and shutdown of the inverter output module. By comparing the current value with the first preset current value, and performing a blocking process on the target switch on the third arm when the current value is greater than the first preset current value, the target switch can be protected from overcurrent damage. This avoids the problem of high bus voltage and shutdown of the inverter output module when current limiting is applied to the inverter output side of a three-arm topology circuit, thereby improving the stability of the three-arm topology circuit.

[0055] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0056] This application also provides a current limiting device for a three-arm topology circuit. It should be noted that the current limiting device for the three-arm topology circuit in this application can be used to execute the current limiting method for the three-arm topology circuit provided in this application. The current limiting device for the three-arm topology circuit provided in this application will be described below.

[0057] Figure 8 This is a schematic diagram of a current limiting device for a three-arm bridge topology circuit according to an embodiment of this application. Figure 8 As shown, the device includes: a first acquisition unit 801, a first comparison unit 802, and a first processing unit 803.

[0058] Specifically, the first acquisition unit 801 is used to acquire the current value flowing through the inverter inductor;

[0059] The first comparison unit 802 is used to compare the current value with a first preset current value;

[0060] The first processing unit 803 is used to perform wave blocking processing on the target switch on the third bridge arm if the current value is greater than the first preset current value.

[0061] In summary, the current limiting device for the three-arm topology circuit provided in this application embodiment acquires the current value flowing through the inverter inductor through the first acquisition unit 801; the first comparison unit 802 compares the current value with a first preset current value; and the first processing unit 803 performs a blocking process on the target switch on the third arm if the current value is greater than the first preset current value. This solves the problem in related technologies where, when current limiting is applied to the inverter output side of the three-arm topology circuit, the switches of the second and third arms need to be turned off simultaneously, which can lead to high bus voltage and shutdown of the inverter output module. By comparing the current value with the first preset current value, and performing a blocking process on the target switch on the third arm when the current value is greater than the first preset current value, the target switch can be protected from overcurrent damage. This avoids the problem of high bus voltage and shutdown of the inverter output module when current limiting is applied to the inverter output side of the three-arm topology circuit, thereby improving the stability of the three-arm topology circuit.

[0062] Optionally, in the current limiting device for the three-arm topology circuit provided in the embodiments of this application, the device further includes: a second comparison unit, used to compare the current value with a second preset current value after the target switch on the third arm is subjected to wave blocking processing, wherein the second preset current value is greater than the first preset current value; and a second processing unit, used to perform wave blocking processing on the target switch on the second arm if the current value is greater than the second preset current value.

[0063] Optionally, in the current limiting device for the three-arm topology circuit provided in the embodiments of this application, the device further includes: a third processing unit, used to unblock the target switch on the third arm if the current value is detected to be no greater than a first preset current value after the target switch on the third arm has been blocked.

[0064] Optionally, in the current limiting device for the three-arm topology circuit provided in the embodiments of this application, the device further includes: a fourth processing unit, used to unblock the target switch on the second arm if the current value is detected to be no greater than a second preset current value after the target switch on the second arm has been blocked.

[0065] Optionally, in the current limiting device for the three-arm topology circuit provided in the embodiments of this application, the device further includes: a first determining unit, configured to determine the model and performance of the switching transistors on the second and third arms before comparing the current value with a first preset current value; and a first configuring unit, configured to configure a first preset current value and a second preset current value according to the model and performance of the switching transistors on the second and third arms, wherein the first preset current value is the second maximum current threshold that the switching transistors on the second and third arms can withstand, and the second preset current value is the maximum current threshold that the switching transistors on the second and third arms can withstand.

[0066] The current limiting device of the three-bridge-arm topology circuit includes a processor and a memory. The first acquisition unit 801, the first comparison unit 802 and the first processing unit 803 are all stored in the memory as program units. The processor executes the program units stored in the memory to realize the corresponding functions.

[0067] The processor contains a core, which retrieves the corresponding program unit from memory. One or more cores can be configured, and adjusting core parameters can improve the stability of the three-arm bridge topology.

[0068] The memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0069] This invention provides a storage medium storing a program that, when executed by a processor, implements a current limiting method for the three-bridge-arm topology circuit.

[0070] This invention provides a processor for running a program, wherein the program executes a current limiting method for the three-bridge-arm topology circuit.

[0071] This invention provides a device including a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, it performs the following steps: acquiring the current value flowing through the inverter inductor; comparing the current value with a first preset current value; and if the current value is greater than the first preset current value, performing wave blocking processing on the target switch on the third bridge arm.

[0072] When the processor executes the program, it also performs the following steps: after the target switch on the third bridge arm is subjected to wave blocking processing, the method further includes: comparing the current value with a second preset current value, wherein the second preset current value is greater than the first preset current value; if the current value is greater than the second preset current value, then the target switch on the second bridge arm is subjected to wave blocking processing.

[0073] When the processor executes the program, it also performs the following steps: after the target switch on the third bridge arm is blocked, the method further includes: if the current value is detected to be no greater than the first preset current value, then the target switch on the third bridge arm is unblocked.

[0074] When the processor executes the program, it also performs the following steps: after the target switch on the second bridge arm is blocked, the method further includes: if the current value is detected to be no greater than the second preset current value, the target switch on the second bridge arm is unblocked.

[0075] When the processor executes the program, it also performs the following steps: before comparing the current value with the first preset current value, the method further includes: determining the model and performance of the switching transistors on the second bridge arm and the third bridge arm; configuring the first preset current value and the second preset current value according to the model and performance of the switching transistors on the second bridge arm and the third bridge arm, wherein the first preset current value is the second maximum current threshold that the switching transistors on the second bridge arm and the third bridge arm can withstand, and the second preset current value is the maximum current threshold that the switching transistors on the second bridge arm and the third bridge arm can withstand.

[0076] This application also provides a computer program product, which, when executed on a data processing device, is suitable for executing an initialization program having the following method steps: obtaining the current value flowing through the inverter inductor; comparing the current value with a first preset current value; and if the current value is greater than the first preset current value, performing wave blocking processing on the target switch on the third bridge arm.

[0077] When executed on a data processing device, it is also suitable to execute an initialization program with the following steps: after the target switch on the third bridge arm is subjected to wave blocking processing, the method further includes: comparing the current value with a second preset current value, wherein the second preset current value is greater than the first preset current value; if the current value is greater than the second preset current value, then wave blocking processing is performed on the target switch on the second bridge arm.

[0078] When executed on a data processing device, it is also suitable to execute an initialization program with the following steps: after the target switch on the third bridge arm is blocked, the method further includes: if the current value is detected to be no greater than the first preset current value, then the target switch on the third bridge arm is unblocked.

[0079] When executed on a data processing device, it is also suitable to execute an initialization program with the following steps: after the target switch on the second bridge arm is subjected to wave blocking processing, the method further includes: if the current value is detected to be no greater than the second preset current value, then the target switch on the second bridge arm is subjected to deblocking processing.

[0080] When executed on a data processing device, it is also suitable to execute an initialization procedure having the following method steps: before comparing the current value with a first preset current value, the method further includes: determining the model and performance of the switching transistors on the second bridge arm and the third bridge arm; configuring the first preset current value and the second preset current value according to the model and performance of the switching transistors on the second bridge arm and the third bridge arm, wherein the first preset current value is the second maximum current threshold that the switching transistors on the second bridge arm and the third bridge arm can withstand, and the second preset current value is the maximum current threshold that the switching transistors on the second bridge arm and the third bridge arm can withstand.

[0081] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0082] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0083] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0084] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0085] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0086] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0087] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0088] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0089] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0090] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A current limiting method for a three-arm bridge topology circuit, applied to a three-arm bridge topology circuit, wherein the three-arm bridge topology circuit includes a first arm, a second arm, and a third arm, the first arm, the second arm, and the third arm are connected in parallel, and the third arm is connected to an inverter inductor, characterized in that, The method includes: Obtain the current value flowing through the inverter inductor; The current value is compared with a first preset current value; If the current value is greater than the first preset current value, then the target switch on the third bridge arm is subjected to wave blocking processing. After the target switch on the third bridge arm is subjected to wave blocking processing, the method further includes: The current value is compared with a second preset current value, wherein the second preset current value is greater than the first preset current value; If the current value is greater than the second preset current value, then the target switch on the second bridge arm is subjected to wave blocking processing. Before comparing the current value with a first preset current value, the method further includes: Determine the type and performance of the switching transistors on the second and third bridge arms; Based on the model and performance of the switching transistors on the second and third bridge arms, the first preset current value and the second preset current value are configured, wherein the first preset current value is the second maximum current threshold that the switching transistors on the second and third bridge arms can withstand, and the second preset current value is the maximum current threshold that the switching transistors on the second and third bridge arms can withstand.

2. The method of claim 1, wherein, After the target switch on the third bridge arm is subjected to wave blocking processing, the method further includes: If the current value is detected to be no greater than the first preset current value, the target switch on the third bridge arm is unsealed.

3. The method of claim 1, wherein, After the target switch on the second bridge arm is subjected to wave blocking processing, the method further includes: If the current value is detected to be no greater than the second preset current value, the target switch on the second bridge arm is unsealed.

4. A current limiting device of a three-leg topology circuit, applied to a three-leg topology circuit, the three-leg topology circuit comprising a first leg, a second leg and a third leg, the first leg, the second leg and the third leg being connected in parallel, the third leg being connected with an inverter inductance, characterized in that, The device includes: The first acquisition unit is used to acquire the current value flowing through the inverter inductor; The first comparison unit is used to compare the current value with a first preset current value; The first processing unit is used to perform wave blocking processing on the target switch on the third bridge arm if the current value is greater than the first preset current value. The device further includes: a second comparison unit, configured to compare the current value with a second preset current value after the target switch on the third bridge arm has been subjected to wave blocking processing, wherein the second preset current value is greater than the first preset current value; and a second processing unit, configured to perform wave blocking processing on the target switch on the second bridge arm if the current value is greater than the second preset current value. The device further includes: a first determining unit, configured to determine the model and performance of the switching transistors on the second and third bridge arms before comparing the current value with a first preset current value; and a first configuring unit, configured to configure a first preset current value and a second preset current value according to the model and performance of the switching transistors on the second and third bridge arms, wherein the first preset current value is the second maximum current threshold that the switching transistors on the second and third bridge arms can withstand, and the second preset current value is the maximum current threshold that the switching transistors on the second and third bridge arms can withstand.

5. The apparatus of claim 4, wherein, The device further includes: The third processing unit is used to unblock the target switch on the third bridge arm if the current value is detected to be no greater than the first preset current value after the target switch on the third bridge arm has been blocked.

6. A computer-readable storage medium, characterized in that, The storage medium includes a stored program, wherein the program executes the current limiting method for the three-arm topology circuit according to any one of claims 1 to 3.

7. A processor, comprising: The processor is used to run a program, wherein the program executes the current limiting method for the three-arm topology circuit according to any one of claims 1 to 3.

Images