Stacked electronic components

Abstract

This invention provides a multilayer electronic component. The electronic component includes a multilayer, a first inductor, and a second inductor. The first inductor includes a first via array, a second via array, a first conductor layer, a second conductor layer, and a third conductor layer. The second conductor layer is connected to one end of the first via array and extends close to the second via array. The third conductor layer is connected to the second via array and extends close to the first via array.

Description

Technical Field

[0001] This invention relates to a stacked electronic component comprising two inductors. Background Technology

[0002] The following structure is widely used in small mobile communication devices: a common antenna is set up in the system and multiple applications using different frequency bands, and a frequency divider is used to separate the multiple signals transmitted and received by the antenna.

[0003] Generally, a frequency divider that separates a first signal at a frequency within a first frequency band and a second signal at a frequency within a second frequency band higher than the first frequency band includes: a common port; a first signal port; a second signal port; a first filter disposed on a first signal path from the common port to the first signal port; and a second filter disposed on a second signal path from the common port to the second signal port. For example, an LC resonator composed of an inductor and a capacitor can be used as the first and second filters.

[0004] As a frequency divider, frequency dividers using a stack of multiple dielectric layers, as disclosed in Chinese Patent Application Publication No. 107408932A, are known. Additionally, as an inductor for an LC resonator, a U-shaped inductor with via conductors connected to both ends of a conductor layer, as disclosed in Chinese Patent Application Publication No. 107408932A, is known.

[0005] In recent years, the market has demanded miniaturization and space-saving design for small mobile communication devices, as well as miniaturization of the frequency dividers used in these devices. When the LC resonator constituting the filter contains two mutually coupled inductors, miniaturization of the frequency divider can lead to excessive electromagnetic field coupling between the two inductors. Consequently, the desired characteristics sometimes cannot be achieved.

[0006] As described in Chinese Patent Application Publication No. 107408932A, when a frequency divider includes two mutually coupled U-shaped inductors, the magnetic coupling between the two inductors can be adjusted by offsetting the two inductors along the long side of the conductor layer constituting the inductors. However, when the two inductors are arranged in this way, useless space is created in the stack-up, resulting in a larger planar shape of the frequency divider.

[0007] The aforementioned problems are not limited to two mutually coupled U-shaped inductors, but also apply to the case of two mutually coupled inductors, each wound around an axis orthogonal to the stacking direction of the laminate. Furthermore, the aforementioned problems are not limited to frequency dividers, but apply to all laminated electronic components containing two mutually coupled inductors. Summary of the Invention

[0008] The purpose of this invention is to provide a stacked electronic component that can adjust the electromagnetic field coupling between two inductors and achieve miniaturization.

[0009] This invention provides a stacked electronic component comprising: a stack including a plurality of stacked dielectric layers; a first inductor integrated with the stack and wound about a first axis orthogonal to the stacking direction of the plurality of dielectric layers; and a second inductor integrated with the stack and wound about a second axis orthogonal to the stacking direction. The area of ​​a first region obtained by vertically projecting a first space encompassing the first axis and enclosed by the first inductor onto a virtual plane perpendicular to the first axis is different from the area of ​​a second region obtained by vertically projecting a second space encompassing the second axis and enclosed by the second inductor onto a virtual plane perpendicular to the second axis. The second inductor is configured such that, when viewed from a direction parallel to the second axis, at least a portion of the second space overlaps with a portion of the first space.

[0010] The first inductor includes a first via array, a second via array, a first conductor layer, a second conductor layer, and a third conductor layer. The first and second via arrays are each constructed by connecting two or more vias in series. Each of the first, second, and third conductor layers includes at least one conductor layer. The first conductor layer connects one end of the first via array to one end of the second via array. The second conductor layer is connected to the other end of the first via array and extends close to the other end of the second via array. The third conductor layer is connected to the other end of the second via array and extends close to the other end of the first via array.

[0011] In the stacked electronic component of the present invention, the first axis and the second axis may also be parallel to each other.

[0012] Alternatively, in the stacked electronic component of the present invention, the area of ​​the first region may be larger than the area of ​​the second region.

[0013] Alternatively, in the stacked electronic component of the present invention, the dimension of the first space in the stacking direction may be larger than the dimension of the second space in the stacking direction.

[0014] Alternatively, in the stacked electronic component of the present invention, the second inductor may include: a plurality of conductor portions, each wound less than one turn around a second axis; and at least one connecting portion connecting the plurality of conductor portions in series.

[0015] Additionally, the stacked electronic component of the present invention may further include a first port, a second port, and a signal path connecting the first port and the second port. Alternatively, in this case, the first inductor and the second inductor may each be disposed between the signal path and ground from a circuit structure perspective. Alternatively, in this case, the second inductor may include: a first conductor portion and a second conductor portion each wound around a second axis less than one turn; and a connection portion connecting the first conductor portion and the second conductor portion. Alternatively, the second conductor portion may be disposed between the first conductor portion and ground from a circuit structure perspective. Alternatively, the first conductor portion may be magnetically coupled to the first inductor.

[0016] Additionally, the stacked electronic component of the present invention may further include a plurality of signal terminals and at least one ground terminal. Alternatively, the stack may have a bottom surface and a top surface located at both ends in the stacking direction, and four side surfaces connecting the bottom surface and the top surface. Alternatively, the plurality of signal terminals and at least one ground terminal may be disposed on the bottom surface. Alternatively, in this case, a third conductor layer may be disposed between the first conductor layer and the bottom surface. Alternatively, when viewed from a direction parallel to the stacking direction, the third conductor layer may extend across one of the plurality of signal terminals. Alternatively, at least one ground terminal may include a first ground terminal and a second ground terminal. Alternatively, a first inductor may be electrically connected to the first ground terminal. Alternatively, a second inductor may be electrically connected to the second ground terminal.

[0017] In addition, the stacked electronic component of the present invention may also include a circuit integrated with the stack, which does not include a first inductor and a second inductor.

[0018] In the stacked electronic component of the present invention, the first inductor includes a first via array, a second via array, a first conductor layer, a second conductor layer, and a third conductor layer. The second conductor layer is connected to the first via array and extends close to the second via array. The third conductor layer is connected to the second via array and extends close to the first via array. Therefore, according to the present invention, the electromagnetic field coupling between the two inductors can be adjusted, and the stacked electronic component can be miniaturized.

[0019] Other objects, features and advantages of the present invention will become fully apparent from the following description. Attached Figure Description

[0020] Figure 1 This is a circuit diagram illustrating the circuit structure of a stacked electronic component according to one embodiment of the present invention.

[0021] Figure 2 This is a circuit diagram illustrating the circuit structure of a stacked electronic component according to one embodiment of the present invention.

[0022] Figure 3 This is a perspective view showing the appearance of a stacked electronic component according to one embodiment of the present invention.

[0023] Figures 4A to 4C This is an explanatory diagram showing the pattern formation surface of the dielectric layers of the first to third layers in a laminated electronic component according to one embodiment of the present invention.

[0024] Figures 5A-5C This is an explanatory diagram showing the pattern formation surface of the dielectric layers of layers 4 to 6 in a laminated electronic component according to one embodiment of the present invention.

[0025] Figures 6A to 6C This is an explanatory diagram showing the pattern formation surface of the dielectric layers of layers 7 to 9 in a laminated electronic component according to one embodiment of the present invention.

[0026] Figures 7A to 7C This is an explanatory diagram showing the pattern formation surface of the dielectric layers of layers 10 to 12 in a laminated electronic component according to one embodiment of the present invention.

[0027] Figure 8A This is an explanatory diagram showing the pattern formation surface of the dielectric layer of the 13th layer in a stacked electronic component according to one embodiment of the present invention.

[0028] Figure 8B This is an explanatory diagram showing the pattern formation surface of the dielectric layers of layers 14 to 21 in a laminated electronic component according to one embodiment of the present invention.

[0029] Figure 8C This is an explanatory diagram showing the pattern formation surface of the dielectric layer of the 22nd layer in a laminated electronic component according to one embodiment of the present invention.

[0030] Figure 9A and Figure 9B This is an explanatory diagram showing the pattern formation surfaces of the dielectric layers of the 23rd and 24th layers in a laminated electronic component according to one embodiment of the present invention.

[0031] Figure 10 This is a perspective view showing the interior of a stack of laminated electronic components according to one embodiment of the present invention.

[0032] Figure 11 This is a perspective view showing the interior of a stack of laminated electronic components according to one embodiment of the present invention.

[0033] Figure 12 It means Figure 10 and Figure 11 A side view of a portion of the interior of the stacked body shown.

[0034] Figure 13 It means Figure 10 and Figure 11 A side view of a portion of the interior of the stacked body shown.

[0035] Figure 14 It means Figure 10 and Figure 11 A side view of a portion of the interior of the stacked body shown.

[0036] Figure 15 It means Figure 10 and Figure 11 A side view of a portion of the interior of the stacked body shown.

[0037] Figure 16 It means Figure 10 and Figure 11 A top view of a portion of the interior of the stacked structure shown.

[0038] Figure 17 It means Figure 10 and Figure 11 A top view of a portion of the interior of the stacked structure shown.

[0039] Figure 18 This is a characteristic diagram illustrating the attenuation characteristics between a common port and a first signal port in a stacked electronic component according to one embodiment of the present invention.

[0040] Figure 19 This is a characteristic diagram illustrating the attenuation characteristics between a common port and a second signal port in a stacked electronic component according to one embodiment of the present invention. Detailed Implementation

[0041] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, referring to... Figure 1 The general structure of a stacked electronic component (hereinafter referred to as electronic component) 1 according to one embodiment of the present invention will be described. Figure 1 In the example of electronic component 1, a frequency divider (duplexer) is shown. The frequency divider includes a first filter 10 that selectively allows a first signal with a frequency within a first passband to pass through, and a second filter 20 that selectively allows a second signal with a frequency within a second passband higher than the first passband to pass through.

[0042] Electronic component 1 further includes: a common port 2; a first signal port 3; a second signal port 4; a first signal path 5 connecting the common port 2 and the first signal port 3; and a second signal path 6 connecting the common port 2 and the second signal port 4. The first filter 10 is disposed between the common port 2 and the first signal port 3 from a circuit structure perspective. The second filter 20 is disposed between the common port 2 and the second signal port 4 from a circuit structure perspective. The first signal path 5 is the path from the common port 2 through the first filter 10 to the first signal port 3. The second signal path 6 is the path from the common port 2 through the second filter 20 to the second signal port 4.

[0043] A first signal with a frequency within the first passband is selectively passed through a first signal path 5 equipped with a first filter 10. A second signal with a frequency within the second passband is selectively passed through a second signal path 6 equipped with a second filter 20. In this way, the electronic component 1 separates the first signal and the second signal.

[0044] Next, refer to Figure 1 An example of the structure of the first filter 10 will be described below. The first filter 10 includes inductors L11, L12, and L13 and capacitors C11, C12, C13, C14, C15, and C16. Inductors L11 and L12 are located in the first signal path 5 from a circuit structure perspective. Furthermore, inductor L11 is located closer to the first signal port 3 than inductor L12 from a circuit structure perspective. One end of inductor L11 is connected to the first signal port 3. The other end of inductor L11 is connected to one end of inductor L12. The other end of inductor L12 is connected to the common port 2.

[0045] Capacitor C11 is connected in parallel with inductor L11. Capacitor C12 is connected in parallel with inductor L12. One end of capacitor C13 is connected to one end of inductor L11. The other end of capacitor C13 is connected to the other end of inductor L12.

[0046] One end of capacitor C14 is connected to one end of inductor L11. One end of capacitor C15 is connected to the junction of inductors L11 and L12. The other ends of capacitors C14 and C15 are each connected to one end of inductor L13. The other end of inductor L13 is connected to ground. Capacitor C16 is connected in parallel with inductor L13. From a circuit structure perspective, inductor L13 is positioned between the first signal path 5 and ground.

[0047] Next, refer to Figure 2An example of the structure of the second filter 20 will be described below. The second filter 20 includes inductors L21 and L22 and capacitors C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, and C31. One end of capacitor C21 is connected to the second signal port 4. The other end of capacitor C21 is connected to one end of capacitor C22. The other end of capacitor C22 is connected to one end of capacitor C23. The other end of capacitor C23 is connected to the common port 2.

[0048] One end of capacitor C24 is connected to one end of capacitor C21. The other end of capacitor C24 is connected to the other end of capacitor C22. One end of capacitor C25 is connected to the junction of capacitors C22 and C23.

[0049] From a circuit structure perspective, inductor L21 is positioned between the second signal path 6 and ground. Inductor L21 includes inductor portions 211 and 212. One end of inductor portion 211 is connected to the connection point of capacitors C21 and C22. The other end of inductor portion 211 is connected to one end of inductor portion 212. The other end of inductor portion 212 is connected to ground.

[0050] From a circuit structure perspective, inductor L22 is positioned between the second signal path 6 and ground. Furthermore, from a circuit structure perspective, inductor L22 is positioned closer to the common port 2 than inductor L21. Inductor L22 includes inductor portions 221 and 222. One end of inductor portion 221 is connected to the other end of capacitor C25. The other end of inductor portion 221 is connected to one end of inductor portion 222. The other end of inductor portion 222 is connected to ground.

[0051] The inductor portion 211 of inductor L21 and the inductor portion 221 of inductor L22 are magnetically coupled to each other. The inductor portion 212 of inductor L21 and the inductor portion 222 of inductor L22 are not magnetically coupled to each other.

[0052] Capacitor C26 is connected in parallel with the inductor portion 211 of inductor L21. Capacitor C27 is connected in parallel with the inductor portion 212 of inductor L21. One end of capacitor C28 is connected to one end of inductor portion 211. The other end of capacitor C28 is connected to the other end of inductor portion 212.

[0053] Capacitor C29 is connected in parallel with the inductor portion 221 of inductor L22. Capacitor C30 is connected in parallel with the inductor portion 222 of inductor L22. One end of capacitor C31 is connected to one end of inductor portion 221. The other end of capacitor C31 is connected to the other end of inductor portion 222.

[0054] Next, refer to Figure 3 The other structures of electronic component 1 will be described. Figure 3 This is a perspective view showing the appearance of electronic component 1.

[0055] Electronic component 1 also includes a laminate 50 comprising multiple dielectric layers and multiple conductors. The laminate 50 is used to integrate the common port 2, the first signal port 3, the second signal port 4, inductors L11, L12, L13, L21, L22, and capacitors C11-C16, C21-C31. The first filter 10 and the second filter 20 are each constructed using multiple conductors.

[0056] The laminate 50 has a bottom surface 50A and a top surface 50B located at both ends of the lamination direction T of the plurality of dielectric layers, and four side surfaces 50C to 50F connecting the bottom surface 50A and the top surface 50B. Side surfaces 50C and 50D face opposite sides to each other, and side surfaces 50E and 50F also face opposite sides to each other. Side surfaces 50C to 50F are perpendicular to the top surface 50B and the bottom surface 50A.

[0057] Here, as Figure 3 As shown, the X, Y, and Z directions are defined. The X, Y, and Z directions are orthogonal to each other. In this embodiment, the direction parallel to the stacking direction T is designated as the Z direction. Furthermore, the direction opposite to the X direction is designated as the -X direction, the direction opposite to the Y direction as the -Y direction, and the direction opposite to the Z direction as the -Z direction.

[0058] like Figure 3 As shown, bottom surface 50A is located at one end of the laminate 50 in the -Z direction. Top surface 50B is located at one end of the laminate 50 in the Z direction. Both bottom surface 50A and top surface 50B are rectangular shapes, with the longer side surface in the X direction. Side surface 50C is located at one end of the laminate 50 in the -X direction. Side surface 50D is located at one end of the laminate 50 in the X direction. Side surface 50E is located at one end of the laminate 50 in the -Y direction. Side surface 50F is located at one end of the laminate 50 in the Y direction.

[0059] When viewed from the Z direction, the planar shape of the laminate 50, i.e., the shape of the bottom surface 50A (the shape of the top surface 50B), is rectangular. The long side of this rectangle is parallel to the X direction, and the short side of this rectangle is parallel to the Y direction.

[0060] Electronic component 1 also includes signal terminals 112, 113, and 114 disposed on the bottom surface 50A of the laminate 50, and grounding terminals 111, 115, 116, 117, 118, and 119 connected to ground. Grounding terminal 111 is disposed near a corner where the bottom surface 50A, side surface 50D, and side surface 50E intersect. Signal terminal 113 is disposed near a corner where the bottom surface 50A, side surface 50D, and side surface 50F intersect. Signal terminal 114 is disposed near a corner where the bottom surface 50A, side surface 50C, and side surface 50F intersect. Grounding terminal 115 is disposed near a corner where the bottom surface 50A, side surface 50C, and side surface 50E intersect.

[0061] Signal terminal 112 is disposed between ground terminal 111 and ground terminal 115. Ground terminal 116 is disposed between ground terminal 111 and signal terminal 113. Ground terminal 117 is disposed between signal terminal 113 and signal terminal 114. Ground terminal 118 is disposed between signal terminal 114 and ground terminal 115. Ground terminal 119 is disposed at the center of the bottom surface 50A.

[0062] Signal terminal 112 corresponds to common port 2, signal terminal 113 corresponds to first signal port 3, and signal terminal 114 corresponds to second signal port 4. Therefore, common port 2, first signal port 3, and second signal port 4 are disposed on the bottom surface 50A of the laminate 50.

[0063] Next, refer to Figures 4A to 9B An example of the plurality of dielectric layers and plurality of conductors constituting the laminate 50 will be described. In this example, the laminate 50 has 24 dielectric layers stacked together. Hereinafter, these 24 dielectric layers will be referred to as dielectric layers 1 to 24 from bottom to top. In addition, the dielectric layers 1 to 24 will be represented by symbols 51 to 74.

[0064] exist Figures 4A to 8C In the diagram, multiple circles represent multiple through holes. Multiple through holes are formed in each dielectric layer 51-72. Each through hole is formed by filling the holes with conductive paste. Each through hole is connected to a conductor layer or other through-holes.

[0065] Figure 4A This indicates the patterned surface of the first dielectric layer 51. Terminals 111 to 119 are formed on the patterned surface of the dielectric layer 51. Figure 4B This indicates the patterning surface of the second dielectric layer 52. Conductor layers 521, 522, 523, 524, and 525 are formed on the patterning surface of the dielectric layer 52.

[0066] Figure 4CThis indicates the patterned surface of the third dielectric layer 53. Conductor layers 531, 532, 533, 534, 535, 536, 537, 538, 539, 5310, 5311, and 5312 are formed on the patterned surface of the dielectric layer 53. One end of conductor layer 531 is connected to conductor layer 5311. The other end of conductor layer 531 is connected to conductor layer 5312. Figure 4C In the diagram, dashed lines represent the boundaries between conductor layer 531 and conductor layer 5311, as well as the boundaries between conductor layer 531 and conductor layer 5312.

[0067] Figure 5A This indicates the patterned surface of the fourth dielectric layer 54. Conductor layers 541, 542, 543, 544, 545, 546, 547, and 548 are formed on the patterned surface of the dielectric layer 54. Conductor layers 541 and 543 are connected to conductor layer 542. Figure 5B This indicates the patterned surface of the fifth dielectric layer 55. Conductor layers 551, 552, 553, and 554 are formed on the patterned surface of the dielectric layer 55. Conductor layer 554 is connected to conductor layer 553. Figure 5C This indicates the patterned surface of the sixth dielectric layer 56. Conductor layers 561 and 562 are formed on the patterned surface of the dielectric layer 56.

[0068] Figure 6A This indicates the patterned surface of the 7th dielectric layer 57. Conductor layers 571 and 572 are formed on the patterned surface of the dielectric layer 57. Conductor layer 572 is connected to conductor layer 571. Figure 6B This indicates the patterning surface of the 8th dielectric layer 58. No conductor layer is formed on the patterning surface of the dielectric layer 58. Figure 6C This indicates the patterned surface of the 9th dielectric layer 59. A conductor layer 591 is formed on the patterned surface of the dielectric layer 59.

[0069] Figure 7A This indicates the patterned surface of the 10th dielectric layer 60. A conductor layer 601 is formed on the patterned surface of the dielectric layer 60. Figure 7B This indicates the patterning surface of the 11th dielectric layer 61. No conductor layer is formed on the patterning surface of the dielectric layer 61. Figure 7C This indicates the patterning surface of the 12th dielectric layer 62. Conductor layers 621 and 622 are formed on the patterning surface of the dielectric layer 62. When viewed from a direction parallel to the stacking direction T (Z direction), the conductor layers 621 and 622 can have the same shape.

[0070] Figure 8AThis indicates the patterning surface of the 13th dielectric layer 63. Conductor layers 631 and 632 are formed on the patterning surface of the dielectric layer 63. When viewed from a direction parallel to the stacking direction T (Z direction), the conductor layers 631 and 632 can have the same shape. Figure 8B This indicates the pattern formation surfaces of dielectric layers 64-71, layers 14 to 21. No conductor layers are formed in dielectric layers 64-71. Figure 8C This indicates the patterning surface of the 22nd dielectric layer 72. Conductor layers 721, 722, 723, 724, 725, 726, and 727 are formed on the patterning surface of the dielectric layer 72. When viewed from a direction parallel to the stacking direction T (Z direction), conductor layers 722, 723, and 724 can have the same shape. When viewed from a direction parallel to the stacking direction T (Z direction), conductor layers 726 and 727 can also have the same shape.

[0071] Figure 9A This indicates the patterning surface of the 23rd dielectric layer 73. Conductor layers 731, 732, 733, 734, 735, 736, and 737 are formed on the patterning surface of the dielectric layer 73. When viewed from a direction parallel to the stacking direction T (Z direction), conductor layers 732, 733, and 734 can have the same shape. When viewed from a direction parallel to the stacking direction T (Z direction), conductor layers 736 and 737 can have the same shape. Figure 9B This indicates the patterning surface of the 24th dielectric layer 74. A mark 741 composed of a conductor layer is formed on the patterning surface of the dielectric layer 74.

[0072] Figure 2 The stack 50 shown is constructed by stacking dielectric layers 51 to 74 from the first layer to the 24th layer in such a way that the pattern-forming surface of the first dielectric layer 51 becomes the bottom surface 50A of the stack 50, and the opposite side of the pattern-forming surface of the 24th dielectric layer 74 becomes the upper surface 50B of the stack 50.

[0073] When stacking dielectric layers 51 to 72, layers 1 to 22, Figures 4A to 8C The multiple vias shown are each connected to a conductor layer overlapping in the stacking direction T or to other vias overlapping in the stacking direction T. Additionally, Figures 4A to 8C The through-hole shown is located inside the terminal or the conductor layer and is connected to the terminal or the conductor layer.

[0074] Figure 10 and Figure 11 This refers to the interior of the laminate 50, which consists of dielectric layers 51 to 74 stacked from layer 1 to layer 24. For example... Figure 10 and Figure 11 As shown, inside the laminate 50, there are laminated... Figures 4A to 9A Multiple conductor layers and multiple through-holes are shown. Furthermore, in... Figure 10 and Figure 11 The mark 741 has been omitted.

[0075] The laminate 50 is manufactured, for example, using ceramic as the material for dielectric layers 51-74 and employing a low-temperature co-firing method. In this case, firstly, multiple ceramic green sheets that will later become dielectric layers 51-74 are fabricated. Each ceramic green sheet has multiple pre-firing conductor layers that will later become multiple conductor layers and multiple pre-firing through-holes that will later become multiple through-holes. Next, the multiple ceramic green sheets are laminated to form a green sheet laminate. Next, the green sheet laminate is cut to form a pre-firing laminate. Finally, the ceramic and conductors in the pre-firing laminate are fired through a low-temperature co-firing process to complete the laminate 50.

[0076] Next, refer to Figures 4A to 15 The structure of inductors L11, L12, L13, L21, and L22 is explained in detail. Figures 12-15 This is a side view showing a portion of the interior of the stacked body 50. Figure 12 This shows a portion of the interior of the stack 50 as viewed from the side 50D, mainly showing inductors L11, L12, and L13. Figure 13 This shows a portion of the interior of the stack 50 as viewed from the side 50E, mainly showing inductors L12, L13, and L22. Figure 14 This shows a portion of the interior of the laminate 50 as viewed from the side 50C, mainly showing inductors L21 and L22. Figure 15 This shows a portion of the interior of the stack 50 as viewed from the side 50F, mainly showing inductors L11 and L21.

[0077] Inductors L11, L12, L13, L21, and L22 are integrated with the laminate 50. As described later, each of inductors L11, L12, L21, and L22 includes multiple via rows. Each of the multiple via rows is formed by connecting two or more via rows arranged in the lamination direction T in series.

[0078] First, the structure of inductor L11 will be explained. For example... Figure 12 and Figure 15 As shown, the inductor L11 is wound around an axis A11 that is parallel to the direction orthogonal to the stacking direction T. In this embodiment, in particular, the axis A11 extends in a direction parallel to the Y direction.

[0079] Additionally, inductor L11 includes a conductor portion wound less than one turn around axis A11. The conductor portion of inductor L11 includes conductor layer 11C1 (see reference). Figure 10 and Figure 11The conductor layer 11C1 has a shape that is longer in a direction parallel to the X direction. The conductor layer 11C1 includes conductor layers 721 and 731 (see reference) which are disposed at different positions in the stacking direction T and connected in parallel by four through holes. Figure 8C and Figure 9A Conductor layers 721 and 731 each extend in a direction parallel to the X direction.

[0080] The conductor portion of inductor L11 also includes two via rows 11T1 and two via rows 11T2 (see reference). Figure 10 and Figure 11 Two through-hole rows 11T1 are connected in parallel near one end of the conductor layer 11C1 along the long side. Two through-hole rows 11T2 are connected in parallel near the other end of the conductor layer 11C1 along the long side.

[0081] Next, the structure of inductor L12 will be explained. For example... Figure 12 and Figure 13 As shown, the inductor L12 is wound around an axis A12 that is parallel to a direction orthogonal to the stacking direction T. In this embodiment, in particular, the axis A12 extends in a direction parallel to the X direction. Furthermore, the inductor L12 includes: conductor portions L12A, L12B, and L12C, each wound less than one turn around the axis A12; a connecting portion L12D that connects conductor portions L12A and L12B in series; and a connecting portion L12E that connects conductor portions L12B and L12C in series.

[0082] Conductor portions L12A, L12B, and L12C respectively include conductor layers 12C1, 12C2, and 12C3 (see reference). Figure 10 and Figure 11 The conductor layers 12C1, 12C2, and 12C3 each have a longer shape in a direction parallel to the Y direction.

[0083] Conductor layer 12C1 includes conductor layers 722 and 732 (see reference) disposed at different positions in the stacking direction T and connected in parallel by two through holes. Figure 8C and Figure 9A The conductor layer 12C2 includes conductor layers 723 and 733 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by two through holes. Figure 8C and Figure 9A The conductor layer portion 12C3 includes conductor layers 724 and 734 (see reference) which are disposed at different positions in the stacking direction T and connected in parallel by two through holes. Figure 8C and Figure 9A Conductor layers 722-724 and 732-734 each extend in a direction parallel to the Y direction.

[0084] The conductor portion L12A also includes via arrays 12T1 and 12T2 (see reference). Figure 10 and Figure 11 Through-hole row 12T1 is connected to the portion near one end of the conductor layer 12C1 in the long side direction. Through-hole row 12T2 is connected to the portion near the other end of the conductor layer 12C1 in the long side direction.

[0085] The conductor portion L12B also includes through-hole arrays 12T3 and 12T4 (see reference). Figure 10 and Figure 11 Through-hole row 12T3 is connected to the portion near one end of the conductor layer 12C2 in the long side direction. Through-hole row 12T4 is connected to the portion near the other end of the conductor layer 12C2 in the long side direction.

[0086] The conductor portion L12C also includes via arrays 12T5 and 12T6 (see reference). Figure 10 and Figure 11 Through-hole row 12T5 is connected to the portion near one end of the conductor layer 12C3 in the long side direction. Through-hole row 12T6 is connected to the portion near the other end of the conductor layer 12C3 in the long side direction.

[0087] The connecting portion L12D connects the through-hole row 12T2 of the conductor portion L12A to the through-hole row 12T3 of the conductor portion L12B. Additionally, the connecting portion L12D includes a conductor layer portion 12C4 (see reference). Figure 10 The conductor layer 12C4 includes conductor layers 621 and 631 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by two through holes. Figure 7C and Figure 8A ).

[0088] The connecting portion L12E connects the through-hole row 12T4 of the conductor portion L12B to the through-hole row 12T5 of the conductor portion L12C. Additionally, the connecting portion L12E includes a conductor layer portion 12C5 (see reference). Figure 10 The conductor layer portion 12C5 includes conductor layers 622 and 632 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by two through holes. Figure 7C and Figure 8A ).

[0089] Figure 5A and Figure 5B The conductor layers 542 and 552 shown are positioned at different locations in the stacking direction T and are connected in parallel using three vias. The conductor layers 542 and 552 connect the via arrays 11T3 and 11T4 of the conductor portion of inductor L11 to the via array 12T1 of the conductor portion L12A of inductor L12.

[0090] Next, the structure of inductor L13 will be described. Inductor L13 is wound around an axis A13 parallel to the stacking direction T. Inductor L13 consists of conductor layer 531 (see reference). Figure 4C )constitute.

[0091] Next, the structure of inductor L21 will be explained. For example... Figure 14 and Figure 15 As shown, inductor L21 is wound around an axis A21 that is parallel to the direction orthogonal to the stacking direction T. In this embodiment, in particular, axis A21 extends in a direction parallel to the Y direction.

[0092] Additionally, inductor L21 includes a conductor portion wound less than one turn around axis A21. The conductor portion of inductor L21 includes conductor layer 21C1 (see reference). Figure 10 and Figure 11 The conductor layer portion 21C1 includes conductor layers 725 and 735 (see reference) which are disposed at different positions in the stacking direction T and connected in parallel by two through holes. Figure 8C and Figure 9A Conductor layers 725 and 735 each include a first portion extending in the X direction and a second portion extending in the Y direction.

[0093] The conductor portion of inductor L21 also includes via arrays 21T1 and 21T2 (see reference). Figure 10 and Figure 11 Through-hole row 21T1 is connected to the portion near one end of the conductor layer 21C1 in the long side direction. Through-hole row 21T2 is connected to the portion near the other end of the conductor layer 21C1 in the long side direction.

[0094] Inductor L21 also includes conductor layers 21C2 and 21C3 (see reference) Figure 11 Conductor layer 21C1 connects one end of via array 21T1 to one end of via array 21T2. Conductor layer 21C2 is connected to the other end of via array 21T1 and extends close to the other end of via array 21T2. Conductor layer 21C3 is connected to the other end of via array 21T2 and extends close to the other end of via array 21T1.

[0095] Conductor layer 21C2 includes conductor layers 561 and 571 (see reference) which are disposed at different positions in the stacking direction T and connected in parallel by two through holes. Figure 5C and Figure 6A The conductor layer portion 21C3 includes conductor layers 544 and 553 (see reference) which are disposed at different positions in the stacking direction T and connected in parallel by two through holes. Figure 5A and Figure 5B ).

[0096] Conductor layers 21C1 and 21C2 and vias 21T1 and 21T2 constitute the inductor portion 211 of inductor L21. Conductor layer 21C3 constitutes the inductor portion 212 of inductor L21. Conductor layer 21C3 (conductor layers 544 and 553) passes through conductor layers 526 and 5310 (see reference). Figure 4B and Figure 4C ) and multiple through holes are connected to grounding terminal 117.

[0097] Next, the structure of inductor L22 will be explained. For example... Figure 13 and Figure 14 As shown, inductor L22 is wound around an axis A22 that is parallel to the direction orthogonal to the stacking direction T. In this embodiment, in particular, axis A22 extends in a direction parallel to the Y direction. Furthermore, inductor L22 includes conductor portions L22A and L22B, each wound less than one turn around axis A22, and a connecting portion L22C that connects conductor portions L22A and L22B in series.

[0098] Conductor portions L22A and L22B respectively include conductor layers 22C1 and 22C2 (refer to...) Figure 10 and Figure 11 The conductor layers 22C1 and 22C2 each have a shape that is longer in a direction parallel to the X direction.

[0099] Conductor layer 22C1 includes conductor layers 726 and 736 (see reference) which are disposed at different positions in the stacking direction T and connected in parallel by four through holes. Figure 8C and Figure 9A The conductor layer portion 22C2 includes conductor layers 727 and 737 (see reference) which are disposed at different positions in the stacking direction T and connected in parallel by four through holes. Figure 8C and Figure 9A Conductor layers 726, 727, 736, and 737 each extend in a direction parallel to the X direction.

[0100] The conductor portion L22A also includes two via rows 22T1 and two via rows 22T2 (see reference). Figure 10 and Figure 11 Near one end of the conductor layer 22C1 along its long side, two through-hole rows 22T1 are connected in parallel. Near the other end of the conductor layer 22C1 along its long side, two through-hole rows 22T2 are connected in parallel.

[0101] The conductor section L22B also includes two via rows 22T3 and two via rows 22T4 (see reference). Figure 10 and Figure 11Two through-hole rows 22T3 are connected in parallel near one end of the conductor layer 22C2 along the long side. Two through-hole rows 22T4 are connected in parallel near the other end of the conductor layer 22C2 along the long side.

[0102] The connecting portion L22C connects the two through-hole rows 22T2 of the conductor portion L22A to the two through-hole rows 22T3 of the conductor portion L22B. Additionally, the connecting portion L22C includes a conductor layer portion 22C3 (see reference). Figure 10 and Figure 11 The conductor layer portion 22C3 includes conductor layers 591 and 601 (see reference) which are disposed at different positions in the stacking direction T and connected in parallel by four through holes. Figure 6C and Figure 7A ).

[0103] Conductor portion L22A constitutes inductor portion 221 of inductor L22. Conductor portion L22B constitutes inductor portion 222 of inductor L22. From a circuit structure perspective, conductor portion L22B is positioned between conductor portion L22A and ground. The two vias 22T4 of conductor portion L22B pass through conductor layers 525 and 539 (see reference). Figure 4B and Figure 4C It and multiple through holes are connected to grounding terminals 115 and 118.

[0104] Next, capacitors C11-C16, C21-C31 and... Figures 4A to 9B The correspondence of the internal components of the stacked body 50 shown is explained. The capacitor C11 is composed of... Figures 4B to 5A , Figure 8C and Figure 9A The capacitor C12 is composed of conductor layers 521, 532, 541, 551 and dielectric layers 52, 53, 54 between these conductor layers. Figure 7C , Figure 8A , Figure 8C and Figure 9A The capacitor C13 is composed of conductor layers 621, 622, 631, 632, 722-724, 732-734, and dielectric layers 62 and 72 between these conductor layers.

[0105] Capacitor C14 is made of Figure 4C The capacitor C15 is composed of conductor layers 5311 and 532. Figure 5A The capacitor C16 is composed of conductor layer 542 and dielectric layer 53 between these conductor layers. Figure 4C and Figure 5A The conductor layers 5312 and 543 shown are formed by the dielectric layer 53 between these conductor layers.

[0106] Capacitor C21 is made of Figure 4C and Figure 5A The capacitor C22 is composed of conductor layers 533 and 545 and the dielectric layer 53 between these conductor layers. Figure 4C , Figure 5A and Figure 5C The capacitor C23 is composed of conductor layers 534 and 545 and the dielectric layer 53 between these conductor layers. Figure 4C and Figure 5A The capacitor C24 is composed of conductor layers 533 and 534, and the dielectric layer 53 between these conductor layers. The capacitor C25 is composed of conductor layers 533 and 534. Figure 4C , Figure 5A and Figure 5C The conductor layers 536, 546, and 547 shown, and the dielectric layer 53 between these conductor layers, constitute the structure.

[0107] Capacitor C26 is made of Figure 5C , Figure 6A , Figure 8C and Figure 9A The capacitor C27 is composed of conductor layers 561, 571, 725, and 735, and dielectric layers 56 and 72 between these conductor layers. Figure 5A and Figure 5B The capacitor C28 is composed of conductor layers 544 and 553 and the dielectric layer 54 between these conductor layers. Figure 5B and Figure 6A The conductor layers 554 and 572 shown and the dielectric layers 55 and 56 between these conductor layers constitute the structure.

[0108] Capacitor C29 is made of Figure 6C , Figure 7A , Figure 8C and Figure 9A The capacitor C30 is composed of conductor layers 591, 601, 726, and 736, and dielectric layers 59 and 72 between these conductor layers. Figure 8C and Figure 9A The capacitor C31 is composed of conductor layers 727 and 737 and dielectric layers 59 and 72 between these conductor layers. Figure 4C and Figure 5A The conductor layers 537 and 548 shown are formed by the dielectric layer 53 between these conductor layers.

[0109] Next, refer to Figures 10-17 The structural features of the electronic component 1 in this embodiment will be described. Figure 16 and Figure 17 It means Figure 10 and Figure 11A top view of a portion of the interior of the stacked body 50 shown.

[0110] like Figures 10-15 As shown, inductor L12 is positioned in front of inductor L11 in a direction orthogonal to the stacking direction T, namely the -Y direction. Inductors L21 and L22 are positioned in front of inductors L11 and L12, respectively, in a direction orthogonal to the stacking direction T, namely the -X direction.

[0111] exist Figure 12 and Figure 15 In the diagram, the area enclosed by the dashed line marked S11 represents the space containing axis A11 and bounded by inductor L11. Additionally, in... Figure 12 and Figure 13 In the diagram, the area enclosed by the dashed line marked S12 represents the space containing axis A12 and bounded by inductor L12. Additionally, in... Figure 14 and Figure 15 In the diagram, the area enclosed by the dashed line marked S21 represents the space containing axis A21 and bounded by inductor L21. Additionally, in Figure 13 and Figure 14 In the diagram, the area enclosed by the dashed line marked S22 represents the space containing axis A22 and enclosed by inductor L22.

[0112] exist Figure 15 In the diagram, the area enclosed by the dashed line marked S11 is also the area obtained by projecting space S11 perpendicularly onto a virtual plane (XZ plane) perpendicular to axis A11. Hereinafter, this area will be referred to as the projection region of space S11. The area of ​​the projection region of space S11 is equivalent to the opening area of ​​inductor L11.

[0113] In addition, Figure 12 In the diagram, the area enclosed by the dashed line marked S12 is also the area obtained by projecting space S12 perpendicularly onto a virtual plane (YZ plane) perpendicular to axis A12. Hereinafter, this area will be referred to as the projection region of space S12. The area of ​​the projection region of space S12 is equivalent to the opening area of ​​inductor L12.

[0114] In addition, Figure 15 In the diagram, the area enclosed by the dashed line marked S21 is the region obtained by projecting space S21 perpendicularly onto a virtual plane (XZ plane) perpendicular to axis A21. Hereinafter, this region will be referred to as the projection region of space S21. The area of ​​the projection region of space S21 is equivalent to the opening area of ​​inductor L21.

[0115] In addition, Figure 13In the diagram, the area enclosed by the dashed line marked S22 is also the area obtained by projecting space S22 perpendicularly onto a virtual plane (XZ plane) perpendicular to axis A22. Hereinafter, this area will be referred to as the projection region of space S22. The area of ​​the projection region of space S22 is equivalent to the opening area of ​​inductor L22.

[0116] like Figure 12 and Figure 15 As shown, the area of ​​the projected region of space S11 is larger than the area of ​​the projected region of space S12. Additionally, as... Figure 12 and Figure 15 As shown, the area of ​​the projected region of space S21 is larger than the area of ​​the projected region of space S12. Additionally, as... Figure 12 and Figure 13 As shown, the area of ​​the projected region of space S22 is larger than the area of ​​the projected region of space S12.

[0117] In addition, such as Figure 13 and Figure 15 As shown, the areas of the projected regions of space S21 and S22 are different from each other. In this embodiment, in particular, the area of ​​the projected region of space S21 is larger than the area of ​​the projected region of space S22. In addition, the dimension of the projected region of space S21 in the stacking direction T is larger than the dimension of the projected region of space S22 in the stacking direction T.

[0118] When viewed from a direction parallel to axis A11 (Y direction), inductor L11 is configured such that a portion of space S11 overlaps with at least a portion of space S12.

[0119] When viewed from a direction parallel to axis A12 (X direction), inductor L12 is configured such that at least a portion of space S12 overlaps with space S22. Furthermore, inductor L12 is configured such that axis A12 is parallel to the long side of the bottom surface 50A (long side of the upper surface 50B) of the laminate 50.

[0120] Inductor L13 is configured such that its axis A13 does not intersect spaces S11, S21, and S22, but does intersect space S12. In other words, inductor L13 is configured to overlap with inductor L12 when viewed from the Z direction. Between inductors L12 and L13, specifically, in conductor layer 531 (refer to...) Figure 4C ) and conductor layers 621, 622 (refer to Figure 7C There is no capacitor conductor layer between them to form a capacitor.

[0121] When viewed from a direction parallel to axis A21 (Y direction), inductor L21 is configured such that a portion of space S21 overlaps with at least a portion of space S22. In other words, when viewed from a direction parallel to axis A22 (Y direction), inductor L22 is configured such that at least a portion of space S22 overlaps with a portion of space S21.

[0122] The conductor layer 21C3 of inductor L21 is disposed between the conductor layer 21C1 and the bottom surface 50A of inductor L21. When viewed from a direction parallel to the stacking direction T (Z direction), the conductor layer 21C3 extends across the signal terminal 114. In addition, inductor L21 is electrically connected to the ground terminal 117. Inductor L22 is electrically connected to ground terminals 115 and 118.

[0123] The inductor L22 includes: a conductor portion L22A constituting the inductor portion 221 of the inductor L22; a conductor portion L22B constituting the inductor portion 222 of the inductor L22; and a connection portion L22C connecting the conductor portions L22A and L22B in series. The conductor portion L22A (inductor portion 221) is magnetically coupled to the conductor layers 21C1 and 21C2 and the via rows 21T1 and 21T2 constituting the inductor portion 211 of the inductor L21.

[0124] exist Figure 17 The diagram shows two conductor layers 721 and 731 that constitute the conductor layer portion 11C1 of inductor L11. For example... Figure 17 As shown, the area of ​​conductor layer 721 is larger than the area of ​​conductor layer 731. When viewed from a direction parallel to the stacking direction T (Z direction), conductor layer 731 is disposed inside the outer edge of conductor layer 721. The shape of conductor layer 731 when viewed from the Z direction is similar to the shape of conductor layer 721 when viewed from the Z direction. Conductor layer 721 is disposed between conductor layer 731 and axis A11.

[0125] The above description of conductor layers 721 and 731 also applies to the group of conductor layers 72x and 73x (x is an integer between 2 and 7). If conductor layers 721 and 731 in the above description of conductor layers 721 and 731 are replaced with conductor layers 72x and 73x respectively, it becomes a description of conductor layers 72x and 73x. Furthermore, when describing the group of conductor layers 72x and 73x constituting inductor L12, axis A11 in the above description is replaced with axis A12. Additionally, when describing the group of conductor layers 725 and 735 constituting inductor L21, axis A11 in the above description is replaced with axis A21. Furthermore, when describing the group of conductor layers 72x and 73x constituting inductor L22, axis A11 in the above description is replaced with axis A22.

[0126] exist Figure 16 The diagram shows two conductor layers 621 and 631 that constitute the conductor layer portion 12C4 of inductor L12. For example... Figure 16 As shown, the area of ​​conductor layer 631 is larger than the area of ​​conductor layer 621. When viewed from a direction parallel to the stacking direction T (Z direction), conductor layer 621 is positioned inside the outer edge of conductor layer 631. The shape of conductor layer 621 when viewed from the Z direction is similar to the shape of conductor layer 631 when viewed from the Z direction. Conductor layer 631 is positioned between conductor layer 621 and axis A12.

[0127] The above description of conductor layers 621 and 631 also applies to the group of conductor layers 622 and 632, the group of conductor layers 561 and 571, the group of conductor layers 543 and 553, and the group of conductor layers 591 and 601. If conductor layers 621 and 631 in the above description of conductor layers 621 and 631 are replaced with conductor layers 622 and 632 respectively, it becomes a description of conductor layers 622 and 632.

[0128] Furthermore, if the conductor layers 621 and 631 in the above description of conductor layers 621 and 631 are replaced with conductor layers 561 and 571 or conductor layers 543 and 553 respectively, and the axis A12 in the above description of conductor layers 621 and 631 is replaced with axis A21, then it becomes a description of conductor layers 561 and 571 or conductor layers 543 and 553.

[0129] Furthermore, if the conductor layers 621 and 631 in the above description of conductor layers 621 and 631 are replaced with conductor layers 591 and 601 respectively, and the axis A12 in the above description of conductor layers 621 and 631 is replaced with axis A22, then it becomes a description of conductor layers 591 and 601.

[0130] Next, an example of the characteristics of the electronic component 1 in this embodiment will be shown. Figure 18 This is a characteristic diagram representing the pass-through attenuation characteristics between the common port 2 and the first signal port 3, i.e., the pass-through attenuation characteristics of the first filter 10. Figure 19 This is a characteristic diagram representing the attenuation characteristics between common port 2 and second signal port 4, i.e., the attenuation characteristics of the second filter 20. Figure 18 and Figure 19 In the diagram, the horizontal axis represents frequency, and the vertical axis represents attenuation.

[0131] exist Figure 18In the diagram, symbol 91 represents the attenuation pole formed by inductor L11, and symbol 92 represents the attenuation pole formed by inductor L12. Regarding inductor L12, in the pass-through attenuation characteristics of the first filter 10, attenuation pole 92 is formed on a higher domain side than the first passband. Regarding inductor L11, in the pass-through attenuation characteristics of the first filter 10, attenuation pole 91 is formed between the first passband and attenuation pole 92. That is, in the pass-through attenuation characteristics of the first filter 10, attenuation pole 91 formed by inductor L11 is closer to the first passband than attenuation pole 92 formed by inductor L12.

[0132] exist Figure 19 In the diagram, symbol 93 represents the attenuation pole formed by inductor L21, and symbol 94 represents the attenuation pole formed by inductor L22. Regarding inductor L21, in the pass-through attenuation characteristics of the second filter 20, attenuation pole 93 is formed on the lower domain side of the second passband. Regarding inductor L22, in the pass-through attenuation characteristics of the second filter 20, attenuation pole 94 is formed between attenuation pole 93 and the second passband. That is, in the pass-through attenuation characteristics of the second filter 20, attenuation pole 94 formed by inductor L22 is closer to the second passband than attenuation pole 93 formed by inductor L21.

[0133] The following example illustrates the inductance and Q value of inductors L11, L12, L13, L21, and L22. In this example, the inductance of inductor L11 is 0.8 nH, and its Q value is 125. The inductance of inductor L12 is 3.4 nH, and its Q value is 113. The inductance of inductor L13 is 0.81 nH, and its Q value is 53. The inductance of inductor L21 is 1.5 nH, and its Q value is 73. The inductance of inductor L22 is 2.0 nH, and its Q value is 127.

[0134] Next, the function and effects of the electronic component 1 in this embodiment will be explained. In this embodiment, inductor L21 is configured such that, when viewed from a direction parallel to axis A21 (Y direction), a portion of space S21 overlaps with at least a portion of space S22. In other words, inductor L22 is configured such that, when viewed from a direction parallel to axis A22 (Y direction), at least a portion of space S22 overlaps with a portion of space S22. In this embodiment, axis A21 is parallel to axis A22. Therefore, in this embodiment, inductors L21 and L22 are configured such that the openings of inductor L21 and inductor L22 are opposite to each other, and when viewed from the Y direction, inductor L21 and inductor L22 overlap.

[0135] Here, we consider adjusting the magnetic coupling between inductors L21 and L22. For example, the magnetic coupling can be adjusted by shifting one of inductors L21 or L22 in the X or -X direction. However, this will create useless space within the stack 50, and the planar shape (shape viewed from the Z direction) of the electronic component 1 will become larger.

[0136] In this embodiment, the areas of the projection regions of space S21 and S22 are different from each other. Therefore, according to this embodiment, the magnetic coupling can be adjusted without shifting either inductor L21 or L22 in the X or -X direction.

[0137] However, in order to adjust the area of ​​the projected region of space S21, it is considered to increase the dimension of the stacking direction T of inductor L21. In this case, the distance from the bottom surface 50A of the stack 50 to inductor L21 will become smaller. If a grounding terminal is provided near inductor L21, stray capacitance will be generated between inductor L21 and grounding terminal, and the desired characteristics may not be obtained.

[0138] In this embodiment, the inductor L21 includes: a conductor layer 21C2 connected to one end of the via array 21T1 and extending close to the other end of the via array 21T2; and a conductor layer 21C3 connected to one end of the via array 21T2 and extending close to the other end of the via array 21T1. According to this embodiment, when viewed from a direction parallel to the stacking direction T (Z direction) using at least one of the conductor layers 21C2 and 21C3, the inductor L21 can be configured in a manner that does not overlap with the ground terminal. In this embodiment, particularly when viewed from a direction parallel to the stacking direction T (Z direction), the conductor layer 21C3 extends across the signal terminal 114. Therefore, according to this embodiment, the dimension of the stacking direction T of the inductor L21 can be increased, and the area of ​​the projected region of the space S21 can be adjusted.

[0139] As described above, according to this embodiment, the electromagnetic field coupling between inductors L21 and L22 can be adjusted, and the electronic component 1 can be miniaturized.

[0140] In this embodiment, the electronic component 1 includes a second filter 20 including inductors L21 and L22, and a first filter 10 excluding inductors L21 and L22. To increase the insulation between the first filter 10 and the second filter 20, a grounding terminal is provided between them. In this embodiment, the conductor layer 21C3 is connected to the grounding terminal 117 located between the first filter 10 and the second filter 20. That is, according to this embodiment, the insulation between the first filter 10 and the inductor L21 can be increased, and the inductor L21 is connected to the grounding terminal 117 using the conductor layer 21C3.

[0141] Furthermore, in this embodiment, inductor L22 includes conductor portions L22A and L22B. Conductor portion L22A is magnetically coupled to inductor L21. That is, in this embodiment, a portion of inductor L22 is magnetically coupled to inductor L21. According to this embodiment, by configuring the inductor as described above, the magnetic coupling between inductor L21 and inductor L22 can be adjusted.

[0142] Next, other effects of this embodiment will be explained. In this embodiment, the area of ​​the projected region of space S11, which is equivalent to the opening area of ​​inductor L11, is larger than the area of ​​the projected region of space S12, which is equivalent to the opening area of ​​inductor L12. That is, in this embodiment, the area of ​​the projected region of space S12, which is equivalent to the opening area of ​​inductor L12, is smaller than the area of ​​the projected region of space S11, which is equivalent to the opening area of ​​inductor L11. As a result, a space for arranging other inductors can be formed near inductor L12. In this embodiment, inductor L13 is arranged in the aforementioned space. As described above, inductor L13 is arranged such that its axis A13 does not intersect space S11 but intersects space S12. In this embodiment, inductors L11, L12, and L13 are also wound around axes parallel to each other in directions different from each other. In particular, axes A11, A12, and A13 are orthogonal to each other. As described above, according to this embodiment, electromagnetic field coupling between inductors L11, L12, and L13 can be suppressed, and electronic component 1 can be miniaturized.

[0143] Furthermore, in this embodiment, the inductor L11 is configured such that, when viewed from a direction parallel to axis A11, a portion of space S11 overlaps with at least a portion of space S12. Therefore, according to this embodiment, compared to the case where spaces S11 and S12 do not overlap, the electronic component 1 can be miniaturized.

[0144] Furthermore, according to this embodiment, the first filter 10 includes inductors L11, L12, and L13. According to this embodiment, due to the aforementioned characteristics of inductors L11, L12, and L13, the area of ​​the first filter 10 within the laminate 50 can be reduced, resulting in the miniaturization of the electronic component 1.

[0145] Furthermore, in this embodiment, the area of ​​the projected region of space S12, which is equivalent to the opening area of ​​inductor L12, is smaller than the area of ​​the projected region of space S22, which is equivalent to the opening area of ​​inductor L22. In this embodiment, inductors L12, L13, and L22 are also wound around axes parallel to each other in directions different from each other. In particular, axes A12, A13, and A22 are orthogonal to each other. As described above, according to this embodiment, electromagnetic field coupling between inductors L12, L13, and L22 can be suppressed, and the electronic component 1 can be miniaturized.

[0146] Furthermore, in this embodiment, the inductor L12 is configured such that, when viewed from a direction parallel to axis A12, a portion of space S12 overlaps with at least a portion of space S22. Therefore, according to this embodiment, compared to the case where spaces S12 and S22 do not overlap, the electronic component 1 can be miniaturized.

[0147] Furthermore, in this embodiment, there is no capacitor conductor layer between inductors L12 and L13. Therefore, according to this embodiment, compared to the case where there is a capacitor conductor layer between inductors L12 and L13, the electronic component 1 can be miniaturized.

[0148] Furthermore, in this embodiment, the first filter 10 includes inductors L12 and L13, and the second filter 20 includes inductor L22. According to this embodiment, due to the aforementioned characteristics of inductors L12, L13, and L22, the first filter 10 and the second filter 20 can be brought close together, resulting in the miniaturization of the electronic component 1.

[0149] However, the area of ​​the projected region of space S12, which is comparable to the opening area of ​​inductor L12, is small, therefore the inductance of inductor L12 is relatively small. In this embodiment, inductor L12 includes conductor portions L12A, L12B, and L12C, each wound less than one turn around axis A12. That is, in this embodiment, inductor L12 is wound approximately three turns around axis A12. Therefore, according to this embodiment, the inductance of inductor L12 can be increased. Furthermore, according to this embodiment, the dimension in the direction parallel to axis A12 of inductor L12 (the direction parallel to the X direction) can be increased. Therefore, according to this embodiment, the space for arranging inductor L13 can be increased.

[0150] Furthermore, in this embodiment, the inductor L12 is configured such that the axis A12 is parallel to the long side of the bottom surface 50A (the long side of the upper surface 50B) of the laminate 50. Therefore, according to this embodiment, other inductors can be arranged in a direction parallel to the axis A12; specifically, inductor L22 can be arranged, and inductor L12 can be wound multiple times around the axis A12.

[0151] In this embodiment, inductors L11 and L12 are arranged on the first signal path 5 from a circuit structure perspective, and inductor L13 is arranged between the first signal path 5 and ground from a circuit structure perspective. Alternatively, inductor L13 may have a smaller Q value compared to inductors L11 and L12. As described above, in one example, the Q value of inductor L11 is 125, the Q value of inductor L12 is 113, and the Q value of inductor L13 is 53. In this embodiment, inductors L11 and L12, which preferably have larger Q values, are configured as inductors wound around an axis orthogonal to the stacking direction T, while inductor L13, which may also have a smaller Q value, is configured as an inductor wound around an axis parallel to the stacking direction T. Furthermore, inductor L13, which may also have a smaller Q value, is disposed in the space formed near inductor L12.

[0152] Furthermore, in this embodiment, in inductor L11, two via rows are connected in parallel near both ends of the conductor layer 11C1 along its long side. Similarly, in inductor L22, two via rows are connected in parallel near both ends of the conductor layer 22C1 along its long side, and two via rows are connected in parallel near both ends of the conductor layer 22C2 along its long side.

[0153] Furthermore, in inductor L12, a via array is connected to each end of the conductor layer 12C1 along its long side, a via array is connected to each end of the conductor layer 12C2 along its long side, and a via array is connected to each end of the conductor layer 12C3 along its long side. Similarly, in inductor L21, a via array is connected to each end of the conductor layer 21C1 along its long side.

[0154] As described above, in this embodiment, in each of the inductors L11 and L22, a plurality of (two) rows of vias are connected in parallel at one end of the conductor layer. Therefore, according to this embodiment, the Q value of each of the inductors L11 and L22 can be increased.

[0155] On the other hand, in this embodiment, each of inductors L12 and L21 has a via array connected to one end of the conductor layer. Therefore, according to this embodiment, compared with the case where multiple via arrays are connected in parallel to one end of the conductor layer in all inductors L11, L12, L21, and L22, the size of electronic component 1 can be reduced.

[0156] Furthermore, in the first filter 10, it is preferable to increase the Q value of the inductor L11, which forms the attenuation pole 91 closest to the first passband. Similarly, in the second filter 20, it is preferable to increase the Q value of the inductor L22, which forms the attenuation pole 94 closest to the second passband. In this embodiment, based on this principle, multiple (two) rows of vias are connected in parallel at one end of the conductor layer in each of the inductors L11 and L22, thereby increasing the Q values ​​of each inductor L11 and L22.

[0157] Furthermore, in this embodiment, inductor L12 is disposed in front of inductor L11 in the -Y direction, and inductors L21 and L22 are disposed in front of inductors L11 and L12 respectively in the -X direction. That is, in this embodiment, inductors L11 and L12 are arranged in a row, and inductors L21 and L22 are arranged in a row at a different position than inductors L11 and L12. Therefore, according to this embodiment, compared with the case where inductors L11 and L22 are arranged in a row and inductors L12 and L21 are arranged in a row at a different position than inductors L11 and L22, the useless space generated in the laminate 50 can be reduced, and as a result, the electronic component 1 can be miniaturized.

[0158] As described above, according to this embodiment, the Q values ​​of inductors L11 and L22 can be increased, and the electronic component 1 can be miniaturized.

[0159] Furthermore, in this embodiment, the axis A11 of the wound inductor L11 and the axis A22 of the wound inductor L22 are parallel to each other. In particular, axes A11 and A22 both extend in a direction parallel to the Y direction. Additionally, in each of the inductors L11 and L22, the conductor layer portion has a shape that is longer in the X direction. Therefore, according to this embodiment, compared to the case where axes A11 and A22 are orthogonal to each other, the Y-direction dimension of the laminate 50 can be reduced.

[0160] Furthermore, in this embodiment, the direction parallel to axis A12 and the direction parallel to axis A22 are orthogonal to each other. In particular, the direction parallel to axis A12 is parallel to the X-direction, and the direction parallel to axis A22 is parallel to the Y-direction. Additionally, in this embodiment, inductor L12 is wound approximately three times around axis A12, which is parallel to the X-direction. As described above, the conductor layer portion of inductor L22 has a shape that is longer in the X-direction. Therefore, according to this embodiment, compared to the case where the conductor layer portion of inductor L22 is shorter in the X-direction and parallel to axis A22, the waste space generated when inductor L12 is wound multiple times around axis A12 can be reduced.

[0161] Furthermore, in this embodiment, the conductor layer portion 11C1 of the inductor L11 includes two conductor layers 721 and 731. As described above, during the manufacturing process of the laminate 50, multiple pre-firing conductor layers that will later become multiple conductor layers and a ceramic green sheet with multiple pre-firing through holes that will later become multiple through holes are laminated together. If conductor layer 721 and conductor layer 731 are offset from each other due to the offset of the ceramic green sheet or the multiple pre-firing conductor layers, the characteristics of the inductor L11 will change.

[0162] In this embodiment, the area of ​​conductor layer 721 is larger than the area of ​​conductor layer 731. Therefore, even if conductor layer 731 is offset relative to conductor layer 721, as long as the offset is less than a certain amount, conductor layer 731 will not be exposed from conductor layer 721 when viewed from a direction parallel to the stacking direction T (Z direction). Thus, according to this embodiment, the variation in the characteristics of inductor L11 caused by the mutual offset of conductor layer 721 and conductor layer 731 can be suppressed.

[0163] The above description of conductor layers 721 and 731 also applies to the group of conductor layers 72x and 73x (x is an integer between 2 and 7), the group of conductor layers 621 and 631, the group of conductor layers 622 and 632, the group of conductor layers 561 and 571, the group of conductor layers 543 and 553, and the group of conductor layers 591 and 601. Therefore, according to this embodiment, it is possible to suppress the variation in the characteristics of the first filter 10 and the second filter 20 caused by the offset of the ceramic green sheet or multiple pre-firing conductor layers, and as a result, it is possible to suppress the variation in the characteristics of the electronic component 1.

[0164] Furthermore, the present invention is not limited to the above-described embodiments and various modifications can be made. For example, the number of inductors included in the first filter 10 and the second filter 20 may each be three or more.

[0165] Additionally, axes A11 and A12 can intersect at an angle other than 90°. Similarly, axes A21 and A22 can intersect at an angle other than 90°.

[0166] In addition, in each of inductors L11 and L22, three or more through-hole arrays can be connected in parallel at one end of the conductor layer.

[0167] Furthermore, in each of the inductors L11, L12, L21, and L22, the conductor layer section may also include three or more conductor layers disposed at different positions in the stacking direction T and connected in parallel. When the conductor layer section includes three conductor layers, the conductor layer with the smallest area among the three conductor layers may exist between the other two conductor layers. Alternatively, the conductor layer section may also consist of a single conductor layer.

[0168] Clearly, based on the above description, various methods and variations of implementing the present invention are possible. Therefore, the present invention can be implemented even in forms other than the preferred form described above, within the scope equivalent to the claims.

Claims

1. A stacked electronic component, characterized in that, include: A laminate comprising multiple stacked dielectric layers; A first inductor integrated with the laminate is wound around a first axis orthogonal to the stacking direction of the plurality of dielectric layers; A second inductor integrated with the laminate is wound around a second axis orthogonal to the lamination direction; First port; Second port; and The signal path connecting the first port and the second port. From a circuit structure perspective, both the first inductor and the second inductor are positioned between the signal path and ground, and are connected to the ground. The areas of the first region and the second region are different from each other. The first region is obtained by vertically projecting a first space containing the first axis and enclosed by the first inductor onto a virtual plane perpendicular to the first axis. The second region is obtained by vertically projecting a second space containing the second axis and enclosed by the second inductor onto a virtual plane perpendicular to the second axis. The second inductor is configured such that, when viewed from a direction parallel to the second axis, at least a portion of the second space overlaps with a portion of the first space. The first inductor includes a first via array, a second via array, a first conductor layer, a second conductor layer, and a third conductor layer. The first through-hole row and the second through-hole row are each formed by connecting two or more through holes in series. The first conductor layer portion, the second conductor layer portion, and the third conductor layer portion each include at least one conductor layer. The first conductor layer connects one end of the first via row to one end of the second via row. The second conductor layer is connected to the other end of the first via array and extends close to the other end of the second via array. The third conductor layer is connected to the other end of the second via array and extends close to the other end of the first via array.

2. The stacked electronic component according to claim 1, characterized in that: The first axis and the second axis are parallel to each other.

3. The stacked electronic component according to claim 1, characterized in that: The area of ​​the first region is larger than the area of ​​the second region.

4. The stacked electronic component according to claim 1, characterized in that: The dimension of the first space in the stacking direction is greater than the dimension of the second space in the stacking direction.

5. The stacked electronic component according to claim 1, characterized in that: The second inductor includes: a plurality of conductor portions, each wound less than one turn around the second axis; and at least one connection portion connecting the plurality of conductor portions in series.

6. The stacked electronic component according to claim 1, characterized in that: The second inductor includes: a first conductor portion and a second conductor portion, each wound less than one turn around the second axis; and a connection portion connecting the first conductor portion and the second conductor portion. From a circuit structure perspective, the second conductor portion is positioned between the first conductor portion and the grounding point. The first conductor portion is magnetically coupled to the first inductor.

7. The stacked electronic component according to claim 1, characterized in that: It also includes multiple signal terminals and at least one ground terminal. The laminate has a bottom surface and a top surface located at both ends of the lamination direction, and four side surfaces connecting the bottom surface and the top surface. The plurality of signal terminals and the at least one ground terminal are disposed on the bottom surface.

8. The stacked electronic component according to claim 7, characterized in that: The third conductor layer is disposed between the first conductor layer and the bottom surface. When viewed from a direction parallel to the stacking direction, the third conductor layer extends across one of the plurality of signal terminals.

9. The stacked electronic component according to claim 7, characterized in that: The at least one grounding terminal includes a first grounding terminal and a second grounding terminal. The first inductor is electrically connected to the first ground terminal. The second inductor is electrically connected to the second ground terminal.

10. The stacked electronic component according to claim 1, characterized in that: It also includes circuitry integrated with the laminate, the circuitry excluding the first inductor and the second inductor.

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