Magnetic memory device

Abstract

The present invention relates to magnetic memory devices. Embodiments provide a magnetic memory device capable of reducing the load of a write operation. Generally, according to one embodiment, a magnetic memory device includes a three-terminal memory cell. A first terminal is connected to a first conductor layer. A second terminal is connected to a second conductor layer. A third terminal is connected to a third conductor layer. The memory cell includes a fourth conductor connected to the first, second, and third conductor layers. A magnetoresistive effect element of the memory cell is coupled between the third conductor layer and the fourth conductor layer. A first switching element is coupled to the second conductor layer and the fourth conductor layer. A second switching element is coupled to the first conductor layer and the third conductor layer. The fourth conductor layer includes a first ferromagnetic layer and a first nonmagnetic layer. The first nonmagnetic layer includes at least one of ruthenium, iridium, rhodium, or osmium.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims the priority of Japanese Patent Application No. 2021-149336, filed September 14, 2021, and U.S. Patent Application No. 17 / 684104, filed March 1, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to magnetic storage devices. Background Technology

[0004] Magnetic memory devices that use magnetoresistive elements as storage elements are known. Various methods have been proposed for writing data into magnetoresistive elements. Summary of the Invention

[0005] The embodiment provides a magnetic storage device that can reduce the load of write operations.

[0006] Generally, according to one embodiment, a magnetic memory device includes a three-terminal memory cell. The memory cell has a first terminal connected to a first conductive layer, a second terminal connected to a second conductive layer, and a third terminal connected to a third conductive layer. The memory cell includes a fourth conductive layer having a first portion connected to the first conductive layer, a second portion connected to the second conductive layer, and a third portion connected to the third conductive layer. The third portion is located between the first and second portions. A magnetoresistive element of the memory cell is coupled between the third and fourth conductive layers. A first switching element is coupled between the second and fourth conductive layers. A second switching element is coupled between the first and third conductive layers. The fourth conductive layer includes a first ferromagnetic layer and a first non-magnetic layer. The first non-magnetic layer is located between the first ferromagnetic layer and the magnetoresistive element. The first non-magnetic layer includes a first element selected from ruthenium, iridium, rhodium, and osmium. Attached Figure Description

[0007] Figure 1 This is a block diagram of a magnetic storage device according to an embodiment.

[0008] Figure 2 This is a circuit diagram of a memory cell array according to an embodiment.

[0009] Figure 3 This is a plan view of the memory cell array according to an embodiment.

[0010] Figure 4This is a cross-sectional view of a memory cell array according to an embodiment.

[0011] Figure 5 This is a cross-sectional view of the magnetoresistive element and its peripheral wiring according to an embodiment.

[0012] Figure 6 This is a perspective view of the magnetoresistive element and peripheral wiring according to an embodiment.

[0013] Figure 7 This is a circuit diagram relating to a write operation in a magnetic storage device according to an embodiment.

[0014] Figure 8 This is a cross-sectional view relating to a write operation in a magnetic storage device according to an embodiment.

[0015] Figure 9 This is a cross-sectional view relating to a write operation in a magnetic storage device according to an embodiment.

[0016] Figure 10 This is a plan view illustrating an example of the planar layout of the magnetoresistive element and peripheral wiring during manufacturing according to an embodiment.

[0017] Figure 11 This is a cross-sectional view relating to the manufacture of the magnetoresistive element and peripheral wiring according to the embodiment.

[0018] Figure 12 This is a plan view illustrating an example of the planar layout of the magnetoresistive element and peripheral wiring during manufacturing according to an embodiment.

[0019] Figure 13 This is a cross-sectional view relating to the manufacture of the magnetoresistive element and peripheral wiring according to the embodiment.

[0020] Figure 14 This is a plan view illustrating an example of the planar layout of the magnetoresistive element and peripheral wiring during manufacturing according to an embodiment.

[0021] Figure 15 This is a cross-sectional view relating to the manufacture of the magnetoresistive element and peripheral wiring according to the embodiment.

[0022] Figure 16 This is a plan view illustrating an example of the planar layout of the magnetoresistive element and peripheral wiring during manufacturing according to an embodiment.

[0023] Figure 17 This is a cross-sectional view relating to the manufacture of the magnetoresistive element and peripheral wiring according to the embodiment.

[0024] Figure 18 It is a circuit diagram of a memory primitive array based on a modified example.

[0025] Figure 19 It is a plan view of the memory primitive array based on the modified example.

[0026] Figure 20 This is a cross-sectional view of the memory primitive array based on the modified example. Detailed Implementation

[0027] In the following description, certain exemplary embodiments will be described with reference to the accompanying drawings. In this description, components, elements, aspects, etc., having substantially similar functions and configurations are represented by the same reference numerals. When distinguishing between components, elements, aspects, etc., of the same type / function, superscripts, suffixes, additional index numbers / letters, and / or the like may be added to otherwise common reference numerals to differentiate between such components, elements, aspects, etc. When it is not necessary to differentiate between components, elements, aspects, etc., of the same type / function, common reference numerals may be used to refer to each instance of the component, element, aspect, etc., and no suffix may be added to the common reference numerals.

[0028] In this specification, the magnetic memory device is, for example, a magnetoresistive random access memory (MRAM). Each cell of an MRAM includes a magnetic tunnel junction (MTJ) element that provides a tunneling magnetoresistive effect. Each MTJ element includes a reference layer and a storage layer, wherein a tunnel barrier layer exists between these layers. The magnetoresistive effect causes a change in resistance due to a change in the magnetization direction between the storage layer and the reference layer.

[0029] 1. First Embodiment

[0030] 1.1 Configuration

[0031] First, the configuration of the magnetic storage device according to the first embodiment will be described.

[0032] 1.1.1 Magnetic storage devices

[0033] Figure 1 This is a block diagram illustrating an example configuration of a magnetic storage device according to a first embodiment.

[0034] The magnetic storage device 1 includes a memory cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a writing circuit 14, a reading circuit 15, a voltage generation circuit 16, an input / output (I / O) circuit, and a control circuit 18.

[0035] The memory cell array 10 is a data storage unit in the magnetic storage device 1. The memory cell array 10 includes a plurality of memory cells MC. Each of the memory cells MC is specifically associated with a row and a column. Memory cells MC in the same row are coupled to the same word line WL, and memory cells MC in the same column are coupled to the same set of read bit lines RBL and write bit lines WBL.

[0036] Row selection circuit 11 selects different rows of memory cell array 10. Row selection circuit 11 is coupled to memory cell array 10 via word lines WL. Decoding circuit 13 provides the row selection circuit 11 with the decoding result (row address) of address ADD. Row selection circuit 11 selects the word line WL corresponding to address ADD. In the following, the word line WL corresponding to address ADD is referred to as the selected word line WL. Word lines WL other than (one or more) selected word lines WL are referred to as non-selected word lines WL.

[0037] Column selection circuit 12 selects a column of memory cell array 10. Column selection circuit 12 is coupled to memory cell array 10 via read bit line RBL and write bit line WBL. Decoding result (column address) of address ADD is provided to column selection circuit 12 from decoding circuit 13. Column selection circuit 12 selects the read bit line RBL and write bit line WBL corresponding to address ADD. In the following, the read bit line RBL and write bit line WBL corresponding to address ADD will be referred to as select bit line RBL and select bit line WBL. Read bit line RBL other than (one or more) select bit lines RBL is referred to as non-select bit line RBL. Write bit line WBL other than (one or more) select bit lines WBL is referred to as non-select bit line WBL.

[0038] Decoding circuit 13 is a decoder that decodes the address ADD from input / output circuit 17. Decoding circuit 13 decodes the address ADD and provides the decoding result to row selection circuit 11 and column selection circuit 12. The address ADD includes the selected column address and the selected row address.

[0039] The write circuit 14 includes, for example, a write driver. The write circuit 14 writes data into the memory primitive MC.

[0040] The read circuit 15 includes, for example, a sense amplifier. The read circuit 15 reads data from the memory primitive MC.

[0041] The voltage generation circuit 16 uses a power supply voltage supplied from outside the magnetic storage device 1 to generate voltages for various operations of the memory cell array 10. For example, the voltage generation circuit 16 generates various voltages required for write operations and outputs the voltages to the write circuit 14. The voltage generation circuit 16 also generates various voltages required for read operations and outputs the voltages to the read circuit 15.

[0042] Input / output circuit 17 handles communication with the outside of magnetic storage device 1. Input / output circuit 17 transmits the address ADD received from the outside of magnetic storage device 1 to decoding circuit 13. Input / output circuit 17 also transmits the command CMD received from the outside of magnetic storage device 1 to control circuit 18. Input / output circuit 17 sends and receives various control signals CNT between control circuit 18 and the outside of magnetic storage device 1. Input / output circuit 17 transmits data DAT received from the outside of magnetic storage device 1 to write circuit 14 and outputs data DAT from read circuit 15 to the outside of magnetic storage device 1.

[0043] The control circuit 18 includes, for example, a processor such as a central processing unit (CPU) and a read-only memory (ROM). The control circuit 18 controls the operation of the row selection circuit 11, column selection circuit 12, decoding circuit 13, writing circuit 14, reading circuit 15, voltage generation circuit 16, and input / output circuit 17 based on the control signal CNT and the command CMD.

[0044] 1.1.2 Memory Cell Array

[0045] Circuit configuration

[0046] Figure 2 This is a circuit diagram illustrating an example circuit configuration of a memory cell array according to an embodiment. Figure 2 In the text, each of the word line WL, read bit line RBL, and write bit line WBL is identified by a suffix (" "). <x>The text appears to be a series of symbols and symbols, possibly a corrupted or incomplete sentence. A direct translation is not possible without further context

[0047] The memory cell array 10 includes multiple memory cells MC, multiple word lines WL, multiple read bit lines RBL, and multiple write bit lines WBL. Figure 2 In the example, the multiple memory primitives MC include (M+1)×(N+1) individual memory primitives MC<0,0>, MC<0,1>, ..., MC<0,N>, MC<1,0>, ...<M,N> (where M and N are integers of 2 or greater). In Figure 2 The example shows the case where M and N are integers of 2 or greater, but the invention is not limited thereto, and M and N can be 0 or 1. Multiple word lines WL comprise (M+1) individual word lines WL. <0> WL <1> ...WL <m>Multiple read bit lines RBL consist of (N+1) individual read bit lines RBL. <0> RBL <1> ...RBL <n>Multiple write bit lines WBL comprise (N+1) individual write bit lines WBL. <0> WBL <1> ...WBL <n>.

[0048] Multiple memory cells (MCs) are arranged in a matrix within the memory cell array 10. Each memory cell (MC) is associated with one of multiple word lines (WL) and a pair of read bit lines (RBL) and write bit lines (WBL). That is, the memory cell (MC)<i,j> (where 0≤i≤M, 0≤j≤N) is coupled to word line WL Read bit line RBL <j>and write bit line WBL <j>.

[0049] Memory primitive MC<i,j> It is a three-terminal memory cell, including one coupled to the word line WL. The first end is coupled to the write bit line WBL <j>The second end is coupled to the read bit line RBL <j>The third end. Memory primitive MC<i,j> Including switching element SEL1<i,j> and SEL2<i,j> MTJ magnetoresistive element<i,j> and wiring SOTL<i,j> .

[0050] SOTL cabling<i,j> It includes a first part, a second part, and a third part between the first and second parts. (SOTL wiring)<i,j> The first part is coupled to the word line WL SOTL cabling<i,j> The second part is coupled to the write bit line WBL <j>SOTL cabling<i,j> The third part is coupled to the read bit line RBL. <j>Switching element SEL1<i,j> Coupled to the SOTL wiring<i,j> The second part is related to the write bit line WBL <j>Between. Magnetoresistive element MTJ<i,j> Coupled to the SOTL wiring<i,j> The third part is related to the read bit line RBL. <j>Between. Switching component SEL2<i,j> Coupled to the magnetoresistive element MTJ<i,j> With read bit line RBL <j>between.

[0051] Switching elements SEL1 and SEL2 are two-terminal switching elements. Two-terminal switching elements differ from three-terminal switching elements such as transistors. When the voltage applied between the two terminals of a two-terminal switching element is less than a threshold voltage (the threshold voltage Vth1 for switching element SEL1 and the threshold voltage Vth2 for switching element SEL2, respectively), the two-terminal switching element is in a "high resistance" state or a "off" state. That is, when the applied voltage across the two terminals of the respective switching element is less than the threshold voltages Vth1 and Vth2, switching elements SEL1 and SEL2 are in a non-conductive state, or essentially a non-conductive state. When the voltage applied across the two terminals of the two-terminal switching element is equal to or greater than the threshold voltages (the threshold voltage Vth1 for switching element SEL1 and the threshold voltage Vth2 for switching element SEL2, respectively), the switching element changes (switches) to a "low resistance" state or a "conducting" state. That is, when the voltage across the two terminals of the corresponding switching element is greater than the threshold voltages Vth1 and Vth2, the switching elements SEL1 and SEL2 are in a conductive state, or substantially conductive state. Therefore, when the voltage applied to the corresponding memory cell MC is lower than the threshold voltages Vth1 and Vth2, the switching elements SEL1 and SEL2 enter the off state and act as insulators with high resistance. When the voltage applied to the corresponding memory cell MC exceeds the threshold voltages Vth1 and Vth2, the switching elements SEL1 and SEL2 enter the on state and act as conductors with low resistance. The switching elements SEL1 and SEL2 switch conductivity based on the magnitude of the applied voltage, regardless of the polarity of the voltage (and the direction of the flowing current).

[0052] The SOTL (Site Layout Transmission) is a current path within a memory cell (MC). For example, when switching element SEL1 is on and switching element SEL2 is off, the SOTL serves as a current path between the word line WL and the write bit line WBL. When switching element SEL1 is off and switching element SEL2 is on, a portion of the SOTL serves as a current path between the word line WL and the read bit line RBL.

[0053] A magnetoresistive element (MTJ) is a resistance-changing element. The MTJ can switch between a low-resistance state and a high-resistance state based on the current controlled by switching elements SEL1 and SEL2. The MTJ is used as a storage element to store data in a non-volatile manner by changing its resistance state.

[0054] Floor plan

[0055] Next, the planar layout of the memory cell array according to the embodiment will be described. In the following, the plane parallel to the substrate surface will be referred to as the XY plane.

[0056] Figure 3 This is a plan view illustrating an example planar layout of a memory cell array according to an embodiment. Figure 3 In this context, structures such as insulating layers are omitted.

[0057] The memory cell array 10 also includes multiple vertical structures V1, multiple vertical structures V2, and multiple vertical structures V3. Each of the multiple vertical structures V1 includes a switching element SEL1. Each of the multiple vertical structures V2 includes a magnetoresistive element MTJ and a switching element SEL2.

[0058] Multiple write bit lines WBL are arranged in the X direction. Each of the multiple write bit lines WBL extends in the Y direction.

[0059] Multiple word lines (WLs) are positioned above multiple write bit lines (WBLs). The multiple word lines (WLs) are arranged in the Y direction. Each of the multiple word lines (WLs) extends in the X direction.

[0060] Multiple routing SOTLs are positioned above multiple word lines WL. In a planar view, each of the multiple routing SOTLs has a rectangular shape that is longer in the Y direction than in the X direction. Each of the multiple routing SOTLs extends in the Y direction. In a planar view, each of the multiple routing SOTLs is positioned in a matrix corresponding to a location that overlaps with a word line WL and a write bit line WBL.

[0061] Multiple read bit lines (RBLs) are positioned above multiple routing SOTLs. The multiple read bit lines (RBLs) are arranged in the X direction. Each of the multiple read bit lines (RBLs) extends in the Y direction. In a plan view, each of the multiple read bit lines (RBLs) is positioned at a location overlapping with multiple write bit lines (WBLs).

[0062] Multiple vertical structures V1 extend in the Z direction. In the plan view, the multiple vertical structures V1 have a circular shape. Each of the multiple vertical structures V1 is coupled between a corresponding write bit line WBL and a corresponding routing SOTL. That is, each of the multiple vertical structures V1 is coupled to the second part of the corresponding routing SOTL.

[0063] Multiple vertical structures V2 extend in the Z direction. In a planar view, the multiple vertical structures V2 have a rectangular shape. In a planar view, the multiple vertical structures V2 may also have a square shape. More specifically, in a planar view, each of the multiple vertical structures V2 includes a side having a length equal to the short side of the corresponding routing SOTL and parallel to the short side of the routing SOTL, and a side having a length shorter than the long side of the routing SOTL and overlapping the long side of the routing SOTL. That is, the side surface of the YZ plane parallel to each of the multiple vertical structures V2 is set in the same plane (flush) as the side surface of the YZ plane parallel to the corresponding routing SOTL. Each of the multiple vertical structures V2 is coupled between a corresponding read bit line RBL and a corresponding routing SOTL. That is, each of the multiple vertical structures V2 is coupled to a third portion of the corresponding routing SOTL.

[0064] Multiple vertical structures V3 extend in the Z direction. In the plan view, the multiple vertical structures V3 have a circular shape. Each of the multiple vertical structures V3 is coupled between a corresponding word line WL and a corresponding routing SOTL. That is, each of the multiple vertical structures V3 is coupled to the first part of the corresponding routing SOTL.

[0065] In the above configuration, a group consisting of a wiring SOTL, a vertical structure V1 coupled to the wiring SOTL, a vertical structure V2 and a vertical structure V3 is used as a memory element MC.

[0066] Cross-sectional structure

[0067] Figure 4 It is along Figure 3 The cross-sectional view taken along line IV-IV shows an example of the cross-sectional structure of a memory cell array according to an embodiment. The memory cell array 10 includes a semiconductor substrate 20 and structures L1 and L2. Structure L1 includes conductor layers 21_1, 23_1, 24_1, 25_1, 26_1, and 29_1, and element layers 22_1, 27_1, and 28_1. Structure L2 includes conductor layers 21_2, 23_2, 24_2, 25_2, 26_2, and 29_2, and element layers 22_2, 27_2, and 28_2.

[0068] Structures L1 and L2 are stacked in the Z direction above the semiconductor substrate 20. Structures L1 and L2 each correspond to... Figure 3 The planar layout shown.

[0069] Peripheral circuitry such as row selection circuitry 11 and column selection circuitry 12 can be disposed between semiconductor substrate 20 and structure L1. In some examples, no circuitry may be formed between semiconductor substrate 20 and structure L1. When no circuitry is formed between semiconductor substrate 20 and structure L1, shallow trench isolation (STI) features may be formed in the portion of semiconductor substrate 20 located below structure L1.

[0070] The structure L1 will be described.

[0071] A conductor layer 21_1 is disposed above the semiconductor substrate 20. The conductor layer 21_1 serves as the write bit line WBL. The conductor layer 21_1 extends in the Y direction.

[0072] Component layer 22_1 is disposed on the upper surface of conductor layer 21_1. Component layer 22_1 is used as switching component SEL1.

[0073] Conductor layer 23_1 is disposed on the upper surface of element layer 22_1. Conductor layer 23_1 serves as a contact. Element layer 22_1 and conductor layer 23_1 constitute a vertical structure V1.

[0074] Conductor layer 24_1 is disposed on the upper surface of conductor layer 23_1. Conductor layer 24_1 serves as a wiring SOTL. The portion of conductor layer 24_1 that contacts conductor layer 23_1 corresponds to the second portion of the wiring SOTL. Conductor layer 24_1 extends in the Y direction.

[0075] Conductor layer 25_1 is disposed on the lower surface of conductor layer 24_1, at a portion different from the portion where conductor layer 23_1 is disposed. The portion of conductor layer 24_1 that contacts conductor layer 25_1 corresponds to the first portion of wiring SOTL. Conductor layer 25_1 serves as a contact. Conductor layer 25_1 constitutes the vertical structure V3.

[0076] Conductor layer 26_1 is disposed on the lower surface of conductor layer 25_1. Conductor layer 26_1 serves as word line WL. Conductor layer 26_1 extends in the X direction.

[0077] Component layer 27_1 is disposed on the upper surface of the portion of conductor layer 24_1 between the portion where conductor layer 23_1 is disposed and the portion where conductor layer 25_1 is disposed. The portion of conductor layer 24_1 that contacts component layer 27_1 corresponds to the third portion of the SOTL wiring. Component layer 27_1 serves as a magnetoresistive element (MTJ).

[0078] Component layer 28_1 is disposed on the upper surface of component layer 27_1. Component layer 28_1 serves as a switching component SEL2. Component layers 27_1 and 28_1 constitute a vertical structure V2.

[0079] Conductor layer 29_1 is disposed on the upper surface of element layer 28_1. Conductor layer 29_1 serves as the read bit line RBL. Conductor layer 29_1 extends in the Y direction.

[0080] Using the above configuration, conductor layer 24_1 and vertical structures V1, V2 and V3 are used as a memory cell MC having three terminals respectively coupled to conductor layers 21_1, 26_1 and 29_1.

[0081] Structure L2 has the same overall structure as structure L1. That is, conductor layers 21_2, 23_2, 24_2, 25_2, 26_2, and 29_2, and element layers 22_2, 27_2, and 28_2 have the same structure and function as conductor layers 21_1, 23_1, 24_1, 25_1, 26_1, and 29_1, and element layers 22_1, 27_1, and 28_1, respectively. Therefore, conductor layer 24_2 and vertical structures V1, V2, and V3 serve as a memory cell MC with three terminals respectively coupled to conductor layers 21_2, 26_2, and 29_2.

[0082] 1.1.3 Magnetoresistive components and peripheral wiring

[0083] Figure 5 yes Figure 4 A cross-sectional view of region V shows an example of the cross-sectional structure of the magnetoresistive element and peripheral wiring according to an embodiment. Figure 6 This is a perspective view illustrating an example structure of a magnetoresistive element and peripheral wiring according to an embodiment. Conductor layer 24 includes an antiferromagnetic layer 24a, a ferromagnetic layer 24b, a non-magnetic layer 24c, and a non-magnetic layer 24d. Element layer 27 includes a ferromagnetic layer 27a, a non-magnetic layer 27b, a ferromagnetic layer 27c, a non-magnetic layer 27d, and a ferromagnetic layer 27e. Figure 6 In the diagram, the non-magnetic layer 24d is shown by a dashed line.

[0084] First, the details of the structure of conductor layer 24 will be described.

[0085] The antiferromagnetic layer 24a is a conductive film exhibiting antiferromagnetism. The antiferromagnetic layer 24a is coupled to the ferromagnetic layer 24b via exchange coupling. Therefore, the antiferromagnetic layer 24a fixes the magnetization direction of the ferromagnetic layer 24b in one direction. The antiferromagnetic layer 24a comprises, for example, platinum manganese (PtMn). To prevent current shunting, the film thickness of the antiferromagnetic layer 24a is preferably thin. For example, the film thickness of the antiferromagnetic layer 24a is preferably 10 nanometers (nm) or less. More preferably, the film thickness of the antiferromagnetic layer 24a is 5 nm or less. When the magnetization direction of the ferromagnetic layer 24b is controlled by shape anisotropy and induced magnetic anisotropy through heat treatment or magnetization application, from the viewpoint of preventing current shunting, the antiferromagnetic layer 24a may not be required.

[0086] A ferromagnetic layer 24b is disposed on the upper surface of the antiferromagnetic layer 24a. The ferromagnetic layer 24b is a conductive film exhibiting ferromagnetism. The ferromagnetic layer 24b contains at least one element selected from iron (Fe), cobalt (Co), nickel (Ni), and gadolinium (Gd) as a ferromagnetic material. The ferromagnetic layer 24b has an axial direction that facilitates magnetization in its extension direction (Y direction). In addition to shape anisotropy, the magnetization direction of the ferromagnetic layer 24b is stabilized along the Y direction through exchange coupling with the antiferromagnetic layer 24a. The magnetization direction of the ferromagnetic layer 24b is reversed according to the direction of the current flowing in the ferromagnetic layer 24b. From the viewpoint of preventing current shunting, the film thickness of the ferromagnetic layer 24b is preferably thin. For example, the film thickness of the ferromagnetic layer 24b is preferably 3 nm or less. More preferably, the film thickness of the ferromagnetic layer 24b is 1 nm to 2 nm or less. To prevent current shunting, the ferromagnetic layer 24b preferably has high resistance. For example, the crystal structure of the ferromagnetic layer 24b is preferably an amorphous structure.

[0087] The central portion of the ferromagnetic layer 24b corresponding to the third part of the wiring SOTL is higher in the Z direction than the two ends that clamp the central portion. That is, the central portion of the ferromagnetic layer 24b has a portion that protrudes upward in the Z direction beyond the outer end portions (protrusion portion BP; see Figure 5 The protruding portion BP of the ferromagnetic layer 24b is rectangular in shape. Therefore, the protruding portion of the ferromagnetic layer 24b has a side surface PXZ parallel to the XZ plane (see...). Figure 6 (Shaded surface in the image). A leakage magnetic field SF is generated from the side surface PXZ of ferromagnetic layer 24b.

[0088] The ferromagnetic layer 24b comprises a heavy metal. Specifically, in this example, the ferromagnetic layer 24b contains at least one element selected from neodymium (Nd), samarium (Sm), europium (Eu), terbium (Tb), dysprosium (Dy), and holmium (Ho) as a heavy metal. By including such a heavy metal element, the ferromagnetic layer 24 tends to be in an amorphous phase and is expected to have high electrical resistance.

[0089] The ferromagnetic layer 24b can be a single thin film layer comprising an alloy of the ferromagnetic material and heavy metal mentioned above. When the ferromagnetic layer 24b is a thin film, it typically has an amorphous structure.

[0090] The ferromagnetic layer 24b may be a film stack comprising layers containing ferromagnetic material and layers containing heavy metal stacked on top of each other. When the ferromagnetic layer 24b is a stacked film, at least the layer containing heavy metal has an amorphous structure.

[0091] From the viewpoint of improving film adhesion, an underlayer can be formed on the lower surface of the antiferromagnetic layer 24a (on the semiconductor substrate 20 side), or on the lower surface of the ferromagnetic layer 24b (on the semiconductor substrate 20 side) when the antiferromagnetic layer 24a is not formed. For example, the adhesion-enhancing underlayer includes tantalum (Ta), tungsten (W), titanium (Ti), titanium nitride (TiN), etc. The thickness of such a base layer is preferably 3 nm or less.

[0092] A nonmagnetic layer 24c is disposed on the upper surface of the central portion (protruding portion BP) of the ferromagnetic layer 24b. The nonmagnetic layer 24c is a conductive film made of a nonmagnetic heavy metal. In this example, the nonmagnetic layer 24c includes at least one element selected from ruthenium (Ru), iridium (Ir), rhodium (Rh), and osmium (Os).

[0093] The nonmagnetic layer 24c generates spin-orbit torque (SOT) primarily due to the current flowing within it. To obtain a large SOT, it is necessary to increase the current flowing through the nonmagnetic layer 24c, i.e., increase the current density. Therefore, it is necessary to minimize the current shunting to other layers (especially the antiferromagnetic layer 24a and the ferromagnetic layer 24b). The SOT is injected into the ferromagnetic layer 27a. The nonmagnetic layer 24c antiferromagnetically couples the ferromagnetic layers 24b and 27a through interlayer exchange coupling.

[0094] The nonmagnetic layer 24c has a film thickness of, for example, 3 nanometers (nm) or less in the Z direction. From the viewpoint of generating antiferromagnetic interlayer exchange coupling, the film thickness of the nonmagnetic layer 24c is preferably 2 nm or less. More specifically, when the nonmagnetic layer 24c comprises ruthenium (Ru), the film thickness of the nonmagnetic layer 24c is preferably 0.4 nm to 0.6 nm, or 0.8 nm to 1.2 nm. When the nonmagnetic layer 24c comprises iridium (Ir), the film thickness of the nonmagnetic layer 24c is preferably 0.4 nm to 0.6 nm, or 1.2 nm to 1.6 nm. When the nonmagnetic layer 24c comprises rhodium (Rh), the film thickness of the nonmagnetic layer 24c is preferably 0.6 nm to 1.0 nm, or 1.6 nm to 2.0 nm. When the nonmagnetic layer 24c comprises osmium (Os), the film thickness of the nonmagnetic layer 24c is preferably 0.8 nm to 1.2 nm. When the nonmagnetic layer 24c is an alloy comprising at least two elements selected from ruthenium (Ru), iridium (Ir), rhodium (Rh) and osmium (Os), the energy of the antiferromagnetic interlayer exchange coupling and the film thickness that maximizes this energy can be controlled by the combination of the selected elements, etc.

[0095] A non-magnetic layer 24d is disposed on the upper surfaces of both ends of the ferromagnetic layer 24b, the side surface of the central portion (protruding portion BP) of the ferromagnetic layer 24b, and a portion of the side surface of the non-magnetic layer 24c. The upper surface of the non-magnetic layer 24d is located at a lower height in the Z direction than the upper surface of the non-magnetic layer 24c. The lower surface of the non-magnetic layer 24d is located at a lower height in the Z direction than the lower surface of the non-magnetic layer 24c.

[0096] The nonmagnetic layer 24d is a conductive film made of a nonmagnetic alloy. The nonmagnetic layer 24d has an amorphous structure. The nonmagnetic layer 24d is formed by mixing the ferromagnetic material of the ferromagnetic layer 24b with the heavy metal of the nonmagnetic layer 24c. Therefore, the nonmagnetic layer 24d includes at least one element selected from ruthenium (Ru), iridium (Ir), rhodium (Rh), and osmium (Os), and at least one element selected from iron (Fe), cobalt (Co), nickel (Ni), and gadolinium (Gd). The nonmagnetic layer 24d may also include at least one element selected from neodymium (Nd), samarium (Sm), europium (Eu), terbium (Tb), dysprosium (Dy), and holmium (Ho).

[0097] At least one element selected from ruthenium (Ru), iridium (Ir), rhodium (Rh), and osmium (Os) in conductor layer 24 is distributed at a lower height in the Z direction in the portion where the non-magnetic layer 24d is disposed than in the portion where the non-magnetic layer 24c is disposed. At least one element selected from iron (Fe), cobalt (Co), nickel (Ni), and gadolinium (Gd) in conductor layer 24 is distributed at a higher height in the Z direction in the portion where the non-magnetic layer 24d is disposed than in the portion where the non-magnetic layer 24c is disposed. At least one element selected from neodymium (Nd), samarium (Sm), europium (Eu), terbium (Tb), dysprosium (Dy), and holmium (Ho) in conductor layer 24 is distributed at a higher height in the Z direction in the portion where the non-magnetic layer 24d is disposed than in the portion where the non-magnetic layer 24c is disposed.

[0098] The non-magnetic layer 24d includes non-magnetic layers 24d-1 and 24d-2. Non-magnetic layer 24d-1 is disposed on one upper surface at both ends of the ferromagnetic layer 24b. Non-magnetic layer 24d-2 is disposed on the other upper surface at both ends of the ferromagnetic layer 24b. Non-magnetic layers 24d-1 and 24d-2 are physically separated from each other by a protrusion BP of the ferromagnetic layer 24b and a non-magnetic layer 24c.

[0099] A ferromagnetic layer 27a is disposed on the upper surface of the non-magnetic layer 24c. The ferromagnetic layer 27a is a conductive film with ferromagnetic properties. The ferromagnetic layer 27a serves as a storage layer. The ferromagnetic layer 27a has an axial direction for easy magnetization in a direction perpendicular to the film surface (Z direction). A bias magnetic field AFIE in the Y direction is applied to the ferromagnetic layer 27a at the interface with the non-magnetic layer 24c via interlayer exchange coupling between the non-magnetic layer 24c and the ferromagnetic layer 24b. The direction of the bias magnetic field AFIE is antiparallel to the magnetization direction of the ferromagnetic layer 24b. The direction of the bias magnetic field AFIE is parallel to the direction of the leakage magnetic field SF acting on the ferromagnetic layer 27a. Therefore, the bias magnetic field AFIE and the leakage magnetic field SF act on the ferromagnetic layer 27a to reinforce each other. A leakage magnetic field from the ferromagnetic layer 27a is also generated from the end of the wiring SOTL. Similar to the direction of the leakage magnetic field SF, the direction of the leakage magnetic field from the end of the wiring SOTL is parallel to the direction of the bias magnetic field AFIE. Therefore, in addition to the bias magnetic field AFIE and the leakage magnetic field SF, the leakage magnetic field from the end of the wiring SOTL also acts on the ferromagnetic layer 27a to further reinforce each other. The spin-orbit torque generated in the nonmagnetic layer 24c is injected into the ferromagnetic layer 27a. The magnetization direction of the ferromagnetic layer 27a is configured to be reversed based on the sum of the bias magnetic field AFIE and the leakage magnetic field SF in the Y direction and the spin-orbit torque.

[0100] The ferromagnetic layer 27a comprises iron (Fe). The ferromagnetic layer 27a may also comprise at least one of cobalt (Co) and nickel (Ni). The ferromagnetic layer 27a may additionally comprise boron (B). More specifically, for example, the ferromagnetic layer 27a is iron cobalt boron (FeCoB) or iron boride (FeB).

[0101] To increase the retention energy for data retention, the ferromagnetic layer 27a may comprise a stacked film of layers A and B. Layer A is a layer comprising at least one element selected from cobalt (Co), iron (Fe), and nickel (Ni). Layer B is a layer comprising at least one element selected from platinum (Pt), iridium (Ir), palladium (Pd), and gold (Au). Examples of the stacked film include Co / Pt stacked films, Co / Ir stacked films, Co / Pd stacked films, etc. The stacked film is further stacked with a layer C comprising iron cobalt boron (FeCoB). In this case, the stacked film is positioned to contact the nonmagnetic layer 24c, and layer C is positioned to contact the nonmagnetic layer 27b.

[0102] A nonmagnetic layer 27b is disposed on the upper surface of the ferromagnetic layer 27a. The nonmagnetic layer 27b is a nonmagnetic insulating film. The nonmagnetic layer 27b serves as a tunnel barrier layer. The nonmagnetic layer 27b is disposed between the ferromagnetic layer 27a and the ferromagnetic layer 27c, and together with these two ferromagnetic layers, forms a magnetic tunnel junction. In the crystallization process of the ferromagnetic layer 27a, the nonmagnetic layer 27b serves as a seed material for growing a crystalline film at the interface with the ferromagnetic layer 27a. The nonmagnetic layer 27b has a NaCl crystal structure in which the film surface is oriented towards the (001) surface. The nonmagnetic layer 27b includes, for example, magnesium oxide (MgO).

[0103] A ferromagnetic layer 27c is disposed on the upper surface of the non-magnetic layer 27b. The ferromagnetic layer 27c is a conductive film exhibiting ferromagnetism. The ferromagnetic layer 27c serves as a reference layer. The ferromagnetic layer 27c has an axial direction for easy magnetization in a direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic layer 27c is fixed. Figure 5 In this example, the magnetization direction of the ferromagnetic layer 27c points in the same direction as the ferromagnetic layer 27a. The phrase "the magnetization direction is fixed" means that the magnetization direction will not change due to a torque having an amplitude that could reverse the magnetization direction of the ferromagnetic layer 27a. In this example, the ferromagnetic layer 27c comprises at least one compound selected from cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd).

[0104] A non-magnetic layer 27d is disposed on the upper surface of the ferromagnetic layer 27c. The non-magnetic layer 27d is a non-magnetic conductive film. The non-magnetic layer 27d serves as a spacer layer. In this example, the non-magnetic layer 27d includes at least one element selected from ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr). The film thickness of the non-magnetic layer 27d is 2 nm or less.

[0105] A ferromagnetic layer 27e is disposed on the upper surface of the non-magnetic layer 27d. The ferromagnetic layer 27e is a conductive film exhibiting ferromagnetism. The ferromagnetic layer 27e serves as a shift cancelling layer. The ferromagnetic layer 27e has an axial direction for easy magnetization in a direction perpendicular to the film surface (Z direction). In this example, the ferromagnetic layer 27e comprises at least one compound selected from cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd).

[0106] Ferromagnetic layers 27c and 27e are antiferromagnetically coupled by a nonmagnetic layer 27d. That is, ferromagnetic layers 27c and 27e are coupled with magnetization directions that are antiparallel to each other. This coupling structure of ferromagnetic layer 27c, nonmagnetic layer 27d, and ferromagnetic layer 27e is called a synthetic antiferromagnetic (SAF) structure. Due to the SAF structure, ferromagnetic layer 27e can counteract the influence of the leakage magnetic field of ferromagnetic layer 27c on the magnetization direction of ferromagnetic layer 27a.

[0107] Depending on whether the magnetization directions of the storage layer and the reference layer are parallel or antiparallel, the magnetoresistive element (MTJ) can be in a low-resistance or high-resistance state. In this embodiment, the magnetization direction of the storage layer relative to the magnetization direction of the reference layer is controlled so that write current does not flow through the MTJ. Specifically, a write method using spin-track torque generated by allowing current to flow through the wiring SOTL is employed.

[0108] When a write current Ic0 of a certain magnitude passes through the SOTL wiring in the Y direction, the relative magnetization directions between the memory layer and the reference layer become parallel. In this parallel state, the resistance of the magnetoresistive element MTJ is at its lowest, and the magnetoresistive element MTJ is set to a low-resistance state. This low-resistance state is called the "P (parallel) state" and is defined, for example, as the state of data "0".

[0109] When a write current Ic1, greater than the write current Ic0, passes through the SOTL wiring in the opposite direction to the write current Ic0, the relative magnetization directions between the memory layer and the reference layer become antiparallel. In this antiparallel state, the resistance of the magnetoresistive element MTJ is at its highest, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called the "AP (antiparallel) state" and is defined, for example, as the state of data "1".

[0110] The methods for defining data "1" and data "0" are not limited to the examples mentioned above. For example, the P state can be defined as data "1", and the AP state can be defined as data "0".

[0111] 1.2 Operation

[0112] Figure 7 This is a circuit diagram illustrating an example of a write operation in a magnetic storage device according to an embodiment. Figure 7 The example shows data being written to multiple memory primitives MC.<m,n> Case (0) <m<M,0<n<N)。

[0113] When data is written to the memory primitive MC<m,n> At that time, voltage VDD or VSS is applied to word line WL <m>and write bit line WBL <n>Each of them. When voltage VDD is applied to word line WL <m>At that time, voltage VSS is applied to the write bit line WBL. <n>When voltage VSS is applied to word line WL <m>At that time, voltage VDD is applied to the write bit line WBL. <n>Voltage VDD / 2 is applied to everything except word line WL. <m>All word lines WL except for the write bit line WBL <n>All write bit lines WBL and all read bit lines RBL except for the write bit line WBL.

[0114] Voltage VSS is the reference potential. For example, voltage VSS is 0V. The voltage VDD (potential difference VDD) relative to voltage VSS is the voltage that turns on switching elements SEL1 and SEL2. Potential difference VDD is the voltage that allows current to flow, changing the resistance state of the magnetoresistive element MTJ. Potential difference VDD / 2 is the voltage that turns off switching elements SEL1 and SEL2.

[0115] Therefore, in the word line WL <m>With write bit line WBL <n>A potential difference VDD is generated between them. At word line WL <m>Except for the write bit line WBL <n>A potential difference VDD / 2 is generated between any write bit lines WBL and the word line WL. <m>A potential difference VDD / 2 is generated between the read bit line RBL and any read bit line.

[0116] In addition to the letter line WL <m>Any word line WL other than the write bit line WBL <n>A potential difference VDD / 2 is generated between them. This applies except for the word line WL. <m>Any word line WL other than the write bit line WBL <n>No potential difference is generated between any write bit lines WBL other than the word line WL. <m>No potential difference is generated between any word line WL and any read bit line RBL other than the word line WL.

[0117] Write bit line WBL <n>With read bit line RBL <n>A potential difference of VDD / 2 is generated between them. This occurs except for the write bit line WBL. <n>No potential difference is generated between any write bit line WBL and the corresponding read bit line RBL except for the write bit line WBL.

[0118] Therefore, switching element SEL1<m,n> On. Except for switching component SEL1<m,n> All switching elements SEL1 except for SEL2 are turned off.

[0119] Therefore, it enables current to pass through the wiring SOTL<m,n> To prevent current from passing through except for wiring SOTL<m,n> All wiring SOTL and all magnetoresistive elements MTJ except for SOTL.

[0120] In the write operation mentioned above, the memory primitive MC<m,n> The state is also called the selection state. The memory primitives MC<0,n> to MCn<m-1,n> MC<m+1,n> To MC<m,n> MC<m,0> To MC<m,n-1> and MC<m,n+1> To MC<m,n> The state of these cells is also called the semi-selected state. The state of all memory cells (MCs) that are not in the selected or semi-selected state is also called the non-selected state.

[0121] Figure 8 and Figure 9 This is a cross-sectional view illustrating an example of a write operation in a magnetic storage device according to an embodiment. Figure 8 and Figure 9 The current flowing through the select memory cell MC and the magnetization direction of the magnetoresistive element MTJ are schematically shown. Figure 8 This corresponds to the write operation when writing the data "1". Figure 9 This corresponds to the write operation when writing data "0".

[0122] First, refer to Figure 8 Describe the operation of writing the data "1". Figure 8 The example shows the write current Ic1 flowing from word line WL (right side of the paper) to write bit line WBL (left side of the paper).

[0123] As described above, a potential difference VDD is generated across the conductor layer 24 to turn on the switching element SEL1. By controlling the potential difference VDD, a write current Ic1 flows through the conductor layer 24. When the write current Ic1 flows through the conductor layer 24, particularly through the non-magnetic layer 24c, a spin-orbit torque is generated that attempts to make the magnetization direction of the ferromagnetic layer 27a antiparallel to the magnetization direction of the ferromagnetic layer 27c. This spin-orbit torque is injected into the ferromagnetic layer 27a near the non-magnetic layer 24c.

[0124] The magnetization direction of the ferromagnetic layer 24b is aligned with the flow direction of the write current Ic1. Therefore, a bias magnetic field AFIE in the Y direction, generated by interlayer exchange coupling between the nonmagnetic layer 24c and the ferromagnetic layer 24b, is applied to the ferromagnetic layer 27a. Additionally, a leakage magnetic field SF generated from the protrusion BP of the ferromagnetic layer 24b is applied to the ferromagnetic layer 27a in a direction parallel to the bias magnetic field AFIE.

[0125] Therefore, with the assistance of the sum of the bias magnetic field AFIE and the leakage magnetic field SF, as well as the spin orbital torque, the magnetization direction of the ferromagnetic layer 27a is reversed in a direction that is antiparallel to the magnetization direction of the ferromagnetic layer 27c.

[0126] In this case, to easily and precisely control the leakage magnetic field SF from the magnetic layer 24b, it might be better for the magnetic layer 24b to have a synthetic antiferromagnetic (SAF) structure, corresponding to the following stacked layer structure: lower ferromagnetic layer / intermediate nonmagnetic layer / upper ferromagnetic layer instead of just a single ferromagnetic layer structure. Using the SAF-type structure, the upper and lower ferromagnetic layers are directly connected to the nonmagnetic layer 24c and the antiferromagnetic layer 24a. With the SAF structure, the leakage magnetic field of the lower ferromagnetic layer can controllably reduce the influence of the leakage magnetic field of the upper ferromagnetic layer on the ferromagnetic layer 27a of the MTJ, thus allowing for more precise control of the leakage magnetic field strength. In this case, the intermediate nonmagnetic layer can preferably be Cr, Ru, Ir, or Os, and the upper and lower ferromagnetic layers should include at least one of Co, Fe, or Ni. Generally, amorphous materials such as CoB, CoFeB, and NiFeB are better for these purposes.

[0127] Next, we will refer to Figure 9 Describes the writing of the data "0". Figure 9 The example shows the write current Ic0 flowing from the write bit line WBL (left side of the paper) to the word line WL (right side of the paper).

[0128] As described above, a potential difference VDD is generated across the conductor layer 24 to turn on the switching element SEL1. By controlling the potential difference VDD, a write current Ic0 flows in the conductor layer 24. When the write current Ic0 flows in the conductor layer 24, particularly in the non-magnetic layer 24c, a spin-orbit torque is generated that attempts to make the magnetization direction of the ferromagnetic layer 27a parallel to the magnetization direction of the ferromagnetic layer 27c. This spin-orbit torque is injected into the ferromagnetic layer 27a near the non-magnetic layer 24c.

[0129] The magnetization direction of the ferromagnetic layer 24b is aligned with the flow direction of the write current Ic0. Therefore, a bias magnetic field AFIE in the -Y direction, generated by interlayer exchange coupling between the nonmagnetic layer 24c and the ferromagnetic layer 24b, is applied to the ferromagnetic layer 27a. Additionally, a leakage magnetic field SF generated from the protrusion BP of the ferromagnetic layer 24b is applied to the ferromagnetic layer 27a in a direction parallel to the bias magnetic field AFIE.

[0130] Therefore, with the assistance of the sum of the bias magnetic field AFIE and the leakage magnetic field SF, as well as the spin orbital torque, the magnetization direction of the ferromagnetic layer 27a is reversed in the direction parallel to the magnetization direction of the ferromagnetic layer 27c.

[0131] 1.3 Manufacturing Method

[0132] Figures 10 to 17 Each of these illustrates aspects of the manufacturing process other than the formation of the write bit line WBL, word line WL, vertical structure V1, and vertical structure V3. Figure 10 , Figure 12 , Figure 14 and Figure 16 The planar layout (one or more) shown corresponds to a layout including a routing SOTL. Figure 3 The sub-regions of the planar layout shown.

[0133] Figure 11 The cross-sectional structure shown is along Figure 10 The sectional view taken by line XI-XI. Figure 13 The cross-sectional structure shown is along Figure 12 A sectional view taken from line XIII-XIII. Figure 15 The cross-sectional structure shown is along Figure 14 A cross-sectional view taken by line XV-XV. Figure 17 The cross-sectional structure shown is along Figure 16 A sectional view taken from line XVII-XVII.

[0134] In the following text, it is assumed that multiple write bit lines WBL, multiple word lines WL, multiple vertical structures V1, and multiple vertical structures V3 have been formed on the semiconductor substrate 20. The subsequent fabrication process of the wiring SOTL and the magnetoresistive element MTJ will be described below.

[0135] An antiferromagnetic layer 24a is disposed on the upper surface of a structure comprising multiple write bit lines WBL, multiple word lines WL, multiple vertical structures V1, and multiple vertical structures V3. Conductor layers 23 and 25 exposed on the upper surface of the structure are electrically coupled to the antiferromagnetic layer 24a.

[0136] Subsequently, as Figure 10 and Figure 11 As shown, ferromagnetic layer 24b, nonmagnetic layer 24c, ferromagnetic layer 27a, nonmagnetic layer 27b, ferromagnetic layer 27c, nonmagnetic layer 27d and ferromagnetic layer 27e are stacked on the upper surface of antiferromagnetic layer 24a in this order.

[0137] Subsequently, a mask 31 is formed using photolithography or similar methods. The mask 31 defines the length of the long dimension (Y direction) of the wiring SOTL and the width of the short dimension (X direction) of the wiring SOTL. Then, as... Figure 12 and Figure 13 As shown, an anisotropic etching process using mask 31 forms a slit SH1 that penetrates the ferromagnetic layer 27e, nonmagnetic layer 27d, ferromagnetic layer 27c, nonmagnetic layer 27b, ferromagnetic layer 27a, nonmagnetic layer 24c, ferromagnetic layer 24b, and antiferromagnetic layer 24a. At the bottom of slit SH1, a portion of the upper surface of the insulating layer 30 is exposed. The insulating layer 30 is an insulating film covering the sides of the conductor layers 23 and 25 at a horizontal level below the antiferromagnetic layer 24a. It can be said that conductors 23 and 25 are embedded within the insulating layer 30. Physical etching using an ion beam can be applied to the anisotropic etching process in this procedure.

[0138] The slit SH1 is then filled with the insulating layer 32. Any portion of the insulating layer 32 formed on the upper surface of the ferromagnetic layer 27e can be removed, for example, by chemical mechanical polishing (CMP). Thus, the upper surface of the stacked structure is planarized.

[0139] Next, a mask 33 is formed using photolithography or similar methods. The mask 33 defines the dimensions of the magnetoresistive element MTJ in the Y direction. For example... Figure 14 and Figure 15 As shown, an anisotropic etching process using mask 33 forms a slit SH2 that cuts off the ends of the ferromagnetic layers 27e, 27d, 27c, 27b, and 27a. At the bottom of the slit SH2, the upper surface of the insulator layer 32 and the portion of the conductor layer 24 not directly below mask 33 are exposed. Physical etching using an ion beam is applied to the anisotropic etching process in this procedure.

[0140] Here, the portion of conductor layer 24 not directly beneath mask 33 is affected by the injected etching gas for physical etching and by the impact of the injected etching gas on and interaction with the elements in conductor layer 24. Therefore, a portion of conductor layer 24 may be etched and the material of conductor layer 24 (or a portion thereof) may be altered. The film thickness of nonmagnetic layer 24c may be 3 nm or less. Therefore, the effect of the etching gas may extend to the portion or all of ferromagnetic layer 24b not directly beneath mask 33. That is, a portion of nonmagnetic layer 24c and a portion of ferromagnetic layer 24b may be deactivated or altered. A nonmagnetic layer 24d having an amorphous alloy containing elements from nonmagnetic layer 24c and ferromagnetic layer 24b can be formed in the portion of conductor layer 24 not directly beneath mask 33. The shape of ferromagnetic layer 24b thus has a protruding portion BP located directly beneath mask 33.

[0141] The slit SH2 is embedded by the insulating layer 34. The insulating layer 34, which is formed on the upper surface of the ferromagnetic layer 27e, is removed by, for example, CMP. Thus, the upper surface of the stacked structure is planarized.

[0142] Next, a mask 35 is formed on the upper surface of the formed structure using photolithography or similar methods. The mask 35 defines the lengths of the SOTL wiring and the magnetoresistive element MTJ in the X direction. The mask 35 extends in the Y direction. Then, anisotropic etching is performed using the mask 35, such as... Figure 16 and Figure 17 As shown, a slit is etched along the Y direction to penetrate the ferromagnetic layer 27e, non-magnetic layer 27d, ferromagnetic layer 27c, non-magnetic layer 27b, ferromagnetic layer 27a, non-magnetic layer 24d, non-magnetic layer 24c, ferromagnetic layer 24b, and antiferromagnetic layer 24a. At the bottom of the etched slit, a portion of the upper surface of the insulating layer 30 is exposed. Physical etching using an ion beam can be used as an anisotropic etching method in this process.

[0143] The Y-direction slits are then filled with an insulating material. Any insulating material formed on the upper surface of the ferromagnetic layer 27e can be removed, for example, by CMP. Thus, the upper surface of the stacked structure can be planarized.

[0144] The fabrication process described above forms the shapes of the wiring SOTL and the magnetoresistive element MTJ in the memory cell array 10. The fabrication process described above is merely an example, and the embodiments are not limited thereto. For example, the switching element SEL2 on the magnetoresistive element MTJ can be formed simultaneously with the magnetoresistive element MTJ through the fabrication process described above.

[0145] 1.4 Effects

[0146] In a first embodiment, a spin-orbit torque writing method is applied to an MRAM comprising a magnetoresistive element (MTJ) with vertical magnetization. In this case, a magnetic field bias is required to be applied to the MTJ. Typically, the configuration used to generate the magnetic field bias may contribute to or require additional complexity to the device structure. However, according to this disclosure, the write operation load can be reduced by generating a magnetic field bias while avoiding significant additional device structure complexity.

[0147] The SOTL wiring consists of a first portion coupled to the word line WL, a second portion coupled to the write bit line WBL, and a third portion coupled to the read bit line RBL. A magnetoresistive element MTJ is coupled between the third portion of the SOTL wiring and the read bit line RBL. A switching element SEL1 is coupled between the second portion of the SOTL wiring and the write bit line WBL. A switching element SEL2 is coupled between the magnetoresistive element MTJ and the read bit line RBL. This allows for the configuration of a memory cell MC using a spin-orbit torque write method.

[0148] The SOTL (Spin-Orbit Transmission Module) includes a ferromagnetic layer 24b and a non-magnetic layer 24c disposed between the ferromagnetic layer 24b and the magnetoresistive element MTJ. The non-magnetic layer 24c comprises at least one element selected from ruthenium (Ru), iridium (Ir), rhodium (Rh), and osmium (Os), and has a film thickness of 3 nanometers or less. Therefore, the non-magnetic layer 24c can simultaneously generate a spin-orbit torque through the current flowing through the SOTL and apply a bias magnetic field AFIE in the opposite direction to the current to the ferromagnetic layer 27a. Thus, write operations can be performed without generating an external magnetic field. Therefore, the overhead of the write operation can be reduced.

[0149] The ferromagnetic layer 24b comprises at least one ferromagnetic element selected from iron (Fe), cobalt (Co), nickel (Ni), and gadolinium (Gd), and an element with at least high orbital angular momentum selected from neodymium (Nd), samarium (Sm), europium (Eu), terbium (Tb), dysprosium (Dy), and holmium (Ho). Therefore, it is possible to generate spin-orbit torque in the nonmagnetic layer 24c while simultaneously generating the bias magnetic field AFIE.

[0150] The ferromagnetic layer 24b is an amorphous alloy. Therefore, the flatness of the SOTL wiring can be improved. This ensures the flatness of the magnetoresistive element MTJ, which is positioned directly above the SOTL wiring. Furthermore, electron scattering of the heavy elements in the ferromagnetic layer 24b can be enhanced. Therefore, a larger spin-orbit torque can be generated.

[0151] The wiring SOTL and the magnetoresistive element MTJ can be formed simultaneously by ion beam etching (IBE). Therefore, when viewed in the Z-direction, the wiring SOTL becomes a rectangular shape with a long side and a short side. When viewed in the Z-direction, the magnetoresistive element MTJ has a rectangular shape with a side parallel to the short side of the wiring SOTL and having a side equal in length to the short side of the wiring SOTL, and a side shorter than the long side of the wiring SOTL and overlapping the long side of the wiring SOTL. When viewed in the Z-direction, the non-magnetic layer 24c has a rectangular shape. The ferromagnetic layer 24b includes a portion that has a rectangular shape when viewed in the Z-direction and a protruding portion MP located between this portion and the non-magnetic layer 24c, which also has a rectangular shape when viewed in the Z-direction. Therefore, the ferromagnetic layer 24b can generate a leakage magnetic field SF directly below the magnetoresistive element MTJ. The leakage magnetic field SF acts on the ferromagnetic layer 27a in the direction of reinforcing the bias magnetic field AFIE. Therefore, the write operation load can be reduced.

[0152] The side surface PXZ of the XZ plane of the protrusion BP parallel to the ferromagnetic layer 24b is formed flush with the side surface of the XZ plane parallel to the ferromagnetic layer 27a. Therefore, the influence of the leakage magnetic field SF on the ferromagnetic layer 27a can be increased. Thus, the load of write operations can be reduced.

[0153] When the SOTL wiring and the MTJ magnetoresistive element are formed by ion beam etching, the portion of the SOTL wiring that does not overlap with the MTJ when viewed in the Z direction is damaged by the etching gas. As a result, a portion of the ferromagnetic layer 24b and a portion of the nonmagnetic layer 24c are deactivated or altered and become nonmagnetic layers 24d-1 and 24d-2. Each of the nonmagnetic layers 24d-1 and 24d-2 is in contact with the ferromagnetic layer 24b and the nonmagnetic layer 24c. The nonmagnetic layers 24d-1 and 24d-2 are disposed separately from each other, with the nonmagnetic layer 24c inserted therebetween. The nonmagnetic layers 24d-1 and 24d-2 comprise elements from the ferromagnetic layer 24b and the nonmagnetic layer 24c. As described above, the nonmagnetic layer 24d loses the properties of the ferromagnetic layer 24b and the nonmagnetic layer 24c. However, the nonmagnetic layer 24d retains its function as a conductive film for allowing write current to pass through the nonmagnetic layer 24c. Therefore, the nonmagnetic layer 24d can contribute to the generation of spin-orbit torque.

[0154] 2. Modify the example

[0155] This disclosure is not limited to the above-described exemplary embodiments, and various modifications may be made.

[0156] In the first embodiment, a two-terminal switching element is used to switch elements SEL1 and SEL2, but this disclosure is not limited thereto. For example, a three-terminal switching element can be used as switching elements SEL1 and SEL2.

[0157] 2.1 Circuit Configuration of Memory Cell Array

[0158] Figure 18 This is a circuit diagram illustrating an example of the circuit configuration of a memory primitive array according to a modified example. Figure 18 Roughly corresponding to Figure 2 .

[0159] Switching element SEL1<i,j> Coupled to the SOTL wiring<i,j> The second part is related to the write bit line WBL <j>Between. Magnetoresistive element MTJ<i,j> Coupled to the SOTL wiring<i,j> The third part is related to the read bit line RBL. <j>Between. Switching component SEL2<i,j> Coupled to the SOTL wiring<i,j> The first part and the word line WL between.

[0160] In this modified example, switching elements SEL1 and SEL2 are three-terminal switching elements, instead of the two-terminal switching elements of the first embodiment. For example, switching elements SEL1 and SEL2 may be surrounding gate transistors (SGTs). Switching elements SEL1 and SEL2 can be independently controlled by applying different voltages to their respective gate terminals.

[0161] 2.2 Planar Layout of Memory Cell Array

[0162] Figure 19 This is a plan view illustrating an example of the planar layout of a memory primitive array based on a modified example. Figure 19 Roughly corresponding to Figure 3 .exist Figure 19 For ease of description, the wiring of the gate terminals coupled to the switching elements SEL1 and SEL2 has been omitted.

[0163] In the memory cell array 10, each of the plurality of vertical structures V1 includes a switching element SEL1. Each of the plurality of vertical structures V2 includes a magnetoresistive element MTJ. Each of the plurality of vertical structures V3 includes a switching element SEL2.

[0164] A set of wiring SOTL, a vertical structure V1, a vertical structure V2 and a vertical structure V3 coupled to the wiring SOTL are used as memory primitives MC.

[0165] 2.3 Cross-sectional structure of memory cell array

[0166] Figure 20 It is along Figure 19 The sectional view taken along line XX-XX shows an example of the cross-sectional structure of a modified memory primitive array. Figure 20 Roughly corresponding to the examples Figure 4 .

[0167] Structure L1 includes conductor layers 41_1, 42_1, 44_1, 45_1, 47_1, 48_1, and 50_1, and element layers 43_1, 46_1, and 49_1. Structure L2 includes conductor layers 41_2, 42_2, 44_2, 45_2, 47_2, 48_2, and 50_2, and element layers 43_2, 46_2, and 49_2.

[0168] First, we will describe the structure L1.

[0169] A conductor layer 41_1 is disposed above the semiconductor substrate 20. The conductor layer 41_1 serves as the write bit line WBL. The conductor layer 41_1 extends in the Y direction.

[0170] Conductor layer 42_1 is disposed on the upper surface of conductor layer 41_1. Conductor layer 42_1 serves as a contact.

[0171] Component layer 43_1 is disposed on the upper surface of conductor layer 42_1. Component layer 43_1 serves as a switching element SEL1. Conductor layer 42_1 and component layer 43_1 constitute a vertical structure V1.

[0172] Conductor layer 44_1 is disposed around element layer 43_1. Conductor layer 44_1 serves as the gate electrode of switching element SEL1.

[0173] Conductor layer 45_1 is disposed on the upper surface of component layer 43_1. Conductor layer 45_1 serves as a wiring SOTL. Conductor layer 45_1 extends in the Y direction.

[0174] Component layer 46_1 is disposed on the lower surface of conductor layer 45_1, which is different from the portion where component layer 43_1 is disposed. Component layer 46_1 serves as a switching element SEL2. Component layer 46_1 constitutes a vertical structure V3.

[0175] Conductor layer 47_1 is disposed around element layer 46_1. Conductor layer 47_1 serves as the gate electrode of switching element SEL2.

[0176] Component layers 43_1 and 46_1 are formed by the same process. In this case, component layers 43_1 and 46_1 are set at the same height. That is, the lower surface of component layer 43_1 lies in the same XY plane as the lower surface of component layer 46_1.

[0177] Conductor layer 48_1 is disposed on the lower surface of element layer 46_1. Conductor layer 48_1 serves as word line WL. Conductor layer 48_1 extends in the X direction.

[0178] Component layer 49_1 is disposed on the upper surface of conductor layer 45_1 located between the portion where component layer 43_1 is disposed and the portion where component layer 46_1 is disposed. Component layer 49_1 serves as a magnetoresistive element MTJ.

[0179] Conductor layer 50_1 is disposed on the upper surface of element layer 49_1. Conductor layer 50_1 serves as the read bit line RBL. Conductor layer 50_1 extends in the Y direction.

[0180] Using the above configuration, conductor layer 45_1 and vertical structures V1, V2 and V3 are used as a memory cell MC having three terminals respectively coupled to conductor layers 41_1, 48_1 and 50_1.

[0181] Structure L2 has the same structure as structure L1. That is, conductor layers 41_2, 42_2, 44_2, 45_2, 47_2, 48_2, and 50_2, and element layers 43_2, 46_2, and 49_2 have the same structure and function as conductor layers 41_1, 42_1, 44_1, 45_1, 47_1, 48_1, and 50_1, and element layers 43_1, 46_1, and 49_1, respectively. Therefore, conductor layer 45_2 and vertical structures V1, V2, and V3 are used as a memory cell MC with three terminals respectively coupled to conductor layers 41_2, 48_2, and 50_2.

[0182] 2.4 Based on the effect of the modified example

[0183] According to the modified example, the memory cell MC includes three-terminal switching elements SEL1 and SEL2. Switching element SEL2 is positioned between the routing SOTL and the word line WL. Therefore, switching elements SEL1 and SEL2 can be provided at the same height. Therefore, switching elements SEL1 and SEL2 can be formed in the same process. Therefore, the increase in manufacturing load on the memory cell array 10 can be minimized.

[0184] 3. Other

[0185] In the memory cell array 10 described in the embodiments and modified examples above, two structures L1 and L2 are depicted stacked on the semiconductor substrate 20; however, this disclosure is not limited thereto. For example, three or more structures having similar structures may be stacked on the semiconductor substrate 20. Furthermore, in some examples, only a single structure may be stacked on the semiconductor substrate 20.

[0186] In some examples, the switching element SEL1 can be a three-terminal type, and the switching element SEL can be a two-terminal type.

[0187] In the modified example described above, the three-terminal switching elements SEL1 and SEL2 are positioned at the same height, but this disclosure is not limited thereto. For example, the two-terminal switching elements SEL1 and SEL2 may be positioned at the same height between the routing SOTL and the write bit line WBL, and between the routing SOTL and the word line WL, respectively.

[0188] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein can be implemented in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

[0189] Marker description

[0190] 1: Magnetic storage device

[0191] 10: Memory Primitive Array

[0192] 11: Row selection circuit

[0193] 12: Column Selection Circuit

[0194] 13: Decoding circuit

[0195] 14: Writing Circuit

[0196] 15: Reading circuit

[0197] 16: Voltage generation circuit

[0198] 17: Input / Output Circuit

[0199] 18: Control Circuit

[0200] 20: Semiconductor substrate

[0201] 21, 23, 24, 25, 26, 29, 41, 42, 44, 45, 47, 48, 50: Conductor layer

[0202] 22, 27, 28, 43, 46, 49: Component Layer

[0203] 24a: Antiferromagnetic layer

[0204] 24b, 27a, 27c, 27e: Ferromagnetic layers

[0205] 24c, 24d, 24d-1, 24d-2, 27b, 27d: Non-magnetic layers

[0206] 30, 32, 34: Insulating layer

[0207] 31, 33, 35: Masks < / j> < / j> < / n> < / n> < / n> < / m> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / n> < / n> < / m> < / x>

Claims

1. A magnetic storage device, comprising: A three-terminal memory cell has a first terminal connected to a first conductor layer, a second terminal connected to a second conductor layer, and a third terminal connected to a third conductor layer, wherein... The memory primitive includes: A fourth conductor layer has a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion connected to the third conductor layer, the third portion being located between the first portion and the second portion. A magnetoresistive element is coupled between the third conductor layer and the fourth conductor layer. A first switching element is coupled between the second conductor layer and the fourth conductor layer, and A second switching element is coupled between the first conductor layer and the third conductor layer. The fourth conductor layer includes: The first ferromagnetic layer has a protruding portion that protrudes upward toward the magnetoresistive element; A first non-magnetic layer is disposed on and in contact with the upper surface of the protrusion between the first ferromagnetic layer and the magnetoresistive element; and A second nonmagnetic layer, comprising elements from the first ferromagnetic layer and elements from the first nonmagnetic layer, is disposed on and in contact with the upper surface of the portion of the first ferromagnetic layer located outside the protrusion, the side surface of the protrusion, and the lower portion of the side surface of the first nonmagnetic layer. The first nonmagnetic layer comprises a first element selected from ruthenium, iridium, rhodium and osmium.

2. The magnetic storage device according to claim 1, wherein, The first non-magnetic layer has a film thickness of 3 nanometers or less.

3. The magnetic storage device according to claim 1, wherein, The first ferromagnetic layer includes a second element selected from iron, cobalt, nickel and gadolinium.

4. The magnetic storage device according to claim 3, wherein, The first ferromagnetic layer also includes a third element selected from neodymium, samarium, europium, terbium, dysprosium and holmium.

5. The magnetic storage device according to claim 4, wherein, The first ferromagnetic layer comprises an amorphous alloy containing the second element and the third element.

6. The magnetic storage device according to claim 4, wherein, The first ferromagnetic layer includes a layer containing the second element and a layer containing the third element.

7. The magnetic storage device according to claim 3, wherein, The first non-magnetic layer has a film thickness of 3 nanometers or less.

8. The magnetic storage device according to claim 1, wherein, The magnetoresistive effect element has: Regarding the first resistance value of the first current flowing from the first portion of the fourth conductor layer to the second portion of the fourth conductor layer, and Regarding the second resistance value of the second current flowing from the second portion of the fourth conductor layer to the first portion of the fourth conductor layer, the second resistance value is different from the first resistance value.

9. The magnetic storage device according to claim 1, wherein, The first ferromagnetic layer, the first non-magnetic layer, and the magnetoresistive element are stacked on top of each other in a first direction. The fourth conductor layer has a first rectangular shape, the first rectangular shape having a long side and a short side, and When viewed in the first direction, the magnetoresistive effect element has a second rectangular shape, the second rectangular shape having a first side and a second side, the first side being parallel to the short side of the fourth conductor layer and having a length equal to the short side of the fourth conductor layer, and the second side having a length less than the long side of the fourth conductor layer but overlapping the long side of the fourth conductor layer.

10. The magnetic storage device according to claim 9, wherein, When viewed in the first direction, the first non-magnetic layer has a shape equal to the second rectangular shape, and When viewed in the first direction, the first ferromagnetic layer has a fourth portion and a fifth portion, the fourth portion having a shape equal to the first rectangular shape, the fifth portion having a shape equal to the second rectangular shape, and the fifth portion being between the fourth portion and the first nonmagnetic layer.

11. The magnetic storage device according to claim 1, wherein, The second switching element is a two-terminal switching element coupled between the third conductor layer and the magnetoresistive effect element.

12. The magnetic storage device according to claim 1, wherein, The second switching element is coupled between the first conductor layer and the fourth conductor layer.

13. The magnetic storage device according to claim 1, wherein, The first switching element and the second switching element are two-terminal switching elements.

14. The magnetic storage device according to claim 1, wherein, The first switching element and the second switching element are three-terminal switching elements.

15. The magnetic storage device according to claim 1, wherein, The magnetoresistive effect element is a magnetic tunnel junction element.

16. A magnetic storage device, comprising: A three-terminal memory cell has a first terminal connected to a first conductor layer, a second terminal connected to a second conductor layer, and a third terminal connected to a third conductor layer, wherein... The memory primitive includes: A fourth conductor layer has a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion connected to the third conductor layer, the third portion being located between the first portion and the second portion. A magnetoresistive element is coupled between the third conductor layer and the fourth conductor layer. A first switching element is coupled between the second conductor layer and the fourth conductor layer, and A second switching element is coupled between the first conductor layer and the third conductor layer. The fourth conductor layer includes: The first ferromagnetic layer has a protruding portion that protrudes upward toward the magnetoresistive element; A first non-magnetic layer is disposed on and in contact with the upper surface of the protrusion between the first ferromagnetic layer and the magnetoresistive element; and A second nonmagnetic layer, comprising elements from the first ferromagnetic layer and elements from the first nonmagnetic layer, is disposed on and in contact with the upper surface of the portion of the first ferromagnetic layer located outside the protrusion, the side surface of the protrusion, and the lower portion of the side surface of the first nonmagnetic layer, wherein... The fourth conductor layer has a first rectangular shape, the first rectangular shape having a long side and a short side, and The magnetoresistive element has a second rectangular shape, which has a first side and a second side. The first side is parallel to the short side of the fourth conductor layer and has a length equal to that of the short side of the fourth conductor layer. The second side has a length less than that of the long side of the fourth conductor layer but overlaps with the long side of the fourth conductor layer.

17. The magnetic storage device according to claim 16, wherein, The first non-magnetic layer has a shape equal to the second rectangular shape, and The first ferromagnetic layer has a fourth portion and a fifth portion, the fourth portion having a shape equal to the first rectangular shape, the fifth portion having a shape equal to the second rectangular shape, and the fifth portion being located between the fourth portion and the first nonmagnetic layer.

18. The magnetic storage device according to claim 16, wherein, The first non-magnetic layer has a film thickness of 3 nanometers or less. The first non-magnetic layer includes: The first element selected from ruthenium, iridium, rhodium, and osmium, and The first ferromagnetic layer includes: A second element selected from iron, cobalt, nickel, and gadolinium, and The third element selected from neodymium, samarium, europium, terbium, dysprosium, and holmium.

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