Device and method for thermally stabilizing probe elements using thermally conductive wafers

Abstract

Materials, apparatus, and methods for heat conduction, including those for predictably maintaining the temperature states and conditions of contact elements and supporting hardware at a tester interface such as an automated test equipment (ATE), and a tester interface such as a probe card, the test equipment having a predetermined configuration suitable for specific pin contact elements and thermal conditions. The heat conduction apparatus also includes a substrate with a predetermined form factor that can be easily incorporated into the test equipment during normal test operations. Unlike patterned substrates limited to specific probe element arrangements, the unpatterned surface of the heat conduction apparatus facilitates use with a variety of probe card designs within many automated test equipment (ATE) tools.

Description

Technical Field

[0001] This disclosure generally relates to materials, apparatus, and methods for predictably and consistently obtaining predetermined thermal states and conditions of interface contact elements and supporting hardware for electrical testing of semiconductor devices. Background Technology

[0002] In parametric, wafer-level, and device-level testing, the standard interface hardware for a test device is a "probe card." This card has multiple probe elements that match the arrangement of the input / output (I / O) pads of the device under test (DUT) connected to it. More specifically, in typical wafer testing, the probe card is mounted in a prober, and the probe contact elements (referred to as "probes") contact the bonding pads, solder balls, and / or gold bumps formed on the die of the wafer. To maintain critical test cost metrics and promote test parallelism, probe cards for test applications can be designed with multiple points (multi-point testing) for both non-memory and memory tests. In high-capacity memory device testing, probe cards can be designed so that all devices on the semiconductor wafer are simultaneously contacted by the probe card or a full-wafer contactor. For probe cards designed for massively parallel operation, excessive downtime due to non-probe operations will affect throughput and substantially increase the overall cost of test (CoT).

[0003] During the testing process (as shown in Figures 1A and 1B), when the pin element 13 or probe contacts the bonding pads 14, solder balls 16, pillars, copper pillar bumps, and / or gold bumps on the semiconductor device under test (DUT) 15, the tip area of ​​each pin element will "scratch" across the contact surface of the bonding pads, etc., of the DUT 15 to create a "scratch mark". A major challenge in high-capacity IC testing (die-level and wafer-level) is ensuring consistent probe-to-pad alignment (PTPA) within the detector to optimize the "scratch" of the probe tip against the bonding pads, solder balls, pillars, copper pillar bumps, and / or gold bumps, thereby achieving electrical contact between the contact pins associated with the contactor element and the contact surface of the DUT 15. Electrical connections are achieved by applying controlled displacement of the probe tip over the bonding pad 14, solder ball 15, pillars, copper pillar bumps, and / or gold bumps, thereby allowing the transmission of power signals, ground signals, and test signals. Misalignment of the probe and pad can cause over-pad damage, which will affect device assembly (wire bonding, flip-chip, etc.) before final packaging.

[0004] The demand for high-performance wafer-level contactor technology has driven the further development of uniquely molded and custom-designed contact elements with predetermined flexibility and engineering mechanical properties. Many new advanced contact technologies feature unique contact element geometries and mechanical properties to facilitate consistent, repeatable, and stable electrical contacts. Some of these technologies are constructed using advanced lithographic assembly techniques, some are built using MEMS-based processes, and others are manufactured using high-precision micromachining techniques.

[0005] Wafer-level testing operations are required at low and / or high temperatures to ensure and facilitate proper test procedure execution, device fault identification, and assessment of long-term device reliability. Depending on device or product requirements, wafer-level and / or die-level testing can be performed at temperatures of -55°C (or lower) or 200°C (or higher). Obtaining accurate and consistent PTPA during wafer testing under the thermal testing conditions necessary for identifying performance faults in semiconductor devices is becoming increasingly difficult.

[0006] Generally, probe cards are designed so that the probe tips remain well centered within the probe pads during test execution; however, it is well known that dimensional changes and thermally induced displacements occur in the probe card, docking hardware, and test unit during heating and cooling processes. Fluctuations in equilibrium temperature can cause expansion and / or contraction of various hardware components within the test unit. During testing, such thermally induced dimensional changes can have a significant impact on probe-pad alignment (PTPA).

[0007] Figure 2 (from Harker et al.'s report "Improving Scrub Performance and Reducing Soak Time with a New Mechanism to Stabilize Probe Card Temperature", IEEE SWTest Workshop, 2009) highlights the change in the scratch location (probe mark) of the all-chip contactor with thermal conditions. It shows the actual scratch mark within the probe pad of an all-chip contactor used for high-capacity testing under elevated temperature conditions, ideally with each of the four touchdowns (first TD to fourth TD) directly centered on the bonding pad as indicated by the centered crosshair in Figure 2. During the heating phase (marked by the first TD), the scratch mark is clearly not well aligned with the crosshair at the center of the bonding pad. As the test cell approaches thermal equilibrium, the alignment of the scratch mark with the center of the bonding pad improves consistently (second and third TDs). Once thermal equilibrium is reached for the test cell and probe card, the scratch mark (fourth TD) is well centered on the bonding pad.

[0008] Inconsistent scratch marks can be observed after batch (LOT) changes, wafer changes, probe trace inspections, probe cleaning, and idle periods due to temperature fluctuations in the probe elements and probe card. It is crucial to minimize the time required to restore thermal equilibrium during probing. Regardless of the probe technology or probe card design, variations in probe trace alignment due to temperature changes will occur. For all-wafer contactors, misalignment can be as high as 15 μm to 25 μm, while for smaller pad sizes, variations and misalignments of a few micrometers can cause quality issues that can lead to long-term reliability problems after device packaging.

[0009] As part of the testing process conducted at low or elevated temperatures, a "temperature-soak time" is implemented to allow the test cell to reach thermal stability at a predetermined target temperature. The required soak time can last for several hours. Semiconductor device testing cannot be performed until the target temperature is reached, and this delay significantly increases overall testing costs due to reduced test cell throughput and productivity. The reduced productivity is summarized in Figure 3 (from Harker et al.'s report "Improving Scrub Performance and Reducing Soak Time with a New Mechanism to Stabilize Probe Card Temperature", IEEE SW Test Workshop, 2009). In this figure, PH50 indicates a 50mm x 50mm probe array, PH75 indicates a 75mm x 75mm probe array, PH100 ​​indicates a 100mm x 100mm probe array, PH150 indicates a 150mm x 150mm probe array, and FWC indicates a full-wafer or 300mm probe array contactor. As shown in Figure 3, the amount of test unit downtime caused by the initial immersion time and recovery immersion time required after installation, maintenance and cleaning increases significantly with the size of the contactor array.

[0010] In response to the issue of long immersion times for probe cards and hardware required for test cell stabilization, several techniques have been used by test bench engineers and developed by probe card manufacturers. To reduce the amount of initial and recovery immersion required, some probe card manufacturers have developed heater elements that can be incorporated into probe card designs. These heater elements are added at an additional cost and are design features that must be defined during the initial manufacturing process; however, these elements are only applicable to a subset of all-wafer contactor designs. For existing all-wafer contactors, these heating elements cannot be retrofitted into the probe card construction. Alternatively, ATE tester suppliers have developed heaters that can be incorporated into probe cards, PCBs, interface stacks, and test heads; however, this additional hardware significantly increases overall testing costs and is not backward compatible with older, legacy testers.

[0011] In a conventional method of probe card thermal soaking using radiative heating as shown in Figure 4, the detector wafer chuck is positioned directly beneath the probe card and moved very close to it. In one case, the wafer chuck can be bare (i.e., no wafer is vacuum-picked onto the chuck) or loaded with blanks or products secured to the chuck by a standard vacuum. In this case, the wafer chuck is used as a heat source within the detector for the entire test cell. As the temperature of the wafer chuck increases, it acts as a radiative heat source, directly heating the probe card and all other hardware (i.e., top plate, probe chuck disk, etc.) until the stable target temperature of the test cell is reached. If the wafer chuck is bare (i.e., without a wafer), there is a risk of probe card damage due to coplanarity differences across the probe card or changes in vertical alignment caused by the expansion and contraction of the hardware under thermal load. Using the bare chuck method, any probe card design can be radiatively heated until the target temperature is reached. After a prolonged immersion time, the product wafer is loaded onto the wafer chuck; however, the probe card is cooled and reduced to below the target temperature after the heat source is removed. Similarly, using the product wafer method, a specific probe card design associated with the device under test is heated and positioned beneath the probe card until the target temperature is reached. Because reaching equilibrium temperature takes a long time, the probe card radiative heating method is typically not used when high-temperature testing is required.

[0012] In another conventional heating method, the probe card uses conductive heating as shown in Figure 5, with a blank silicon wafer (D) positioned on a wafer chuck. In this method, the wafer chuck and vacuum wafer are positioned directly below the probe card and overtravel in the z-direction until all probes of the card are in physical contact with the surface of the blank silicon wafer. The blank wafer remains in physical contact with the probes to facilitate heat transfer across the wafer thickness from the wafer chuck to the probe card. The conductive heat transfer resulting from the probe card overtravel to the blank in Figure 5 is more efficient than the radiative heating in Figure 4, allowing for a reduction in immersion time. Using this method, silicon wafers can be used in various probe card arrangements (A1, B1, and C1) and probe element geometries; however, there is a high risk of potential damage to the probe card associated with overtravel using this type of wafer. The wafer surface must be identified using a look-down camera to accurately define the contact plane. If the contact plane is not accurately defined, there is a risk of permanent or catastrophic damage to the probe card due to excessive overtravel. Sufficient overtravel must be applied to ensure all probes make contact across the probe array; however, this contact will cause probe scraping across the wafer surface. This scraping action across the wafer surface can lead to probe tip contamination, material transfer from the wafer, and damage to the probe tips or probe contact surfaces. Furthermore, adhering contaminants may necessitate probe tip cleaning before wafer probing to prevent yield reductions due to impaired electrical contact and high contact resistance.

[0013] In another conventional method using the conductive heating shown in Figure 6, a scrapped or defective patterned wafer is loaded onto a wafer chuck, aligned with a probe card, and overtravel is applied in the z-direction until all probes make physical contact with the bonding pads of the devices on the wafer. For this method, the arrangement of devices and pads on the wafer must be perfectly matched to the probe card array arrangement and device configuration. For example, the device and arrangement geometry of the probes on probe cards A1, B1, and C1 must be perfectly matched to the device and bonding pad arrangement geometry from wafers A2, B2, and C2, respectively. For example, wafer A2 cannot be used with probe card B1, wafer B2 cannot be used with probe card A1, etc. A dedicated wafer must be used for each device arrangement geometry to avoid damage to the probe card. In this method, overtravel is applied and the scrapped wafer is kept in physical contact with the probes to facilitate heat transfer from the wafer chuck to the probe card via the wafer. Additionally, there is a risk associated with applying overtravel to the pads of the scrapped devices. When the probes contact the pads, they will scrape across the pads, generating adhering debris and other contaminants. Scraping of the bonding pads during overtravel and additional scraping caused by repeated expansion or contraction of the interface stack during dip can lead to probe tip contamination, material transfer, and damage to the probe tip or contact surface. Repeated scraping can also generate additional debris and adhering material. Furthermore, adhering contaminants may necessitate probe tip cleaning before wafer probing to prevent yield drops due to damaged electrical contacts and high contact resistance. Cleaning will affect the stability of hot dip, thus requiring an additional step to restore probe-pad alignment (PTPA).

[0014] Existing conventional procedures using probe cards and hardware-based radiative or conductive heating do not adequately address the apparatus and methods for bonding wafers to thermally conductive, non-transferable, and compliant films with the intended properties of protecting probes from damage and contamination during the immersion time. The process of cleaning the probe card after heat immersion is not desirable; therefore, an efficient method is needed for heat immersion without scraping the bonding pads of bare silicon wafers or scrap wafers. A reduction in immersion time (not provided by conventional systems and methods) is desirable, as it offers significant benefits for reduced testing costs and increased throughput in advanced semiconductor devices. Attached Figure Description

[0015] Figures 1A and 1B illustrate typical examples of probe pads or probe bumps for testing devices under test (DUTs).

[0016] Figure 2 illustrates probe marks (or scratch marks) produced by probes on a probe card during wafer-level testing;

[0017] Figure 3 illustrates the amount of downtime associated with various procedures and processes during wafer-level test operations, with thermal soak-time being the primary cause of downtime and having a detrimental impact on test throughput and overall cost.

[0018] Figure 4 illustrates a typical wafer-level test unit, which includes a wafer prober, automated test equipment (ATE), probe card, detector, and wafer chuck. The wafer chuck can be heated or cooled to a target temperature and moved to a position directly below the probe card so that the target temperature can be obtained by radiation heating.

[0019] Figure 5 shows three different probe cards (A1, B1 and C1) and a blank silicon wafer (D). The blank wafer can be loaded onto the heated wafer chuck of the detector, with the wafer chuck positioned directly below the probe card, and a z-overrun is applied until all probes contact the wafer surface.

[0020] Figure 6 shows three different probe cards (A1, B1 and C1) and three different scrap wafers, defective wafers or patterned wafers (A2, B2 and C2). The probe card is uniquely matched and dedicated to the wafer, so that the probes press against the appropriate pads, the wafer chuck is located directly below the probe card, and z-overtravel is applied until all probes contact the wafer surface.

[0021] Figure 7 An example of a heat conduction device 700 having a heat conduction layer (702) applied to a SEMI standard wafer (704) is shown. The heat conduction device 700 is such as a heat conduction wafer (HCW), which can reduce the immersion time required for probe cards.

[0022] Figure 8 Another embodiment of the HCW 700, having different polymer layers that can be used in HCWs, is illustrated;

[0023] Figure 9 illustrates three different probe cards (A1, B1, and C1) and a thermally conductive wafer (HCW) with a pre-defined thermally conductive, non-transferable, and compliant film applied to its surface. The HCW is loaded onto the wafer chuck directly beneath the probe card, and a z-overrun is applied until all probes contact the thermally conductive film.

[0024] Figure 10 This is a flowchart illustrating a method for using a heat conduction device in a test apparatus;

[0025] Figure 11 This showcases usage examples of HCW from high-volume production environments; and

[0026] Figure 12 The test demonstrated an 8-fold reduction in immersion time during DRAM device testing, comparing immersion time with and without HCW when the detector was in standby or idle mode. Detailed Implementation

[0027] This disclosure is particularly applicable to thermally conductive wafers, thermally conductive devices, and methods for reducing immersion time in probe card assemblies, and will be described in this context. This disclosure is also particularly applicable to materials, apparatus, and methods for predictably and consistently maintaining the thermal state and conditions of probe cards having predetermined arrangements, geometries, probe types, and mechanical properties for high-temperature and / or low-temperature large-area array wafer-level testing of memory and non-memory semiconductor devices. However, it will be appreciated that the thermally conductive wafers, thermally conductive devices, and methods have greater utility because they can be used to reduce immersion time (establish thermal equilibrium) of other test equipment and other processes and machines in semiconductor manufacturing processes and can be configured in different ways, all of which are within the scope of this disclosure.

[0028] For wafer-level testing above and / or below ambient temperatures, the contact elements of the probe card can be various test probes, such as MEMS-type microcantilever probes and MEMS-type vertical probes, vertical line probes, cobra probes, spring probes, contact block probes formed on a diaphragm, wired cantilever probes, etc. The associated support structure can be any type of interface commonly used in probe card construction, such as ceramic or organic space transformers used to support the probe card within the test unit, probe interface plates, reinforcing ribs, printed circuit boards, etc. This disclosure will be described in this context; however, it will be understood that the thermally conductive material layer, device, and method are more effective in maintaining the thermal stability of other test devices and interfaces used in IC semiconductor evaluation equipment.

[0029] Thermally conductive materials, thermally conductive devices, and methods for predictably maintaining the temperature states and conditions of contact elements and supporting hardware at a tester interface, such as a probe card, are disclosed. The conductive device comprises: a predetermined configuration suitable for specific pin contact elements and thermal conditions; and a substrate having a predetermined shape factor that can be easily incorporated into the test equipment during normal test operation. Unlike patterned substrates limited to specific probe element arrangements, the unpatterned surface of the thermally conductive device facilitates use with various probe card designs within many automated test equipment (ATE) tools filling test benches. A conductive material generating device is mounted on the surface of the substrate, providing enhanced thermal performance characteristics impossible to achieve with a blank wafer substrate. The material can also be configured with multiple various thermally conductive particles to further enhance thermal conductivity. The conductive device can be used during normal operation of the test machine while being located in manual, semi-automatic, and automated handling devices and electrical test equipment.

[0030] Figure 7 An example of a heat conduction device 700 is illustrated, such as an exemplary thermal conduction wafer (HCW) for reducing the soaking time of a probe card. The HCW is desirablely designed for probe cards requiring soaking to achieve thermal stability, and is therefore suitable for use in ATE tools and / or testers for massively parallel testing of memory integrated circuits and other large-area array integrated circuit devices, such as DRAM or SRAM, requiring stable high-temperature testing. The HCW can be used, for example, during any event where the temperature of the probe card may change (increase and / or decrease), such as during maintenance, during idle time, and / or during batch replacement processes.

[0031] The thermally conductive layer 702 may be made of a solid elastic material having predetermined thermal conductivity, elasticity, density, and surface energy parameters, which allow the probe to contact and deform the film without damaging the geometry of the contact element. For example, the thermally conductive polymer layer may have predetermined properties: an elongation at break in the range of 8%-70%, a Rockwell hardness of E52 to 99, and a surface energy of 30 to 60 x 10⁻⁶. -6 K -1 The coefficient of thermal expansion is 0.10 to 0.45 W / m² at 23°C. -1 K exhibits high thermal conductivity and an upper operating temperature range of 250°C to 320°C. During overtravel, the tip of the probe element should not penetrate the thermally conductive layer. Since the probe does not penetrate into the polymer, the likelihood of any polymer material transferring to the probe contact element is very low. Figure 7In the illustrated embodiments, a single compliant layer may be a polyimide polymer of high-purity, electronic-grade imide monomers, which is free of contaminants and has thermal stability, chemical resistance, and mechanical properties.

[0032] like Figure 7 As shown, in one embodiment, the HCW may have a thermally conductive layer 702, which may be a polymer, placed on top of a wafer 704, such as a SEMI standard silicon wafer. The HCW 700 may have a shape and configuration that allows it to be used by test equipment during normal operation, thereby enabling thermal conditioning without the need for the insertion of special devices or wafers as in conventional systems and methods. In one example, the HCW 700 may have a total thickness of 795 μm (+ / - 17 μm), with the polymer layer 702 having a thickness of 20 μm (+ / - 2 μm) and the wafer having a thickness of 775 μm (+ / - 15 μm). In one embodiment, the polymer layer 702 may be a spin-coated polymer with low viscosity and a maximum temperature of 300 degrees Celsius.

[0033] In one exemplary embodiment, the substrate 704 used for this application (in this example, a silicon wafer) will be within the SEMI standard, as outlined below in the SEMI M1-Specification for Polished Single Crystal Silicon Wafers for 150mm, 200mm, and 300mm silicon wafers.

[0034] thickness 675mm 725mm 775mm tolerance + / -20μm + / -20μm + / -20μm

[0035] Ideally, the thickness of the polymer layer 702 is less than 20 μm, with a thickness tolerance of less than + / - 5 μm. The conductive coating needs to be thin to facilitate thermal conductivity and rapid heat transfer from the wafer chuck to the probe card; however, it must be thick enough to provide the benefits of a compliant film, thereby providing cushioning and protecting the probe from damage and contamination during immersion time.

[0036] Alternatively, the thermally conductive layer 702 can be laminated onto the surface of the wafer 704; however, flatness and planarity are critical for this application and for very small overtravel.

[0037] The thermally conductive film 702 can have low-tack or poor-adhesion properties, allowing for the separation of the tip from the material surface with very little force when contacting the probe tip element after heat soaking. For wafer-level testing, the typical operating temperature range is from -60°C to 200°C. HCW can be used across the entire current test temperature range for wafer-level testing. For elevated temperatures, the polyimide coating can withstand up to 320°C.

[0038] The thermal conductivity of the thermally conductive film 702 and the permeable layer is directly proportional to the temperature difference across the layer and the thermally conductive area (region); however, it is inversely proportional to the layer thickness. In short, the thinnest possible polymer layer will have the best possible thermal conductivity, as multiple layers will continuously influence heat transfer. Adding thermally conductive particles to the polymer matrix will improve the bulk properties of the thin polymer layer, and this may be a better strategy for improving thermal conductivity.

[0039] For each of the HCW implementations, the HCW is a conductive device having: a predetermined configuration suitable for specific pin contact elements and thermal conditions; and a substrate having a predetermined form factor that can be easily incorporated into the test equipment during normal test operations. For example, different implementations with different configurations may exist for known 50mm x 50mm probe arrays, known 75mm x 75mm probe arrays, known 100mm x 100mm probe arrays, known 150mm x 150mm probe arrays, and known all-wafer or 300mm probe array contactors, examples of which are shown in Figure 3. The probe elements of the probe cards used for the five different area (area) arrays shown in Figure 3 are identical; however, the array size and probe arrangement within the array may differ. The same HCW can be used interchangeably for all five area arrays and probe arrangements to facilitate reduced immersion time. Furthermore, the same HCW used for these five different arrays can be used for completely different probe elements. In this implementation, a single HCW can be used in multiple test units that use different probe elements and probe cards to test different semiconductor devices.

[0040] Unlike conventional patterned substrates limited by specific probe element arrangements, the disclosed thermal conductivity devices, such as HCW, can have unpatterned surfaces. The unpatterned surfaces of the thermal conductivity devices facilitate use with various probe card designs within many automated test equipment (ATE) tools. Conductive materials mounted onto the substrate surface create such devices that provide enhanced thermal performance characteristics impossible to achieve with blank wafer substrates. The material can also be configured with multiple particles of various sizes to further enhance thermal conductivity. The particles can be micron-scale and nano-scale thermal conductivity particles that can be incorporated into the conductive layer, such as boron nitride and zinc oxide. The particles are encapsulated within the thermal conductivity layer as fillers within the matrix. The particles can have various shapes, such as fibrous or pyramidal, to promote packing density. The amount of particle filler can be varied to form composite materials with a mixture of 1% to 40% by weight of thermal conductivity particles; or until the structural integrity of the polymer layer is compromised. The addition of particles can reduce the processability, flexibility, and toughness of the layer, allowing for control of the filler load to obtain the necessary performance characteristics.

[0041] A heat transfer device having a similar or identical shape / configuration to the device / wafer being tested by any test machine can be used during normal operation of the test machine, while it is located in manual, semi-automatic, and automated processing units and electrical test equipment. For example, in manual mode, the heat transfer device can be inserted into the test machine during any event where a drop or increase in probe card temperature is expected. In a semi-automatic instance, it is determined in some way that thermal stability of the probe card needs to be generated, and the test machine is then able to automatically move / place the heat transfer device into the test machine and perform operations to maintain or generate thermal stability of the probe card. In an automated instance, the test machine may have a computer / processor with multiple lines of computer code that execute the process of determining when a heat transfer device is needed and then moving the heat transfer device into place to maintain or generate thermal stability.

[0042] Figure 8 Another embodiment of an HCW 700 is illustrated, having a compliant layer 702 made of different polymers that can be used in an HCW. In this embodiment, the compliant layer 702 can be, for example... Figure 8 The high-purity polyimide material shown in the image. Polyimide is a polymer of imide monomers, and it possesses good thermal stability, good chemical resistance, and excellent mechanical properties.

[0043] The HCW 700 is constructed and designed with a thin, compliant, and conductive material layer 702 (an example of its thickness characteristics is provided above). This layer 702 facilitates efficient heat transfer, enabling consistent and predictable heating during maintenance, idle periods, batch changes, and any events that anticipate a drop or increase in probe card temperature. A single HCW wafer can be used for multiple probe card arrangements and probe geometries across multiple test cell platforms (i.e., no phaseout). As shown in Figure 9, the HCW can be used with the three representative probe cards mentioned above, as well as many other probe cards. Regular and repeated use of the thermally conductive wafer with the compliant layer will not affect the performance of the contact elements, and after using the HCW, there is no need for subsequent methods of cleaning and maintaining the contact elements before probing. Regular use of the HCW to reduce immersion time has significant benefits for reduced testing costs and increased throughput in advanced semiconductor devices.

[0044] In various embodiments of heat conduction devices, the conductive layer can possess controlled surface functionalization and adjustable behavior. This is an effective way to alter the mechanical properties of the surface to achieve specific performance objectives, such as thermal conductivity, contact surface cleanliness, debris removal and collection, and surface texturing. Functional coatings with predetermined properties can be applied to the surface of a wafer to provide a new type of material that can be customized and optimized for contact elements and perform a well-defined set of functions, such as thermal conductivity, thickness, hardness, and viscosity. Furthermore, various filler materials, such as the aforementioned particles, can be incorporated into the thickness of the film to further modify and / or enhance performance.

[0045] The aforementioned HCW device 700 facilitates heat transfer via the radiation and conduction mechanisms between the probe wafer chuck and the probe card, while protecting the probe elements from damage during contact. A compliant film acts as a protective buffer to achieve full contact across the entire probe card at relatively low contact displacement (or z-travel). At low z-travel, forces on the probe elements are minimized, yet full contact across the wafer is achieved without any material transfer or contamination. The thermally conductive medium is a planar, featureless, unpatterned, and compliant film layer that provides performance characteristics impossible to achieve on a rigid, unpatterned wafer surface or a rigidly patterned wafer surface with a specific geometry in a semiconductor device.

[0046] In one aspect of this method, the HCW can be placed in a predetermined position within an automated test apparatus, such as a wafer prober, such that the pin elements will periodically interact with a thermally conductive cleaning medium. In an embodiment, a single HCW can be used within a prober to thermally hold many different types of probe cards, as illustrated in Figure 9. Thus, this apparatus and method ensure that clean, thermally held probe cards are available for high-volume wafer-level testing.

[0047] In various embodiments of the heat conduction device 700, the heat conduction layer 702 may have a sacrificial top protective material layer, which may be applied before, during, or after the manufacturing process to protect and isolate the material surface from contamination during the manufacturing process and manual handling operations. The protective sacrificial layer ensures that the surface of the conductive material is free of any contaminants that would impair the performance of the contact element. The protective sacrificial layer is removed after mounting onto a semiconductor testing device. In another embodiment of heat conduction, the heat conduction layer 702 may be formed of a heat conduction material to increase the material's compliance during probe card immersion. In another embodiment, a certain level of particle loading may be present to further enhance thermal conductivity and heat transfer efficiency. Typical particles that can be incorporated into the material layer are micron-scale and nano-scale heat conduction particles, such as boron nitride, zinc oxide, etc., or some other well-known heat conduction materials. The amount of particulate filler can be varied to produce a composite having a mixture of 1% to 40% by weight of heat conduction particles; or until the structural integrity of the polymer layer is compromised.

[0048] Figure 10 An example is illustrated of a method 1000 for thermal conditioning using a heat transfer device, which results in a significantly shorter warm-up time for the test machine compared to conventional methods. It should be noted that the heat transfer device can be used as part of the normal test operation of the test equipment, such that, for example, one or more probe cards of the test equipment do not need to be removed from the test machine during thermal conditioning. The test machine can perform its normal test operation (1002) and then determine whether an event has occurred or is occurring that will cause a temperature change in the probe cards (1004). This event can be detected manually, for example, during batch changes or automatically by a computer system executing multiple lines of instructions to perform the testing process, during which, for example, the heat transfer device automatically moves into place when an event occurs that will cause a temperature change in the probe cards. If no event occurs, the test machine continues to perform the test (1002).

[0049] If the event has occurred (examples of different actions that could lead to the event are described above), the heat transfer device is loaded into the test machine below the probe card (1006). The probe card can then be moved so that it is adjacent to the heat transfer device (the tip of the probe card element touches the heat transfer device) and the clamps passing through the heat transfer device can preheat the probe card (1008). Figure 11 and Figure 12 As shown and discussed below, the preheating time using the heat transfer device is significantly shorter than the typical preheating time and prevents the probe from getting stuck due to excessive temperature changes during the event. Once the event is over, the heat transfer device can be removed (1010), and the test machine can be restored to its normal test operation (1002).

[0050] Figure 11 An exemplary use of a heat transfer device (HCW) is illustrated in a predetermined location within an automated test setup, such as a wafer probe station, in a high-volume manufacturing test environment, where the pre-defined location allows pin elements to periodically interact with a heat-conducting cleaning medium. Figure 11 As shown, this method has a series of processes.

[0051] Procedure 1: Unload wafer 25 from the wafer chuck for batch end execution. In this case, HCW is not used and the detector is allowed to remain idle while the next batch of wafers is prepared. During the idle time, the wafer chuck remains at the target test temperature; however, it does not maintain the probe card temperature required for testing.

[0052] Procedure 2: During the 60-minute detector idle period, the probe card temperature dropped to approximately 43°C. The probe card temperature during the idle period was approximately 22°C lower than the required test temperature.

[0053] Process 3: Install the next batch of 25 wafers into the detector to initiate batch start execution. Load wafer 1 onto the wafer chuck and move it to a position below the probe card for approximately 20 minutes of radiation preheating, until the probe card reaches the target temperature of T = 60°C.

[0054] Process 4: Once the probe card approaches the test temperature, raise chip 1 to contact the probe card for approximately 20 minutes of secondary conduction preheating until the probe card reaches the target temperature of T=65℃.

[0055] Process 5: After 40 minutes of conductive preheating, the probe card temperature stabilizes to a temperature slightly above T=65℃, and probe testing begins on wafer 1.

[0056] Process 6: After probing 25 wafers, the batch is completed and wafer 25 is unloaded, as previously performed.

[0057] Process 7: Instead of allowing the detector to remain idle while preparing for the next batch, the HCW is loaded onto the wafer chuck and brought into contact with the probe card.

[0058] Process 8: During detector idle time, HCW remains in contact with the probe card and provides stable thermal conditions through conduction heating.

[0059] Process 9: Once a batch of 25 wafers has been installed in the detector, the HCW is unloaded and the detector is ready for device testing.

[0060] Process 10: Immediately after unloading the HCW, load wafer 1 onto the wafer chuck and move it to the position below the probe card for radiation preheating for less than 1 minute, so that the probe card can quickly reach the target temperature of T=60℃.

[0061] Process 11: Raise wafer 1 to make it contact the probe card for secondary conduction preheating for less than 6 minutes, so that the probe card reaches the target temperature of T=65℃.

[0062] Process 12: After a preheating period of less than 6 minutes, the probe card temperature stabilizes to a temperature slightly above T=65℃, and probe testing begins on wafer 1.

[0063] Figure 12 The advantages and benefits of heat transfer devices are illustrated. Specifically, when heat transfer devices are not used to achieve thermal stability, the probe card temperature fluctuates (dropping to approximately 40°C in high-temperature testing examples), and approximately 40 minutes of preheating is required before the testing process can be restarted. In contrast, when heat transfer devices are used, the probe card temperature remains more stable (closer to the specified probe / test temperature, such as...). Figure 11 (As shown), and after loading the heat transfer device, it requires less than 6 minutes of preheating to resume probe / testing. This significant difference in preheating time (an 8-fold reduction in immersion time) means reduced detector / tester downtime and increased tester / problem throughput. Other advantages include reduced contamination risk and probe abrasion resistance.

[0064] The methods and apparatus described herein offer one or more advantages, including but not limited to heat-dip holding of contactors and probe cards. While this disclosure has been described with reference to certain exemplary embodiments, those described herein are not intended to be limiting. For example, variations or combinations of the steps in the shown and described embodiments may be used in certain situations without departing from this disclosure. Various modifications and combinations of exemplary embodiments, as well as other advantages and embodiments of this disclosure, will become apparent to those skilled in the art upon reference to the accompanying drawings, description, and claims. The scope of this disclosure is intended to be defined by the appended claims and their equivalents. Although the foregoing has referred to specific embodiments of the invention, those skilled in the art will understand that changes may be made to the embodiments of the invention without departing from the principles and spirit of this disclosure, the scope of which is defined by the appended claims.

[0065] For purposes of explanation, the foregoing description has been made with reference to specific embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. In view of the above teachings, many modifications and variations are possible. The embodiments chosen and described are intended to best explain the principles of the present disclosure and its practical application, thereby enabling those skilled in the art to best utilize the present disclosure and various embodiments and modifications suited to the intended particular purpose.

[0066] The systems and methods disclosed herein can be implemented or distributed among such elements via one or more components, systems, servers, devices, or other sub-components. When implemented as a system, such a system may include and / or involve components such as software modules, general-purpose CPUs, RAM, etc., as seen in general-purpose computers. In implementations where innovation resides on a server, such server may include or involve components such as CPUs, RAM, etc., as seen in general-purpose computers.

[0067] Furthermore, the systems and methods described herein can be implemented using different or entirely different software, hardware, and / or firmware components, in addition to the implementations described above. Regarding other components (e.g., software, processing components, etc.) and / or computer-readable media associated with or embodying the invention, such as aspects of the innovations described herein, they can be implemented according to many general-purpose or special-purpose computing systems or configurations. Various exemplary computing systems, environments, and / or configurations suitable for use with the innovations described herein may include, but are not limited to: software or other components located within or embodied in a personal computer; servers or server computing devices such as routing / connectivity components; handheld or laptop devices; multiprocessor systems; microprocessor-based systems; set-top boxes; consumer electronic devices; network PCs; other existing computer platforms; and distributed computing environments including one or more of the above systems or devices.

[0068] In some cases, aspects of the system and method may be achieved or executed by logical components and / or logical instructions comprising, for example, program modules that execute in association with such components or circuits. Generally, program modules may include routines, programs, objects, components, data structures, etc., that perform specific tasks or execute specific instructions herein. The invention can also be practiced in the context of distributed software, computer, or circuit setups, where circuits are connected via communication buses, circuits, or links. In distributed setups, control / instructions can be executed either locally or from remote computer storage media (including memory storage devices).

[0069] The software, circuits, and components described herein may also include and / or utilize one or more types of computer-readable media. Computer-readable media can be any usable medium residing on, associated with, or accessible by such circuitry and / or computing components. By way of example, and not limitation, computer-readable media may include computer storage media and communication media. Computer storage media includes media that are volatile or non-volatile, removable or non-removable, implemented in any way or by any technique for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by computing components. Communication media may include computer-readable instructions, data structures, program modules, and / or other components. Furthermore, communication media may include wired media, such as wired networks or direct wired connections; however, no such type of media is included herein, including transient media. Any combination of the above is also included within the scope of computer-readable media.

[0070] In the description of this invention, the terms component, module, device, etc., can refer to any type of logical or functional software element, circuit, block, and / or process that can be implemented in a variety of ways. For example, the functions of various circuits and / or blocks can be combined with each other to form any other number of modules. Each module can even be implemented as a software program stored in physical memory (e.g., random access memory, read-only memory, CD-ROM memory, hard disk drive, etc.) for reading by a central processing unit to implement the functions of the innovations described herein. Alternatively, the module may contain programmable instructions transmitted via a transmission carrier to a general-purpose computer or processing / graphics hardware. Furthermore, the module can be implemented as hardware logic circuitry that implements the functions covered by the innovations described herein. Finally, the module can be implemented using dedicated instructions (SIMD instructions), field-programmable logic arrays, or any combination thereof that provide the required level of performance and cost.

[0071] As disclosed herein, features consistent with this disclosure can be implemented via computer hardware, software, and / or firmware. For example, the systems and methods disclosed herein can be embodied in various forms, including, for example, data processors such as computers, as well as databases, digital electronic circuits, firmware, software, or combinations thereof. Furthermore, while some of the disclosed embodiments describe specific hardware components, systems and methods consistent with the innovations herein can be implemented using any combination of hardware, software, and / or firmware. Moreover, the aforementioned features, other aspects, and principles of the innovations herein can be implemented in various environments. Such environments and related applications can be specially configured to perform various routines, processes, and / or operations according to the invention, or they may include general-purpose computers or computing platforms that are selectively activated or reconfigured by code to provide necessary functionality. The processes disclosed herein are inherently independent of any particular computer, network, architecture, environment, or other device and can be implemented by suitable combinations of hardware, software, and / or firmware. For example, various general-purpose machines can be used with programs written according to the teachings of the invention, or dedicated devices or systems can be more readily constructed to perform the required methods and techniques.

[0072] The methods and systems described herein (such as logic components) can also be implemented as functions programmable into any of a variety of circuits, including programmable logic devices (“PLDs”), such as field-programmable logic arrays (“FPGAs”), programmable array logic (“PALs”), electrically programmable logic and memory devices, standard cell-based devices, and application-specific integrated circuits (ASICs). Other possibilities for implementing aspects include memory devices, microcontrollers with memory (such as EEPROMs), embedded microprocessors, firmware, software, etc. Furthermore, aspects can be embodied in microprocessors that feature software-based circuit simulation, discrete logic (sequential and combinatory), custom devices, fuzzy (neural) logic, quantum devices, and any mixture of the above device types. Underlying device technologies can be provided with a variety of component types, such as metal-oxide-semiconductor field-effect transistor (“MOSFET”) technologies like complementary metal-oxide-semiconductor (“CMOS”), bipolar technologies like emitter-coupled logic (“ECL”), polymer technologies (e.g., silicon conjugated polymers and metal conjugated polymer-metal structures), hybrid analog and digital, etc.

[0073] It should also be noted that, in terms of its behavior, register transfers, logical components, and / or other characteristics, the various logic and / or functions disclosed herein can be enabled using any number of hardware, firmware combinations, and / or as data and / or instructions embodied in various machine-readable or computer-readable media. Computer-readable media that can embody such formatted data and / or instructions include, but are not limited to, various forms of non-volatile storage media (e.g., optical, magnetic, or semiconductor storage media), but also exclude temporary media. Unless the context explicitly requires otherwise, throughout the description, the terms “comprise,” “comprising,” and the like should be interpreted in an inclusive rather than exclusive or exhaustive sense; that is, in the sense of “including but not limited to.” The use of singular or plural terms also includes both singular and plural, respectively. Furthermore, the terms “in this document,” “below,” “above,” “below,” and similar terms refer to the entire application and not any particular part of it. When the word "or" is used to refer to a list of two or more items, the word covers all of the following interpretations: any item in the list, all items in the list, and any combination of items in the list.

[0074] While certain preferred embodiments of the invention have been specifically described herein, it will be apparent to those skilled in the art that variations and modifications can be made to the various embodiments shown and described herein without departing from the spirit and scope of the invention. Therefore, the invention is intended to be limited only to the scope required by applicable laws and regulations.

[0075] While the foregoing has been described with reference to specific embodiments of this disclosure, those skilled in the art will understand that modifications can be made to the embodiments of the invention without departing from the principles and spirit of this disclosure, the scope of which is defined by the appended claims.

Claims

1. A heat transfer device for automating semiconductor testing machines, the device comprising: A substrate capable of being processed by the processor mechanism of an automated semiconductor testing machine; and A thermally conductive layer is applied to the top surface of the substrate, which maintains or generates thermal stability of the probe card, which is part of the automated semiconductor testing machine. The thermally conductive layer is compliant and protects one or more probe elements in contact with the thermally conductive layer during a heat immersion event.

2. The apparatus of claim 1, wherein the thermally conductive layer further comprises a polymer layer.

3. The apparatus of claim 2, wherein the polymer is polyimide.

4. The apparatus of claim 3, wherein the polyimide layer has a plurality of particles embedded therein, the plurality of particles improving the thermal conductivity of the polyimide layer.

5. The apparatus of claim 1, wherein the substrate further comprises a silicon wafer.

6. The apparatus of claim 5, wherein the silicon wafer further comprises a SEMI standard semiconductor silicon wafer.

7. The apparatus of claim 1, further comprising: a sacrificial top layer located on top of the heat-conducting layer, the sacrificial top layer preventing contamination of the heat-conducting layer when not in use.

8. The apparatus of claim 6, wherein the thermally conductive layer has a thickness of about 20 µm and the substrate has a thickness of about 775 µm.

9. A method for testing a semiconductor device, the method comprising: An automated test machine is used to perform tests on multiple semiconductor devices at test temperatures different from ambient temperatures. The automated test machine has a probe card with multiple probe elements configured to establish an electrical connection with each test point of the semiconductor device. Determine if an event is occurring where the temperature of the probe card deviates from the test temperature; The heat transfer device is moved to a position in which it contacts the plurality of probe elements of the probe card; The heat conduction device is used to perform heat conduction to keep the plurality of probe elements of the probe card at a temperature closer to the test temperature during the event; and Once the event is complete, perform the test at the test temperature. The heat conduction device described therein is the heat conduction device according to any one of claims 1-8.

10. The method of claim 9, further comprising: Reduce the time between testing and recovery after the event.

11. The method of claim 9, wherein the test temperature is a temperature higher than the ambient temperature.

12. The method of claim 9, wherein the test temperature is a temperature lower than the ambient temperature.

13. The method of claim 10, further comprising: The heat transfer device is mounted onto the wafer chuck to perform the heat transfer.

14. The method of claim 13, further comprising: The heat conduction device is unloaded from the wafer chuck when the event is completed.

15. The method of claim 14, wherein the event is selected from one of a maintenance event, idle time of an automated test machine, and a batch replacement process.

16. Automated testing machines, including: A chuck for securing a semiconductor device being tested by the automated test machine, the semiconductor device having multiple points through which signals enter or leave the semiconductor device; The test equipment has a probe card with multiple probe elements configured to establish an electrical connection with each point of the semiconductor device and perform tests on the semiconductor device at a test temperature different from the ambient temperature. and A heat transfer device comprising: a substrate capable of being handled by the chuck of the automated testing machine; A thermally conductive layer is applied to the top surface of the substrate, which maintains or generates thermal stability of the probe card as part of the automated semiconductor testing machine during events in which the temperature of the probe card deviates from the test temperature. The thermally conductive layer is compliant and protects one or more probe elements in contact with the thermally conductive layer during heat immersion events.

17. The machine of claim 16, wherein the heat-conducting layer further comprises a polymer layer.

18. The machine of claim 17, wherein the polymer is polyimide.

19. The machine of claim 18, wherein the polyimide layer has a plurality of particles embedded therein, the plurality of particles improving the thermal conductivity of the polyimide layer.

20. The machine of claim 16, wherein the substrate further comprises a silicon wafer.

21. The machine of claim 20, wherein the silicon wafer further comprises a SEMI standard semiconductor silicon wafer.

22. The machine of claim 16, wherein the heat conduction device further comprises: a sacrificial top layer located on top of the heat conduction layer, the sacrificial top layer preventing contamination of the heat conduction layer when not in use.

23. The machine of claim 21, wherein the heat-conducting layer has a thickness of about 20 µm and the substrate has a thickness of about 775 µm.

24. The machine of claim 16, wherein the event is selected from one of a maintenance event, idle time of an automated test machine, and a batch replacement process.

25. The machine of claim 16, further comprising a processor and memory, and multiple lines of computer code executed by the processor to configure the processor for: It has been determined that the event is occurring; The heat transfer device is moved to a position in which it contacts the plurality of probe elements of the probe card; and This causes the heat conduction device to perform heat conduction to keep the plurality of probe elements of the probe card at a temperature closer to the test temperature during the event.

26. The machine of claim 25, wherein the processor is further configured to perform the test at the test temperature once the event is complete.

27. The machine of claim 26, wherein the processor is further configured to reduce the time period before the test is recoverable after the event.

28. The machine of claim 16, wherein the test temperature is a temperature higher than the ambient temperature.

29. The machine of claim 16, wherein the test temperature is a temperature lower than the ambient temperature.

30. The machine of claim 27, wherein the processor is further configured to cause the heat transfer device to be loaded onto the chuck to perform the heat transfer, and wherein the processor is further configured to cause the heat transfer device to be unloaded from the chuck upon completion of the event.

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